R5975AD Up to 2.5 A step-down switching regulator for aerospace applications Datasheet - preliminary data – Advanced mold and frame designs for superior resilience in harsh environments (acceleration, EMI, thermal, humidity) – Extended screening capability on request Applications HSOP8 - exposed pad Dedicated to aerospace applications Features Description General features – 2.5 A DC output current – Operating input voltage from 4 V to 36 V – 3.3 V / (±2%) reference voltage – Large ambient temperature range: -40 °C to 125 °C – Output voltage adjustable from 1.235 V to 35 V – Low dropout operation: 100% duty cycle – 500 kHz internally fixed frequency – Voltage feed-forward – Zero load current operation – Internal current limiting – Inhibit for zero current consumption – Synchronization – Protection against feedback disconnection – Thermal shutdown The R5975AD is a step-down monolithic power switching regulator with a minimum switch current limit of 3.1 A, it is therefore able to deliver up to 2.5 A DC current to the load depending on the application conditions. The output voltage can be set from 1.235 V to 35 V. The high current level is also achieved thanks to a HSOP8 package with exposed frame, that allows to reduce the RTHJ-A down to approximately 40 °C/W. The device uses an internal P-channel DMOS transistor (with a typical RDS(on) of 250 m) as switching element to minimize the size of the external components. An internal oscillator fixes the switching frequency at 500 kHz. The large ambient temperature range makes it ideal for aerospace and defense applications. Pulse-by-pulse current limit with the internal frequency modulation offers an effective constant current short-circuit protection. Aerospace and defense features – Suitable for use in aerospace and defense applications – Dedicated traceability and part marking – Production parts approval documents available – Adapted extended life time and obsolescence management – Extended product change notification process – Designed and manufactured to meet subppm quality goals November 2014 DocID027135 Rev 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/47 www.st.com Contents R5975AD Contents 1 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Datasheet parameters over the temperature range . . . . . . . . . . . . . . . 10 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 7 2/47 5.1 Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 Voltage monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 Current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.6 PWM comparator and power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.7 Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.8 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Additional features and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 Zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.1 Error amplifier and compensation network . . . . . . . . . . . . . . . . . . . . . . . . 19 7.2 LC filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.3 PWM comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DocID027135 Rev 1 R5975AD 8 Contents Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.1 Component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.2 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.3 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.3.1 8.3.2 Thermal resistance RTHJ-A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Thermal impedance ZthJ-A(t) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.4 RMS current of the embedded power MOSFET . . . . . . . . . . . . . . . . . . . 32 8.5 Short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.6 Positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.7 Negative buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.8 Floating boost current generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.9 Synchronization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.10 Compensation network with MLCC at the output . . . . . . . . . . . . . . . . . . . 40 8.11 External soft-start network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 DocID027135 Rev 1 3/47 47 List of tables R5975AD List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. 4/47 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Uncompensated error amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 List of ceramic capacitors for the R5975AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 HSOP8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 DocID027135 Rev 1 R5975AD List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Internal circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Oscillator circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Synchronization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Current limitation circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Driving circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Block diagram of the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Error amplifier equivalent circuit and compensation network . . . . . . . . . . . . . . . . . . . . . . . 20 Module plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Phase plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power losses estimation (VIN = 5 V, fSW = 500 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power losses estimation (VIN = 12 V, fSW = 500 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Measurement of the thermal impedance of the demonstration board . . . . . . . . . . . . . . . . 31 Maximum continuous output current vs. duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Short-circuit current VIN = 12 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Short-circuit current VIN = 24 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Short-circuit current VIN = 36 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Negative buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Floating boost topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 350 mA LED boost current source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Synchronization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MLCC compensation network circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Soft-start network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Line regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Shutdown current vs. junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Output voltage vs. junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Junction temperature vs. output current (VIN = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Junction temperature vs. output current (VIN = 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Efficiency vs. output current (VIN = 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Efficiency vs. output current (VIN = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 HSOP8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DocID027135 Rev 1 5/47 47 Pin settings R5975AD 1 Pin settings 1.1 Pin connection Figure 1. Pin connection (top view) $0Y 1.2 Pin description Table 1. Pin description 6/47 No. Pin Description 1 OUT 2 SYNCH 3 INH 4 COMP 5 FB 6 VREF 3.3 V VREF. No cap is requested for stability 7 GND Ground 8 VCC Unregulated DC input voltage Regulator output Master/slave synchronization A logical signal (active high) disables the device. If INH is not used the pin must be grounded. When it is open, an internal pull-up disables the device E/A output for frequency compensation Feedback input. Connecting directly to this pin results in an output voltage of 1.23 V. An external resistive divider is required for higher output voltages DocID027135 Rev 1 R5975AD Electrical data 2 Electrical data 2.1 Maximum ratings Table 2. Absolute maximum ratings Symbol Value Unit 40 V V V V8 Input voltage V1 OUT pin DC voltage OUT pin peak voltage at t = 0.1 µs -1 to 40 -5 to 40 I1 Maximum output current int. limit. V4, V5 Analog pins 4 V -0.3 to VCC V -0.3 to 4 V 2.25 W Operating junction temperature range -40 to 150 °C Storage temperature range -55 to 150 °C Value Unit 40(1) °C/W V3 INH V2 SYNCH PTOT TJ TSTG 2.2 Parameter Power dissipation at TA 60 °C Thermal data Table 3. Thermal data Symbol RTHJ-A Parameter Maximum thermal resistance junction ambient 1. Package mounted on demonstration board. DocID027135 Rev 1 7/47 47 Electrical characteristics 3 R5975AD Electrical characteristics TJ = -40 °C to 125 °C, VCC = 12 V, unless otherwise specified. Table 4. Electrical characteristics Symbol VCC Parameter Operating input voltage range Test condition V0 = 1.235 V; I0 = 2 A Min. 4 fSW Maximum limiting current VCC = 5 V Switching frequency Duty cycle Max. Unit 36 V 0.250 0.5 3.1 3.6 4.1 A 425 500 575 kHz 100 % RDS(on) MOSFET on-resistance IL Typ. 0 Dynamic characteristics V5 Voltage feedback 4.4 V < VCC < 36 V, 20 mA < I0 < 2 A 1.198 1.235 1.272 V 5 7 mA 2.7 mA DC characteristics Iqop Iq Iqst-by Total operating quiescent current Quiescent current Total standby quiescent current Duty cycle = 0; VFB = 1.5 V VINH > 2.2 V 50 100 µA VCC = 36 V; VINH > 2.2 V 50 100 µA 0.8 V Inhibit INH threshold voltage Device ON Device OFF 2.2 V 3.5 V Error amplifier VOH High level output voltage VFB = 1 V VOL Low level output voltage VFB = 1.5 V Io source Source output current Io sink Sink output current Ib Source bias current gm VCOMP = 1.9 V; VFB = 1 V VCOMP = 1.9 V; VFB = 1.5 V 0.4 190 300 µA 1 1.5 mA 2.5 DC open loop gain RL = Transconductance ICOMP = -0.1 mA to 0.1 mA; VCOMP = 1.9 V V 50 4 µA 65 dB 2.3 mS Synch function 8/47 High input voltage VCC = 4.4 to 36 V Low input voltage VCC = 4.4 to 36 V Slave synch current(1) Vsynch = 0.74 V Vsynch = 2.33 V 0.11 0.21 Master output amplitude Isource = 3 mA 2.75 3 V Output pulse width No load, Vsynch = 1.65 V 0.20 0.35 µs DocID027135 Rev 1 2.5 VREF V 0.74 V 0.25 0.45 mA R5975AD Electrical characteristics Table 4. Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit 3.2 3.3 3.399 V Reference section Reference voltage IREF = 0 to 5 mA, VCC = 4.4 V to 36 V Line regulation IREF = 0 mA, VCC = 4.4 V to 36 V 5 10 mV Load regulation IREF = 0 mA 8 15 mV 18 35 mA Short-circuit current 5 1. Guaranteed by design. DocID027135 Rev 1 9/47 47 Datasheet parameters over the temperature range 4 R5975AD Datasheet parameters over the temperature range 100% of the population in the production flow is tested at three different ambient temperatures (-40 C, +25 C, +125 C) to guarantee the datasheet parameters inside the junction temperature range (-40 C; +125 C). The device operation is guaranteed when the junction temperature is inside the (-40 C; +150 C) temperature range. The user can estimate the silicon temperature increase with respect to the ambient temperature evaluating the internal power losses generated during device operation (please refer to Section 2.2). However, the embedded thermal protection disables the switching activity to protect the device in case the junction temperature reaches the TSHTDWN (+150 C ± 10 C) temperature. All the datasheet parameters can be guaranteed to a maximum junction temperature of +125 C, to avoid triggering the thermal shutdown protection during the testing phase due to self-heating. 10/47 DocID027135 Rev 1 R5975AD 5 Functional description Functional description The main internal blocks are shown in the device block diagram in Figure 2. They are: A voltage regulator supplying the internal circuitry. From this regulator, a 3.3 V reference voltage is externally available. A voltage monitor circuit which checks the input and the internal voltages. A fully integrated sawtooth oscillator with a frequency of 500 kHz 15%, including also the voltage feed-forward function and an input/output synchronization pin. Two embedded current limitation circuits which control the current that flows through the power switch. The pulse-by-pulse current limit forces the power switch off cycle-bycycle if the current reaches an internal threshold, while the frequency shifter reduces the switching frequency in order to significantly reduce the duty cycle. A transconductance error amplifier. A pulse width modulator (PWM) comparator and the relative logic circuitry necessary to drive the internal power. A high side driver for the internal P-MOS switch. An inhibit block for standby operation. A circuit to implement the thermal protection function. Figure 2. Block diagram $0Y DocID027135 Rev 1 11/47 47 Functional description 5.1 R5975AD Power supply and voltage reference The internal regulator circuit (shown in Figure 3) consists of a start-up circuit, an internal voltage pre-regulator, the bandgap voltage reference, and the bias block that provides current to all the blocks. The starter supplies the start-up currents to the entire device when the input voltage goes high and the device is enabled (inhibit pin connected to ground). The pre-regulator block supplies the bandgap cell with a pre-regulated voltage, VREG, that has a very low supply voltage noise sensitivity. 5.2 Voltage monitor An internal block continuously senses the VCC, VREF and VBG. If the voltages go higher than their thresholds, the regulator begins operating. There is also a hysteresis on the VCC (UVLO). Figure 3. Internal circuit $0Y 5.3 Oscillator and synchronization Figure 4 shows the block diagram of the oscillator circuit. The clock generator provides the switching frequency of the device, which is internally fixed at 500 kHz. The frequency shifter block acts to reduce the switching frequency in case of strong overcurrent or short-circuit. The clock signal is then used in the internal logic circuitry and is the input of the ramp generator and synchronizer blocks. The ramp generator circuit provides the sawtooth signal, used for PWM control and the internal voltage feed-forward, while the synchronizer circuit generates the synchronization signal. The device also has a synchronization pin which can work both as master and slave. Beating frequency noise is an issue when more than one voltage rail is on the same board. A simple way to avoid this issue is to operate all the regulators at the same switching frequency. 12/47 DocID027135 Rev 1 R5975AD Functional description The synchronization feature of a set of the R5975AD is simply obtained by connecting together their SYNCH pins. The device with the highest switching frequency is the master which provides the synchronization signal to the others. Therefore the SYNCH is an I/O pin to deliver or recognize a frequency signal. The synchronization circuitry is powered by the internal reference (VREF) so a small filtering capacitor (100 nF) connected between the VREF pin and the signal ground of the master device is recommended for its proper operation. However, when a set of synchronized devices populates a board it is not possible to know in advance the one working as master, so the filtering capacitor must be designed for a whole set of devices. When one or more devices are synchronized to an external signal, its amplitude must be in compliance with specifications given in Table 4 on page 8. The frequency of the synchronization signal must be, at a minimum, higher than the maximum guaranteed natural switching frequency of the device (275 kHz, see Table 4) while the duty cycle of the synchronization signal can vary from approximately 10% to 90%. The small capacitor under VREF pin is required for this operation. Figure 4. Oscillator circuit block diagram $0Y DocID027135 Rev 1 13/47 47 Functional description R5975AD Figure 5. Synchronization example 5.4 Current protection The R5975AD features two types of current limit protection; pulse-by-pulse and frequency foldback. The schematic of the current limitation circuitry for the pulse-by-pulse protection is shown in Figure 6. The output power PDMOS transistor is split into two parallel PDMOS transistors. The smallest one includes a resistor in series, RSENSE. The current is sensed through RSENSE and, if it reaches the threshold, the mirror becomes unbalanced and the PDMOS is switched off until the next falling edge of the internal clock pulse. Due to this reduction of the ON time, the output voltage decreases. As the minimum switch-on time necessary to sense the current in order to avoid a false overcurrent signal is too short to obtain a sufficiently low duty cycle at 500 kHz (see Section 8.5 on page 32), the output current in strong overcurrent or short-circuit conditions may not be properly limited. For this reason, the switching frequency is also reduced, therefore keeping the inductor current under its maximum threshold. The frequency shifter (Figure 4) functions based on the feedback voltage. As the feedback voltage decreases (due to the reduced duty cycle), the switching frequency decreases also. 14/47 DocID027135 Rev 1 R5975AD Functional description Figure 6. Current limitation circuitry 9&& 56(16( ,2)) 57+ '5,9(5 $ ,/ $ 287 $$ , , 127 3:0 $0Y 5.5 Error amplifier The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose non inverting input is connected to the internal voltage reference (1.235 V), while the inverting input (FB) is connected to the external divider or directly to the output voltage. The output (COMP) is connected to the external compensation network. The uncompensated error amplifier has the following characteristics: Table 5. Uncompensated error amplifier characteristics Description Values Transconductance 2300 µS Low frequency gain 65 dB Minimum sink/source voltage 1500 µA/300 µA Output voltage swing 0.4 V/3.65 V Input bias current 2.5 µA The error amplifier output is compared to the oscillator sawtooth to perform PWM control. DocID027135 Rev 1 15/47 47 Functional description 5.6 R5975AD PWM comparator and power stage This block compares the oscillator sawtooth and the error amplifier output signals to generate the PWM signal for the driving stage. The power stage is a highly critical block, as it functions to guarantee a correct turn-on and turn-off of the PDMOS. The turn-on of the power element, or more accurately, the rise time of the current at turn-on, is a very critical parameter. At the first approach, it appears that the faster the rise time, the lower the turn-on losses. However, there is a limit introduced by the recovery time of the recirculation diode. In fact, when the current of the power element is equal to the inductor current, the diode turns off and the drain of the power is able to go high. But, during its recovery time, the diode can be considered a high value capacitor and this produces a very high peak current, responsible for numerous problems: Spikes on the device supply voltage that cause oscillations (and therefore noise) due to the board parasites. Turn-on overcurrent leads to a decrease in the efficiency and system reliability. Major EMI problems. Shorter free-wheeling diode life. The fall time of the current during turn-off is also critical, as it produces voltage spikes (due to the parasitic elements of the board) that increase the voltage drop across the PDMOS. In order to minimize these problems, a new driving circuit topology has been used, and the block diagram is shown in Figure 7. The basic idea is to change the current levels used to turn the power switch on and off, based on the PDMOS and the gate clamp status. This circuitry allows the power switch to be turned off and on quickly and addresses the free-wheeling diode recovery time problem. The gate clamp is necessary to ensure that VGS of the internal switch does not go higher than VGSmax. The on/off control block protects against any cross conduction between the supply line and ground. 16/47 DocID027135 Rev 1 R5975AD Functional description Figure 7. Driving circuitry 9&& 9JVPD[ ,2)) &/$03 *$7( 3'026 '5$,1 6723 '5,9( 212)) &21752/ '5$,1 9287 / 2)) (65 ,/2$' 21 & ,21 $0Y 5.7 Inhibit function The inhibit feature is used to put the device in standby mode. With the INH pin higher than 2.2 V, the device is disabled and the power consumption is reduced to less than 100 µA. With the INH pin lower than 0.8 V, the device is enabled. If the INH pin is left floating, an internal pull-up ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also VCC compatible. 5.8 Thermal shutdown The shutdown block generates a signal that turns off the power stage if the temperature of the chip goes higher than a fixed internal threshold (150 ± 10 °C). The sensing element of the chip is very close to the PDMOS area, ensuring fast and accurate temperature detection. A hysteresis of approximately 20 °C keeps the device from turning on and off continuously. DocID027135 Rev 1 17/47 47 Additional features and protection R5975AD 6 Additional features and protection 6.1 Feedback disconnection If the feedback is disconnected, the duty cycle increases towards the maximum allowed value, bringing the output voltage close to the input supply. This condition could destroy the load. To avoid this hazardous condition, the device is turned off if the feedback pin is left floating. 6.2 Output overvoltage protection Overvoltage protection, or OVP, is achieved by using an internal comparator connected to the feedback, which turns off the power stage when the OVP threshold is reached. This threshold is typically 30% higher than the feedback voltage. When a voltage divider is required to adjust the output voltage (Figure 19 on page 34), the OVP intervention is set at: Equation 1 R1 + R2 V OVP = 1.3 -------------------- V FB R2 where R1 is the resistor connected between the output voltage and the feedback pin, and R2 is between the feedback pin and ground. 6.3 Zero load Due to the fact that the internal power is a PDMOS, no bootstrap capacitor is required and so the device works properly even with no load at the output. In this case it works in burst mode, with a random burst repetition rate. 18/47 DocID027135 Rev 1 R5975AD 7 Closing the loop Closing the loop Figure 8. Block diagram of the loop $0Y 7.1 Error amplifier and compensation network The output LC filter of a step-down converter contributes with 180-degree phase shift in the control loop. For this reason a compensation network between the COMP pin and GROUND is added. The simplest compensation network, together with the equivalent circuit of the error amplifier, are shown in Figure 9. RC and CC introduce a pole and a zero in the open loop gain. CP does not significantly affect system stability but it is useful to reduce the noise of the COMP pin. The transfer function of the error amplifier and its compensation network is: Equation 2 A V0 1 + s R c C c A 0 s = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2 s R0 C0 + Cp Rc Cc + s R0 Cc + R0 C0 + Cp + Rc Cc + 1 where Avo = Gm · Ro DocID027135 Rev 1 19/47 47 Closing the loop R5975AD Figure 9. Error amplifier equivalent circuit and compensation network ($ &203 )% 5& &3 && 9 ǻ9 5 & 0ȍ S) *P ǻ9 5& &3 && $0Y The poles of this transfer function are (if Cc >> C0+CP): Equation 3 1 F P1 = ---------------------------------2 R0 Cc Equation 4 1 F P2 = ---------------------------------------------------2 Rc C0 + Cp whereas the zero is defined as: Equation 5 1 F Z1 = --------------------------------2 Rc Cc FP1 is the low frequency which sets the bandwidth, while the zero FZ1 is usually put near to the frequency of the double pole of the LC filter (see below). FP2 is usually at a very high frequency. 20/47 DocID027135 Rev 1 R5975AD 7.2 Closing the loop LC filter The transfer function of the LC filter is given by: Equation 6 R LOAD 1 + ESR C OUT s A LC s = -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2 s L C OUT ESR + R LOAD + s ESR C OUT R LOAD + L + R LOAD where RLOAD is defined as the ratio between VOUT and IOUT. If RLOAD>>ESR, the previous expression of ALC can be simplified and becomes: Equation 7 1 + ESR C OUT s A LC s = ---------------------------------------------------------------------------------------2 L C OUT s + ESR C OUT s + 1 The zero of this transfer function is given by: Equation 8 1 F O = -----------------------------------------------2 ESR C OUT F0 is the zero introduced by the ESR of the output capacitor and it is very important to increase the phase margin of the loop. The poles of the transfer function can be calculated through the following expression: Equation 9 2 – ESR C ESR C – 4 L C OUT OUT OUT F PLC1 2 = ---------------------------------------------------------------------------------------------------------------------------------------2 L C OUT In the denominator of ALC the typical second order system equation can be recognized: Equation 10 2 s + 2 n s + 2 n If the damping coefficient is very close to zero, the roots of the equation become a double root whose value is n. Similarly for ALC the poles can usually be defined as a double pole whose value is: Equation 11 1 F PLC = -----------------------------------------2 L C OUT DocID027135 Rev 1 21/47 47 Closing the loop 7.3 R5975AD PWM comparator The PWM gain is given by the following formula: Equation 12 V cc G PWM s = ------------------------------------------------------------ V OSCMAX – V OSCMIN where VOSCMAX is the maximum value of a sawtooth waveform and VOSCMIN is the minimum value. A voltage feed-forward is implemented to ensure a constant GPWM. This is obtained by generating a sawtooth waveform directly proportional to the input voltage VCC. Equation 13 V OSCMAX – V OSCMIN = K V CC where K is equal to 0.038. Therefore the PWM gain is also equal to: Equation 14 1 G PWM s = ---- = const K This means that even if the input voltage changes, the error amplifier does not change its value to keep the loop in regulation, therefore ensuring a better line regulation and line transient response. In summary, the open loop gain can be expressed as: Equation 15 R2 G s = G PWM s -------------------- A O s A LC s R1 + R2 Example: Considering RC = 4.7 k, CC = 22 nF and CP = 150 pF, the poles and zeroes of A0 are: FP1 = 9 Hz FP2 = 220 kHz FZ1 = 1.6 kHz If L = 10 µH, COUT = 330 µF and ESR = 25 m, the poles and zeroes of ALC become: FPLC = 2.8 kHz FZESR = 20 kHz F0 = 44 kHz Finally R1 = 5.6 k and R2 = 3.3 k. 22/47 DocID027135 Rev 1 R5975AD Closing the loop The gain and phase bode diagrams are plotted respectively in Figure 10 and Figure 11. Figure 10. Module plot Figure 11. Phase plot The cut-off frequency and the phase margin are: Equation 16 F C = 44kHz Phase margin = 54° DocID027135 Rev 1 23/47 47 Application information 8 R5975AD Application information Figure 12. Application schematic 8.1 Component selection Input capacitor The input capacitor must be able to support the maximum input operating voltage and the maximum RMS input current. As step-down converters draw current from the input in pulses, the input current is squared and the height of each pulse is equal to the output current. The input capacitor has to absorb all this switching current, which can be up to the load current divided by two (worst case, with duty cycle of 50%). For this reason, the quality of these capacitors must be very high to minimize the power dissipation generated by the internal ESR, thereby improving system reliability and efficiency. The critical parameter is usually the RMS current rating, which must be higher than the RMS input current. The maximum RMS input current (flowing through the input capacitor) is: Equation 17 2 2 2D D I RMS = I O D – --------------- + ------2 where is the expected system efficiency, D is the duty cycle and IO is the output DC current. This function reaches its maximum value at D = 0.5 and the equivalent RMS current is equal to IO divided by 2 (considering = 1). The maximum and minimum duty cycles are: Equation 18 V OUT + V F D MAX = ------------------------------------V INMIN – V SW 24/47 DocID027135 Rev 1 R5975AD Application information and Equation 19 V OUT + V F D MIN = -------------------------------------V INMAX – V SW where VF is the freewheeling diode forward voltage and VSW the voltage drop across the internal PDMOS. Considering the range DMIN to DMAX, it is possible to determine the max. IRMS going through the input capacitor. Capacitors that can be considered are: Electrolytic capacitors These are widely used due to their low price and their availability in a wide range of RMS current ratings. The only drawback is that, considering ripple current rating requirements, they are physically larger than other capacitors. Ceramic capacitors If available for the required value and voltage rating, these capacitors usually have a higher RMS current rating for a given physical dimension (due to very low ESR). The drawback is the considerably high cost. Tantalum capacitors Very good, small tantalum capacitors with very low ESR are becoming more available. However, they can occasionally burn if subjected to very high current during charge. Therefore, it is better to avoid this type of capacitor for the input filter of the device. They can, however, be subjected to high surge current when connected to the power supply. Table 6. List of ceramic capacitors for the R5975AD Manufacturer Series Capacitor value (µF) Rated voltage (V) TAIYO YUDEN UMK325BJ106MM-T 10 50 MURATA GRM42-2 X7R 475K 50 4.7 50 Output capacitor The output capacitor is very important to meet the output voltage ripple requirement. Using a small inductor value is useful to reduce the size of the choke but it increases the current ripple. So, to reduce the output voltage ripple, a low ESR capacitor is required. Nevertheless, the ESR of the output capacitor introduces a zero in the open loop gain, which helps to increase the phase margin of the system. If the zero goes to a very high frequency, its effect is negligible. For this reason, ceramic capacitors and very low ESR capacitors in general should be avoided. Tantalum and electrolytic capacitors are usually a good choice for this purpose. A list of some tantalum capacitor manufacturers is provided in Table 7. DocID027135 Rev 1 25/47 47 Application information R5975AD Table 7. Output capacitor selection Manufacturer Series Cap value (µF) Rated voltage (V) ESR (m) Sanyo POSCAP(1) TAE 47 to 680 2.5 to 10 25 to 35 TV 68 to 330 4 to 6.3 25 to 40 AVX TPS 100 to 470 4 to 35 50 to 200 KEMET T494/5 100 to 470 4 to 20 30 to 200 Sprague 595D 220 to 390 4 to 20 160 to 650 1. POSCAP capacitors have some characteristics which are very similar to tantalum. Inductor The inductor value is very important as it fixes the ripple current flowing through the output capacitor. The ripple current is usually fixed at 20 - 40% of IOmax, which is 0.6 - 1.2 A with IOmax = 3 A. The approximate inductor value is obtained using the following formula: Equation 20 V IN – V OUT L = ---------------------------------- T ON I where TON is the ON time of the internal switch, given by D · T. For example, with VOUT = 3.3 V, VIN = 12 V and IO = 0.9 A, the inductor value is about 12 µH. The peak current through the inductor is given by: Equation 21 I I PK = I O + ----2 and it can be observed that if the inductor value decreases, the peak current (which must be lower than the current limit of the device) increases. So, when the peak current is fixed, a higher inductor value allows a higher value for the output current. In Table 8, some inductor manufacturers are listed. Table 8. Inductor selection 8.2 Manufacturer Series Inductor value (µH) Saturation current (A) Coilcraft DO3316T 5.6 to 12 3.5 to 4.7 Coilcraft MSS1260T 5.6 to 15 3.5 to 8 Wurth Elektronik WE-PD L 4.7 to 27 3.55 to 6 Layout considerations The layout of switching DC-DC converters is very important to minimize noise and interference. Power-generating portions of the layout are the main cause of noise and so high switching current loop areas should be kept as small as possible and lead lengths as short as possible. High impedance paths (in particular the feedback connections) are susceptible to interference, so they should be as far as possible from the high current paths. A layout 26/47 DocID027135 Rev 1 R5975AD Application information example is provided in Figure 13. The input and output loops are minimized to avoid radiation and high frequency resonance problems. The feedback pin connections to the external divider are very close to the device to avoid pick-up noise. Another important issue is the ground plane of the board. Since the package has an exposed pad, it is very important to connect it to an extended ground plane in order to reduce the thermal resistance junction to ambient. Figure 13. Layout example 8.3 Thermal considerations 8.3.1 Thermal resistance RTHJ-A RTHJ-A is the equivalent static thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this device, the path through the exposed pad is the one conducting the largest amount of heat. The static RTHJ-A measured on the application is about 40 °C/W. The junction temperature of the device is: Equation 22 T J = T A + R thJA P TOT DocID027135 Rev 1 27/47 47 Application information R5975AD The dissipated power of the device is tied to three different sources: Conduction losses due to the not insignificant RDS(on), which are equal to: Equation 23 2 P ON = R DS on I OUT D where D is the duty cycle of the application. Note that the duty cycle is theoretically given by the ratio between VOUT and VIN, but in practice it is substantially higher than this value to compensate for the losses in the overall application. For this reason, the switching losses related to the RDS(on) increases compared to an ideal case. Switching losses due to turning on and off. These are derived using the following equation: Equation 24 T ON + T OFF P SW = V IN I OUT ------------------------------------ F SW = V IN I OUT T SW F SW 2 where TRISE and TFALL represent the switching times of the power element that cause the switching losses when driving an inductive load (see Figure 14). TSW is the equivalent switching time. Figure 14. Switching losses Quiescent current losses. Equation 25 P Q = V IN I Q where IQ is the quiescent current. 28/47 DocID027135 Rev 1 R5975AD Application information Example: – VIN = 12 V – VOUT = 3.3 V – IOUT = 2.5 A RDS(on) has a typical value of 0.25 at 25 °C and increases up to a maximum value of 0.5 at 150 °C. We can consider a value of 0.4 . TSW is approximately 70 ns. IQ has a typical value of 5 mA at VIN = 12 V. The overall losses are: Equation 26 2 P TOT = R DS on I OUT D + V IN I OUT T SW F SW + V IN I Q = 2 = 0.4 2 0.3 + 12 2 70 10 –9 3 500 10 + 12 5 10 –3 1.38W The junction temperature of the device is: Equation 27 T J = T A + R thJA P TOT Equation 28 T J = 60 + 1.38 42 128C 8.3.2 Thermal impedance ZthJ-A(t) The thermal impedance of the system, considered as the device in HSO8 package soldered on the application board, takes on an important rule when the maximum output power is limited by the static thermal performance and not by the electrical performance of the device. Therefore, the embedded power elements could manage an higher current but the system is already taking away the maximum power generated by the internal losses. In case the output power increases, the thermal shutdown is triggered because the junction temperature triggers the designed thermal shutdown threshold. The RTH is a static parameter of the package; it sets the maximum power loss which can be generated from the system given the operation conditions. If we suppose, as an example, TA = 40 C, 140 C is the maximum operating temperature before triggering the thermal shutdown and RTH = 40 C/W, therefore, the maximum power loss achievable with the thermal performance of the system is: Equation 29 T J MAX – T AMB 100 T P MAX DC = ----------- = -------------------------------------- = ---------- = 2.5W 40 R TH R TH Figure 15 represents the estimation of power losses for different output voltages at VIN = 5 V and TAMB = 40 C. The calculations are performed considering the RDS(on) of the power element equal to 0.4 A. DocID027135 Rev 1 29/47 47 Application information R5975AD Figure 15. Power losses estimation (VIN = 5 V, fSW = 500 kHz) The red trace represents the maximum power which can be taken away, as calculated above, whilst the other traces are the total internal losses for different output voltage. The embedded conduction losses are proportional to the duty cycle required for the conversion. Assuming the input voltage constant, the switching losses are proportional to the output current while the quiescent losses can be considered as constant. As a consequence, in Figure 15, the maximum power loss is for VOUT = 3.3 V, where the system can manage a continuous output current up to 2.4 A. The device could deliver a continuous output current up to 2.5 A to the load, however, the maximum power loss of 2.5 W is reached with an output current of 2.4 A, so the maximum output power is derated. Figure 16 plots the power losses for VIN = 12 V and the main output rails. Figure 16. Power losses estimation (VIN = 12 V, fSW = 500 kHz) 30/47 DocID027135 Rev 1 R5975AD Application information At TAMB = 40 C and VIN = 12 V, the device is no more thermally limited (see Figure 16). As a consequence, the calculation of the internal power losses must be done for each specific operating condition given by the final application. In applications where the current to the output is pulsed, the thermal impedance should be considered instead of the thermal resistance. The thermal impedance of the system could be much lower than the thermal resistance, which is a static parameter. As a consequence, the maximum power losses can be higher than 2.5 W if a pulsed output power is requested from the load: Equation 30 T J MAX – T AMB T P MAX t = ----------------- = -------------------------------------Z TH t Z TH t Therefore, depending on the pulse duration and its frequency, the maximum output current can be delivered to the load. The characterization of the thermal impedance is strictly dependent on the layout of the board. In Figure 17 the measurement of the thermal impedance of the demonstration board of the R5975AD is provided. Figure 17. Measurement of the thermal impedance of the demonstration board As can be seen, for example, for load pulses with a duration of 1 second, the actual thermal impedance is lower than 20 C/W. This means that, for short pulses, the device can deliver a higher output current value. DocID027135 Rev 1 31/47 47 Application information 8.4 R5975AD RMS current of the embedded power MOSFET As the R5975AD embeds the high side switch, the internal power dissipation is sometimes the bottleneck for the output current capability (refer to Section 8.3 on page 27 for an estimation of the operating temperature). Nevertheless, as mentioned in Section : Description on page 1, the device can manage a continuous output current of 2.5 A in most of the application conditions. However, the rated maximum RMS current of the power elements is 2 A, where: Equation 31 I RMS HS = I LOAD D and the real duty cycle is D: Equation 32 V OUT + R DS(on) LS + DCR I LOAD D = ---------------------------------------------------------------------------------------------------V IN + R DS(on) LS – R DS(on) HS I LOAD Fixing the limit of 2 A for IRMS HS, the maximum output current can be derived, as illustrated in Figure 18. Figure 18. Maximum continuous output current vs. duty cycle 8.5 Short-circuit protection In overcurrent protection mode, when the peak current reaches the current limit, the device reduces the TON down to its minimum value (approximately 250 nsec) and the switching frequency to approximately one third of its nominal value even when synchronized to an external signal (see Section 5.4 on page 14). In these conditions, the duty cycle is strongly reduced and, in most applications, this is enough to limit the current to ILIM. In any event, in 32/47 DocID027135 Rev 1 R5975AD Application information case of heavy short-circuit at the output (VO = 0 V) and depending on the application conditions (VCC value and parasitic effect of external components), the current peak could reach values higher than ILIM. This can be understood considering the inductor current ripple during the ON and OFF phases: On phase Equation 33 V IN – V out – DCR L + R DS(on) I I L TON = -------------------------------------------------------------------------------------- T ON L Off phase Equation 34 – V D + V out + DCR L I I L TOFF = -------------------------------------------------------------- T OFF L where VD is the voltage drop across the diode, DCRL is the series resistance of the inductor. In short-circuit conditions VOUT is negligible, so during TOFF the voltage across the inductor is very small, as equal to the voltage drop across parasitic components (typically the DCR of the inductor and the VFW of the free-wheeling diode) while during TON, the voltage applied to the inductor is instead maximized as approximately equal to VIN. So, Equation 33 and 34 in overcurrent conditions can be simplified to: Equation 35 V IN – DCR L + R DS(on) I V IN I L TON = ------------------------------------------------------------------ T ON MIN --------- 250ns L L considering TON, which has already been reduced to its minimum. Equation 36 – V D + V out + DCR L I – V D + V out + DCR L I I L TOFF = -------------------------------------------------------------- 3 T SW -------------------------------------------------------------- 12s L L considering that fSW has been already reduced to one third of the nominal. In case a short-circuit at the output is applied, and VIN = 12 V, the inductor current is controlled in most of the applications (see Figure 19). When the application must sustain the short-circuit condition for an extended period, the external components (mainly the inductor and diode) must be selected based on this value. In case the VIN is very high, it could occur that the ripple current during TOFF (Equation 36) does not compensate the current increase during TON (Equation 35). Figure 21 shows an example of a power-up phase with VIN = VIN MAX = 36 V whereIL TON > IL TOFF, so the current escalates and the balance between Equation 35 and Equation 36 occurs at a current slightly higher than the current limit. This must be taken into account in particular to avoid the risk of an abrupt inductor saturation. DocID027135 Rev 1 33/47 47 Application information R5975AD Figure 19. Short-circuit current VIN = 12 V Figure 20. Short-circuit current VIN = 24 V 34/47 DocID027135 Rev 1 R5975AD Application information Figure 21. Short-circuit current VIN = 36 V 8.6 Positive buck-boost regulator The device can be used to implement a step-up/down converter with a positive output voltage. The output voltage is given by: Equation 37 D V OUT = V IN ------------1–D where the ideal duty cycle D for the buck boost converter is: Equation 38 V OUT D = -----------------------------V IN + V OUT However, due to power losses in the passive elements, the real duty cycle is always higher than this. The real value (that can be measured in the application) should be used in the following formulas. The peak current flowing in the embedded switch is: Equation 39 I LOAD I RIPPLE I LOAD V IN D I SW = --------------- + -------------------- = --------------- + ----------- --------1–D 2 1 – D 2 L f SW DocID027135 Rev 1 35/47 47 Application information R5975AD while its average current is equal to: Equation 40 I LOAD I SW = --------------1–D This is due to the fact that the current flowing through the internal power switch is delivered to the output only during the OFF phase. The switch peak current must be lower than the minimum current limit of the overcurrent protection (see Table 4 on page 8 for details) while the average current must be lower than the rated DC current of the device. As a consequence, the maximum output current is: Equation 41 I OUT MAX I SW MAX 1 – D where ISW MAX represents the rated current of the device. The current capability is reduced by the term (1-D) and so, for example, with a duty cycle of 0.5, and considering an average current through the switch of 3 A, the maximum output current deliverable to the load is 1.5 A. Figure 22 below shows the circuit schematic of this topology for a 12 V output voltage and 5 V input. Figure 22. Positive buck-boost regulator 36/47 DocID027135 Rev 1 R5975AD 8.7 Application information Negative buck-boost regulator In Figure 23, the schematic circuit for a standard buck-boost topology is shown. The output voltage is: Equation 42 D V OUT = – V IN ------------1–D where the ideal duty cycle D for the buck-boost converter is: Equation 43 – V OUT D = -----------------------------V IN – V OUT The considerations given in Section 8.7 for the real duty cycle are still valid here. Also Equation 39 to 41 can be used to calculate the maximum output current. So, for example, considering the conversion VIN = 12 V to VOUT = -5 V, ILOAD = 0.5 A: Equation 44 5 D = ---------------- = 0.706 5 + 12 Equation 45 I LOAD 0.5 I SW = --------------- = ------------------------ = 1.7A 1–D 1 – 0.706 An important point to take into account is that the ground pin of the device is connected to the negative output voltage. Therefore, the device is subjected to a voltage equal to VIN - VO, which must be lower than 36 V (the maximum operating input voltage). Figure 23. Negative buck-boost regulator DocID027135 Rev 1 37/47 47 Application information 8.8 R5975AD Floating boost current generator The R5975AD does not support a nominal boost conversion as this topology requires a low side switch, however, a floating boost can be useful in applications where the load can be floating. A typical example is a current generator for LEDs driving, as the LED does not require a connection to the ground. Figure 24. Floating boost topology $0Y Figure 25. 350 mA LED boost current source The device is powered from the output voltage so the maximum voltage drop across the LEDs and resistor sense is 36 V. The output voltage is given by: Equation 46 V IN V OUT = ------------1–D 38/47 DocID027135 Rev 1 R5975AD Application information where the ideal duty cycle D for the boost converter is: Equation 47 V OUT – V IN D = -----------------------------V OUT As for positive and inverting buck-boost (see Section 8.6 on page 35 and Section 8.7 on page 37.) the measured real duty cycle must be used to calculate the switch current level. The peak current flowing in the embedded switch is: Equation 48 I LOAD I RIPPLE I LOAD V IN D I SW = --------------- + -------------------- = --------------- + ----------- --------1–D 2 1 – D 2 L f SW while its average current is equal to: Equation 49 I LOAD I SW = --------------1–D This is due to the fact that the current flowing through the internal power switch is delivered to the output only during the OFF phase. The switch peak current must be lower than the minimum current limit of the overcurrent protection (see Table 4 on page 8 for details) while the average current must be lower than the rated DC current of the device. As a consequence, the maximum output current is: Equation 50 I OUT MAX I SW MAX 1 – D where ISW MAX represents the rated current of the device. Figure 25 shows a tested circuit to implement a boost current source for high current LED driving (350 mA). To implement a boost conversion the LED string must be composed of a minimum device number having a total voltage drop larger than maximum input voltage. The input voltage can be either a DC or AC thanks to the input bridge rectifier. In the case of a DC voltage source D1, D2, D3, D4, C1, and C2 can be removed from the circuit and 1 µF capacitor value can be used for C5. DocID027135 Rev 1 39/47 47 Application information 8.9 R5975AD Synchronization example See Section 5.3 on page 12 for details. Figure 26. Synchronization example 8.10 Compensation network with MLCC at the output The R5975AD standard compensation network (please refer to Figure 12 on page 24 and Section 7 on page 19) introduces a single zero and a low frequency pole in the system bandwidth, so a high ESR output capacitor must be selected to compensate the 180-degree phase shift given by the LC double pole. The selection of the output capacitor must guarantee that the zero introduced by this component is inside the designed system bandwidth and close to the frequency of the double pole introduced by the LC filter. A general rule for the selection of this compound for the system stability is provided in Equation 51. Equation 51 1 f Z ESR = ------------------------------------------------ bandwidth 2 ESR C OUT f LC f Z ESR 10 f LC MLCCs (multiple layer ceramic capacitor) with values in the range of 10 µF - 22 µF and rated voltages in the range of 10 V - 25 V are available today at relatively low cost from many manufacturers. These capacitors have very low ESR values (a few m) and are therefore occasionally used for the output filter in order to reduce the voltage ripple and the overall size of the application. However, the zero given by the output capacitor falls outside the designed bandwidth and so the system becomes unstable with the standard compensation network. Figure 27 shows the type III compensation network stabilizing the system with ceramic capacitors at the output (the optimum components value depends on the application). This configuration introduces two zeroes and a low frequency pole in the designed bandwidth and so guarantees a proper phase margin. 40/47 DocID027135 Rev 1 R5975AD Application information Figure 27. MLCC compensation network circuit 5 10 9729 95() 9&& 6<1& & X) 9 & Q) 9 &203 ,1+ 5 . 9287 / 9287 5 )% (;3$'*1' & 5 &287 ' 4 %& & Q) 6736/8 9,1 & & Q) 5 VPDOOVLJQDO *1' *1' SRZHUSODQH & 5 & $0Y 8.11 External soft-start network At startup, the device can quickly increase the current up to the current limit in order to charge the output capacitor. If soft ramp-up of the output voltage is required, an external soft-start network can be implemented, as shown in Figure 28. The capacitor C is charged up to an external reference through R and the BJT clamps the COMP pin. This clamps the duty cycle, limiting the slew rate of the output voltage. Figure 28. Soft-start network example DocID027135 Rev 1 41/47 47 Typical characteristics 9 R5975AD Typical characteristics Figure 29. Line regulator 9 9 Figure 30. Shutdown current vs. junction temperature & & $0Y $0Y Figure 31. Output voltage vs. junction temperature Figure 32. Junction temperature vs. output current (VIN = 5 V) $0Y Figure 33. Junction temperature vs. output current (VIN = 12 V) Figure 34. Efficiency vs. output current (VIN = 12 V) s/E ϭϮsͲ Ĩ^t ϱϬϬŬ,njͲ >ϭϬђ, ϵϱ͘ϬϬ ϵϬ͘ϬϬ ϴϱ͘ϬϬ sKhdϴs sKhdϱs ϴϬ͘ϬϬ sKhdϯ͘ϯs sKhdϮ͘ϱs ϳϱ͘ϬϬ sKhdϭ͘ϴs ϳϬ͘ϬϬ ϲϱ͘ϬϬ ϲϬ͘ϬϬ Ϭ͘Ϭ Ϭ͘ϱ ϭ͘Ϭ ϭ͘ϱ Ϯ͘Ϭ Ϯ͘ϱ $0Y 42/47 DocID027135 Rev 1 R5975AD Typical characteristics Figure 35. Efficiency vs. output current (VIN = 5 V) s/E ϱsͲ Ĩ^t ϱϬϬŬ,njͲ >ϭϬђ, ϵϬ͘ϬϬ ϴϱ͘ϬϬ ϴϬ͘ϬϬ sKhdϯ͘ϯs sKhdϮ͘ϱs ϳϱ͘ϬϬ sKhdϭ͘ϴs sKhdϭ͘ϱs ϳϬ͘ϬϬ ϲϱ͘ϬϬ ϲϬ͘ϬϬ Ϭ͘Ϭ Ϭ͘ϱ ϭ͘Ϭ ϭ͘ϱ Ϯ͘Ϭ Ϯ͘ϱ $0Y DocID027135 Rev 1 43/47 47 Package information 10 R5975AD Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions, and product status are available at: www.st.com. ECOPACK is an ST trademark. 44/47 DocID027135 Rev 1 R5975AD Package information Figure 36. HSOP8 package outline $ Table 9. HSOP8 package mechanical data Dimensions (mm) Dimensions (inch) Symbol Min. Typ. A Max. Min. Typ. 1.70 Max. 0.0669 A1 0.00 A2 1.25 b 0.31 0.51 0.0122 0.0201 c 0.17 0.25 0.0067 0.0098 D 4.80 4.90 5.00 0.1890 0.1929 0.1969 D1 3 3.1 3.2 0.118 0.122 0.126 E 5.80 6.00 6.20 0.2283 0.2441 E1 3.80 3.90 4.00 0.1496 0.1575 E2 2.31 2.41 2.51 0.091 e 0.10 0.00 0.0039 0.0492 0.095 0.099 1.27 h 0.25 0.50 0.0098 0.0197 L 0.40 1.27 0.0157 0.0500 k ccc 0° (min.), 8° (max.) 0.10 DocID027135 Rev 1 0.0039 45/47 47 Ordering information 11 R5975AD Ordering information Table 10. Ordering information Order codes Package R5975AD Tube HSOP8 R5975ADTR 12 Packaging Tape and reel Revision history Table 11. Document revision history 46/47 Date Revision 03-Nov-2014 1 Changes Initial release DocID027135 Rev 1 R5975AD IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved DocID027135 Rev 1 47/47 47