L5973AD 2A SWITCH STEP DOWN SWITCHING REGULATOR 1 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ GENERAL FEATURES Figure 1. Package 2A INTERNAL SWITCH OPERATING INPUT VOLTAGE FROM 4.4V TO 36V 3.3V / (±2%) REFERENCE VOLTAGE OUTPUT VOLTAGE ADJUSTABLE FROM 1.235V TO 35V LOW DROPOUT OPERATION: 100% DUTY CYCLE 500KHz INTERNALLY FIXED FREQUENCY VOLTAGE FEEDFORWARD ZERO LOAD CURRENT OPERATION INTERNAL CURRENT LIMITING INHIBIT FOR ZERO CURRENT CONSUMPTION SYNCHRONIZATION PROTECTION AGAINST FEEDBACK DISCONNECTION THERMAL SHUTDOWN HSOP8 (Exposed pad) Table 1. Order Codes Part Number HSOP8 L5973ADTR HSOP8 in Tape & Reel switching regulator with a switch current limit of 2A so it is able to deliver more than 1.5A DC current to the load depending on the application conditions. The output voltage can be set from 1.235V to 35V. The high current level is also achieved thanks to an SO8 package with exposed frame, that allows to reduce the Rth(j-amb) down to approximately 40°C/W 1.1 APPLICATIONS: ■ CONSUMER: STB, DVD, TV, VCR,CAR RADIO, LCD MONITORS ■ NETWORKING: XDSL, MODEMS,DC-DC MODULES ■ COMPUTER: PRINTERS, AUDIO/GRAPHIC CARDS, OPTICAL STORAGE, HARD DISK DRIVE ■ INDUSTRIAL: CHARGERS, CAR BATTERY DC-DC CONVERTERS 2 Package L5973AD The device uses an internal P-Channel D-MOS transistor (with a typical of 200mΩ) as switching element to avoid the use of bootstrap capacitor and guarantee high efficiency. An internal oscillator fixes the switching frequency at 500KHz to minimize the size of external components. Having a minimum input voltage of 4.4V only, it is particularly suitable for 5V bus, available in all computer related applications. Pulse by pulse current limit with the internal frequency modulation offers an effective constant current short circuit protection. DESCRIPTION The L5973AD is a step down monolithic power Figure 2. Test and Application Circuit VREF 3.3V VCC VIN = 4.4V to 35V SYNC. C1 10µF 35V CERAMIC COMP C4 22nF C3 220pF 6 8 2 1 OUT D1 STPS340U L5973AD 3 4 INH 7 L1 15µH VOUT=3.3V R1 5.6K 5 FB GND R3 4.7K C2 330µF 10V R2 3.3K D03IN1453 December 2004 Rev. 3 1/14 L5973AD Table 2. Thermal Data Symbol Rth (j-amb) Parameter Thermal Resistance Junction to ambient Max. Value Unit 40 (*) °C/W (*) Package mounted on board Figure 3. Pin Connection (top view) OUT 1 8 VCC SYNC 2 7 GND INH 3 6 VREF COMP 4 5 FB D98IN955 Table 3. Pin Description N. Name 1 OUT 2 SYNC Master/Slave Synchronization. When it is open, a signal synchronous with the turn-off of the internal power is present at the pin. When connected to an external signal at a frequency higher than the internal one, then the device is synchronized by the external signal. Connecting together the SYNC pin of two devices, the one with the higher frequency works as master and the other one, works as slave. 3 INH A logical signal (active high) disables the device. With IHN higher than 2.2V the device is OFF and with INH lower than 0.8V, the device is ON. If INH is not used the pin must be grounded. When it is open, an internal pull-up disables the device. 4 Description Regulator Output. COMP E/A output to be used for frequency compensation. 5 FB Stepdown feedback input. Connecting the output voltage directly to this pin results in an output voltage of 1.235V. An external resistor divider is required for higher output voltages (the typical value for the resistor connected between this pin and ground is 4.7K). 6 VREF Reference voltage of 3.3V. No filter capacitor is needed to stability. 7 GND Ground. 8 VCC Unregulated DC input voltage. Table 4. Absolute Maximum Ratings Symbol Value Unit 40 V Output DC voltage Output peak voltage at t = 0.1µs -1 to 40 -5 to 40 V V Maximum output current int. limit. Input Voltage V1 I1 V4, V5 Analog pins V3 INH V2 SYNC Ptot Power dissipation at Tamb ≤ 60°C Tj Tstg 2/14 Parameter V8 4 V -0.3V to VCC -0.3 to 4 V 2.25 W Operating junction temperature range -40 to 150 °C Storage temperature range -55 to 150 °C L5973AD Table 5. Electrical Characteristics (Tj = 25°C, VCC = 12V, unless otherwise specified.) Symbol VCC RDSON Parameter Operating input voltage range Test Condition Vo = 1.235V; Io = 2A Min. Maximum limiting current fs Switching frequency VCC = 4.4V to 36V Max. 36 V 0.250 0.5 Ω 4.4 Mosfet on Resistance Il Typ. 2 2.3 A 500 Duty cycle 0 Unit KHz 100 % 1.25 V DYNAMIC CHARACTERISTICS (see test circuit ). V5 Voltage feedback 4.4V < VCC < 36V η Efficiency VO = 5V, VCC = 12V 1.220 1.235 90 % DC CHARACTERISTICS Iqop Iq Iqst-by Total Operating Quiescent Current 5 Quiescent current Duty Cycle = 0; VFB = 1.5V Total stand-by quiescent current Vinh > 2.2V 50 7 mA 2.7 mA 100 µA 0.8 V INHIBIT INH Threshold Voltage Device ON Device OFF 2.2 V 3.5 V ERROR AMPLIFIER VOH High level output voltage VFB = 1V VOL Low level output voltage VFB = 1.5V 0.4 V Source output current VCOMP = 1.9V; VFB = 1V 200 300 µA Io sink Sink output current VCOMP = 1.9V; VFB = 1.5V 1 1.5 mA Ib Source bias current DC open loop gain RL = ∞ 50 Transconductance Icomp = -0.1mA to 0.1mA VCOMP = 1.9V Io source gm 2.5 4 µA 57 dB 2.3 mS SYNC FUNCTION High Input Voltage VCC = 4.4V to 36V Low Input Voltage VCC = 4.4V to 36V 2.5 VREF V 0.74 V Slave Sink Current Vsync = 0.74V (1) Vsync = 2.33V 0.11 0.21 0.25 0.45 mA mA Master Output Amplitude Isource = 3mA 2.75 3 V Output Pulse Width no load, Vsync = 1.65V 0.20 0.35 µs 3.234 3.3 3.366 V 3.2 3.3 3.399 V 5 10 mV REFERENCE SECTION Reference Voltage IREF = 0 to 5mA VCC = 4.4V to 36V Line Regulation IREF = 0mA VCC = 4.4V to 36V Load Regulation IREF = 0 to 5mA Short Circuit Current 10 8 15 mV 18 30 mA Note: 1. Guaranteed by design 3/14 L5973AD 3 FUNCTIONAL DESCRIPTION The main internal blocks are shown in Fig. 1, where is reported the device block diagram. They are: ● A voltage regulator that supplies the internal circuitry. From this regulator, a 3.3V reference voltage is externally available. ● A voltage monitor circuit that checks the input and internal voltages. ● A fully integrated sawtooth oscillator whose frequency is500KHz ● Two embedded current limitations circuitries which control the current that flows through the power switch. The Pulse by Pulse Current Limit forces the power switch OFF cycle by cycle if the current reaches an internal threshold, while the Frequency Shifter reduces the switching frequency in order to strongly reduce the duty cycle. ● A transconductance error amplifier. ● A pulse width modulator (PWM) comparator and the relative logic circuitry necessary to drive the internal power. ● An high side driver for the internal P-MOS switch. ● An inhibit block for stand-by operation. ● A circuit to realize the thermal protection function. Figure 4. Block Diagram VCC VOLTAGES MONITOR TRIMMING VREF BUFFER SUPPLY THERMAL SHUTDOWN 1.235V 3.5V INHIBIT INH PEAK TO PEAK CURRENT LIMIT COMP E/A FB + 1.235V SYNC VREF PWM + - D Q Ck DRIVER FREQUENCY SHIFTER OSCILLATOR GND LPDMOS POWER OUT D00IN1125 3.1 POWER SUPPLY & VOLTAGE REFERENCE The internal regulator circuit (shown in Figure 2) consists of a start-up circuit, an internal voltage Preregulator, the Bandgap voltage reference and the Bias block that provides current to all the blocks. The Starter gives the start-up currents to the whole device when the input voltage goes high and the device is enabled (inhibit pin connected to ground). The Preregulator block supplies the Bandgap cell with a preregulated voltage VREG that has a very low supply voltage noise sensitivity. 4/14 L5973AD 3.2 VOLTAGES MONITOR An internal block senses continuously the Vcc, Vref and Vbg. If the voltages go higher than their thresholds, the regulator starts to work. There is also an hysteresis on the VCC (UVLO). Figure 5. Internal Regulator Circuit VCC STARTER PREREGULATOR VREG BANDGAP IC BIAS D00IN1126 VREF 3.3 OSCILLATOR & SYNCHRONIZATOR Figure 6 shows the block diagram of the oscillator circuit. The Clock Generator provides the switching frequency of the device that is internally fixed at 500KHz. The frequency shifter block acts reducing the switching frequency in case of strong overcurrent or short circuit. The clock signal is then used in the internal logic circuitry and is the input of the Ramp Generator and Synchronizator blocks. The Ramp Generator circuit provides the sawtooth signal, used to realize the PWM control and the internal voltage feed forward, while the Synchronizator circuit generates the synchronization signal. Infact the device has a synchronization pin that can works both as Master and Slave. As Master to synchronize external devices to the internal switching frequency. As Slave to synchronize itself by external signal. In particular, connecting together two devices, the one with the lower switching frequency works as Slave and the other one works as Master. To synchronize the device, the SYNC pin has to pass from a low level to a level higher than the synchronization threshold with a duty cycle that can vary approximately from 10% to 90%, depending also on the signal frequency and amplitude. The frequency of the synchronization signal must be at least higher than the internal switching frequency of the device (500KHz). 5/14 L5973AD Figure 6. Oscillator Circuit FREQUENCY SHIFTER CLOCK t Ibias_osc CLOCK GENERATOR RAMP GENERATOR RAMP SYNCHRONIZATOR SYNC D00IN1131 3.4 CURRENT PROTECTION The L5973AD has two current limit protections, pulse by pulse and frequency fold back. The schematic of the current limitation circuitry for the pulse by pulse protection is shown in figure 7. The output power PDMOS transistor is split in two parallel PDMOS. The smallest one has a resistor in series, RSENSE. The current is sensed through Rsense and if reaches the threshold, the mirror is unbalanced and the PDMOS is switched off until the next falling edge of the internal clock pulse. Due to this reduction of the ON time, the output voltage decreases. Since the minimum switch ON time (necessary to avoid false overcurrent signal) is not enough to obtain a sufficiently low duty cycle at 500KHz, the output current, in strong overcurrent or short circuit conditions, could increase again. For this reason the switching frequency is also reduced, so keeping the inductor current under its maximum threshold. The Frequency Shifter (see fig. 6) depends on the feedback voltage. As the feedback voltage decreases (due to the reduced duty cycle), the switching frequency decreases too. Figure 7. Current Limitation Circuitry VCC RSENSE IOFF RTH DRIVER A1 IL A2 OUT A1/A2=95 I I NOT PWM D00IN1134 6/14 L5973AD 3.5 ERROR AMPLIFIER The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose non inverting input is connected to the internal voltage reference (1.235V), while the inverting input (FB) is connected to the external divider or directly to the output voltage. The output (COMP) is connected to the external compensation network. The uncompensated error amplifier has the following characteristics: Transconductance 2300µS Low frequency gain 65dB Minimum sink/source voltage Output voltage swing Input bias current 1500µA/300µA 0.4V/3.65V 2.5µA The error amplifier output is compared with the oscillator sawtooth to perform PWM control. 3.6 PWM COMPARATOR AND POWER STAGE This block compares the oscillator sawtooth and the error amplifier output signals generating the PWM signal for the driving stage. The power stage is a very critical block cause it has to guarantee a correct turn on and turn off of the PDMOS. The turn on of the power element, or better, the rise time of the current at turn on, is a very critical parameter to compromise. At a first approach, it looks like the faster it is the rise time, the lower are the turn on losses. But there is a limit introduced by the recovery time of the recirculation diode. In fact when the current of the power element equals the inductor current, the diode turns off and the drain of the power is free to go high. But during its recovery time, the diode can be considered as an high value capacitor and this produces a very high peak current, responsible of many problems: Spikes on the device supply voltage that cause oscillations (and thus noise) due to the board parasitics. Turn on overcurrent causing a decrease of the efficiency and system reliability. Big EMI problems. Shorter freewheeling diode life. The fall time of the current during the turn off is also critical. In fact it produces voltage spikes (due to the parasitics elements of the board) that increase the voltage drop across the PDMOS. In order to minimize all these problems, a new topology of driving circuit has been used and its block diagram is shown in fig. 8. The basic idea is to change the current levels used to turn on and off the power switch, according with the PDMOS status and with the gate clamp status. This circuitry allow to turn off and on quickly the power switch and to manage the above question related to the freewheeling diode recovery time problem. The gate clamp is necessary to avoid that Vgs of the internal switch goes higher than Vgsmax. The ON/OFF Control block avoids any cross conduction between the supply line and ground. 7/14 L5973AD Figure 8. Driving Circuitry VCC Vgsmax IOFF CLAMP GATE PDMOS DRAIN STOP DRIVE ON/OFF CONTROL DRAIN VOUT L OFF ESR ILOAD ON C ION D00IN1133 3.7 INHIBIT FUNCTION The inhibit feature allows to put in stand-by mode the device. With INH pin higher than 2.2V the device is disabled and the power consumption is reduced to less than 100µA. With INH pin lower than 0.8V, the device is enabled. If the INH pin is left floating, an internal pull up ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also Vcc compatible. 3.8 THERMAL SHUTDOWN The shutdown block generates a signal that turns off the power stage if the temperature of the chip goes higher than a fixed internal threshold (150°C). The sensing element of the chip is very close to the PDMOS area, so ensuring an accurate and fast temperature detection. An hysteresis of approximately 20°C avoids that the devices turns on and off continuously 4 ADDITIONAL FEATURES AND PROTECTIONS 4.1 FEEDBACK DISCONNECTION In case of feedback disconnection, the duty cycle increases versus the maximum allowed value, bringing the output voltage close to the input supply. This condition could destroy the load. To avoid this dangerous condition, the device is turned off if the feedback pin remains floating. 4.2 OUTPUT OVERVOLTAGE PROTECTION The overvoltage protection, OVP, is realized by using an internal comparator, which input is connected to the feedback, that turns off the power stage when the OVP threshold is reached. This threshold is typically 30% higher than the feedback voltage. When a voltage divider is requested for adjusting the output voltage (see test application circuit), the OVP intervention will be set at: R 1 + R2 V OVP = 1.3 ⋅ -------------------- ⋅ V FB R2 Where R1 is the resistor connected between the output voltage and the feedback pin, while R2 is between the feedback pin and ground. 8/14 L5973AD 4.3 ZERO LOAD Due to the fact that the internal power is a PDMOS, no boostrap capacitor is required and so, the device works properly also with no load at the output. In this condition it works in burst mode, with random repetition rate of the burst. 4.4 APPLICATION CIRCUIT In figure 9 is shown the demo board application circuit, where the input supply voltage, Vcc, can range from 4.4V to 25V due to the rated voltage of the input capacitor and the output voltage is adjustable from 1.235V to Vcc. Figure 9. Demo board Application Circuit VREF 3.3V VCC VIN = 4.4V to 25V SYNC. C1 10µF 25V CERAMIC COMP C4 22nF C3 220pF 6 8 3 4 INH 7 VOUT=3.3V D1 STPS2L25U L5973AD 2 L1 15µH OUT 1 R1 5.6K 5 FB GND C2 330µF 6.3V R2 3.3K R3 4.7K D03IN1454 Table 6. Component List Reference Part Number C1 Description Manufacturer 10µF, 25V TOKIN C2 POSCAP 6TPB330M 330µF, 6.3V Sanyo C3 C1206C221J5GAC 220pF, 5%, 50V KEMET C4 C1206C223K5RAC 22nF, 10%, 50V KEMET R1 5.6K, 1%, 0.1W 0603 Neohm R2 3.3K, 1%, 0.1W 0603 Neohm R3 4.7K, 1%, 0.1W 0603 Neohm D1 STPS2L25U 2A, 25V ST L1 DO3316P-153 15µH, 3A COILCRAFT 9/14 L5973AD Figure 10. Junction Temperature vs. Output Current Figure 12. Efficiency vs. Output Current Tj(°C) 95 100 80 Vin=5V Tamb=25°C 70 Vo=1.8V 60 90 Vo=2.5V Vo=3.3V Efficiency (%) 90 50 40 Vout=3.3V 85 80 Vout=2.5V 75 Vin=5V Vout=1.8V 70 30 20 0.2 65 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0.2 2 0.4 0.6 0.8 1 Io(A) Figure 11. Junction Temperature vs Output Current Vo=3.3V Vin=12V Tamb=25°C Efficiency (%) Vo=2.5V 60 50 1.8 2 Vout=5V 85 Vout=3.3V 80 75 30 Vout=2.5V Vin=12V 70 40 65 20 0.4 0.6 0.8 1 1.2 Io(A) 10/14 90 Vo=5V 70 0.2 1.6 95 100 80 1.4 Figure 13. Efficiency vs. Output Current Tj(C) 110 90 1.2 Io(A) 1.4 1.6 1.8 2 0.2 0.4 0.6 0.8 1 1.2 Io(A) 1.4 1.6 1.8 2 L5973AD 5 APPLICATION IDEAS Figure 14. Positive Buck-Boost regulator 8 COMP C1 10uF 10V Ceramic C3 22nF R3 4.7k D2 STPS2L25U VOUT=12V/0.6A 1 D1 STPS2L25U L5973AD 4 2 C2 220pF L1 15uH OUT Vcc VIN=5V SYNC 6 VREF 5 3 7 24k FB INH GND C4 100uF 16V M1 STN4NE03L 2.7k 3.3V Figure 15. Buck-Boost regulator VREF 3.3V 6 VCC VIN = 5V 8 COMP C2 10µF 25V CERAMIC 3 4 C4 22nF C3 220pF L5973AD 2 SYNC. C1 10µF 10V CERAMIC 1 5 7 L1 15µH OUT D1 STPS2L25U 2.7K VOUT=-12V/ 0.6A FB INH C5 100µF 16V GND 24K R3 4.7K D03IN1455 Figure 16. Dual output voltage with auxiliary winding N1/N2=2 VREF 3.3V VCC VIN = 5V SYNC. C1 10µF 25V CERAMIC COMP C3 22nF C2 220pF 6 8 2 1 3 INH 7 VOUT1=5V/ 50mA OUT VOUT=3.3V/ 0.5A Lp 22µH L5973AD 4 D2 1N4148 D1 STPS25L25U 5 FB GND R3 4.7K C4 100µF 10V C5 47µF 10V D03IN1456 Refer to L5973AD application note (AN1723) to have additional information, details, and more application ideas. L5973AD belongs to L597x family. Related part numbers are: ● L5970D: 1.5A (Isw), 250KHz Step Down DC-DC Converter in SO8 ● L5972D: 2A (Isw), 250KHz Step Down DC-DC Converter in SO8 ● L5973D: 2.5A (Isw), 250KHz Step Down DC-DC Converter in HSOP8 In case higher current is needed, the nearest DC-DC Converter family is L497x. 11/14 L5973AD 6 PACKAGE INFORMATION Figure 17. HSOP8 (Exposed Pad) Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 1.350 1.750 0.531 0.069 A1 0.100 0.250 0.004 0.010 A2 1.100 1.650 0.043 0.065 B 0.330 0.510 0.013 0.020 C 0.190 0.250 0.07 0.010 D 4.800 5.000 0.189 0.197 E 3.800 4.000 0.150 0.157 1.270 e 0.05 H 5.800 6.200 0.228 0.244 h 0.250 0.500 0.010 0.020 L 0.400 1.270 0.016 0.05 k ddd OUTLINE AND MECHANICAL DATA 0˚ (min), 8˚ (max) 0.100 0.010 (1) Dimension D does not include mold flash, protusions or gate burrs shall not exeed 0.15mm (both side). HSOP8 (Exposed Pad) Exposed Pad: D1 = 3.1mm E1 = 2.41mm 7195016 12/14 L5973AD 7 REVISION HISTORY Table 7. Revision History Date Revision Description of Changes December 2003 1 First Issue January 2004 2 Migration to EDOCS dms December 2004 3 Added D1 & E1 dimensions in HSOP8 package information. 13/14 L5973AD Information furnished is believed to be accurate and reliable. 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