L5959 Multifunction voltage regulator for car radio Features ■ Four outputs – 8.5V @ 200mA (V8P5) – 8/10V @ 1000mA selectable 10V or 8V (V810) – 3.3V @ 100mA permanent (VSTBY) – 3.3V @ 800mA (VREGSW) ■ Two protected high side driver (HSD1, HSD2) ■ Reset function ■ Battery voltage (under/over) warning output ■ Load dump protection Description ■ Independent thermal shutdown on all regulators and HSDs ■ Overcurrent limitation The L5959 contains a four voltage regulator and two protected HSDs. HSDs are protected against loss of ground and loss of battery. ■ Storage CAP output (STCAP) The IC includes a monitoring circuit for detection. ■ Small CAP required by stability of regulators ■ All pins ESD protected The IC features a very low quiescent current in stand-by and independent thermal shutdown. Table 1. August 2007 Multiwatt15 Device summary Order code Package Packing L5959 Multiwatt15 Tube Rev 2 1/19 www.st.com 1 Contents L5959 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 3 Pins connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 L5959 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Enable logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3/19 List of figures L5959 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. 4/19 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Timing diagram of regulators and HSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 STCAP and RST diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VBATVW (over/under voltage warning) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Independent thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 RST glitch rejection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Enable on/off delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Multiwatt15 (vertical) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . 17 L5959 Block diagram 1 Block diagram Figure 1. Block diagram VBAT HSD1 Two HSD HSD2 STCAP V810 V810 VSTBY VSTBY VREGSW VREGSW V8P5 V8P5 VBATVW RST LOAD-DUMP RESET EN0 EN1 ENABLE RSTDLY EN2 Table 2. Enable logic V810 V810 (8V) (10V) Off Off EN2 EN1 EN0 VREGSW V8P5 HSD1 HSD2 0 0 0 Off Off Off 0 0 1 On On On Off On On 0 1 0 On Off Off Off Off Off 0 1 1 On On On Off Off On 1 0 0 On On On Off Off Off 1 0 1 On On On Off On Off 1 1 0 On On On On Off Off 1 1 1 On On On On Off On Off 5/19 Pins description L5959 2 Pins description 2.1 Pins connection Figure 2. Pins connection (top view) 15 VBAT 14 V810 13 V8P5 12 VREGSW 11 STCAP 10 VSTBY 9 HSD1 8 GND 7 VBATVW 6 EN2 5 EN1 4 EN0 3 RSTDLY 2 RST 1 HSD2 D06AU1637 6/19 L5959 Electrical specification 3 Electrical specification 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit VBATDC DC operating supply voltage 30 V VBATTR Transient supply voltage 50 V Output current IO RESR internally limited Output capacitor series eq. resistance (MAX.) 0.5 Ω Top Operating temperature range -40 to 105 °C Tstg Storage temperature -55 to 150 °C Tj Junction temperature -55 to 150 °C Pd Power dissipation Tcase = 85°C 43 W 3.2 Thermal data Table 4. Thermal data Symbol Rth j-case Parameter Multiwatt Unit 1.8 °C/W Thermal resistance junction to case max. 3.3 Electrical characteristics Table 5. Electrical characteristics (VS = 14.4V; Tamb = 25°C; unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit INPUT SUPPLIES Vbat Input supply Operating 9 18 V Input supply voltage 2 Operating 6 18 V Battery voltage Reverse polarity non operating VSTCAP Input supply voltage 2 Reverse polarity non operating Iq Total quiescent current EN0 = EN1 = EN2 = 0 V; VBAT = 14 V; IVSTBY = 100 µA VBAT Over-voltage shutdown Verify all outputs except VSTBY disabled and VBATVW* asserted low (VBAT Rising) VSTCAP Vbat VOV VHYSOV Hysteresis of over-voltage shutdown 55 75 µA 24 27 30 V 200 750 1500 mV 7/19 Electrical specification Table 5. Symbol VUV VHYSUV L5959 Electrical characteristics (continued) (VS = 14.4V; Tamb = 25°C; unless otherwise specified) Parameter VBAT Under-voltage warning Test Condition Verify VBATVW* asserted low (VBAT Falling) Hysteresis of under-voltage warning Min. Typ. Max. Unit 7 7.4 7.8 V 70 300 500 mV 3.14 3.3 3.46 V VSTBY Vo (VSTBY) Output voltage of VSTBY ΔV Line regulation VBAT = 6 to 18V; I = 100mA -10 0 +10 mV ΔVi Load regulation IVSTBY = 0.5 to 100 mA -40 -5 +10 mV Over shoot IVSTBY = 100 to 0.5 mA, Co=1µF 2.5 6 % Vover PSRR VN Vdrop Im TSEN Supply voltage ripple rejection IVSTBY = 50 mA; fo = 20 to 1 kHz; VBAT = 14 Vdc, 1.0 Vac(pp) 50 70 dB IVSTBY = 50 mA; fo = 20 to 20 kHz; VBAT = 14 Vdc, 1.0 Vac(pp) 45 55 dB Output noise Weighted filter fo = 20 Hz to 20 kHz IVSTBY = 5 mA Drop out voltage 85 200 µV IVSTBY = 100mA(1) 2.6 V Drop out voltage IVSTBY = 5 mA 2.3 V Current limit Rshort = 0Ω 150 300 mA VSTBY thermal shutdown IVSTBY = 500 µA; Increase Ta until VSTBY disabled 150 190 °C 3.46 V 200 VREGSW Vo Output voltage 3.3V (VREGSW) VTRK 8/19 VREGSW output tracking voltage on VSTBY 3.14 3.3 IVSTBY = 50 mA IVREGSW = 0.5 to 800 mA Measure VSTBY – VREGSW -40 40 mV IVSTBY = 0.5 mA to 100 mA IVREGSW = 0.5 to 800 mA Measure VSTBY – VREGSW -50 50 mV ΔV Line regulation Vin1 = 9 to 18V; I = 800mA -40 10 40 mV ΔVi Load regulation IVREGSW = 1 to 800mA -50 -15 10 mV L5959 Table 5. Symbol PSRR Electrical specification Electrical characteristics (continued) (VS = 14.4V; Tamb = 25°C; unless otherwise specified) Parameter Supply voltage ripple rejection Test Condition Min. Typ. IVREGSW = 400 mA; fo = 20 to 1 kHz; VBAT = 14 Vdc, 1.0 Vac(pp) 50 70 dB IVREGSW = 400 mA; fo = 20 to 20 kHz; VBAT = 14 Vdc, 1.0 Vac(pp) 45 55 dB Output noise Weighted filter fo = 20 Hz to 20 kHz IVREGSW = 5 mA Vdrop Drop out voltage Vdrop VN Unit 200 µV IVREGSW = 800 mA 2.6 V Drop out voltage IVREGSW = 5 mA 2.3 V Current limit Rshort = 0Ω 2.5 A VREGSW thermal shutdown IVREGSW = 500 µA; Increase Ta until VREGSW disabled 150 190 °C tdon Turn-on delay; Ivregsw= 5mA 10 45 110 µs tdoff Turn-off delay, IVREGSW = 700 mA 45 110 µs 8.3 8.5 8.7 V Im TSEN 85 Max. 1 1.5 V8P5 (VBAT=9.5V to 18 V) Vo (V8P5) Output voltage 8.5V ΔV Line regulation VBAT = 9.5 to 18V; I = 200mA -50 3.0 50 mV ΔVi Load regulation IV8P5 = 1 to 200mA -30 3 20 mV IV8P5 = 100 mA; fo = 20 to 1 kHz; VBAT = 14 Vdc, 1.0 Vac(pp) 50 60 dB IV8P5 = 100 mA; fo = 20 to 20 kHz; VBAT = 14 Vdc, 1.0 Vac(pp) 35 40 dB PSRR Supply voltage ripple rejection Output noise Weighted filter fo = 20 Hz to 20 kHz IV8P5 = 5 mA 190 450 µV Drop out voltage IV8P5 = 200mA 0.45 0.9 V Current limit Rshort = 0Ω 275 450 700 mA V8P5 thermal shutdown IV8P5 = 500 µA; Increase Ta until V8P5 disabled 150 190 °C tdon Turn-on delay; IV8P5 = 5mA 10 45 110 µs tdoff Turn-off delay, IV8P5 = 200 mA 45 110 µs 7.6 8.0 8.4 V -50 3 50 mV VN Vdrop Im TSEN V810 (8V) (VBAT = 9.2V to 18 V) Vo (V810) ΔV Output voltage 8.0V Line regulation VBAT = 9.2 to 18V; I = 1000mA 9/19 Electrical specification Table 5. Electrical characteristics (continued) (VS = 14.4V; Tamb = 25°C; unless otherwise specified) Symbol ΔVi PSRR L5959 Parameter Load regulation Supply voltage ripple rejection Test Condition Min. Typ. Max. Unit -100 -20 10 mV IV810 = 500 mA; fo = 20 to 1 kHz; VBAT = 14 Vdc, 1.0 Vac(pp) 50 55 dB IV810 = 500 mA; fo = 20 to 20 kHz; VBAT = 14 Vdc, 1.0 Vac(pp) 30 35 dB IV810 = 0.5 to 1000 mA Output noise Weighted filter fo = 20 Hz to 20 kHz IV810 = 5 mA 175 450 µV Drop out voltage IV810(8V) = 1000mA (1) 0.45 0.9 V Current limit Rshort = 0Ω 1.5 2.3 3.5 A V810(8v) thermal shutdown IV810(8V) = 500 µA; Increase Ta until V810(8V) disabled 150 190 °C tdon Turn-on delay; IV810(8V) = 5mA 10 45 110 µs tdoff Turn-off delay, IV810(8V) = 1000 mA 45 110 µs 9.5 10.0 10.5 V VN Vdrop Im TSEN V810 (10V) (VBAT=11.2V to 18 V) Vo (V810) Output Voltage 10.0V ΔV Line regulation VBAT = 11.2 to 18V; I = 1000mA -50 2.5 50 mV ΔVi Load regulation IV810 = 0.5 to 1000 mA -100 -25 10 mV IV810 = 500 mA; fo = 20 to 1 kHz; VBAT = 14 Vdc, 1.0 Vac(pp) 50 55 dB IV810 = 500 mA; fo = 20 to 20 kHz; VBAT = 14 Vdc, 1.0 Vac(pp) 30 35 dB PSRR Supply voltage ripple rejection Output noise Weighted filter fo = 20 Hz to 20 kHz IV810 = 5 mA 175 450 µV Drop out voltage IV810(10V) = 1000mA (1) 0.4 0.9 V Current limit Rshort = 0Ω 1.5 2.3 3.5 A V810(10V) thermal shutdown IV810(8V) = 500 µA; Increase Ta until V810(10V) disabled 150 190 °C tdon Turn-on delay; IV810(8V) = 5mA 10 45 110 µs tdoff Turn-off delay, IV810(8V) = 1000 mA 45 110 µs Idc = 100mA 0.25 0.6 V Idc = 200mA, t=5S 0.50 1.2 V VN Vdrop Im TSEN HIGH SIDE DRIVER1 VdropSW 10/19 Drop voltage HDS1 L5959 Table 5. Electrical specification Electrical characteristics (continued) (VS = 14.4V; Tamb = 25°C; unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit 240 300 400 mA 2 10 mA 0.15 10 mA 190 °C 50 110 µs ISTG HSD1 short to ground current VHSD1=0V ISTB HSD1 short to VBAT current VHSD1=VBAT ΔIQ(VBAT) HSD1 bias current change IHSD1 = 0 to 100 mA; Measure change in VBAT current HSD1 thermal shutdown IHSD1 = 500 µA; Increase Ta until HSD1 disabled 150 tdon Turn-on delay; IHSD1= 10mA 10 tdoff Turn-off delay, IHSD1= 100 mA 70 110 µs Rise time 10% to 90%, IHSD1 = 10mA 35 75 µs Idc = 300mA 0.2 0.6 V Idc =450mA, t=5S 0.3 1.2 V 0.75 1 A TSEN tr HIGH SIDE DRIVER2 VdropSW Drop voltage HDS2 ISTG HSD2 short to ground current VHSD2=0V ISTB HSD2 short to VBAT current VHSD2=VBAT 3.5 10 mA ΔIQ(VBAT) HSD2 bias current change IHSD2 = 0 to 300 mA; Measure change in VBAT current 0.15 10 mA HSD2 thermal shutdown IHSD2 = 500 µA; Increase Ta until HSD2 disabled 150 190 °C tdon Turn-on delay; IHSD2= 10mA 10 45 110 µs tdoff Turn-off delay, IHSD2= 300 mA 70 110 µs Rise time 10% to 90%, IHSD2 = 10mA 30 75 µs TSEN tr 0.55 RST (open collector output) VTH VSTBY reset threshold VHYS Hysteresis of reset on rising VSTBY trRST Rise time tfRST Fall time Force VSTBY low until RST* asserted 10 RSTDLY current V 50 200 mV 10% to 90%, RRST= 47 kΩ, CRST = 50 pF 20 30 µs 90% to 10%,RRST= 47 kΩ, CRST = 50 pF 300 1000 ns 2.5 2.75 3.5 V 6 8.5 12 µA VIH_RSTDLY RSTDLY input voltage threshold Verify RST is de asserted ISRC 0.93 * 0.95 * 0.97 * VSTBY VSTBY VSTBY RSTDLY = 0 VDC 11/19 Electrical specification Table 5. Symbol tpor Tglitch L5959 Electrical characteristics (continued) (VS = 14.4V; Tamb = 25°C; unless otherwise specified) Parameter RST POR delay time Test Condition CRSTDLY = 0.1 µF Glitch rejection filter time Min. Typ. Max. Unit 20 30 50 ms 5 12.5 20 µs 2.0 V ENABLE INPUT (VREGSW, V8P5, V810, HSD1, HSD2) VIH Threshold recognized as high level VIL Threshold recognized as low level 0.8 VHYSEN Hysteresis of enable 0.15 0.35 ILKGEN Enable input pull-down current 10 30 VEN = VIL(mIN) to VSTBY V V 50 µA 1. Drop condition means that the supply voltage drop down to 100 mV from the regulated output and the regulator is sourcing its maximal load. 2. Stability Request is design info, not tested. 12/19 L5959 4 Timing diagrams Timing diagrams Figure 3. Timing diagram of regulators and HSD DUMP 27.4V VBAT 26.6V 18V 9V 3.3V VSTBY EN 000 111 000 111 3.3V VREGSW 8.5V V8P5 8V V810 18V HSD1 9V 10V HSD2 9V AC00329 Figure 4. STCAP and RST diagram 14V VBAT STCAP VSTBY 3.3V 3.18V 3.13V 3.3V 2.7V t RSTDLY RST t AC00330 t 13/19 Timing diagrams Figure 5. L5959 VBATVW (over/under voltage warning) DUMP 26.6V 27.4V 7.4V 18V VBAT 14.4V 7.67V 3.3V VBATVW 3.3V VSTBY 3.3V VREGSW 8.5V V8P5 8V V810 27.4V HSD1 18V 14.4V 27.4V HSD2 18V 14.4V EN 000 111 AC00331 14/19 L5959 Timing diagrams Figure 6. Independent thermal shutdown 14.4V VBAT THERMAL SHUTDOWN (of VSTBY) ON T = 160 VSTBY THERMAL SHUTDOWN (of VREGSW) ON T = 160 VREGSW THERMAL SHUTDOWN (of V8P5) ON T = 160 V8P5 THERMAL SHUTDOWN (of V810) ON T = 160 V810 THERMAL SHUTDOWN (of HSD1) ON T = 160 HSD1 THERMAL SHUTDOWN (of HSD2) ON T = 160 HSD2 EN 111 AC00332 15/19 Timing diagrams Figure 7. L5959 RST glitch rejection < Tglitch VSTBY > Tglitch 3.3V 5V Tglitch RST TPOR AC00333 Figure 8. Enable on/off delay Tdon Tdoff 90% VERGSW (V810, V8PS, HSDI, HSD2) 10% EN 000 111 000 AC00334 16/19 L5959 5 Package information Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 9. Multiwatt15 (vertical) mechanical data and package dimensions DIM. mm MIN. TYP. inch MAX. MIN. TYP. A5 MAX. 0.197 B 2.65 C 1.6 D OUTLINE AND MECHANICAL DATA 0.104 0.063 1 0.039 E 0.49 0.55 0.019 F 0.66 0.75 0.026 0.022 G 1.02 1.27 1.52 0.040 0.050 0.060 G1 17.53 17.78 18.03 0.690 0.700 0.710 H1 19.6 0.030 0.772 H2 20.2 0.795 L 21.9 22.2 22.5 0.862 0.874 0.886 L1 21.7 22.1 22.5 0.854 0.87 0.886 L2 17.65 18.1 0.695 L3 17.25 17.5 17.75 0.679 0.689 L4 10.3 10.7 10.9 0.406 0.421 L7 2.65 2.9 0.104 0.713 0.699 0.429 0.114 M 4.25 4.55 4.85 0.167 0.179 0.191 M1 4.73 5.08 5.43 0.186 0.200 0.214 S 1.9 2.6 0.075 0.102 S1 1.9 2.6 0.075 0.102 Dia1 3.65 3.85 0.144 0.152 Multiwatt15 (Vertical) 0016036 J 17/19 Revision history 6 L5959 Revision history Table 6. 18/19 Document revision history Date Revision Changes 26-Jun-2006 1 Initial release. 28-Aug-2007 2 Minor changes, improved quality of the drawings. L5959 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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