L5955 Multiple multifunction voltage regulator for car radio Features ■ 2 stand-by regulators: 3.3V (125mA) 1.5V (300mA) ■ 6 regulators: 10V (40mA) 8.5V (200mA) 3.3V (850mA) 8/10V (1A) 5/3.3/1.8V (200mA) 1.8/2.5V(200mA) Flexiwatt27 ■ All regulators are low dropout outputs ■ The different outputs voltage are controlled by I2C Bus. ■ Reg3 on/off controlled by enable ■ Reg1, Reg2, Reg4, Reg5, Reg6 on/off controlled by I2CBus. ■ 3 high side drivers: 2A (HSD1) 0.45A (HSD2 & HSD3) ■ No external charge pump capacitors are required ■ Stand-by mode controlled by EN pin for I2C Bus and Reg1, Reg2, Reg3, Reg4, Reg5, Reg6, HSD1, HSD2, HSD3 ■ LVW function externally selectable ■ Individual thermal shutdown Table 1. August 2007 ■ Independent current limiting ■ Short circuit protection ■ Load dump protection and overvoltage shutdown Description The L5955 is an integration of three high side drivers, six regulators and two stand-by regulators with RESET function developed to provide the power to a complete audio system. The outputs of the IC are controlled by I2C bus and Enable pin. The device is equipped with sequencing and slew rate controls for the st-by regulators. Device summary Order code Package Packing L5955 Flexiwatt27 Tube Rev 1 1/17 www.st.com 17 Contents L5955 Contents 1 Block and pin connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Write mode: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Chip address byte: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 Data byte: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/17 L5955 Block and pin connection diagrams Block diagram VBAT1 Vstby2 Figure 1. Vstby1 1 Block and pin connection diagrams ST-By REG 3.3V VSTBY1 BG1 BANDGAP CSLEW VBAT3_1/2 MRST* MRSTDLY SDA SCL EN LVWIN LVW* HSD1 HSD2 HSD3 Standby Regulators POR Logic VBG CSLEW And BG2 Sequencing VSTBY2 St_By REG 1.5V 10V Linear Regulator REG1 8.5V Linear Regulator REG2 3.3V Linear Regulator REG3 8V Linear Regulator 10V selectable REG4 5V Linear Regulator 1.8-3.3V selectable REG5 1.8V Linear Regulator 2.5V selectable REG6 Vstby1 Vstby2 I2C Interface Low Voltage Warning VBAT1 VBG High Side Driver High Side Driver High Side Driver GND VBAT2 Figure 2. PGND Pin connection (top view) 27 TAB2 26 REG4 25 VBAT3_2 24 REG3 23 VBAT2 22 REG6 21 SCL 20 STBY2 19 VBAT1 18 STBY1 17 MRST 16 REG5 15 MRSTDLY 14 GND 13 LVW 12 REG1 11 LVW_IN 10 REG2 9 Cslew 8 HSD3 7 EN 6 HSD2 5 VBAT3_1 4 HSD1 3 PGND 2 SDA 1 TAB1 D04AU1548 3/17 Electrical specification L5955 2 Electrical specification 2.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol VS1, VS2, VS3_1, VS3_2 VS1, VS2, VS3_1, VS3_2 VS1,2,3_1,3 Parameter DC operating supply voltage Transient supply over voltages, rise time = 10ms delay time = 115ms Overvoltage shutdown Value Unit 0.6 to 26.5 V 34 V 27 V _2,ovs 2.2 Vin Input voltages (EN, SDA, SCL, LVW, MRST, MRSTDLY, CSLEW) -0.6 to 5.5 V Vout Output control voltage -0.6 to 18 V Top Operating temperature range -40 to 85 °C Tstg Storage temperature range -40 to 150 °C Value Unit 1 °C/W Thermal data Table 3. Symbol Rth j-case 4/17 Thermal data Parameter Thermal resistance junction to case L5955 Electrical specification 2.3 Electrical characteristics Table 4. Electrical characteristics (Refer to the application circuit, Vbat =Vbat1+Vbat2+Vbat3= 14V, IST-BY1 = 0.5mA, IST-BY2 = 0.5mA, IREG1 = IREG2 = IREG3 = IREG4 = IREG5 = IREG6 = 5mA, RHSD1 = RHSD2 = RHSD3 = 16Ω) Symbol Parameter Test condition Stand-by quiescent current Vbat = 14V, EN = 0. IST-BY1 = Istby2=100uA, IQ(Vbat)=Ivbat1+Ivabt2+Ivbat3 Maximum quiescent current Vbat = 14V, EN=VSTBY1 Istby1=125mA Istby2=300mA IREG1 = 40mA IREG2 = 200mA, IREG3 = 850mA IREG4 = 1A, IREG5 = 250mA IREG6 = 200mA, IHSD1 = 2A IHSD2,3 = 450mA IEN Enable input current Vbat = 14V; 5V<Enable ≥ 0V; VIL VIH Enable threshold voltage Vbat = 14V; IqST-BY Iq Min. Typ. Max. Unit 170 μA 100 mA 10 2 μA 0.8 V V VST-BY1 = 0.5V to VTH (ST-BY1) VST-BY2 = 0.5V to VTH (ST-BY2) Rising 0 0 0.4 0.4 V VH MRST VST-BY1 = VTH (ST-BY1) to 0.5V VST-BY2 = VTH (ST-BY2) to 0.5V Falling 0 0 0.4 0.4 V VTH MRST MRST output voltage threshold Force VST-BY1 & VST-BY2 Low until MRST asserted VST-BY2 · 0.93 VST-BY1 · 0.93 VST-BY2 · 0.97 VST-BY1 · 0.97 VL MRST MRST output voltage td MRST MRST delay time tpor MRST Power on reset delay time tf MRST MRST fall time ISCR MRST MRSTDLY current ILKG MRSTDLY leakage current see Figure 4 CMRSTLY = 220nF see Figure 4 MRSTDLY = 0 20 6 MRSTDLY = 5V V μs 13 RRST = 47kΩ, CRST = 50pF see Figure 4 V ms 1 μs 12 μA 6 μA MRSTDLY Vsat MRSTDLY saturation voltage IMRSTDLY =0.5mA 0 0.4 V VTH LVWIN input voltage threshold 1.25 V (nominal) 1.22 1.28 V ILKG lvwin input leakage current 2 µA VOH LVW output voltage VSTBY1 V MRSTDLY IOH=-100µA VSTBY1 -0.2 5/17 Electrical specification Table 4. L5955 Electrical characteristics (continued) (Refer to the application circuit, Vbat =Vbat1+Vbat2+Vbat3= 14V, IST-BY1 = 0.5mA, IST-BY2 = 0.5mA, IREG1 = IREG2 = IREG3 = IREG4 = IREG5 = IREG6 = 5mA, RHSD1 = RHSD2 = RHSD3 = 16Ω) Symbol Parameter Test condition Min. Typ. Unit 0.2 V VOL LVW output voltage IOL = 100µA TS Thermal shutdown for HSDS, REGS, VST-BY1, VST-BY2 HSDS, REGS, VST-BY1, VST-BY2 min. load. Increase Tamb until HSDS, REGS, VST-BY1,2 Disabled 170 °C HSDS, REGS, VST-BY1, VST-BY2 Thermal shutdown hysteresis for min. load. HSDS, REGS, VST-BY1, VST-BY2 Decrease Tamb until HSDS, REGS, VST-BY1,2 Disabled 10 °C TS HYS Io CSLEW output current ton ST-BY1, ST-BY2. minimum turn on time 0 Max. 7 CSLEW=7nF; see Figure 5 1.6 3.14 14 µA ms 3.3V/125mA VST-BY1 VST-BY1 Output voltage IST-BY1 = 125mA ΔVline Line regulation ΔVload Iq1 VDROPOUT Ilim1 ΔVlead ΔVlag SVR1 3.46 V 7V ≤ VBAT ≤ 18V (Measure ΔVreg1 across VBAT range) 10 mV Load regulation 0.5mA ≤ IST-BY1 ≤ 125mA (Measure ΔVreg1 across VBAT range) 50 mV Δ Quiescent current (measure ΔIBAT) IST-BY1 = 2mA, VBAT = 14V, IST-BY1 = 125mA, VBAT = 14V 150 10 μA mA 2.6 1.2 V V 350 mA force VST-BY2 Low; Measure VST-BY1 - VST-BY2 2.5 V force VST-BY1 Low; Measure VST-BY1 - VST-BY2 0.25 V Dropout voltage (measure VBAT - IST-BY1 = 125mA VST-BY1 when VST-BY1drops 0.1V) IST-BY1 = 5mA Current limit VST-BY1 absolute differential output voltage Supply voltage rejection ST-BY1 160 fo = 120-10kHz, VBAT = 14V with 1.0Vp-p AC, fo = 20-20kHz, VBAT = 14V with 1.0Vp-p AC 50 dB 45 dB 1.5V/300mA VST-BY2 VST-BY2 Output voltage IST-BY2 = 300mA ΔVline Line regulation 7V ≤ VBAT ≤ 18V (measure Δ VST-BY2 across VBAT range) 6/17 1.425 1.575 V 50 mV L5955 Table 4. Symbol ΔVload VDROPOUT Ilim2 SVR3 Electrical specification Electrical characteristics (continued) (Refer to the application circuit, Vbat =Vbat1+Vbat2+Vbat3= 14V, IST-BY1 = 0.5mA, IST-BY2 = 0.5mA, IREG1 = IREG2 = IREG3 = IREG4 = IREG5 = IREG6 = 5mA, RHSD1 = RHSD2 = RHSD3 = 16Ω) Parameter Test condition Min. Typ. Max. Unit Load regulation 0.5mA ≤ IST-BY2 ≤ 300mA 100 mV Dropout voltage (measure VBAT VST-BY2 when VST-BY2 drops0.1V) IST-BY2 = 300mA IST-BY2 = 5mA 4.1 3 V V 700 mA Current limit Supply voltage rejection ST-BY2 360 fo = 120-10kHz, VBAT = 14V with 1.0Vp-p AC, fo = 20-20kHz, VBAT = 14V with 1.0Vp-p AC 50 dB 45 dB 10V/40mA REG1 output VREG1 Output voltage IREG1 = 40mA ΔVline Line regulation ΔVload Load regulation VDROPOUT 9.50 10 10.5 V 11.4V ≤ VBAT≤ 18V (measure Δ VREG1 across VBAT range) 55 mV 5mA ≤ IREG1 ≤ 40mA 55 mV 1200 300 mV mV 200 mA Dropout voltage (measure VBAT - IREG1 = 40mA VREG1 when VREG1 drops 0.1V) IREG1 = 5mA Ilim1 Current limit 60 SVR Supply voltage rejection (guaranteed by characterizationtest at 1kHz with 50dB Limit) 50 dB 8.5V/200mA REG2 output VREG2 Output voltage IREG2 = 200mA ΔVline Line regulation ΔVload Load regulation VDROPOUT 8.3 8.7 V 9.6V ≤ VBAT ≤ 18V (measure Δ VREG2 across VBAT range) 50 mV 5mA ≤ IREG2 ≤ 200mA 50 mV 1100 600 mV mV 525 mA Dropout voltage (measure VBAT - IREG2 = 200mA VREG2 when VREG2 drops 0.1V) IREG2 = 5mA Ilim2 Current limit 225 SVR Ripple rejection (guaranteed By characterization-test at 1kHz with 50dB limit) 50 8.5 dB 3.3V/850mA REG3 output VREG3 Output voltage IREG3 = 850mA ΔVline Line regulation ΔVload Load regulation VDROPOUT 3.46 V 7V ≤ VBAT ≤ 18V (Measure Δ VREG2 Across VBAT range) 40 mV 5mA ≤ IREG3 ≤ 850mA 100 mV 3.46 2.86 V V Dropout voltage (measure VBAT - IREG3 = 850mA VREG3 when VREG3 drops 0.1V) IREG3 = 5mA 3.14 7/17 Electrical specification Table 4. Symbol L5955 Electrical characteristics (continued) (Refer to the application circuit, Vbat =Vbat1+Vbat2+Vbat3= 14V, IST-BY1 = 0.5mA, IST-BY2 = 0.5mA, IREG1 = IREG2 = IREG3 = IREG4 = IREG5 = IREG6 = 5mA, RHSD1 = RHSD2 = RHSD3 = 16Ω) Parameter Ilim4 Current limit SVR Ripple rejection (guaranteed by characterization-test at 1kHz with 50dB Limit) Test condition Min. 1.25 Typ. Max. Unit 2.5 A 50 dB 8V/10V/1A REG4 output VREG4 ΔVline ΔVload VDROPOUT Output voltage IREG4 = 1A Line regulation 11.4V ≤ VBAT ≤ 18V, For VREG4=10V 9.3V<VBAT<18V For VREG4=8V (measure Δ VREG4 across VBAT range) Load regulation 7.6 9.50 5mA ≤ IREG4≤ 1A Dropout voltage (measure VBAT - IREG4 = 1A VREG4 when VREG4 drops 0.1V) IREG4 = 5mA Ilim4 Current limit 1.5 SVR Ripple rejection (guaranteed By characterization-test at 1kHz with 50dB Limit) 50 8.4 10.5 V V 50 mV 50 mV 150 mV 1.100 600 mV mV 3 A dB 1.8-3.3-5V/250mA REG5 output VREG5 1.71 3.14 4.75 1.89 3.46 5.25 V V V Line regulation 7V ≤ VBAT ≤ 18V for VREG5=1.8V, 3.3V 9V<VBAT>18V for VREG5=5V (measure Δ VREG5 across VBAT range) 40 mV Load regulation 5mA ≤ IREG5 ≤ 250mA 100 mV 4.89 4.29 3.46 2.86 1.85 1.25 V V V V V V 700 mA Output voltage IREG5 = 250mA ΔVline ΔVload IREG5 = 250mA @ VREG5=1.8V IREG5 = 5mA @ VREG5=1.8V Dropout voltage (measure VBAT - IREG5 = 250mA @ VREG5=3.3V VDROPOUT VREG5 when VREG5 drops 0.1V) IREG5 = 5mA @ VREG5=3.3V IREG5 = 250mA @ VREG5=5V IREG5 = 5mA @ VREG5=5V Ilim5 Current limit 300 SVR Ripple rejection (guaranteed by characterization-test at 1kHz with 50dB limit) 50 8/17 dB L5955 Table 4. Electrical specification Electrical characteristics (continued) (Refer to the application circuit, Vbat =Vbat1+Vbat2+Vbat3= 14V, IST-BY1 = 0.5mA, IST-BY2 = 0.5mA, IREG1 = IREG2 = IREG3 = IREG4 = IREG5 = IREG6 = 5mA, RHSD1 = RHSD2 = RHSD3 = 16Ω) Symbol Parameter Test condition Min. Typ. Max. Unit 1.89 2.62 V V 1.8-2.5V/200mA REG6 output 1.71 2.38 VREG6 Output voltage IREG6 = 200mA ΔVline Line regulation 7V ≤ VBAT ≤ 18V (measure Δ VREG6 across VBAT range) 40 mV ΔVload Load regulation 5mA ≤ IREG6 ≤ 200mA 50 mV 4.89 4.29 4.22 3.62 V V V V 600 mA IREG6 = 200mA @ VREG6=1.8V Dropout voltage (measure VBAT - IREG6 = 5mA @ VREG6=1.8V VDROPOUT VREG6 when VREG6 drops 0.1V) IREG6 = 200mA @ VREG6=2.5V IREG6 = 5mA @ VREG6=2.5V Ilim6 Current limit 240 SVR Ripple rejection (guaranteed by characterization-test at 1kHz with 50dB limit) 50 dB 2A HSD1 Vsat Ileak1 Ilim IHSD1 = 1A continuous time operation IHSD1=2A t=5seconds 0.6 V 1.2 V Output leakage current All Driver Outputs are Off 50 μA Current limiting RHSD1 = 0.5Ω 4 A IHSD2,3 = 300mA continuous time operation IHSD2,3=450mA t=5 seconds 0.6 V 1.2 V Output leakage current All driver outputs are Off 50 μA Current limiting RHSD2,3 = 0.5Ω 1 A 1.5 V Output saturation voltage 2.4 0.45A HSD2 & HSD3 Vsat Ileak2,3 Ilim Output saturation voltage 0.550 I2 Characteristics for C VIL LOW level input voltage VIH HIGH level input voltage VHYS Input hysteresis VOL1 3 V 0.2 V Sink current = 3mA 0.4 V Sink current = 6mA 0.6 V 0.5V ≤ VI ≤ 4.5V 10 μA 400 kHz LOW level output VOL1 I1 fSCL Input current SCL clock frequency 9/17 Functional description 3 L5955 Functional description The three high side drivers are one 2A output (HSD1) and two 450mA outputs (HSD2 & 3). The six regulator outputs are 10V at 40mA (REG1), 8.5V at 200mA (REG2), 3.3V at 850mA (REG3), 8/10V at 1A (REG4), 1.8V/3.3V/5V at 250mA (REG5) and 1.8V/2.5V at 200mA (REG6). The two stand-by regulators are 3.3V at 125mA (ST-BY1) and 1.5V at 300mA (ST-BY2). ST-BY1 and ST-BY2 are equipped with Reset function. ST-BY1 and ST-BY2 share one Reset output (MRST). A slew rate limiter and a sequencing function control ST-BY1 and ST-BY2 turn on/off. The 8.5V regulator output (REG2) has a tighter tolerance output than the other regulator outputs. The 8.5V output is a ±2.5% (5% total range) output over temperature to improve performance and reduce cost on the 8.5V output. The other outputs are ±5% over temperature. The two STAND-BY regulators are switched on/off from battery line. The REG3 is switched on/off by Enable pin which also activate the I2C BUS. The other Regulators and HSD’s are turned on/off independently by I2C BUS, which also controls the regulators' output voltages. With ENABLE pin set to 0 the total current sunk from the battery line minimized. Figure 3. Reset and power-on reset schematic 5V rst* RST* 1μA RESET DRIVER LATCH S Q IVCP(1FAULT) VSTBY1 VSTBY2 MA FF1 5.6pF R Q 5V 1μA FOR MRST REG6 FOR RSTR6 CRSTDLY PULL DOWN LATCH S Q MB 0.22 μF FF2 R Q WINDOW COMPARATOR D02AU1401 10/17 L5955 Functional description Figure 4. Reset timing <td MRST <td RSTR6 td MRST td RSTR6 tpor VREG6 VSTBY1 or 2 tf MRST tf RSTR6 MRST* RSTR6 Figure 5. D02AU1402 SLEW function V VSTBY1 3.3V VSTBY2 1.5V t tON Sequencing function V VBAT t V STBY1 dVlead dVlead Figure 6. STBY2 dVIag dVIag D02AU1404 t 11/17 Functional description Figure 7. L5955 Definition of timing on the I2C Bus. SDA tBUP tF tR tLOW tHD;STA tSP SCL tHD;DAT P tHD;DAT tHIGH tSU;DAT S tSU;STA tSU;STO Sr Figure 8. P D99AU1007 Typical application circuit VBAT1 VBAT2 19 18 23 20 VBAT3_1 5 VBAT3_2 25 12 10 EN 7 SCL 21 26 SDA 2 16 Cslew MRSTDLY T.B.D. 24 22 9 15 4 0.1μF 8 x 10μF STBY2 REG1 REG2 REG3 REG4 REG5 REG6 HSD1 6 HSD2 8 HSD3 13 LVW STBY1 10K VBAT1 STBY1 MRST 17 T.B.D. 14 GND 3 PGND 1 TAB1 27 TAB2 11 LVW_IN T.B.D. 3.1 Write mode: Chip address S Data byte 0 MSB LSB A MSB A .. .. LSB S = START condition - SDA goes from high to low while SCL is high A = Acknowledge - the device being written to, pulls down on data line (SDA) during the acknowledge clock pulse. P = STOP condition - SDA goes from low to high while SCL is high. 12/17 P L5955 Functional description 3.2 Chip address byte: Table 5. Chip address byte Chip address Read/write A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 1 0 0 0 0 b4 b3 3.3 Data byte: Table 6. Data byte b7 b6 b5 b2 b1 b0 HSD3EN HSD2EN0 HSD1EN0 REG2EN REG1EN Data byte 0 REG6 SET REG5 SET2 REG5 SET1 REG4 SET Data byte 1 REG6EN REG5EN REG4EN Default mode is 0000 0000 which corresponds to all outputs being off, low power mode. Table 7. Data byte 0 description Name REG6 SET REG5 SET1 REG5 SET2 REG4 SET HSD3EN HSD2EN HSD1EN Description State Definition bit 0 1.8V b7 1 2.5V b7 00 5.0V b5, b6 01 3.3V b5, b6 10 1.8V b5, b6 11 x b5, b6 0 8.0V b4 1 10.0V b4 0 Off b2 1 On b2 0 Off b1 1 On b1 0 Off b0 1 On b0 REG6 output voltage configuration REG5 output voltage configuration REG4 output voltage configuration HSD3 Enable HSD2 Enable HSD1 Enable 13/17 Functional description Table 8. Data byte 1 description Name REG6 EN REG5 EN REG4 EN REG2 EN REG1 EN 14/17 L5955 Description State Definition 0 Off 1 On 0 Off 1 On 0 Off 1 On 0 Off 1 On 0 Off 1 On REG6 Enable bit b6 REG5 Enable b5 REG4 Enable b4 REG2 Enable b2 REG1 Enable b1 L5955 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 9. Flexiwatt27 (vertical) mechanical data and package dimensions DIM. MIN. 4.45 1.80 A B C D E F (1) G G1 H (2) H1 H2 H3 L (2) L1 L2 (2) L3 L4 L5 M M1 N O R R1 R2 R3 R4 V V1 V2 V3 0.75 0.37 0.80 25.75 28.90 22.07 18.57 15.50 7.70 3.70 3.60 mm TYP. 4.50 1.90 1.40 0.90 0.39 1.00 26.00 29.23 17.00 12.80 0.80 22.47 18.97 15.70 7.85 5 3.5 4.00 4.00 2.20 2 1.70 0.5 0.3 1.25 0.50 MAX. 4.65 2.00 MIN. 0.175 0.070 1.05 0.42 0.57 1.20 26.25 29.30 0.029 0.014 0.031 1.014 1.139 22.87 19.37 15.90 7.95 0.869 0.731 0.610 0.303 4.30 4.40 0.145 0.142 inch TYP. 0.177 0.074 0.055 0.035 0.015 0.040 1.023 1.150 0.669 0.503 0.031 0.884 0.747 0.618 0.309 0.197 0.138 0.157 0.157 0.086 0.079 0.067 0.02 0.12 0.049 0.019 MAX. 0.183 0.079 OUTLINE AND MECHANICAL DATA 0.041 0.016 0.022 0.047 1.033 1.153 0.904 0.762 0.626 0.313 0.169 0.173 5˚ (Typ.) 3˚ (Typ.) 20˚ (Typ.) 45˚ (Typ.) Flexiwatt27 (vertical) (1): dam-bar protusion not included (2): molding protusion included V C B V H H1 V3 A H2 O H3 R3 L4 R4 V1 R2 L2 N R L3 4 Package information L L1 V1 V2 R2 D R1 L5 Pin 1 R1 R1 E G G1 F FLEX27ME M M1 7139011 15/17 Revision history 5 L5955 Revision history Table 9. 16/17 Document revision history Date Revision 29-Aug-2007 1 Changes Initial release. L5955 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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