L6731D Adjustable step-down controller with synchronous rectification dedicated to DDR memory Features ■ Input voltage range from 1.8 V to 14 V ■ Supply voltage range from 4.5 V to 14 V ■ Adjustable output voltage down to 0.6 V with ±0.8 % Accuracy over line voltage and temperature (0 °C~125 °C) ■ Fixed frequency voltage mode control ■ TON lower than 100 ns ■ 0 % to 100 % duty cycle ■ VDDR input sense ■ Regulates VTT and VTTREF within 1 % of VDDQ ■ Soft-start and inhibit ■ High current embedded drivers Applications ■ Predictive anti-cross conduction control ■ ■ Programmable high-side and low-side RDS(on) sense over-current-protection High performance / high density DC-DC modules ■ Low voltage distributed DC-DC HTSSOP16 (exposed pad) ■ Selectable switching frequency 250 kHz / 500 kHz ■ niPoL converters ■ DDR memory supply ■ Power good output ■ DDR termination supply ■ Sink/source capability for DDR memory and termination supply ■ Graphic cards ■ Over-voltage protection ■ Thermal shutdown ■ Package: HTSSOP16 Table 1. June 2008 Device summary Order codes Package Packaging L6731D HTSSOP16 Tube L6731DTR HTSSOP16 Tape and reel Rev 3 1/23 www.st.com 23 Contents L6731D Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Pin connections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2 Internal LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 Bypassing the LDO to avoid the voltage drop with low Vcc . . . . . . . . . . . 11 5.4 Internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.6 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.7 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.8 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.9 HICCUP mode during an OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.10 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.11 Minimum on-time (TON, MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/23 L6731D 1 Summary description Summary description The controller is an integrated circuit realized in BCD5 (BiCMOS-DMOS, version 5) fabrication that provides complete control logic and protection for high performance step-down DC-DC and niPoL converters. It is designed to drive N-channel MOSFETs in a synchronous rectified buck topology. The output voltage of the converter can be precisely regulated down to 600 mV with a maximum tolerance of ±0.8 %. If an external reference is used, it will be transferred divided by 2 to the N.I. input of the error-amplifier, in accordance to the DDR memory specifications. An internal resistor divider and a voltage buffer allow to achieve an accuracy of 1 % on both Vtt and Vttref. It's possible to provide an external reference from 0V to 2.5 V in order to meet the specification for DDRI and DDRII. The input voltage can range from 1.8 V to 14 V, while the supply voltage can range from 4.5 V to 14 V. High peak current gate drivers provide for fast switching to the external power section, and the output current can be in excess of 20 A. The PWM duty cycle can range from 0 % to 100 % with a minimum on-time (TON, MIN) lower than 100 ns making possible conversions with very low duty cycle at high switching frequency. The device provides voltage-mode control that includes a selectable frequency oscillator (250 kHz or 500 kHz). The error amplifier features a 10 MHz gain-bandwidth-product and 5 V/µs slew-rate that permits to realize high converter bandwidth for fast transient response. The device monitors the current by using the RDS(on) of both the high-side and low-side MOSFET(s), eliminating the need for a current sensing resistor and guaranteeing an effective over-current-protection in all the application conditions. When necessary, two different current limit protections can be externally set through two external resistors. During the soft-start phase a constant current protection is provided while after the soft-start the device enters in hiccup mode in case of over-current. The converter can always sink current. Other features are power good, not latched over-voltage-protection, feed-back disconnection and thermal shutdown. The HTSSOP16 package allows the realization of really compact DC/DC converters. 3/23 Summary description 1.1 L6731D Functional description Figure 1. Block diagram VCC=4.5V to14V Vin=1.8V to14V OCL OCH VCCDR VCC BOOT LDO SS/INH Monitor Protection and Ref HGATE OSC DDR-IN - Vo PHASE L6731D R LGATE + - R PGOOD + - 0.6V + PWM PGND E/A + - SGND VFB VTTREF 4/23 COMP L6731D Electrical data 2 Electrical data 2.1 Maximum rating Table 2. Absolute maximum ratings Symbol Parameter VCC Value Unit -0.3 to 18 V 0 to 6 V 0 to VBOOT - VPHASE V BOOT -0.3 to 24 V PHASE -1 to 18 VCC to GND and PGND, OCH, PGOOD VBOOT VPHASE Boot voltage VHGATE VPHASE VBOOT VPHASE -3 PHASE spike, transient < 50 ns (FSW = 500 kHz) SS, FB, DDR-IN, SYNC, VTTREF, OCL, LGATE, COMP, VCCDR OCH pin PGOOD pin Other pins 2.2 Maximum withstanding voltage range test condition: CDF-AEC-Q100-002 “human body model” acceptance criteria: “normal performance” V +24 -0.3 to 6 V ±1500 ±1000 V ±2000 Thermal data Table 3. Symbol Thermal data Value Unit 50 °C/W Storage temperature range -40 to 150 °C TJ Junction operating temperature range -40 to 125 °C TA Ambient operating temperature range -40 to +85 °C RthJA(1) TSTG Description Thermal resistance junction to ambient 1. Package mounted on demonstration board 5/23 Pin connections and functions 3 L6731D Pin connections and functions Figure 2. Pin connection (top view) PGOOD 1 16 VCC VTTREF 2 15 VCCDR SGND 3 14 LGATE FB 4 13 PGND COMP 5 12 BOOT SS/INH 6 11 HGATE DDR-IN 7 10 PHASE OCL 8 9 OCH HTSSOP16 Table 4. Pin n. Name Function 1 PGOOD This pin is an open collector output and it is pulled low if the output voltage is not within the specified thresholds (90 %-110 %). If not used it may be left floating. Pull-up this pin to VCCDR with a 10 K resistor to obtain a logical signal. 2 VTTREF This pin is connected to the output of an internal buffer that provides ½ of DDR-IN. This pin can be connected to the VTTREF input of the DDR memory itself. Filter to GND with 10 nF capacitor. 3 SGND All the internal references are referred to this pin. This pin is connected to the error amplifier inverting input. Connect it to VOUT through the compensation network. This pin is also used to sense the output voltage in order to manage the over voltage conditions and the PGood signal. 4 FB 5 COMP This pin is connected to the error amplifier output and is used to compensate the voltage control feedback loop. SS/INH The soft-start time is programmed connecting an external capacitor from this pin and GND. The internal current generator forces a current of 10 µA through the capacitor. When the voltage at this pin is lower than 0.5 V the device is disabled. DDR-IN By setting the voltage at this pin is possible to select the internal/external reference and the switching frequency: VEAREF 0-80 % of VCCDR -> External reference/FSW = 250 kHz VEAREF = 80 %-95 % of VCCDR -> VREF = 0.6 V/FSW = 500 kHz VEAREF = 95 %-100 % of VCCDR -> VREF = 0.6 V/FSW = 250 kHz An internal clamp limits the maximum VEAREF at 2.5 V (typ.). The device captures the analog value present at this pin at the start-up when VCC meets the UVLO threshold. 6 7 6/23 Pin functions L6731D Pin connections and functions Table 4. Pin n. Pin functions (continued) Name Function A resistor connected from this pin to ground sets the valley- current-limit. The valley current is sensed through the low-side MOSFET(s). The internal current generator sources a current of 100 µA (IOCL) from this pin to ground through the external resistor (ROCL). The over-current threshold is given by the following equation: 8 OCL I OCL • R OCL I VALLEY = --------------------------------2 • R DSONLS Connecting a capacitor from this pin to GND helps in reducing the noise injected from VCC to the device, but can be a low impedance path for the high-frequency noise related to the GND. Connect a capacitor only to a "clean" GND. 9 OCH A resistor connected from this pin and the high-side MOSFET(s) drain sets the peak-current-limit. The peak current is sensed through the high-side MOSFET(s). The internal 100 µA current generator (IOCH) sinks a current from the drain through the external resistor (ROCH). The over-current threshold is given by the following equation: I OCH • R OCH I PEAK = --------------------------------R DSONHS 10 PHASE This pin is connected to the source of the high-side MOSFET(s) and provides the return path for the high-side driver. This pin monitors the drop across both the upper and lower MOSFET(s) for the current limit together with OCH and OCL. 11 HGATE This pin is connected to the high-side MOSFET(s) gate. 12 BOOT Through this pin is supplied the high-side driver. Connect a capacitor from this pin to the PHASE pin and a diode from VCCDR to this pin (cathode versus BOOT). 13 PGND This pin has to be connected closely to the low-side MOSFET(s) source in order to reduce the noise injection into the device. 14 LGATE This pin is connected to the low-side MOSFET(s) gate. 15 VCCDR 5 V internally regulated voltage. It is used to supply the internal drivers. Filter it to ground with at least 1 µF ceramic cap. 16 VCC Supply voltage pin. The operative supply voltage range is from 4.5 V to 14 V. 7/23 Electrical characteristics 4 L6731D Electrical characteristics VCC = 12 V, TA = 25 °C unless otherwise specified. Table 5. Electrical characteristics Symbol Parameter Test condition VCC stand by current Min Typ Max Unit OSC = open; SS to GND 4.5 6.5 VCC quiescent current OSC= open; HG = open, LG = open, PH = open 8.5 10 Turn-ON VCC threshold VOCH = 1.7 V 4.0 4.2 4.4 V Turn-OFF VCC threshold VOCH = 1.7 V 3.6 3.8 4.0 V VCC supply current ICC mA Power-ON VCC VIN OK Turn-ON VOCH threshold 1.1 1.25 1.47 V VIN OK Turn-OFF VOCH threshold 0.9 1.05 1.27 V 4.5 5 5.5 V SS = 2 V 7 10 13 SS = 0 to 0.5 V 20 30 45 237 250 263 kHz 450 500 550 kHz VCCDR regulation VCCDR voltage VCC =5.5 V to 14 V IDR = 1 mA to 100 mA Soft-start and inhibit ISS Soft start current µA Oscillator fOSC ∆VOSC Accuracy Ramp amplitude 2.1 V Output voltage VFB Output voltage VDIS = 0 to Vth 0.597 0.6 0.603 V 70 100 150 kΩ 0.290 0.5 µA Error amplifier REAREF IFB EAREF input resistance Vs. GND I.I. bias current VFΒ = 0 V Ext Ref Clamp 2.3 V Error amplifier offset Vref = 0.6 V GV Open loop voltage gain Guaranteed by design 100 dB GBWP Gain-bandwidth product Guaranteed by design 10 MHz Slew-rate COMP = 10 pF Guaranteed by design 5 V/µs VOFFSET SR 8/23 -5 +5 mV L6731D Electrical characteristics Table 5. Electrical characteristics (continued) Symbol Parameter Test condition Min Typ Max Unit Gate drivers RHGATE_ON High side source resistance RHGATE_OFF High side sink resistance Low side source resistance RLGATE_ON RLGATE_OFF Low side sink resistance VBOOT - VPHASE = 5 V 1.7 Ω VBOOT - VPHASE = 5 V 1.12 Ω VCCDR = 5 V 1.15 Ω VCCDR = 5 V 0.6 Ω Protections IOCH OCH current source IOCL OCL current source 90 100 110 µΑ 90 100 110 µΑ VFB rising VEAREF = 0.6 V 120 % VFB falling VEAREF = 0.6 V 117 % Under voltage threshold (V FB / V EAREF ) V FB falling 80 % Upper threshold (V FB / V EAREF ) V FB rising 108 110 112 % Lower threshold (V FB / V EAREF ) V FB falling 88 90 92 % PGOOD voltage low I PGOOD = -5 mA Over voltage trip (VFB / VEAREF) OVP VOCH = 1.7 V B B B B B B Power good B B VBPGOODB Table 6. B B B B B B B B B B B 0.5 B V Thermal characteristics (VCC = 12 V) Symbol Parameter Test condition Min Typ Max TJ = 0 °C~ 125 °C 0.596 0.6 0.605 TJ = -40 °C~ 125 °C 0.593 0.6 0.605 Unit Output voltage VFB Output voltage V 9/23 Device description L6731D 5 Device description 5.1 Oscillator The switching frequency can be fixed to two values: 250 kHz or 500 kHz by setting the proper voltage at the EAREF pin (see Table 4. Pins function and section 4.3 Internal and external reference). 5.2 Internal LDO An internal LDO supplies the internal circuitry of the device. The input of this stage is the VCC pin and the output (5 V) is the VCCDR pin (Figure 3.). Figure 3. 4.5V÷14V LDO block diagram LDO The LDO can be by-passed, providing directly a 5 V voltage to VCCDR. In this case VCC and VCCDR pins must be shorted together as shown in Figure 4. VCCDR pin must be filtered with at least 1 µF capacitor to sustain the internal LDO during the recharge of the bootstrap capacitor. VCCDR also represents a voltage reference for PGOOD pin (see Table 4. Pins Function). 10/23 L6731D 5.3 Device description Bypassing the LDO to avoid the voltage drop with low Vcc If VCC ≈ 5 V the internal LDO works in dropout with an output resistance of about 1 Ω. The maximum LDO output current is about 100 mA and so the output voltage drop is 100 mV, to avoid this the LDO can be bypassed. Figure 4. 5.4 Bypassing the LDO Internal and external references It is possible to set the internal/external reference and the switching frequency by setting the proper voltage at the DDR-IN pin. The maximum value of the external reference is 2.5 V (typ.): ● VEAREF from 0 % to 80 % of VCCDR -> External reference/FSW = 250 kHz ● VEAREF from 80 % to 95 % of VCCDR -> VREF = 0.6 V/FSW = 500 kHz ● VEAREF from 95 % to 100 % of VCCDR -> VREF = 0.6 V/FSW = 250 kHz Providing an external reference from 0V to 450mV the output voltage will be regulated but some restrictions must be considered: ● OV threshold saturates to a minimum value of 300 mV (OV is tracking the reference; tracking small references will result in a narrow threshold reducing noise immunity) ● The under-voltage-protection doesn't work; ● The PGOOD signal remains low; To set the resistor divider it must be considered that a 100 k pull-down resistor is integrated into the device (see Figure 5.). Finally it must be taken into account that the voltage at the DDR-IN pin is captured by the device at the start-up when VCC is about 4 V. 11/23 Device description 5.5 L6731D Error amplifier Figure 5. Error amplifier reference VCCDR 0.6V/500KHz DDR-IN 0.6V/250KHz DDR-IN/2 250KHz 100K Error Amplifier Ref. 2.5V 5.6 Soft-start When both VCC and VIN are above their turn-ON thresholds (VIN is monitored by the OCH pin) the start-up phase takes place. Otherwise the SS pin is internally shorted to GND. At start-up, a ramp is generated charging the external capacitor CSS with an internal current generator. The initial value for this current is 35 µA and charges the capacitor up to 0.5V. After that it becomes 10 µA until the final charge value of approximately 4 V (see Figure 6.). Figure 6. Device start-up: voltage at the SS pin Vcc Vin 4.2V VCC VIN 1.25V t Vss 4V 0.5V t 12/23 L6731D Device description The reference of the error amplifier is clamped with this voltage (Vss) until it reaches the programmed value. The L6731D can always sink or source current. If an over current is detected during the soft-start phase, the device provides a constant-current-protection. In this way, in case of short soft-start time and/or small inductor value and/or high output capacitors value and so, in case of high ripple current during the soft-start, the converter can start in any case, limiting the current (see 5.8: Monitoring and protections) but not entering in HICCUP mode. During normal operation, if any under-voltage is detected on one of the two supplies, the SS pin is internally shorted to GND and so the SS capacitor is rapidly discharged. 5.7 Driver section The high-side and low-side drivers allow using different types of power MOSFETs (also multiple MOSFETs to reduce the RDS(on)), maintaining fast switching transitions. The lowside driver is supplied by VCCDR while the high-side driver is supplied by the BOOT pin. A predictive dead time control avoids MOSFETs cross-conduction maintaining very short dead time duration in the range of 20 ns. The control monitors the phase node in order to sense the low-side body diode recirculation. If the phase node voltage is less than a certain threshold (-350 mV typ.) during the dead time, it will be reduced in the next PWM cycle. The predictive dead time control does not work when the high-side body diode is conducting because the phase node does not go negative. This situation happens when the converter is sinking current for example and, in this case, an adaptive dead time control operates. 5.8 Monitoring and protections The output voltage is monitored by means of pin FB. If it is not within ±10 % (typ.) of the programmed value, the power good (PGOOD) output is forced low. The device provides over-voltage-protection: when the voltage sensed on FB pin reaches a value 20 % (typ.) greater than the reference, the low-side driver is turned on as long as the over voltage is detected (see Figure 7.). Figure 7. OVP LGate FB It must be taken into account that there is an electrical network between the output terminal and the FB pin and therefore the voltage at the pin is not a perfect replica of the output voltage. However due to the fact that the converter can sink current, in the most of cases the 13/23 Device description L6731D low-side will turn-on before the output voltage exceeds the over-voltage threshold, because the error amplifier will throw off balance in advance. Even if the device doesn't report an over-voltage, the behavior is the same, because the low-side is turned-on immediately. The following figure shows the device behavior during an over-voltage event. The output voltage rises with a slope of 100 mV/µs, emulating in this way the breaking of the high-side MOSFET as an over-voltage cause. Figure 8. OVP: the low-side MOSFET is turned-on in advance VOUT 109% VFB LGate The device realizes the over-current-protection (OCP) sensing the current both on the highside MOSFET(s) and the low-side MOSFET(s) and so 2 current limit thresholds can be set (see OCH pin and OCL pin in Table 4. Pins function): ● Peak current limit ● Valley current limit The peak current protection is active when the high-side MOSFET(s) is turned on, after a masking time of about 100 ns. The valley-current-protection is enabled when the low-side MOSFET(s) is turned on after a masking time of about 400 ns. If, when the soft-start phase is completed, an over current event occurs during the on time (peak-current-protection) or during the off time (valley-current-protection) the device enters in HICCUP mode: the highside and low-side MOSFET(s) are turned OFF, the soft-start capacitor is discharged with a constant current of 10 µA and when the voltage at the SS pin reaches 0.5 V the soft-start phase restarts. During the soft-start phase the OCP provides a constant-current-protection. If during the TON the OCH comparator triggers an over current the high-side MOSFET(s) is immediately turned OFF (after the masking time and the internal delay) and returned on at the next PWM cycle. The limit of this protection is that the TON can't be less than masking time plus propagation delay because during the masking time the peak-current-protection is disabled. In case of very hard short circuit, even with this short TON, the current could escalate. The valley-current-protection is very helpful in this case to limit the current. If during the offtime the OCL comparator triggers an over current, the high-side MOSFET(s) is not turned on until the current is over the valley-current-limit. This implies that, if it is necessary, some pulses of the high-side MOSFET(s) will be skipped, guaranteeing a maximum current due to the following formula: 14/23 L6731D Device description Equation 1 I MAX = IVALLEY + Vin − Vout ⋅ TON , MIN L During soft-start the OC acts in constant current mode: a current control loop limits the value of the error amplifier output (comp), in order to avoid its saturation and thus recover faster when the output returns in regulation. Figure 9. shows the behavior of the device during an over current condition that persists also in the soft-start phase. L6732 provides Under Voltage (UV) protection: when the voltage on FB pin falls below 80% of the reference, the IC will enter HICCUP mode. Feedback disconnection is also provided by sourcing a 100 nA current from FB pin. if FB results being floating, the IC will detect and OV so latching its condition with low side MOSFET firmly ON. 5.9 HICCUP mode during an OCP Figure 9. Constant current and hiccup mode during an OCP VSS VCOMP IL 5.10 Thermal shutdown When the junction temperature reaches 150 °C ±10 °C the device enters in thermal shutdown. Both MOSFETs are turned off and the soft-start capacitor is rapidly discharged with an internal switch. The device doesn't restart until the junction temperature goes down to 120 °C and, in any case, until the voltage at the soft-start pin reaches 500 mV. 5.11 Minimum on-time (TON, MIN) The device can manage minimum on-times lower than 100ns. This feature comes down from the control topology and from the particular over-current-protection system of the L6731D. In fact, in a voltage mode controller the current has not to be sensed to perform the regulation and, in the case of L6731D, neither for the over-current protection, given that 15/23 Device description L6731D during the off-time the valley-current-protection can operate in every case. The first advantage related to this feature is the possibility to realize extremely low conversion ratios. Figure 10. shows a conversion from 14 V to 0.3 V at 500 kHz with a TON of about 50 ns. Figure 10. 14 V -> 0.3 V @ 500 kHz, 5 A VOUT IL VPHASE 50ns The on-time is limited by the turn-on and turn-off times of the MOSFETs. 16/23 L6731D Application details 6 Application details 6.1 Inductor design The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current (∆IL) between 20 % and 30 % of the maximum output current. The inductance value can be calculated with the following relationship: Equation 2 L≅ Vin − Vout Vout ⋅ Fsw ⋅ ∆I L Vin Where FSW is the switching frequency, Vin is the input voltage and Vout is the output voltage. Increasing the value of the inductance reduces the ripple current but, at the same time, increases the converter response time to a load transient. If the compensation network is well designed, during a load transient the device is able to set the duty cycle to 100 % or to 0 %. When one of these conditions is reached, the response time is limited by the time required to change the inductor current. During this time the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitor size. 6.2 Output capacitors The output capacitors are basic components for the fast transient response of the power supply. They depend on the output voltage ripple requirements, as well as any output voltage deviation requirement during a load transient. During a load transient, the output capacitors supply the current to the load or absorb the current stored in the inductor until the converter reacts. In fact, even if the controller recognizes immediately the load transient and sets the duty cycle at 100 % or 0 %, the current slope is limited by the inductor value. The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL): Equation 3 ∆Vout ESR = ∆Iout ⋅ ESR Moreover, there is an additional drop due to the effective capacitor discharge or charge that is given by the following formulas: Equation 4 ∆VoutCOUT = ∆Iout 2 ⋅ L 2 ⋅ Cout ⋅ (Vin, min⋅ D max − Vout ) Equation 5 ∆VoutCOUT = ∆Iout 2 ⋅ L 2 ⋅ Cout ⋅Vout Formula (4) is valid in case of positive load transient while the formula (5) is valid in case of negative load transient. DMAX is the maximum duty cycle value that in the L6731D is 100%. 17/23 Application details L6731D For a given inductor value, minimum input voltage, output voltage and maximum load transient, a maximum ESR and a minimum Cout value can be set. The ESR and Cout values also affect the static output voltage ripple. In the worst case the output voltage ripple can be calculated with the following formula: Equation 6 ∆Vout = ∆I L ⋅ ( ESR + 1 ) 8 ⋅ Cout ⋅ Fsw Usually the voltage drop due to the ESR is the biggest one while the drop due to the capacitor discharge is almost negligible. 6.3 Input capacitors The input capacitors have to sustain the RMS current flowing through them, that is: Equation 7 Irms = Iout ⋅ D ⋅ (1 − D) Where D is the duty cycle. The equation reaches its maximum value, IOUT /2 with D = 0.5. The losses in worst case are: Equation 8 P = ESR ⋅ (0.5 ⋅ Iout ) 2 6.4 Compensation network The loop is based on a voltage mode control (Figure 18.). The output voltage is regulated to the internal/external reference voltage and scaled by the external resistor divider. The error amplifier output VCOMP is then compared with the oscillator triangular wave to provide a pulse-width modulated (PWM) with an amplitude of VIN at the PHASE node. This waveform is filtered by the output filter. The modulator transfer function is the small signal transfer function of VOUT/VCOMP. This function has a double pole at frequency FLC depending on the L-COUT resonance and a zero at FESR depending on the output capacitor's ESR. The DC Gain of the modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage: VOSC. 18/23 L6731D Application details Figure 11. Compensation network The compensation network consists in the internal error amplifier, the impedance networks ZIN (R3, R4 and C20) and ZFB (R5, C18 and C19). The compensation network has to provide a closed loop transfer function with the highest 0 dB crossing frequency to have fastest transient response (but always lower than fsw/10) and the highest gain in DC conditions to minimize the load regulation error. A stable control loop has a gain crossing the 0 dB axis with -20 dB/decade slope and a phase margin greater than 45 °. To locate poles and zeroes of the compensation networks, the following suggestions may be used: ● Modulator singularity frequencies: Equation 9 ω LC = 1 L ⋅ Cout ω ESR = 1 ESR ⋅ Cout Equation 10 ● Compensation network singularity frequencies: Equation 11 ω P1 = 1 ⎛ C ⋅C ⎞ R5 ⋅ ⎜⎜ 18 19 ⎟⎟ ⎝ C18 + C19 ⎠ 19/23 Application details L6731D Equation 12 ωP 2 = 1 R4 ⋅ C20 ωZ 1 = 1 R5 ⋅ C19 Equation 13 Equation 14 ωZ 2 = ● 1 C20 ⋅ (R3 + R4 ) Compensation network design: – Put the gain R5/R3 in order to obtain the desired converter bandwidth Equation 15 ϖC = R5 Vin ⋅ ⋅ϖ LC R3 ∆Vosc – Place ωZ1 before the output filter resonance ωLC; – Place ωZ2 at the output filter resonance ωLC; – Place ωP1 at the output capacitor ESR zero ωESR; – Place ωP2 at one half of the switching frequency; – Check the loop gain considering the error amplifier open loop gain. Figure 12. Asymptotic bode plot of converter's open loop gain 20/23 L6731D 7 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 13. HTSSOP16 mechanical data TSSOP16 EXPOSED PAD MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. 1.2 A1 0.047 0.15 A2 0.8 b c 1 MAX. 0.004 0.031 0.19 0.30 0.007 0.012 0.09 0.20 0.004 0.0089 0.193 D 4.9 5 5.1 D1 2.8 3.0 3.1 E 6.2 6.4 6.6 0.244 0.169 E1 4.3 4.4 4.5 E2 2.8 3.0 3.1 e 1.102 1.102 0.65 K 0° L 0.45 0.60 0.039 0.006 1.05 0.041 0.197 0.201 0.118 1.220 0.252 0.260 0.173 0.177 0.118 1.220 0.0256 8° 0° 0.75 0.018 8° 0.024 0.030 7419276A 21/23 Revision history 8 L6731D Revision history Table 7. 22/23 Document revision history Date Revision Changes 21-Dec-2005 1 Initial release. 31-May-2006 2 New template, thermal data updated 04-Jun-2008 3 Updated: Table 4 on page 6, Table 5 on page 8, Section 5.4 on page 11, Figure 13 on page 21 L6731D Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 23/23