L6919E 5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER WITH DYNAMIC VID MANAGEMENT ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2 PHASE OPERATION WITH SYNCRHONOUS RECTIFIER CONTROL ULTRA FAST LOAD TRANSIENT RESPONSE INTEGRATED HIGH CURRENT GATE DRIVERS: UP TO 2A GATE CURRENT TTL-COMPATIBLE 5 BIT PROGRAMMABLE OUTPUT FROM 0.800V TO 1.550V WITH 25mV STEPS DYNAMIC VID MANAGEMENT 0.6% OUTPUT VOLTAGE ACCURACY 10% ACTIVE CURRENT SHARING ACCURACY DIGITAL 2048 STEP SOFT-START OVERVOLTAGE PROTECTION OVERCURRENT PROTECTION REALIZED USING THE LOWER MOSFET'S R dsON OR A SENSE RESISTOR OSCILLATOR EXTERNALLY ADJUSTABLE AND INTERNALLY FIXED AT 200kHz POWER GOOD OUTPUT AND INHIBIT FUNCTION REMOTE SENSE BUFFER PACKAGE: SO-28 SO-28 ORDERING NUMBERS:L6919E L6919ETR DESCRIPTION The device is a power supply controller specifically designed to provide a high performance DC/DC conversion for high current microprocessors. The device implements a dual-phase step-down controller with a 180° phase-shift between each phase. A precise 5-bit digital to analog converter (DAC) allows adjusting the output voltage from 0.800V to 1.550V with 25mV binary steps managing On-The-Fly VID code changes. The high precision internal reference assures the selected output voltage to be within ±0.6%. The high peak current gate drive affords to have fast switching to the external power mos providing low switching losses. The device assures a fast protection against load over current and load over/under voltage. An internal crowbar is provided turning on the low side mosfet if an over-voltage is detected. In case of over-current, the system works in Constant Current mode. APPLICATIONS ■ POWER SUPPLY FOR SERVERS AND WORKSTATIONS ■ POWER SUPPLY FOR HIGH CURRENT MICROPROCESSORS ■ DISTRIBUTED POWER SUPPLY BLOCK DIAGRAM O S C / I NH S GN D VC C D R V CC D AC 3 2k L O G IC PW M PGN D PGN DS2 CUR REN T REA DIN G ISE N2 I FB 3 2k CH2 O CP PW M2 R EMO TE BU FFE R ERR OR A MPL IF IER V S EN FB L GAT E1 PGN DS1 CH 2 OC P C H1 OCP 32k September 2003 LS ISE N1 LO G IC PW M A DA PT IV E A N T I CRO SS CO N DU CT IO N FB R E1 PHAS E1 CUR REN T REA DIN G TO TAL C UR REN T 32k FB G CH1 O CP U GA T V CC DR CU R R EN T C OR R EC TI ON VID 4 VID 3 VID 2 VID 1 VID 0 C U RR EN T COR R EC TI ON DIGIT AL SOFT- START PW M1 C U R R EN T AV G LOGIC AN D P ROTE CTION S PGO O D A DA PTIV E A NT I CRO SS CO ND UCT IO N 2 P H AS E O S C IL L ATOR BOO T 1 HS COM P Vc c LS L GAT E2 PHAS E2 HS U GA T E2 BOO T 2 V cc 1/33 L6919E ABSOLUTE MAXIMUM RATINGS Symbol Vcc, VCCDR VBOOT-VPHASE Parameter to PGND Boot Voltage Unit 15 V 15 V 15 V -0.3 to Vcc+0.3 V VID0 to VID4 -0.3 to 5 V All other pins to PGND -0.3 to 7 V VUGATE1-VPHASE1 VUGATE2-VPHASE2 LGATE1, PHASE1, LGATE2, PHASE2 to PGND Vphase Value 26 V ±1000 V ±2000 V Value Unit Thermal Resistance Junction to Ambient 60 °C/W Maximum junction temperature 150 °C -40 to 150 °C 0 to 125 °C 2 W UGATEx Pin OTHER PINS Sustainable Peak Voltage t < 20ns @ 600kHz Maximum Withstanding Voltage Range Test Condition: CDF-AEC-Q100-002”Human Body Model” Acceptance Criteria: “Normal Performance” THERMAL DATA Symbol Rth j-amb Tmax Tstorage Tj PMAX Parameter Storage temperature range Junction Temperature Range Max power dissipation at Tamb = 25°C PIN CONNECTION 2/33 1 28 PGND VCCDR 2 27 LGATE2 PHASE1 3 26 PHASE2 UGATE1 4 25 UGATE2 BOOT1 5 24 BOOT2 VCC 6 23 PGOOD SGND 7 22 VID4 COMP 8 21 VID3 FB 9 20 VID2 L6919E LGATE1 VSEN 10 19 VID1 FBR 11 18 VID0 FBG 12 17 OSC / INH / FAULT ISEN1 13 16 ISEN2 PGNDS1 14 15 PGNDS L6919E ELECTRICAL CHARACTERISTICS VCC = 12V ±15%, TJ = 0 to 70°C unless otherwise specified Symbol Parameter Test Condition Min Typ Max Unit Vcc SUPPLY CURRENT ICC Vcc supply current HGATEx and LGATEx open VCCDR=VBOOT=12V 7.5 10 12.5 mA ICCDR VCCDR supply current LGATEx open; VCCDR=12V 2 3 4 mA IBOOTx Boot supply current HGATEx open; PHASEx to PGND VCC=VBOOT=12V 0.5 1 1.5 mA Turn-On VCC threshold VCC Rising; VCCDR=5V 8.2 9.2 10.2 V Turn-Off VCC threshold VCC Falling; VCCDR=5V 6.5 7.5 8.5 V Turn-On VCCDR Threshold VCCDR Rising VCC=12V 4.2 4.4 4.6 V Turn-Off VCCDR Threshold VCCDR Falling VCC=12V 4.0 4.2 4.4 V 150 165 178 kHz kHz POWER-ON OSCILLATOR/INHIBIT/FAULT fOSC Initial Accuracy OSC = OPEN OSC = OPEN; Tj=0°C to 125°C 135 127 INH Inhibit threshold ISINK=5mA 0.5 dMAX Maximum duty cycle OSC = OPEN; IFB = 0 72 80 % OSC = OPEN; IFB = 70µA 30 40 % 3 V ∆Vosc Ramp Amplitude FAULT Voltage at pin OSC V OVP or UVP Active 4.75 5.0 5.25 V Output Voltage Accuracy VID0, VID1, VID2, VID3, VID4 see Table1; FBR = VOUT; FBG = GND -0.6 - 0.6 % VID pull-up Current VIDx = GND 4 5 6 µA VID pull-up Voltage VIDx = OPEN 2.9 - 3.3 V REFERENCE AND DAC IDAC ERROR AMPLIFIER DC Gain SR 80 dB 15 V/µs DC Gain 1 V/V Common Mode Rejection Ratio 40 dB 15 V/µs Slew-Rate COMP=10pF DIFFERENTIAL AMPLIFIER (REMOTE BUFFER) CMRR SR Slew Rate VSEN=10pF 3/33 L6919E ELECTRICAL CHARACTERISTICS (continued) VCC = 12V ±15%, TJ = 0 to 70°C unless otherwise specified Symbol Parameter Test Condition Min Typ Max Unit 45 50 55 µA DIFFERENTIAL CURRENT SENSING IISEN1, IISEN2 Bias Current IPGNDSx Bias Current 45 50 55 µA Bias Current at Over Current Threshold 80 85 90 µA 47.5 0 50 1 52.5 µA µA 30 ns IISEN1, IISEN2 IFB Active Droop Current ILOAD = 0 ILOAD ≤ 0% ILOAD = 100% GATE DRIVERS High Side Rise Time VBOOTx-VPHASEx=10V; CHGATEx to PHASEx=3.3nF 15 IHGATEx High Side Source Current VBOOTx-VPHASEx=10V 2 RHGATEx High Side Sink Resistance VBOOTx-VPHASEx=12V; Low Side Rise Time ILGATEx RLGATEx tRISE HGATE tRISE LGATE A 2 2.5 Ω VCCDR=10V; CLGATEx to PGNDx=5.6nF 30 55 ns Low Side Source Current VCCDR=10V 1.8 Low Side Sink Resistance VCCDR=12V 0.7 1.1 1.5 Ω 1.5 A PROTECTIONS PGOOD Upper Threshold (VSEN/DAC Output) VSEN Rising 108 112 116 % PGOOD Lower Threshold (VSEN/DAC Output) VSEN Falling 84 88 92 % OVP Over Voltage Threshold (VSEN) VSEN Rising 1.915 2.05 V UVP Under Voltage Trip (VSEN/DAC Output) VSEN Falling 55 65 % 0.4 V 1 µA VPGOODL PGOOD Voltage Low IPGOOD = -4mA IPGOODH PGOOD Leakage VPGOOD = 5V 4/33 60 L6919E Table 1. Voltage Identification (VID) Codes VID4 VID3 VID2 VID1 VID0 Output Voltage (V) VID4 VID3 VID2 VID1 VID0 Output Voltage (V) 0 0 0 0 0 1.575 1 0 0 0 0 1.175 0 0 0 0 1 1.550 1 0 0 0 1 1.150 0 0 0 1 0 1.525 1 0 0 1 0 1.125 0 0 0 1 1 1.500 1 0 0 1 1 1.100 0 0 1 0 0 1.475 1 0 1 0 0 1.075 0 0 1 0 1 1.450 1 0 1 0 1 1.050 0 0 1 1 0 1.425 1 0 1 1 0 1.025 0 0 1 1 1 1.400 1 0 1 1 1 1.000 0 1 0 0 0 1.375 1 1 0 0 0 0.975 0 1 0 0 1 1.350 1 1 0 0 1 0.950 0 1 0 1 0 1.325 1 1 0 1 0 0.925 0 1 0 1 1 1.300 1 1 0 1 1 0.900 0 1 1 0 0 1.275 1 1 1 0 0 0.875 0 1 1 0 1 1.250 1 1 1 0 1 0.850 0 1 1 1 0 1.225 1 1 1 1 0 0.825 0 1 1 1 1 1.200 1 1 1 1 1 Shutdown The device automatically regulates 25mV higher than the Hammer specs avoiding the use of any external offset resistor Reference Schematic Vin GNDin CIN VCCDR BOOT1 VCC 2 6 5 24 4 25 3 26 1 27 13 16 14 L6919E 15 UGATE1 HS1 L1 UGATE2 PHASE1 HS2 LGATE2 ISEN1 LS2 LOAD Rg PGNDS1 Rg PGNDS2 PGND 28 Rg VID4 22 S3 VID3 S2 VID2 S1 VID1 S0 COUT ISEN2 Rg S4 L2 PHASE2 LGATE1 LS1 BOOT2 PGOOD 23 21 PGOOD VSEN 10 20 19 VID0 FB 18 OSC / INH RFB 9 17 RF CF SGND 7 COMP 11 FBR 12 8 FBG 5/33 L6919E PIN FUNCTION N Name 1 LGATE1 Channel 1 LS driver output. A little series resistor helps in reducing device-dissipated power. 2 VCCDR LS drivers supply: it can be varied from 5V to 12V buses. Filter locally with at least 1µF ceramic cap vs. PGND. 3 PHASE1 Channel 1 HS driver return path. It must be connected to the HS1 mosfet source and provides the return path for the HS driver of channel 1. 4 UGATE1 Channel 1 HS driver output. A little series resistor helps in reducing device-dissipated power. 5 BOOT1 Channel 1 HS driver supply. This pin supplies the relative high side driver. Connect through a capacitor (100nF typ.) to the PHASE1 pin and through a diode to VCC (cathode vs. boot). 6 VCC Device supply voltage. The operative supply voltage is 12V ±10%. Filter with 1µF (Typ.) capacitor vs. GND. 7 GND All the internal references are referred to this pin. Connect it to the PCB signal ground. 8 COMP 9 FB This pin is connected to the error amplifier inverting input and is used to compensate the voltage control feedback loop. A current proportional to the sum of the current sensed in both channel is sourced from this pin (50µA at full load, 70µA at the Constant Current threshold). Connecting a resistor between this pin and VSEN pin allows programming the droop effect. 10 VSEN Manages Over&Under-voltage conditions and the PGOOD signal. It is internally connected with the output of the Remote Sense Buffer for Remote Sense of the regulated voltage. If no Remote Sense is implemented, connect it directly to the regulated voltage in order to manage OVP, UVP and PGOOD. Connecting 1nF capacitor max vs. SGND can help in reducing noise injection. 11 FBR Remote sense buffer non-inverting input. It has to be connected to the positive side of the load to perform a remote sense. If no remote sense is implemented, connect directly to the output voltage (in this case connect also the VSEN pin directly to the output regulated voltage). 12 FBG Remote sense buffer inverting input. It has to be connected to the negative side of the load to perform a remote sense. Pull-down to ground if no remote sense is implemented. 13 ISEN1 Channel 1 current sense pin. The output current may be sensed across a sense resistor or across the low-side mosfet RdsON. This pin has to be connected to the low-side mosfet drain or to the sense resistor through a resistor Rg. The net connecting the pin to the sense point must be routed as close as possible to the PGNDS net in order to couple in common mode any picked-up noise. 14 PGNDS1 Channel 1 Power Ground sense pin. The net connecting the pin to the sense point must be routed as close as possible to the ISEN1 net in order to couple in common mode any picked-up noise. 15 PGNDS2 Channel 2 Power Ground sense pin. The net connecting the pin to the sense point must be routed as close as possible to the ISEN2 net in order to couple in common mode any picked-up noise. 16 ISEN2 Channel 2 current sense pin. The output current may be sensed across a sense resistor or across the low-side mosfet RdsON. This pin has to be connected to the low-side mosfet drain or to the sense resistor through a resistor Rg. The net connecting the pin to the sense point must be routed as close as possible to the PGNDS net in order to couple in common mode any picked-up noise. 6/33 Description This pin is connected to the error amplifier output and is used to compensate the control feedback loop. L6919E PIN FUNCTION (continued) N Name Description 17 OSC/INH FAULT Oscillator pin. It allows programming the switching frequency of each channel: the equivalent switching frequency at the load side results in being doubled. Internally fixed at 1.24V, the frequency is varied proportionally to the current sunk (forced) from (into) the pin with an internal gain of 6kHz/µA (See relevant section for details). If the pin is not connected, the switching frequency is 150kHz for each channel (300kHz on the load). The pin is forced high (5V Typ.) when an Over/Under Voltage is detected; to recover from this condition, cycle VCC. Forcing the pin to a voltage lower than 0.6V, the device stop operation and enter the inhibit state. 18-22 VID4-0 23 PGOOD This pin is an open collector output and is pulled low if the output voltage is not within the above specified thresholds and during soft start. It cannot be pulled-up above 5V. If not used may be left floating. 24 BOOT2 Channel 2 HS driver supply. This pin supplies the relative high side driver. Connect through a capacitor (100nF typ.) to the PHASE2 pin and through a diode to VCC (cathode vs. boot). 25 UGATE2 Channel 2 HS driver output. A little series resistor helps in reducing device-dissipated power. 26 PHASE2 Channel 2 HS driver return path. It must be connected to the HS2 mosfet source and provides the return path for the HS driver of channel 2. 27 LGATE2 Channel 2 LS driver output. A little series resistor helps in reducing device-dissipated power. 28 PGND Voltage IDentification pins. Internally pulled-up, connect to GND to program a ‘0’ while leave floating to program a ‘1’. They are used to program the output voltage as specified in Table 1 and to set the PGOOD, OVP and UVP thresholds. The device automatically regulates 25mV higher than the HAMMER DAC avoiding the use of any external set-up resistor. LS drivers return path. This pin is common to both sections and it must be connected through the closest path to the LS mosfets source pins in order to reduce the noise injection into the device. 7/33 L6919E DEVICE DESCRIPTION The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections for a high performance dual-phase step-down DC-DC converter optimized for microprocessor power supply. It is designed to drive N Channel MOSFETs in a dual-phase synchronous-rectified buck topology. A 180 deg phase shift is provided between the two phases allowing reduction in the input capacitor current ripple, reducing also the size and the losses. The output voltage of the converter can be precisely regulated, programming the VID pins, from 0.825V to 1.575V with 25mV binary steps, with a maximum tolerance of ±0.6% over temperature and line voltage variations. The device automatically regulates 25mV higher than the HAMMER DAC avoiding the use of any external set-up resistor. The device manages On-The-Fly VID Code changes stepping to the new configuration following the VID table with no need for external components. The device provides an average current-mode control with fast transient response. It includes a 150kHz free-running oscillator. The error amplifier features a 15V/µs slew rate that permits high converter bandwidth for fast transient performances. Current information is read across the lower mosfets RdsON or across a sense resistor in fully differential mode. The current information corrects the PWM output in order to equalize the average current carried by each phase. Current sharing between the two phases is then limited at ±10% over static and dynamic conditions. The device protects against Over-Current, with an OC threshold for each phase, entering in constant current mode. Since the current is read across the low side mosfets, the constant current keeps constant the bottom of the inductors current triangular waveform. When an under voltage is detected the device latches and the FAULT pin is driven high. The device performs also Over-Voltage protection that disables immediately the device turning ON the lower driver and driving high the FAULT pin. OSCILLATOR The switching frequency is internally fixed at 150kHz. Each phase works at the frequency fixed by the oscillator so that the resulting switching frequency at the load side results in being doubled. The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the oscillator is typically 25 A (Fsw=150kHz) and may be varied using an external resistor (ROSC) connected between OSC pin and GND or Vcc. Since the OSC pin is maintained at fixed voltage (Typ. 1.237V), the frequency is varied proportionally to the current sunk (forced) from (into) the pin considering the internal gain of 6KHz/µA. In particular connecting it to GND the frequency is increased (current is sunk from the pin), while connecting ROSC to Vcc=12V the frequency is reduced (current is forced into the pin), according to the following relationships: 6 kH z 1.237 7.422 ⋅ 10 R O SC vs. GND: f S = 150 kHz + --------------- ⋅ 6 ----------- = 150kHz + -----------------------------µA R ( KΩ ) R O SC O SC 7 12 – 1.237 kHz 6.457 ⋅ 10 R O SC vs. 12V: f S = 150kHz – --------------------------- ⋅ 6 ----------- = 150 kHz – -----------------------------µA R O SC R O SC ( KΩ ) Note that forcing a 25µA into this pin, the device stops switching because no current is delivered to the oscillator. Figure 1. ROSC vs. Switching Frequency 14000 800 Rosc(KΩ ) vs. GND Rosc(KΩ ) vs. 12V 12000 10000 8000 6000 4000 2000 600 500 400 300 200 100 0 25 50 75 100 Frequency (KHz) 8/33 700 125 150 0 150 250 350 450 Frequency (KHz) 550 650 L6919E DIGITAL TO ANALOG CONVERTER The built-in digital to analog converter allows the adjustment of the output voltage from 0.800V to 1.550V with 25mV as shown in the previous table 1. The internal reference is trimmed to ensure output voltage precision of ±0.6% and a zero temperature coefficient around 70°C. The internal reference voltage for the regulation is programmed by the voltage identification (VID) pins. These are TTL compatible inputs of an internal DAC that is realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an amplifier obtaining the VPROG voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are provided (realized with a 5µA current generator up to 3.0V Typ); in this way, to program a logic "1" it is enough to leave the pin floating, while to program a logic "0" it is enough to short the pin to GND. Programming the "11111" code, the device enters the NOCPU mode: all mosfets are turned OFF and protections are disabled. The condition is latched. The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the Over / Under Voltage protection (OVP/UVP) thresholds. DYNAMIC VID TRANSITION The device is able to manage On-The-Fly VID Code changes that allow Output Voltage modification during normal device operation. The device checks every clock cycle (synchronously with the PWM ramp) for VID code modifications. Once the new code is stable for more than one clock cycle, the reference steps up or down in 25mV increments every clock cycle until the new VID code is reached. During the transition, VID code changes are ignored; the device re-starts monitoring VID after the transition has finished. PGOOD, signal is masked during the transition and it is re-activated after the transition has finished while OVP / UVP are still active. Figure 2. Dynamic VID transition VID t Reference 25mV steps transition t VOUT t 1 Clock Cycle Blanking Time DRIVER SECTION The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the RdsON), maintaining fast switching transition. The drivers for the high-side mosfets use BOOTx pins for supply and PHASEx pins for return. The drivers for the low-side mosfets use VCCDRV pin for supply and PGND pin for return. A minimum voltage of 4.6V at VCCDRV pin is required to start operations of the device. The controller embodies a sophisticated anti-shoot-through system to minimize low side body diode conduction time maintaining good efficiency saving the use of Schottky diodes. The dead time is reduced to few nanoseconds assuring that high-side and low-side mosfets are never switched on simultaneously: when the high-side mosfet turns off, the voltage on its source begins to fall; when the voltage reaches 2V, the low-side mosfet gate drive is applied with 30ns delay. When the low-side mosfet turns off, the voltage at LGATEx pin is sensed. When it drops below 1V, the high-side mosfet gate drive is applied with a delay of 30ns. If the current flowing in the inductor is negative, the source of high-side mosfet will never drop. 9/33 L6919E Figure 3. Drivers peak current: High Side (left) and Low Side (right) CH3 = HGATE1; CH4 = HGATE2 CH3 = LGATE1; CH4 = LGATE2 To allow the turning on of the low-side mosfet even in this case, a watchdog controller is enabled: if the source of the high-side mosfet don't drop for more than 240ns, the low side mosfet is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative. The BOOTx and VCCDR pins are separated from IC's power supply (VCC pin) as well as signal ground (SGND pin) and power ground (PGND pin) in order to maximize the switching noise immunity. The separated supply for the different drivers gives high flexibility in mosfet choice, allowing the use of logic-level mosfet. Several combination of supply can be chosen to optimize performance and efficiency of the application. Power conversion is also flexible; 5V or 12V bus can be chosen freely. The peak current is shown for both the upper and the lower driver of the two phases in figure 3. A 10nF capacitive load has been used. For the upper drivers, the source current is 1.9A while the sink current is 1.5A with VBOOT -VPHASE = 12V; similarly, for the lower drivers, the source current is 2.4A while the sink current is 2A with VCCDR = 12V. CURRENT READING AND OVER CURRENT The current flowing trough each phase is read using the voltage drop across the low side mosfets RdsON or across a sense resistor (RSENSE) and internally converted into a current. The Tran conductance ratio is issued by the external resistor Rg placed outside the chip between ISENx and PGNDSx pins toward the reading points. The full differential current reading rejects noise and allows to place sensing element in different locations without affecting the measurement's accuracy. The current reading circuitry reads the current during the time in which the low-side mosfet is on (OFF Time). During this time, the reaction keeps the pin ISENx and PGNDSx at the same voltage while during the time in which the reading circuitry is off, an internal clamp keeps these two pins at the same voltage sinking from the ISENx pin the necessary current (Needed if low-side mosfet RdsON sense is implemented to avoid absolute maximum rating overcome on ISENx pin). The proprietary current reading circuit allows a very precise and high bandwidth reading for both positive and negative current. This circuit reproduces the current flowing through the sensing element using a high speed Track & Hold Tran conductance amplifier. In particular, it reads the current during the second half of the OFF time reducing noise injection into the device due to the mosfet turn-on (See fig. 4). Track time must be at least 200ns to make proper reading of the delivered current This circuit sources a constant 50µA current from the PGNDSx pin and keeps the pins ISENx and PGNDSx at the same voltage. Referring to figure 4, the current that flows in the ISENx pin is then given by the following equation: R SENSE ⋅ I PHASE I ISENx = 50µA + ---------------------------------------------= 50µ A + I INFO x Rg 10/33 L6919E Figure 4. Current Reading Timing (Left) and Circuit (Right) ILS1 LGATEX Rg ILS2 Rg IPHASE IISENx Total current information RSENSE ISENX PGNDSX 50µA Track & Hold Where RSENSE is an external sense resistor or the rds,on of the low side mosfet and Rg is the transconductance resistor used between ISENx and PGNDSx pins toward the reading points; IPHASE is the current carried by each phase and, in particular, the current measured in the middle of the oscillator period The current information reproduced internally is represented by the second term of the previous equation as follow: R SENSE ⋅ I PHASE I INFO x = ---------------------------------------------Rg Since the current is read in differential mode, also negative current information is kept; this allow the device to check for dangerous returning current between the two phases assuring the complete equalization between the phase's currents. From the current information of each phase, information about the total current delivered (IFB =IINFO1 +IINFO2) and the average current for each phase (IAVG =(IINFO1 +IINFO2)/2 ) is taken. IINFOX is then compared to IAVG to give the correction to the PWM output in order to equalize the current carried by the two phases. The transconductance resistor Rg can be designed in order to have current information of 25µA per phase at full nominal load; the over current intervention threshold is set at 140% of the nominal (IINFOx = 35µA). According to the above relationship, the over current threshold (IOCPx) for each phase, which has to be placed at one half of the total delivered maximum current, results: 35 µA ⋅ Rg I OCPx = --------------------------R S ENSE I OCP x ⋅ R SE NSE Rg = -----------------------------------------35 µA Since the device senses the output current across the low-side mosfets (or across a sense resistors in series with them) the device limits the bottom of the inductor current triangular waveform: an over current is detected when the current flowing into the sense element is greater than IOCPx (IINFOx > 35µA). Introducing now the maximum ON time dependence with the delivered current (where T is the switching period T=1/fSW): R SENSE 0.80 ⋅ T I F B = 0 µA T ON,MAX = 0.80 – ( I FB ⋅ 5.73 k ) ⋅ T = 0.80 – ---------------------- ⋅ I OUT ⋅ 5.73k ⋅ T Rg 0.40 ⋅ T I F B = 7 0µA This linear dependence has a value at zero load of 0.80·T and at maximum current of 0.40·T typical and results in two different behaviors of the device: 11/33 L6919E 1. TON Limited Output Voltage. This happens when the maximum ON time is reached before the current in each phase reaches IOCPx (IINFOx < 35µA). Figure 5a shows the maximum output voltage that the device is able to regulate considering the TON limitation imposed by the previous relationship. If the desired output characteristic crosses the TON limited maximum output voltage, the output resulting voltage will start to drop after crossing. In this case, the device doesn't perform constant current limitation but only limits the maximum ON time following the previous relationship. The output voltage follows the resulting characteristic (dotted in Figure 5b) until UVP is detected or anyway until IFB = 70µA. Figure 5. TON Limited Operation VOUT VOUT 0.80·VIN 0.80·VIN Resulting Output characteristic TON Limited Output characteristic Desired Output characteristic and UVP threshold 0.40·VIN 0.40·VIN IOCP=2·IOCPx (IFB=70µA) IOUT a) Maximum output Voltage IOCP=2·IOCPx (IFB=70µA) IOUT b) TON Limited Output Voltage 2. Constant Current Operation This happens when ON time limitation is reached after the current in each phase reaches I OCPx (IINFOx>35µA). The device enters in Quasi-Constant-Current operation: the low-side mosfets stays ON until the current read becomes lower than IOCPx (IINFOx < 35µA) skipping clock cycles. The high side mosfets can be turned ON with a TON imposed by the control loop at the next available clock cycle and the device works in the usual way until another OCP event is detected. This means that the average current delivered can slightly increase also in Over Current condition since the current ripple increases. In fact, the ON time increases due to the OFF time rise because of the current has to reach the IOCPx bottom. The worst-case condition is when the ON time reaches its maximum value. When this happens, the device works in Constant Current and the output voltage decrease as the load increase. Crossing the UVP threshold causes the device to latch (FAULT pin is driven high). Figure 6 shows this working condition It can be observed that the peak current (Ipeak) is greater than the IOCPx but it can be determined as follow: V IN – Vo ut M IN V IN – Vo ut M IN Ipea k = I OCPx + --------------------------------------- ⋅ Ton M AX = I OCPx + --------------------------------------- ⋅ 0.40 ⋅ T L L Where VoutMIN is the minimum output voltage (VID-30% as follow). The device works in Constant-Current, and the output voltage decreases as the load increase, until the output voltage reaches the Under-Voltage threshold (VoutMIN). When this threshold is crossed, all mosfets are turned off, the FAULT pin is driven high and the device stops working. Cycle the power supply to restart operation. The maximum average current during the Constant-Current behavior results: Ipe ak – I OCP x I M AX,TOT = 2 ⋅ IMA X + 2 ⋅ IOCPx + ------------------------------------ 2 12/33 L6919E Figure 6. Constant Current operation Ipeak Vout Droop effect IMAX IOCPx TonMAX UVP Iout IMAX,TOT TonMAX (IFB=50µA) a) Maximum current for each phase IOCP=2·IOCPx (IFB=70µA) b) Output Characteristic In this particular situation, the switching frequency results reduced. The ON time is the maximum allowed (TonMAX) while the OFF time depends on the application: Ipe ak – I OCP x T O FF = L ⋅ -------------------------------------V OUT 1 f = -----------------------------------------T ONm a x + T O FF Over current is set anyway when I INFOx reaches 35µA (IFB = 70µA). The full load value is only a convention to work with convenient values for I FB. Since the OCP intervention threshold is fixed, to modify the percentage with respect to the load value, it can be simply considered that, for example, to have on OCP threshold of 170%, this will correspond to IINFOx = 35µA (IFB = 70µA). The full load current will then correspond to IINFOx = 20.6µA (IFB = 41.1µA). Integrated Droop Function The device uses a droop function to satisfy the requirements of high performance microprocessors, reducing the size and the cost of the output capacitor. This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a dependence of the output voltage on the load current As shown in figure 7, the ESR drop is present in any case, but using the droop function the total deviation of the output voltage is minimized. In practice the droop function introduces a static error (VDROOP in figure 8) proportional to the output current. Since the device has an average current mode regulation, the information about the total current delivered is used to implement the Droop Function. This current (equal to the sum of both IINFOx) is sourced from the FB pin. Connecting a resistor between this pin and VOUT, the total current information flows only in this resistor because the compensation network between FB and COMP has always a capacitor in series (See fig. 8). The voltage regulated is then equal to: VOUT = VID - RFB · IFB Since IFB depends on the current information about the two phases, the output characteristic vs. load current is given by: R SENSE V OUT = VID – R FB ⋅ ---------------------- ⋅ I OUT Rg 13/33 L6919E Figure 7. Output transient response without (a) and with (b) the droop function ESR DROP ESR DROP VMAX VDROOP VNOM VMIN (a) (b) Figure 8. Active Droop Function Circuit VDROOP To VO UT RFB COMP FB Total Current Info (IINFO1+IINFO2) Ref The feedback current is equal to 50µA at nominal full load (IFB = IINFO1 + IINFO2) and 70µA at the OC intervention threshold, so the maximum output voltage deviation is equal to: ∆VFULL_POSITIVE_LOAD = -RFB · 50µA ∆VOC_INTERVENTION = -RFB · 70µA Droop function is provided only for positive load; if negative load is applied, and then IINFOx < 0, no current is sunk from the FB pin. The device regulates at the voltage programmed by the VID. REMOTE VOLTAGE SENSE A remote sense buffer is integrated into the device to allow output voltage remote sense implementation without any additional external components. In this way, the output voltage programmed is regulated between the remote buffer inputs compensating motherboard trace losses or connector losses if the device is used for a VRM module. The very low offset amplifier senses the output voltage remotely through the pins FBR and FBG (FBR is for the regulated voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN pin with unity gain eliminating the errors. Keeping the FBR and FBG traces parallel and guarded by a power plane results in common mode coupling for any picked-up noise. If remote sense is not required, it is enough connecting RFB directly to the regulated voltage: VSEN becomes not connected and still senses the output voltage through the remote buffer. In this case the FBG and FBR pins must be connected anyway to the regulated voltage (See figure 10). The remote buffer is included in the trimming chain in order to achieve ±0.5% accuracy on the output voltage when the RB Is used: eliminating it from the control loop causes the regulation error to be increased by the RB offset worsening the device performances. 14/33 L6919E Figure 9. - Remote Buffer Connections Reference REMOTE BUFFER 64k 64k FBR IFB 64k FBG VSEN FB CF COMP Reference REMOTE BUFFER 64k 64k 64k RFB Remote VOUT ERROR AMPLIFIER FBR ERROR AMPLIFIER IFB 64k 64k FBG FB VSEN RFB RF Remote Ground CF COMP RF VOUT RB used (±0.5% Accuracy) RB Not Used OUTPUT VOLTAGE MONITOR AND PROTECTIONS The device monitors through pin VSEN the regulated voltage in order to build the PGOOD signal and manage the OVP / UVP conditions. Power good output is forced low if the voltage sensed by VSEN is not within ±12% (Typ.) of the programmed value. It is an open drain output and it is enabled only after the soft start is finished (2048 clock cycles after startup). During Soft-Start this pin is forced low. Under voltage protection is provided. If the output voltage monitored by VSEN drops below the 60% of the reference voltage for more than one clock period, the device turns off all mosfets and the OSC/FAULT is driven high (5V). The condition is latched, to recover it is required to cycle the power supply. Over Voltage protection is also provided: when the voltage monitored by VSEN reaches the OVP threshold VOVP the controller permanently switches on both the low-side mosfets and switches off both the high-side mosfets in order to protect the load. The OSC/ FAULT pin is driven high (5V) and power supply (Vcc) turn off and on is required to restart operations. The over voltage percentage is then set by the ratio between the fixed OVP threshold VOVP and the reference programmed by VID: V O VP O VP [ % ] = ----------------------------------------------------------------------- ⋅ 100 Re feren ceVo ltage ( VID ) Both Over Voltage and Under Voltage are active also during soft start (Under Voltage after than the output voltage reaches 0.6V). The reference used in this case to determine the UV thresholds is the increasing voltage driven by the 2048 soft start digital counter while the reference used for the OV threshold is the final reference programmed by the VID pins. SOFT START AND INHIBIT At start-up a ramp is generated increasing the loop reference from 0V to the final value programmed by VID in 2048 clock periods as shown in figure 10. Once the soft start begins, the reference is increased: upper and lower MOS begin to switch and the output voltage starts to increase with closed loop regulation. At the end of the digital soft start, the Power Good comparator is enabled and the PGOOD signal is then driven high (See fig. 10). The Under Voltage comparator is enabled when the reference voltage reaches 0.6V. The Soft-Start will not take place, if both VCC and VCCDR pins are not above their own turn-on thresholds. During normal operation, if any under-voltage is detected on one of the two supplies the device shuts down. Forcing the OSC/INH pin to a voltage lower than 0.6V (Typ.) disables the device: all the power mosfets and protections are turned off until the condition is removed. 15/33 L6919E Figure 10. Soft Start VCC=VCCDR Turn ON threshold VLGATEx t VOUT t PGOOD t 2048 Clock Cycles t Timing Diagram Acquisition: (CH1=LGATEx; CH2=VCC; CH3=VOUT; INPUT CAPACITOR The input capacitor is designed considering mainly the input RMS current that depends on the duty cycle as reported in figure 11. Considering the dual-phase topology, the input RMS current is highly reduced comparing with a single phase operation. Rms Current Normalized (IRMS/IOUT) Figure 11. Input RMS Current vs. Duty Cycle (D) and Driving Relationships 0.50 Single Phase Dual Phase I rms 0.25 IOUT = 2 I OUT 2 ⋅ 2D ⋅ (1 − 2D) if D < 0.5 ⋅ (2D - 1) ⋅ (2 − 2D) if D > 0.5 0.25 0.50 0.75 Duty Cycle (VOUT/VIN) It can be observed that the input rms value is one half of the single-phase equivalent input current in the worst case condition that happens for D = 0.25 and D = 0.75. The power dissipated by the input capacitance is then equal to: P RM S = ESR ⋅ ( I RM S ) 2 Input capacitor is designed in order to sustain the ripple relative to the maximum load duty cycle. To reach the high RMS value needed by the CPU power supply application and also to minimize components cost, the input capacitance is realized by more than one physical capacitor. The equivalent RMS current is simply the sum of the single capacitor's RMS current. Input bulk capacitor must be equally divided between high-side drain mosfets and placed as close as possible 16/33 L6919E to reduce switching noise above all during load transient. Ceramic capacitor can also introduce benefits in high frequency noise decoupling, noise generated by parasitic components along power path. OUTPUT CAPACITOR Since the microprocessors require a current variation beyond 50A doing load transients, with a slope in the range of tenth A/µs, the output capacitor is a basic component for the fast response of the power supply. Dual phase topology reduces the amount of output capacitance needed because of faster load transient response (switching frequency is doubled at the load connections). Current ripple cancellation due to the 180° phase shift between the two phases also reduces requirements on the output ESR to sustain a specified voltage ripple. When a load transient is applied to the converter's output, for first few microseconds the current to the load is supplied by the output capacitors. The controller recognizes immediately the load transient and increases the duty cycle, but the current slope is limited by the inductor value. The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL): ∆VOUT = ∆IOUT · ESR A minimum capacitor value is required to sustain the current during the load transient without discharge it. The voltage drop due to the output capacitor discharge is given by the following equation: 2 ∆I OUT ⋅ L ∆V OUT = ----------------------------------------------------------------------------------4 ⋅ C OUT ⋅ ( V IN ⋅ D MAX – V OUT ) Where DMAX is the maximum duty cycle value. The lower is the ESR, the lower is the output drop during load transient and the lower is the output voltage static ripple. INDUCTOR DESIGN The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current ∆IL between 20% and 30% of the maximum output current. The inductance value can be calculated with this relationship: V IN – V OUT V OUT L = ------------------------------ ⋅ --------------f S W ⋅ ∆I L V IN Where fSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter response time to a load transient. The response time is the time required by the inductor to change its current from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance required. The response time to a load transient is different for the application or the removal of the load: if during the application of the load the inductor is charged by a voltage equal to the difference between the input and the output voltage, during the removal it is discharged only by the output voltage. The following expressions give approximate response time for ∆I load transient in case of enough fast compensation network response: L ⋅ ∆I t a pplic atio n = -----------------------------V IN – V OUT L ⋅ ∆I t rem ov al = --------------V OUT The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst case is the response time after removal of the load with the minimum output voltage programmed and the maximum input voltage available. 17/33 L6919E Figure 12. Inductor ripple current vs VOUT 9 L=1.5µH, Vin=12V Inductor Ripple [A] 8 L=2µH, Vin=12V 7 6 L=3µH, Vin=12V 5 4 L=1.5µH, Vin=5V 3 L=2µH, Vin=5V 2 L=3µH, Vin=5V 1 0 0.5 1.5 2.5 3.5 Output Voltage [V] MAIN CONTROL LOOP The control loop is composed by the Current Sharing control loop and the Average Current Mode control loop. Each loop gives, with a proper gain, the correction to the PWM in order to minimize the error in its regulation: the Current Sharing control loop equalize the currents in the inductors while the Average Current Mode control loop fixes the output voltage equal to the reference programmed by VID. Figure 13 reports the block diagram of the main control loop. Figure 13. Main Control Loop Diagram L1 + PWM1 CURRENT SHARING DUTY CYCLE CORRECTION 1/5 1/5 IINFO2 IINFO1 L2 + PWM2 ERROR AMPLIFIER 4/5 + CO RO - COMP D02IN1392 REFERENCE PROGRAMMED BY VID FB ZF(S) RFB Current Sharing (CS) Control Loop Active current sharing is implemented using the information from Tran conductance differential amplifier in an average current mode control scheme. A current reference equal to the average of the read current (IAVG) is internally built; the error between the read current and this reference is converted to a voltage with a proper gain and it is used to adjust the duty cycle whose dominant value is set by the error amplifier at COMP pin (See fig. 14). The current sharing control is a high bandwidth control loop allowing current sharing even during load transients. The current sharing error is affected by the choice of external components; choose precise Rg resistor (±1% is 18/33 L6919E necessary) to sense the current. The current sharing error is internally dominated by the voltage offset of Tran conductance differential amplifier; considering a voltage offset equal to 2mV across the sense resistor, the current reading error is given by the following equation: ∆I RE AD 2mV -------------------- = ---------------------------------------I M AX R SENSE ⋅ I M AX Where ∆IREAD is the difference between one phase current and the ideal current (IMAX/2). For RSENSE = 4mΩ and IMAX = 40A the current sharing error is equal to 2.5%, neglecting errors due to Rg and Rsense mismatches. Figure 14. Current Sharing Control Loop + L1 PWM1 CURRENT SHARING DUTY CYCLE CORRECTION 1/5 1/5 + PWM2 IINFO2 IINFO1 L2 COMP VOUT D02IN1393 Average Current Mode (ACM) Control Loop The average current mode control loop is reported in figure 15. The current information IFB sourced by the FB pin flows into RFB implementing the dependence of the output voltage from the read current. The ACM control loop gain results (obtained opening the loop after the COMP pin): PWM ⋅ Z F ( s ) ⋅ ( R DROOP + Z P ( s ) ) G LO O P ( s ) = -------------------------------------------------------------------------------------------------------------------ZF (s ) 1 ( Z P ( s ) + Z L ( s ) ) ⋅ -------------- + 1 + ------------ ⋅ R FB A(s) A ( s ) Where: R s en se – R DROOP = ------------------- ⋅ R FB is the equivalent output resistance determined by the droop function; Rg – ZP(s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and the applied load Ro; – ZF(s) is the compensation network impedance; – ZL(s) is the parallel of the two inductor impedance; – A(s) is the error amplifier gain; 4 ∆V IN – PWM = --- ⋅ ------------------- · is the ACM PWM transfer function where ∆VOSC is the oscillator ramp amplitude 5 ∆V O SC and has a typical value of 3V Removing the dependence from the Error Amplifier gain, so assuming this gain high enough, the control loop gain results: 19/33 L6919E V IN ZF ( s) Rs Z P ( s ) 4 G LO O P ( s ) = – --- ⋅ ------------------- ⋅ ------------------------------------ ⋅ -------- + -------------- 5 ∆V OS C Z P ( s ) + Z L ( s ) Rg R FB With further simplifications, it results: V IN Z F ( s ) R o + R DROOP 1 + s ⋅ Co ⋅ ( R DROOP //Ro + ESR ) 4 G L OO P ( s ) = – --- ⋅ ------------------- ⋅ --------------- ⋅ -------------------------------------- ⋅ ---------------------------------------------------------------------------------------------------------------------------------RL RL 5 ∆V O SC R FB 2 L L R o + ------s ⋅ C o ⋅ --- + s ⋅ --------------- + Co ⋅ ESR + Co ⋅ ------- + 1 2 2 2 2 ⋅ Ro Considering now that in the application of interest it can be assumed that Ro>>RL; ESR<<Ro and RDROOP<<Ro, it results: V IN ZF (s ) 1 + s ⋅ Co ⋅ ( R DROOP + ESR ) 4 G L OO P ( s ) = – --- ⋅ ------------------- ⋅ --------------- ⋅ ---------------------------------------------------------------------------------------------------------------------------------RL 5 ∆V O SC R FB 2 L- + s ⋅ --------------L + C o ⋅ ESR + C o ⋅ ------ +1 s ⋅ Co ⋅ -2 2 2 ⋅ Ro The ACM control loop gain is designed to obtain a high DC gain to minimize static error and cross the 0dB axes with a constant -20dB/dec slope with the desired crossover frequency ωT. Neglecting the effect of ZF(s), the transfer function has one zero and two poles. Both the poles are fixed once the output filter is designed and the zero is fixed by ESR and the Droop resistance. To obtain the desired shape an RF-CF series network is considered for the ZF(s) implementation. A zero at ωF=1/RFCF is then introduced together with an integrator. This integrator minimizes the static error while placing the zero in correspondence with the L-C resonance a simple -20dB/dec shape of the gain is assured (See Figure 15). In fact, considering the usual value for the output filter, the LC resonance results to be at frequency lower than the above reported zero.Compensation network can be simply designed placing ωZ = ωLC and imposing the cross-over frequency ωT as desired obtaining: L C o ⋅ --2 C F = -------------------RF R FB ⋅ ∆V O SC 5 L R F = ---------------------------------- ⋅ --- ⋅ ω T ⋅ -------------------------------------------------------V IN 4 2 ⋅ ( R DROOP + ESR ) Figure 15. ACM Control Loop Gain Block Diagram (left) and Bode Diagram (right) dB IFB ZF CF RF GLOOP RFB VCOMP K REF PWM L/2 d••VIN ZF(s) VOUT ωLC Cout ESR Rout 4 VI N 1 K = --- ⋅ --------------- ⋅ ---------5 ∆Vo sc R FB ωZ ωT ω dB LAYOUT GUIDELINES Since the device manages control functions and high-current drivers, layout is one of the most important things 20/33 L6919E to consider when designing such high current applications. A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radiation and a proper connection between signal and power ground can optimize the performance of the control loops. Integrated power drivers reduce components count and interconnections between control functions and drivers, reducing the board space. Here below are listed the main points to focus on when starting a new layout and rules are suggested for a correct implementation. ■ Power Connections. These are the connections where switching and continuous current flows from the input supply towards the load. The first priority when placing components has to be reserved to this power section, minimizing the length of each connection as much as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a power plane and anyway realized by wide and thick copper traces. The critical components, i.e. the power transistors, must be located as close as possible, together and to the controller. Considering that the "electrical" components reported in figure are composed by more than one "physical" component, a ground plane or "star" grounding connection is suggested to minimize effects due to multiple connections. Figure 16. Power connections and related connections layout guidelines (same for both phases) VIN Rgate HS HGATEx PHASEx L Rgate LS COUT D LOAD CIN LGATEx PGNDx a. PCB power and ground planes areas V IN BOOTx CBOOTx HS PHASEx L +VCC LS VCC COUT D CIN SGND LOAD CVCC b. PCB small signal components placement Fig. 16a shows the details of the power connections involved and the current loops. The input capacitance (CIN), 21/33 L6919E or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are required. ■ Power Connections Related. Fig.16b shows some small signal components placement, and how and where to mix signal and power ground planes. The distance from drivers and mosfet gates should be reduced as much as possible. Propagation delay times as well as for the voltage spikes generated by the distributed inductance along the copper traces are so minimized. In fact, the further the mosfet is from the device, the longer is the interconnecting gate trace and as a consequence, the higher are the voltage spikes corresponding to the gate PWM rising and falling signals. Even if these spikes are clamped by inherent internal diodes, propagation delays, noise and potential causes of instabilities are introduced jeopardizing good system behavior. One important consequence is that the switching losses for the high side mosfet are significantly increased. For this reason, it is suggested to have the device oriented with the driver side towards the mosfets and the GATEx and PHASEx traces walking together toward the high side mosfet in order to minimize distance (see fig 17). In addition, since the PHASEx pin is the return path for the high side driver, this pin must be connected directly to the High Side mosfet Source pin to have a proper driving for this mosfet. For the LS mosfets, the return path is the PGND pin: it can be connected directly to the power ground plane (if implemented) or in the same way to the LS mosfets Source pin. GATEx and PHASEx connections (and also PGND when no power ground plane is implemented) must also be designed to handle current peaks in excess of 2A (30 mils wide is suggested). Gate resistors of few ohms help in reducing the power dissipated by the IC without compromising the system efficiency. Figure 17. Device orientation (left) and sense nets routing (right) Towards HS mosfet To LS mosfet (or sense resistor) (30 mils wide) Towards LS mosfet (30 mils wide) Towards HS mosfet (30 mils wide) To LS mosfet (or sense resistor) To regulated output The placement of other components is also important: – The bootstrap capacitor must be placed as close as possible to the BOOTx and PHASEx pins to minimize the loop that is created. – Decoupling capacitor from Vcc and SGND placed as close as possible to the involved pins. – Decoupling capacitor from VCCDR and PGND placed as close as possible to those pins. This capacitor sustains the peak currents requested by the low-side mosfet drivers. – Refer to SGND all the sensible components such as frequency set-up resistor (when present) and also the optional resistor from FB to GND used to give the positive droop effect. – Connect SGND to PGND on the load side (output capacitor) to avoid undesirable load regulation effect and to ensure the right precision to the regulation when the remote sense buffer is not used. 22/33 L6919E – An additional 100nF ceramic capacitor is suggested to place near HS mosfet drain. This helps in reducing noise. – PHASE pin spikes. Since the HS mosfet switches in hard mode, heavy voltage spikes can be observed on the PHASE pins. If these voltage spikes overcome the max breakdown voltage of the pin, the device can absorb energy and it can cause damages. The voltage spikes must be limited by proper layout, the use of gate resistors, Schottky diodes in parallel to the low side mosfets and/or snubber network on the low side mosfets, to a value lower than 26V, for 20nSec, at FSW of 600kHz max. ■ Current Sense Connections. Remote Buffer: The input connections for this components must be routed as parallel nets from the FBG/FBR pins to the load in order to compensate losses along the output power traces and also to avoid the pick-up of any common mode noise. Connecting these pins in points far from the load, will cause a non-optimum load regulation, increasing output tolerance. Current Reading: The Rg resistor has to be placed as close as possible to the ISENx and PGNDSx pins in order to limit the noise injection into the device. The PCB traces connecting these resistors to the reading point must be routed as parallel traces in order to avoid the pick-up of any common mode noise. It's also important to avoid any offset in the measurement and to get a better precision, to connect the traces as close as possible to the sensing elements, dedicated current sense resistor or low side mosfet RdsON. Moreover, when using the low side mosfet RdsON as current sense element, the ISENx pin is practically connected to the PHASEx pin. DO NOT CONNECT THE PINS TOGETHER AND THEN TO THE HS SOURCE! The device won't work properly because of the noise generated by the return of the high side driver. In this case route two separate nets: connect the PHASEx pin to the HS Source (route together with HGATEx) with a wide net (30 mils) and the ISENx pin to the LS Drain (route together with PGNDSx). Moreover, the PGNDSx pin is always connected, through the Rg resistor, to the PGND: DO NOT CONNECT DIRECTLY TO THE PGND! In this case the device won't work properly. Route anyway to the LS mosfet source (together with ISENx net). Right and wrong connections are reported in Figure 18. Symmetrical layout is also suggested to avoid any unbalance between the two phases of the converter. Figure 18. PCB layout connections for sense nets NOT CORRECT VIA to GND plane To PHASE connection CORRECT To LS Drain and Source To HS Gate and Source Wrong (left) and correct (right) connections for the current reading sensing nets. 23/33 L6919E Demo Board Description The L6919E demo board shows the operation of the device in a dual phase application. This evaluation board allows output voltage adjustability (0.800V - 1.550V) through the switches S0-S4 and high output current capability. The board has been laid out with the possibility to use up to two D2PACK mosfets for the low side switch in order to give maximum flexibility in the mosfet choice. The four layers demo board's copper thickness is of 70µm in order to minimize conduction losses considering the high current that the circuit is able to deliver. Demo board schematic circuit is reported in Figure 19. Figure 19. Demo Board Schematic Vin JP6 DZ1 GNDin JP2 JP1 VCCDR Vcc C5 D4 VCC 2 6 5 24 C8 GNDcc C7 BOOT1 C4 Q2 4 25 Q4 26 LGATE1 Q1 LGATE2 1 27 13 16 PGNDS1 14 R5 U1 VID3 S2 VID2 S1 VID1 22 PGNDS2 R1 R4 PGOOD 23 21 PGOOD VSEN 10 20 VID0 GNDCORE R3 L6919E 15 PGND VID4 R20 Q3a 28 S3 R19 ISEN2 R6 S4 C14, C23 D2 R12 ISEN1 VoutCORE R17 Q3 R13 Q1a To pin VCC L2 PHASE2 3 S0 C3 R14 PHASE1 D1 C6 UGATE2 R15 R18 D3 BOOT2 UGATE1 L1 C9,C10 C11..C13 R11 R16 R10 19 R7 FB 18 9 JP3 C24 OSC / INH 17 R21 JP4 R8 R2 C2 SGND 7 C1 JP5 R9 COMP 11 FBR 12 8 FBG FBG FBR Several jumpers allow setting different configurations for the device: JP3, JP4 and JP5 allow configuring the remote buffer as desired. Simply shorting JP4 and JP5 the remote buffer is enabled and it senses the output voltage on-board; to implement a real remote sense, leave these jumpers open and connect the FBG and FBR connectors on the demo board to the remote load. To avoid using the remote buffer, simply short all the jumpers JP3, JP4 and JP5. Local sense through the R7 is used for the regulation. The input can be configured in different ways using the jumpers JP1, JP2 and JP6; these jumpers control also the mosfet driver supply voltage. Anyway, power conversion starts from VIN and the device is supplied from V CC (See Figure 20). Figure 20. Power supply configuration To Vcc pin To HS Drains (Power Input) To BOOTx (HS Driver Supply) Vin JP6 GNDin DZ1 JP2 JP1 Vcc GNDcc 24/33 To VCCDR pin (LS Driver Supply) L6919E Two main configurations can be distinguished: Single Supply (VCC=VIN=12V) and Double Supply (VCC=12V VIN=5V or different). – Single Supply: In this case JP6 has to be completely shorted. The device is supplied with the same rail that is used for the conversion. With an additional zener diode DZ1 a lower voltage can be derived to supply the mosfets driver if Logic level mosfet are used. In this case JP1 must be left open so that the HS driver is supplied with VIN-VDZ1 through BOOTx and JP2 must be shorted to the left to use VIN or to the right to use VIN-VDZ1 to supply the LS driver through VCCDR pin. Otherwise, JP1 must be shorted and JP2 can be freely shorted in one of the two positions. – Double Supply: In this case VCC supply directly the controller (12V) while VIN supplies the HS drains for the power conversion. This last one can start indifferently from the 5V bus (Typ.) or from other buses allowing maximum flexibility in the power conversion. Supply for the mosfet driver can be programmed through the jumpers JP1, JP2 and JP6 as previously illustrated. JP6 selects now VCC or VIN depending on the requirements. Some examples are reported in the following Figures 21 and 22. Figure 21. Jumpers configuration: Double Supply Vcc = 12V HS Drains = 5V Vin = 5V HS Supply = 5V GNDin DZ1 JP6 JP2 JP1 VCCDR (LS Supply) = 5V Vcc = 12V GNDcc (a) VCC = 12V; VBOOTx = VCCDR = VIN = 5V Vcc = 12V HS Drains = 5V Vin = 5V HS Supply = 12V GNDin DZ1 JP6 JP2 JP1 VCCDR (LS Supply) = 12V Vcc = 12V GNDcc (b) VCC = VBOOTx = VCCDR = 12V; VIN = 5V Figure 22. Jumpers configuration: Single Supply Vcc = 12V HS Drains = 12V Vin = 12V HS Supply = 5.2V GNDin JP6 DZ1 6.8V JP2 JP1 VCCDR (LS Supply) = 12V Vcc = Open GNDcc (a) VCC = VIN = VCCDR = 12V; VBOOTx = 5.2V Vcc = 12V HS Drains = 12V Vin = 12V HS Supply = 12V GNDin JP6 DZ1 JP2 JP1 Vcc = Open VCCDR (LS Supply) = 12V GNDcc (b) VCC = VIN = VBOOTx = VCCDR = 12V 25/33 L6919E PCB AND COMPONENT LAYOUT Figure 23. PCB and Components Layouts (Dimensions: 10.8mm x 8.2mm) Component Side Internal SGND Plane 26/33 Internal PGND Plane Solder Side L6919E CPU Power Supply: 5 to 12VIN; 1.2VOUT; 45ADC Considering the high slope for the load transient, a high switching frequency has to be used. In addition to fast reaction, this helps in reducing output and input capacitor. Inductance value is also reduced. A switching frequency of 200kHz for each phase is then considered allowing large bandwidth for the compensation network. Considering the high output current, power conversion will start from the 12V bus. – Current Reading Network and Over Current: Since the maximum output current is IMAX = 45A, the over current threshold has been set to 45A (22.5A x 2)in the worst case (max mosfet temperature). Since the device limits the valley of the triangular ripple across the inductors, the current ripple must be considered too. Considering the inductor core saturation, a current ripple of 10A has to be considered so that the OCP threshold in worst case becomes OCPx=17A (22.5A-5A). Considering to sense the output current across the low-side mosfet RdsON, SUB85N03L-04P has 4.3mΩ max at 25°C that becomes 5.6mΩ at 100ºC considering the temperature variation; the resulting transconductance resistor Rg has to be: R d sO N 5.6m Rg = I OCPx ⋅ ------------------ = 17 ⋅ ------------- = 2.7k Ω 35 µ 35 µ (R3 to R6) – Droop function Design: Considering a voltage drop of 70mV at full load, the feedback resistor RFB has to be: 70mV R FB = ---------------- = 1k Ω (R7) 70 µ A – Inductor design: Transient response performance needs a compromise in the inductor choice value: the biggest the inductor, the highest the efficient but the worse the transient response and vice versa. Considering then an inductor value of 0.8µH, the current ripple becomes: Vin – Vout d 12 – 1.2 1.2 1 ∆I = ----------------------------- ⋅ ----------- = --------------------- ⋅ -------- ⋅ ------------- = 6.5A (L1, L2) Fsw 12 200k L 0.8 µ – Output Capacitor: Five Rubycon MBZ (2200µF / 6.3V / 12mΩ max ESR) has been used implementing a resulting ESR of 2.4mΩ resulting in an ESR voltage drop of 45A · 2.4mΩ = 108mV after a 45A load transient. – Compensation Network: A voltage loop bandwidth of 20kHz is considered to let the device fast react after load transient. The RF CF network results: R F B ⋅ ∆V O S 5 L 1K ⋅ 2 5 0.8 µ RF = ------------------------------ ⋅ --- ⋅ ω T ⋅ ------------------------------------------------------- = --------------- ⋅ --- ⋅ 20K ⋅ 2 Π ⋅ --------------------------------------------------------------- = 2.0k Ω (R8) VIN 12 4 2 ⋅ ( RDROOP + ESR ) 4 5.6m 2 ⋅ ------------- ⋅ 1.2k + 2.4m 2.7 CF 1µ L Co ⋅ --6 ⋅ 2200 µ ⋅ ------2- = 33nF (C2) 2 = -------------------- = ---------------------------------------RF 2k Further adjustments can be done on the work bench to fit the requirements and to compensate layout parasitic components. 27/33 L6919E Part List R2 R1, R20,R21 R3, R4, R5, R6 R7 R8 R9 R10 R11 R12 to R19 147k Not Mounted 2.7k 1k 1.8k 47k 510 82 0 C1 C2 C3, C4 C5, C6, C7, C8 C9, C10 C11 to C13 C14 to C18 C24 Not Mounted 22n 100n 1µ 10µ or 22µ / 16V 1800µ / 16V 2200µ / 6.3V 100n SMD 0805 SMD 0805 SMD 0805 Ceramic SMD 1206 TDK Multilayer Ceramic SMD 1206 Rubycon MBZ Radial 10x23 Rubycon MBZ Radial 10x20 SMD 0805 L1, L2 U1 0.8µ L6919E 77121 - 4Turns STMicroelectronics SO28 Q1, Q3 Q2, Q4 SUB85N03-04P SUB70N03-09BP Vishay Vishay D2PACK D2PACK D1, D2 D3, D4 STPS340U 1N4148 STMicroelectronics STMicroelectronics SMB SOT23 S0,S4 S1,S2,S3 Short Open 1% SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 1% 1% 1% STATIC PERFORMANCES Figure 24 shows the demo board measured efficiency versus load current in steady state conditions without airflow at ambient temperature. Figure 24. System Efficiency 90 85 Efficiency [%] 80 75 70 c 65 60 55 50 0 5 10 15 20 25 Output Current [A] 28/33 30 35 40 45 L6919E Figure 25 shows the mosfets temperature versus output current in steady state condition without any air-flow or heat sink. It can be observed that the mosfets are under 100ºC in any conditions. Load regulation is also reported from 10A to 45A. Figure 25. Mosfet Temperature and Load Regulation 1.250 90 80 High-side MOS Q2 1.240 High-side MOS Q4 1.230 Low -side MOS Q1 70 Vout [V] MOS Temperature [ o C] 100 Low -side MOS Q3 60 50 1.220 1.210 1.200 1.190 40 1.180 30 1.170 20 0 0 5 10 15 20 25 30 35 Output Current [A] 40 45 5 10 15 20 25 30 35 40 45 Output Current [A] DYNAMIC PERFORMANCES Figure 26 shows the system response to a load transient from 3A to 45A. The output voltage is contained in the ±50mV range. Additional output capacitors can help in reducing the initial voltage spike mainly due to the ESR. Figure 26. 3A to 45A Load Transient Response Figure 27 shows the system response to a VID transient from 1.200V to 0.800V and vice versa at minimum load (3A). Figure 27. Dynamic VID Response 29/33 L6919E DEMO BOARD ENHANCEMENTS: 1.200V / 52A CPU Power Supply Considering the same application schematic, minor changes can be done to achieve the 52A thermal output current required by AMD Hammer processor core. Part list has been modified as follow: Part List R2 R1, R20,R21 R3, R4, R5, R6 R7 R8 R9 R10 R11 R12 to R19 147k Not Mounted 1.5k 1k 1.8k 47k 510 82 0 C1 C2 C3, C4 C5, C6, C7, C8 C9, C10 C11 to C13 C14 to C18 C24 Not Mounted 10n 100n 1µ 10µ or 22µ / 16V 1800µ / 16V 2200µ / 6.3V 100n SMD 0805 SMD 0805 SMD 0805 Ceramic SMD 1206 TDK Multilayer Ceramic SMD 1206 Rubycon MBZ Radial 10x23 Rubycon MBZ Radial 10x20 SMD 0805 L1, L2 U1 0.8µ L6919E 77121 - 4Turns STMicroelectronics SO28 Q1, Q1a, Q3, Q3a Q2, Q4 SUB85N03-04P SUB70N03-09BP Vishay-Siliconix Vishay-Siliconix D2PACK D2PACK D1, D2 D3, D4 STPS340U 1N4148 STMicroelectronics STMicroelectronics SMB SOT23 S0,S4 S1,S2,S3 Short Open 1% SMD 0806 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 1% 1% 1% STATIC PERFORMANCES Figure 28 shows the demo board measured efficiency versus load current in steady state conditions without airflow at ambient temperature. Figure 28. System Efficiency 90 85 80 Efficiency [%] 75 70 65 60 55 50 45 40 0 5 10 15 20 25 30 35 Output Current [A] 30/33 40 45 50 55 60 L6919E Figure 29 shows the mosfets temperature versus output current in steady state condition without any air-flow or heat sink. It can be observed that the mosfets are under 105°C in any conditions. Load regulation is also reported from 10A to 55A. Figure 29. Mosfet Temperature and Load Regulation. 105 High-side M OS Q2 95 High-side M OS Q4 85 Lo w-side M OS Q1 75 Lo w-side M OS Q3 65 1.235 1.225 1.215 Vout [V] MOS Temperature [ oC] 115 1.205 1.195 55 1.185 45 1.175 35 1.165 25 1.155 0 5 10 15 20 25 30 35 40 45 50 55 60 Output Current [A] 0 5 10 15 20 25 30 35 40 45 50 55 60 Output Current [A] Figure 30 shows the system response to a load transient from 3A to 45A. The output voltage is contained in the ±50mV range. Additional output capacitors can help in reducing the initial voltage spike mainly due to the ESR. Figure 30. 3A to 45A Load Transient Response Figure 31 shows the system response to a VID transient from 1.200V to 0.800V and vice versa at minimum load (3A). Figure 31. Dynamic VID Response 31/33 L6919E mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 2.65 MAX. 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 c1 0.020 45° (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 S 32/33 OUTLINE AND MECHANICAL DATA 8 ° (max.) SO28 L6919E Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. 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