STMICROELECTRONICS M41T00S

M41T00S
Serial access real-time clock
Features
■
2.0 to 5.5 V clock operating voltage
■
Counters for seconds, minutes, hours, day,
date, month, year, and century
■
Software clock calibration
■
Automatic switchover and deselect circuitry
(fixed reference)
– VCC = 2.7 to 5.5 V
2.5V ≤ VPFD ≤ 2.7 V
■
Serial interface supports I2C bus (400 kHz
protocol)
■
Low operating current of 300 µA
■
Oscillator stop detection
■
Battery or SuperCap™ backup
■
Operating temperature of –40 to 85°C
■
Ultra-low battery supply current of 1 µA
May 2008
8
1
SO8 (M)
8-pin SOIC
Rev 4
1/26
www.st.com
1
Contents
M41T00S
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
3
2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1
Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.2
Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.3
Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.4
Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.5
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.1
Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.2
Oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.3
Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.4
Preferred initial power-on default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6
Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/26
M41T00S
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
TIMEKEEPER® register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Preferred default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SO8 – 8-lead plastic small outline (150 mils body width), package mechanical data. . . . . 23
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3/26
List of figures
M41T00S
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
4/26
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
8-pin SOIC (M) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Alternative READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SO8 – 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
M41T00S
1
Description
Description
The M41T00S Serial Access TIMEKEEPER® SRAM is a low power serial RTC with a builtin 32.768 kHz oscillator (external crystal controlled). Eight bytes of the SRAM (see Table 2
on page 13) are used for the clock/calendar function and are configured in binary coded
decimal (BCD) format. Addresses and data are transferred serially via a two line,
bidirectional I2C interface. The built-in address register is incremented automatically after
each WRITE or READ data byte.
The M41T00S has a built-in power sense circuit which detects power failures and
automatically switches to the battery supply when a power failure occurs. The energy
needed to sustain the clock operations can be supplied by a small lithium button supply
when a power failure occurs. The eight clock address locations contain the century, year,
month, date, day, hour, minute, and second in 24-hour BCD format. Corrections for 28, 29
(leap year - valid until year 2100), 30 and 31 day months are made automatically.
The M41T00S is supplied in an 8-pin SOIC.
Figure 1.
Logic diagram
VCC VBAT
XI
XO
M41T00S
FT/OUT
SCL
SDA
VSS
AI09165
Table 1.
Signal names
XI
Oscillator input
XO
Oscillator output
FT/OUT
Frequency test / output driver (open drain)
SDA
Serial data input/output
SCL
Serial clock input
VBAT
Battery supply voltage
VCC
Supply voltage
VSS
Ground
5/26
Description
Figure 2.
M41T00S
8-pin SOIC (M) connections
1
8
7
2
3 M41T00S 6
4
5
XI
XO
VBAT
VSS
VCC
FT/OUT(1)
SCL
SDA
AI09166
1. Open drain output
Figure 3.
Block diagram
REAL TIME CLOCK
CALENDAR
32KHz
OSCILLATOR
CRYSTAL
OSCILLATOR FAIL
CIRCUIT
RTC &
CALIBRATION
FREQUENCY TEST
SDA
FT
(1)
FT/OUT
2
I C
INTERFACE
SCL
WRITE
PROTECT
VCC
OUTPUT DRIVER
OUT
INTERNAL
POWER
VBAT
VSO
COMPARE
VPFD
AI09168
1. Open drain output
6/26
M41T00S
2
Operation
Operation
The M41T00S clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 8 bytes
contained in the device can then be accessed sequentially in the following order:
1.
Seconds register
2.
Minutes register
3.
Century/hours register
4.
Day register
5.
Date register
6.
Month register
7.
Year register
8.
Calibration register
The M41T00S clock continually monitors VCC for an out-of-tolerance condition. Should VCC
fall below VPFD, the device terminates an access in progress and resets the device address
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from a an out-of-tolerance system. Once VCC falls below the
switchover voltage (VSO), the device automatically switches over to the battery and powers
down into an ultra-low current mode of operation to preserve battery life. If VBAT is less than
VPFD, the device power is switched from VCC to VBAT when VCC drops below VBAT. If VBAT is
greater than VPFD, the device power is switched from VCC to VBAT when VCC drops below
VPFD. Upon power-up, the device switches from battery to VCC at VSO. When VCC rises
above VPFD, it will recognize the inputs.
For more information on battery storage life refer to Application Note AN1012.
2.1
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a
bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must
be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●
Data transfer may be initiated only when the bus is not busy.
●
During data transfer, the data line must remain stable whenever the clock line is high.
●
Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain high.
2.1.2
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
7/26
Operation
2.1.3
M41T00S
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
2.1.4
Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
2.1.5
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level
put on the bus by the receiver whereas the master generates an extra acknowledge related
clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge
after the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case the transmitter must leave the data line high to enable the master to generate the
STOP condition.
Figure 4.
Serial bus data transfer sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
8/26
M41T00S
Figure 5.
Operation
Acknowledgement sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
MASTER
1
DATA OUTPUT
BY TRANSMITTER
2
8
MSB
9
LSB
DATA OUTPUT
BY RECEIVER
AI00601
2.2
READ mode
In this mode the master reads the M41T00S slave after setting the slave address (see
Figure 7 on page 10). Following the WRITE mode control bit (R/W=0) and the acknowledge
bit, the word address 'An' is written to the on-chip address pointer. Next the START condition
and slave address are repeated followed by the READ mode control bit (R/W=1). At this
point the master transmitter becomes the master receiver. The data byte which was
addressed will be transmitted and the master receiver will send an acknowledge bit to the
slave transmitter. The address pointer is only incremented on reception of an acknowledge
clock. The M41T00S slave transmitter will now place the data byte at address An+1 on the
bus, the master receiver reads and acknowledges the new byte and the address pointer is
incremented to “An+2.”
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 06h). The update will resume due to a stop condition or when the
pointer increments to any non-clock address (07h).
Note:
This is true both in READ mode and WRITE mode.
An alternate READ mode may also be implemented whereby the master reads the
M41T00S slave without first writing to the (volatile) address pointer. The first address that is
read is the last one stored in the pointer (see Figure 8 on page 10).
Slave address location
R/W
SLAVE ADDRESS
START
1
A
LSB
MSB
Figure 6.
1
0
1
0
0
0
AI00602
9/26
Operation
R/W
DATA n+1
ACK
DATA n
ACK
BUS ACTIVITY:
S
ACK
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
READ mode sequence
START
Figure 7.
M41T00S
SLAVE
ADDRESS
STOP
SLAVE
ADDRESS
P
AI00899
NO ACK
DATA n+X
R/W
SLAVE
ADDRESS
2.3
DATA n+X
P
NO ACK
BUS ACTIVITY:
DATA n+1
ACK
DATA n
ACK
S
ACK
SDA LINE
ACK
BUS ACTIVITY:
MASTER
STOP
Alternative READ mode sequence
START
Figure 8.
AI00895
WRITE mode
In this mode the master transmitter transmits to the M41T00S slave receiver. Bus protocol is
shown in Figure 9. Following the START condition and slave address, a logic '0' (R/W=0) is
placed on the bus and indicates to the addressed device that word address “An” will follow
and is to be written to the on-chip address pointer. The data word to be written to the
memory is strobed in next and the internal address pointer is incremented to the next
address location on the reception of an acknowledge clock. The M41T00S slave receiver
will send an acknowledge clock to the master transmitter after it has received the slave
address see Figure 6 on page 9 and again after it has received the word address and each
data byte.
10/26
M41T00S
2.4
Operation
Data retention mode
With valid VCC applied, the M41T00S can be accessed as described above with READ or
WRITE cycles. Should the supply voltage decay, the power input will be switched from the
VCC pin to the battery when VCC falls below the battery backup switchover voltage (VSO). At
this time the clock registers will be maintained by the attached battery supply. On power-up,
when VCC returns to a nominal value, write protection continues for tREC.
For a further, more detailed review of lifetime calculations, please see Application Note
AN1012.
SLAVE
ADDRESS
DATA n+X
P
ACK
DATA n+1
ACK
BUS ACTIVITY:
DATA n
ACK
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
STOP
WRITE mode sequence
START
Figure 9.
AI00591
11/26
Clock operation
3
M41T00S
Clock operation
The 8-byte register map (see Table 2) is used to both set the clock and to read the date and
time from the clock, in a binary coded decimal format. Seconds, minutes, and hours are
contained within the first three registers.
Bits D6 and D7 of clock register 02h (century/hours register) contain the CENTURY
ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle,
either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial
state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of Register 03h contain
the Day (day of week). Registers 04h, 05h, and 06h contain the date (day of month), month
and years. The eighth clock register is the calibration register (this is described in the clock
calibration section). Bit D7 of register 00h contains the STOP bit (ST). Setting this bit to a '1'
will cause the oscillator to stop. If the device is expected to spend a significant amount of
time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0'
the oscillator restarts within one second.
The seven clock registers may be read one byte at a time, or in a sequential block. The
calibration register (address location 07h) may be accessed independently. Provision has
been made to assure that a clock update does not occur while any of the seven clock
addresses are being read. If a clock address is being read, an update of the clock registers
will be halted. This will prevent a transition of data during the READ.
3.1
Clock registers
The M41T00S offers 8 internal registers which contain clock and calibration data. These
registers are memory locations which contain external (user accessible) and internal copies
of the data (usually referred to as BiPORT™ TIMEKEEPER cells). The external copies are
independent of internal functions except that they are updated periodically by the
simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain
will be reset upon the completion of a WRITE to any clock address.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 06h). The update will resume either due to a stop condition or when
the pointer increments to any non-clock address (07h).
Clock registers store data in BCD. The calibration register stores data in binary format.
12/26
M41T00S
Table 2.
Clock operation
TIMEKEEPER® register map
Addr
Function/range BCD format
D7
D6
D5
D4
D3
D2
D1
D0
00h
ST
10 seconds
Seconds
Seconds
00-59
01h
OF
10 minutes
Minutes
Minutes
00-59
02h
CEB
CB
Hours (24-hour format)
Century/hours
0-1/00-23
03h
0
0
Day
01-7
04h
0
0
Date: day of month
Date
01-31
05h
0
0
Month
Month
01-12
Year
Year
00-99
06h
07h
10 hours
0
0
10 date
0
10M
10 years
OUT
FT
S
0
Day of week
Calibration
Calibration
Keys:
0 = must be set to '0'
CB = century bit
CEB = century enable bit
FT = frequency test bit
OF = oscillator fail bit
OUT = output level
S = sign bit
ST = stop bit
3.2
Calibrating the clock
The M41T00S is driven by a quartz-controlled oscillator with a nominal frequency of 32,768
Hz. The devices are tested not exceed ±35 ppm (parts per million) oscillator frequency error
at 25oC, which equates to about ±1.53 minutes per month (see Figure 10 on page 15).
When the calibration circuit is properly employed, accuracy improves to better than ±2 ppm
at 25°C.
The oscillation rate of crystals changes with temperature. The M41T00S design employs
periodic counter correction. The calibration circuit adds or subtracts counts from the
oscillator divider circuit at the divide by 256 stage, as shown in Figure 11 on page 15. The
number of times pulses which are blanked (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five calibration bits found in the
calibration register. Adding counts speeds the clock up, subtracting counts slows the clock
down.
The calibration bits occupy the five lower order bits (D4-D0) in the calibration register 07h.
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a
Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs
within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one
second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on.
13/26
Clock operation
M41T00S
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration register (see Figure 11 on page 15).
Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in
the calibration byte would represent +10.7 or –5.35 seconds per month which corresponds
to a total range of +5.5 or –2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M41T00S may
require.
The first involves setting the clock, letting it run for a month and comparing it to a known
accurate reference and recording deviation over a fixed period of time. Calibration values,
including the number of seconds lost or gained in a given period, can be found in application
note AN934, “TIMEKEEPER® calibration.” This allows the designer to give the end user the
ability to calibrate the clock as the environment requires, even if the final product is
packaged in a non-user serviceable enclosure. The designer could provide a simple utility
that accesses the calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use
of the FT/OUT pin. The pin will toggle at 512Hz, when the Stop bit (ST, D7 of 00h) is '0,' and
the Frequency Test bit (FT, D6 of 07h) is '1.'
Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at
the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10 (XX001010) to be loaded into the calibration byte
for correction. Note that setting or changing the Calibration Byte does not affect the
frequency test output frequency.
The FT/OUT pin is an open drain output which requires a pull-up resistor to VCC for proper
operation. A 500-10k resistor is recommended in order to control the rise time. The FT bit is
cleared on power-down.
14/26
M41T00S
Clock operation
Figure 10. Crystal accuracy across temperature
Frequency (ppm)
20
0
–20
–40
–60
ΔF = K x (T – T )2
O
F
–80
2
2
K = –0.036 ppm/°C ± 0.006 ppm/°C
–100
TO = 25°C ± 5°C
–120
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI07888
Figure 11. Clock calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
3.2.1
Century bit
Bits D7 and D6 of Clock Register 02h contain the CENTURY ENABLE bit (CEB) and the
CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or
from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle.
3.2.2
Oscillator fail detection
If the Oscillator Fail bit (OF) is internally set to '1,' this indicates that the oscillator has either
stopped, or was stopped for some period of time and can be used to judge the validity of the
clock and date data.
15/26
Clock operation
M41T00S
In the event the OF bit is found to be set to '1' at any time other than the initial power-up, the
STOP bit (ST) should be written to a '1,' then immediately reset to '0.' This will restart the
oscillator.
The following conditions can cause the OF bit to be set:
●
The first time power is applied (defaults to a '1' on power-up).
●
The voltage present on VCC is insufficient to support oscillation.
●
The ST bit is set to '1.'
●
External interference of the crystal.
The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have
run for at least 4 seconds before attempting to reset the OF Bit to '0.'
3.2.3
Output driver pin
When the FT bit is not set, the FT/OUT pin becomes an output driver that reflects the
contents of D7 of the calibration register. In other words, when D7 (OUT Bit) and D6 (FT bit)
of address location 07h are a '0,' then the FT/OUT pin will be driven low.
Note:
The FT/OUT pin is an open drain which requires an external pull-up resistor.
3.2.4
Preferred initial power-on default
Upon initial application of power to the device, the ST and FT bits are set to a '0' state, and
the OF and OUT bits will be set to a '1.' All other register bits will initially power-on in a
random state (see Table 3).
Table 3.
Preferred default values
Condition
Initial power-up(1)
Subsequent power-up (with battery
1. State of other control bits undefined.
2. UC = Unchanged
16/26
backup)(2)
ST
Out
FT
OF
0
1
0
1
UC
UC
0
UC
M41T00S
4
Maximum ratings
Maximum ratings
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4.
Absolute maximum ratings
Sym
Parameter
TSTG
Storage temperature (VCC off, oscillator off)
VCC
Supply voltage
TSLD(1)
VIO
Lead solder temperature for 10 seconds
Input or output voltages
Value
Unit
–55 to 125
°C
–0.3 to 7
V
260
°C
–0.3 to VCC+0.3
V
IO
Output current
20
mA
PD
Power dissipation
1
W
1. Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C for greater than 30
seconds).
Caution:
Negative undershoots below –0.3 volts are not allowed on any pin while in the battery
backup mode
17/26
DC and AC parameters
5
M41T00S
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC Characteristic
tables are derived from tests performed under the Measurement Conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 5.
Operating and AC measurement conditions
Parameter
Note:
M41T00S
Supply voltage (VCC)
2.7 to 5.5 V
Ambient operating temperature (TA)
–40 to 85°C
Load capacitance (CL)
100 pF
Input rise and fall times
≤ 50 ns
Input pulse voltages
0.2VCC to 0.8 VCC
Input and output timing ref. voltages
0.3VCC to 0.7 VCC
Output Hi-Z is defined as the point where data is no longer driven.
Figure 12. AC measurement I/O waveform
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02568
Table 6.
Capacitance
Parameter(1)(2)
Symbol
CIN
COUT(3)
tLP
Min
Max
Unit
Input capacitance
7
pF
Output capacitance
10
pF
Low-pass filter input time constant (SDA and SCL)
50
ns
1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C, f = 1 MHz
3. Outputs deselected.
18/26
M41T00S
Table 7.
DC and AC parameters
DC characteristics
Sym
ILI
Input leakage current
ILO
Output leakage current
ICC1
Supply current
ICC2
Supply current (standby)
VIL
Input low voltage
VIH
Input high voltage
VOL
Test condition(1)
Parameter
Max
Unit
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
±1
μA
±1
μA
Switch freq = 400 kHz
300
μA
SCL = 0Hz
All Inputs
≥ VCC – 0.2 V
≤ VSS + 0.2 V
70
μA
–0.3
0.3VCC
V
0.7VCC
Output low voltage
(2)
Output low voltage (open drain)
Pull-up supply voltage (open drain)
VBAT(3)
Backup supply voltage
IBAT
Battery supply current
Min
Typ
VCC + 0.3
V
IOL = 3.0mA
0.4
V
IOL = 10mA
0.4
V
FT/OUT
5.5
V
3.5(4)
V
1
µA
Max
Units
kHz
60(3)
kΩ
2.0
TA = 25°C, VCC = 0 V
Oscillator ON, VBAT = 3 V
0.6
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5 V (except where noted).
2. For FT/OUT pin (open drain).
3. STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply.
4. For rechargeable backup, VBAT (max) may be considered to be VCC.
Table 8.
Sym
fO
Crystal electrical characteristics
Parameter(1)(2)
Resonant frequency
RS
Series resistance
CL
Load capacitance
Min
Typ
32.768
12.5
pF
1. Externally supplied if using the SO8 package. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning
Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS
can be contacted at [email protected] or http://www.kdsj.co.jp for further information on this crystal type.
2. Load capacitors are integrated within the M41T00S. Circuit board layout considerations for the 32.768 kHz crystal of
minimum trace lengths and isolation from RF generating signals should be taken into account.
3. For applications requiring backup supply operation below 2.5 V, RS (max) should be considered 40 kΩ.
Figure 13. Power down/up mode AC waveforms
VCC
VSO
tPD
SDA
SCL
trec
DON'T CARE
AI00596
19/26
DC and AC parameters
Table 9.
M41T00S
Power down/up AC characteristics
Parameter(1)(2)
SCL and SDA at VIH before power down
Symbol
tPD
trec
Min
0
SCL and SDA at VIH after power up
Typ
Max
Unit
nS
10
µS
1. VCC fall time should not exceed 5 mV/µs.
2. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5 V (except where noted).
Table 10.
Power down/up trip points DC characteristics
Parameter(1)(2)
Sym
VPFD
VSO
Power-fail deselect
Min
Typ
Max
Unit
2.5
2.6
2.7
V
Hysteresis
Battery backup switchover voltage
(VCC < VBAT; VCC < VPFD)
25
mV
VBAT < VPFD
VBAT
V
VBAT > VPFD
VPFD
V
40
mV
Hysteresis
1. All voltages referenced to VSS.
2. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5 V (except where noted).
Figure 14. Bus timing requirements sequence
SDA
tBUF
tHD:STA
tHD:STA
tR
tF
SCL
tHIGH
P
S
tLOW
tSU:DAT
tHD:DAT
tSU:STA
SR
tSU:STO
P
AI00589
20/26
M41T00S
DC and AC parameters
Table 11.
AC characteristics
Parameter(1)
Sym
Min
0
Typ
Max
Units
400
kHz
fSCL
SCL clock frequency
tLOW
Clock low period
1.3
µs
tHIGH
Clock high period
600
ns
tR
SDA and SCL rise time
300
ns
tF
SDA and SCL fall time
300
ns
tHD:STA
START condition hold time
(after this period the first clock pulse is generated)
600
ns
tSU:STA
START condition setup time
(only relevant for a repeated start condition)
600
ns
100
ns
0
µs
tSU:DAT(2) Data setup time
tHD:DAT
Data hold time
tSU:STO
STOP condition setup time
600
ns
Time the bus must be free before a new
transmission can start
1.3
µs
tBUF
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5 V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling
edge of SCL.
21/26
Package mechanical information
6
M41T00S
Package mechanical information
In order to meet environmental requirements, ST (also) offers these devices in ECOPACK®
packages. ECOPACK® packages are lead-free. The category of second Level Interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label. ECOPACK is an ST trademark. ECOPACK specifications are available at:
www.st.com.
Figure 15. SO8 – 8-lead plastic small package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
1
E
A1
L
L1
SO-A
Note:
22/26
Drawing is not to scale.
M41T00S
Table 12.
Package mechanical information
SO8 – 8-lead plastic small outline (150 mils body width), package mechanical data
mm
inches
Symb
Typ
Min
A
Max
Typ
Min
1.75
Max
0.069
A1
0.10
A2
1.25
B
0.28
0.48
0.011
0.019
C
0.17
0.23
0.007
0.009
4.80
5.00
0.189
0.197
D
4.90
0.25
0.004
0.010
0.049
E
6.00
5.80
6.20
0.228
0.244
E1
3.90
3.80
4.00
0.150
0.157
e
1.27
0.050
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
0°
8°
L1
1.04
0.041
k
0°
N
8
ccc
8°
8
0.10
0.004
23/26
Part numbering
7
M41T00S
Part numbering
Table 13.
Ordering information scheme
Example:
M41T
00S
M
6
E
Device type
M41T
Supply voltage and write protect voltage
00S = VCC = 2.7 to 5.5 V
Package
M = SO8
Temperature range
6 = –40°C to 85°C
Shipping method
E = ECOPACK® package, tubes
F = ECOPACK® package, tape & reel
For other options, or for more information on any aspect of this device, please contact the ST sales office nearest
you.
24/26
M41T00S
8
Revision history
Revision history
Table 14.
Document revision history
Date
Revision
Changes
10-Feb- 2004
0.1
First draft
20-Feb-2004
0.2
Update characteristics (Table 9, 10, 5, 7, 13)
14-Apr-2004
1.0
Product promoted; reformatted; update characteristics, including
Lead-free package information (Figure 4, 10; Table 4, 11, 13)
05-May-2004
1.1
Update DC characteristics (Table 7)
16-Jun-2004
1.2
Added package shipping (Table 13)
13-Sep-2004
2.0
Update maximum ratings (Table 4)
26-Nov-2004
3.0
Promote document; update characteristics; remove references to
SOX18 package (cover page, Figure 4; Table 14)
14-May-2008
4
Reformatted document; updated Section 6, Figure 1, 15, Table 1, 4,
12, 13.
25/26
M41T00S
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