STMICROELECTRONICS M41ST84WMQ6F

M41ST84W
3.0/3.3V I2C Serial RTC
with Supervisory Functions
KEY FEATURES
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AUTOMATIC BATTERY SWITCHOVER and
DESELECT
– Power-fail Deselect, VPFD = 2.60V (nom)
– Switchover, VSO = 2.50V (nom)
400kHz I2C SERIAL INTERFACE
3.0/3.3V OPERATING VOLTAGE
– VCC = 2.7 to 3.6V
ULTRA-LOW BATTERY SUPPLY CURRENT
of 500nA (max)
RoHS COMPLIANCE
Lead-free components are compliant with the
RoHS Directive.
Figure 1. 16-pin SOIC Package
16
1
SO16 (MQ)
Serial RTC Features
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400kHz I2C
44 Bytes of General Purpose NVRAM
Counters for:
– Seconds, Minutes, Hours, Day, Date,
Month, and Year
– Century
– 10ths/100ths of Seconds
– Clock Calibration register allows
compensation for crystal variations over
temperature
Programmable Alarm with Interrupt
– Functions during Battery Back-up Mode
Power-down Timestamp (HT Bit)
2.5 to 5.5V Oscillator Operating Voltage
32KHz Oscillator with Integrated Load
Capacitance (12.5pF)
Microprocessor Supervisory Features
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Programmable Watchdog Timer
– 62.5ms to 128s time-out period
Power-on Reset/Low Voltage Detect Output
PFI/PFO with 1.25V Reference
NVRAM Supervisory Features
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■
Non-volatizes External LPSRAM
– Automatically switches to back-up battery
and deselects (write-protects) external
LPSRAM via chip-enable gate
– Power-fail deselect (write protect) voltage,
VPFD = 2.60V (nom)
– Switchover , VSO = 2.50V (nom)
Battery Low flag
Other Features
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Programmable Squarewave Generator (1Hz
to 32KHz)
–40°C to +85°C Operation
Packaged in a 16-lead SOIC
Rev 7.0
January 2006
1/29
M41ST84W
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Serial RTC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Microprocessor Supervisory Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 16-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
NVRAM Supervisory Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Other Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2.
Table 1.
Figure 3.
Figure 4.
Figure 5.
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
......
......
......
......
......
.....4
.....4
.....5
.....5
.....6
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Slave Address Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11.Alternate READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 12.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-down Time-Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Setting Alarm Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 15.Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Alarm Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 16.Back-Up Mode Alarm Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/29
M41ST84W
Reset Input (RSTIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17.RSTIN Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-fail INPUT/OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
trec Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. trec Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 10. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 18.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 13. Crystal Electrical Characteristics (Externally Supplied) . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 20.SO16 – 16-lead Plastic Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 15. SO16 – 16-lead Plastic Small Outline, Package Mechanical Data . . . . . . . . . . . . . . . . . 26
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 17. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
M41ST84W
SUMMARY DESCRIPTION
The M41ST84W Serial Real-Time Clock is built in
a low power CMOS SRAM process. It has a 64byte memory space with 44 bytes of NVRAM and
20 memory-mapped RTC registers (see Table
3., page 14). The RTC registers are configured in
binary coded decimal (BCD) format.
A built-in, low power 32.768kHz oscillator (external
crystal controlled) provides the time base for the
timekeeping and calendar functions.
The basic clock/calendar functions are handled by
the first eight RTC registers, while the other twelve
bytes provide status/control for the Alarm, Watchdog, and Square Wave functions.
Addresses and data are transferred serially via the
two line, bi-directional I2C interface. The built-in
address register is incremented automatically after each WRITE or READ data byte.
The M41ST84W has a built-in power sense circuit
which detects power failures and automatically
switches to the battery supply when a power failure occurs. The energy needed to sustain the
SRAM and clock operations can be supplied by a
small lithium button-cell supply when a power failure occurs. Functions available to the user include
a non-volatile, time-of-day clock/calendar, Alarm
interrupts, Watchdog Timer and programmable
Square Wave output. Other features include a
Power-On Reset as well as an additional input
(RSTIN) which can also generate an output Reset
(RST). The eight clock address locations contain
the century, year, month, date, day, hour, minute,
second and tenths/hundredths of a second in 24
hour BCD format. Corrections for 28, 29 (leap year
- valid until year 2100), 30 and 31 day months are
made automatically.
The M41ST84W is supplied in a 16-lead SOIC
package.
Figure 2. Logic Diagram
Table 1. Signal Names
VCC
XI
Oscillator Input
XO
Oscillator Output
IRQ/FT/OUT
Interrupt/Frequency Test/Out
Output (Open Drain)
PFI
Power Fail Input
PFO
Power Fail Output
RST
Reset Output (Open Drain)
IRQ/FT/OUT
RSTIN
Reset Input
SQW
SCL
Serial Clock Input
SDA
Serial Data Input/Output
SQW
Square Wave Output
WDI
Watchdog Input
VCC
Supply Voltage
VBAT
Battery Supply Voltage
VSS
Ground
NC
No Connect
VBAT
XI
XO
RST
SCL
SDA
M41ST84W
RSTIN
PFO
WDI
PFI
VSS
4/29
AI03677
M41ST84W
Figure 3. 16-pin SOIC Connections
XI
XO
RST
WDI
RSTIN
PFO
VBAT
VSS
16
1
15
2
14
3
13
4
M41ST84W
12
5
11
6
10
7
8
9
VCC
NC
IRQ/FT/OUT
NC
PFI
SQW
SCL
SDA
AI03678
Figure 4. Block Diagram
REAL TIME CLOCK
CALENDAR
SDA
44 BYTES
USER RAM
400kHz
I2C
INTERFACE
SCL
RTC w/ALARM
& CALIBRATION
WATCHDOG
32KHz
OSCILLATOR
Crystal
SQUARE WAVE
WDI
VCC
AF
WDF
IRQ/FT/OUT(1)
SQW
VINT
VBAT
VBL= 2.5V
COMPARE
VSO = 2.5V
COMPARE
VPFD = 2.65V
COMPARE
BL
POR
RST(1)
RSTIN
PFI
COMPARE
PFO
1.25V
(Internal)
AI03931
Note: 1. Open drain output
5/29
M41ST84W
Figure 5. Hardware Hookup
Regulator
Unregulated
Voltage
VIN
M41ST84W
VCC
VCC
IRQ/FT/OUT
To INT
XI
32KHz(1)
XTAL
XO
From MCU
SDA
SCL
RST
WDI
SQW
To RST
To LED Display
RSTIN
R1
VBAT
PFI
R2
VSS
PFO
To NMI
AI03680
Note: 1. User-supplied crystal
6/29
M41ST84W
OPERATING MODES
The M41ST84W clock operates as a slave device
on the serial bus. Access is obtained by implementing a start condition followed by the correct
slave address (D0h). The 64 bytes contained in
the device can then be accessed sequentially in
the following order:
1.
Tenths/Hundredths of a Second Register
2.
Seconds Register
3.
Minutes Register
4.
Century/Hours Register
5.
Day Register
6.
Date Register
7.
Month Register
8.
Year Register
9.
Control Register
10.
Watchdog Register
11 - 16. Alarm Registers
17 - 19. Reserved
20.
Square Wave Register
21 - 64. User RAM
The M41ST84W clock continually monitors VCC
for an out-of tolerance condition. Should VCC fall
below VPFD, the device terminates an access in
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from a an out-of-tolerance system.
When VCC falls below VSO, the device automatically switches over to the battery and powers
down into an ultra low current mode of operation to
conserve battery life. As system power returns and
VCC rises above VSO , the battery is disconnected,
and the power supply is switched to external VCC.
Write protection continues until VCC reaches
VPFD(min) plus trec (min).
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus Characteristics
The bus is intended for communication between
different ICs. It consists of two lines: a bi-directional data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the
bus is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High.
–
Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is
called “transmitter”, the receiving device that gets
the message is called “receiver”. The device that
controls the message is called “master”. The devices that are controlled by the master are called
“slaves”.
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low during the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
7/29
M41ST84W
Figure 6. Serial Bus Data Transfer Sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
Figure 7. Acknowledgement Sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCLK FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
1
MSB
2
8
9
LSB
DATA OUTPUT
BY RECEIVER
AI00601
8/29
M41ST84W
Figure 8. Bus Timing Requirements Sequence
SDA
tBUF
tHD:STA
tHD:STA
tF
tR
SCL
tHIGH
P
S
tLOW
tSU:DAT
tHD:DAT
tSU:STA
SR
tSU:STO
P
AI00589
Table 2. AC Characteristics
Parameter(1)
Symbol
fSCL
SCL Clock Frequency
tBUF
Time the bus must be free before a new transmission can start
tF
tHD:DAT(2)
Min
Max
Unit
0
400
kHz
1.3
SDA and SCL Fall Time
300
ns
0
µs
START Condition Hold Time
(after this period the first clock pulse is generated)
600
ns
tHIGH
Clock High Period
600
ns
tLOW
Clock Low Period
1.3
µs
tHD:STA
tR
Data Hold Time
µs
SDA and SCL Rise Time
300
ns
tSU:DAT
Data Setup Time
100
ns
tSU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
600
ns
tSU:STO
STOP Condition Setup Time
600
ns
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
9/29
M41ST84W
READ Mode
In this mode the master reads the M41ST84W
slave after setting the slave address (see Figure
9., page 10). Following the WRITE Mode Control
Bit (R/W=0) and the Acknowledge Bit, the word
address ‘An’ is written to the on-chip address
pointer. Next the START condition and slave address are repeated followed by the READ Mode
Control Bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte
which was addressed will be transmitted and the
master receiver will send an Acknowledge Bit to
the slave transmitter. The address pointer is only
incremented on reception of an Acknowledge
Clock. The M41ST84W slave transmitter will now
place the data byte at address An+1 on the bus,
the master receiver reads and acknowledges the
new byte and the address pointer is
incremented to “An+2.”
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter (see Figure
10., page 11).
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer
increments to a non-clock or RAM address.
Note: This is true both in READ Mode and WRITE
Mode.
An alternate READ Mode may also be implemented whereby the master reads the M41ST84W
slave without first writing to the (volatile) address
pointer. The first address that is read is the last
one stored in the pointer (see Figure
11., page 11).
Figure 9. Slave Address Location
R/W
START
A
1
LSB
MSB
SLAVE ADDRESS
1
0
1
0
0
0
AI00602
10/29
M41ST84W
SLAVE
ADDRESS
DATA n+1
ACK
DATA n
ACK
S
ACK
BUS ACTIVITY:
R/W
START
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 10. READ Mode Sequence
STOP
SLAVE
ADDRESS
DATA n+X
P
NO ACK
AI00899
STOP
R/W
SLAVE
ADDRESS
DATA n+X
P
NO ACK
BUS ACTIVITY:
DATA n+1
ACK
DATA n
ACK
S
ACK
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 11. Alternate READ Mode Sequence
AI00895
11/29
M41ST84W
WRITE Mode
Data Retention Mode
In this mode the master transmitter transmits to
the M41ST84W slave receiver. Bus protocol is
shown in Figure 12., page 12. Following the
START condition and slave address, a logic '0' (R/
W=0) is placed on the bus and indicates to the addressed device that word address An will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is
strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge
clock. The M41ST84W slave receiver will send an
acknowledge clock to the master transmitter after
it has received the slave address (see Figure
9., page 10) and again after it has received the
word address and each data byte.
With valid VCC applied, the M41ST84W can be accessed as described above with READ or WRITE
cycles. Should the supply voltage decay, the
M41ST84W will automatically deselect, write protecting itself when VCC falls between VPFD(max)
and VPFD(min). This is accomplished by internally
inhibiting access to the clock registers. At this
time, the Reset pin (RST) is driven active and will
remain active until VCC returns to nominal levels.
When VCC falls below the Battery Back-up
Switchover Voltage (VSO), power input is switched
from the VCC pin to the external battery, and the
clock registers and SRAM are maintained from the
attached battery supply.
All outputs become high impedance. On power up,
when VCC returns to a nominal value, write protection continues for trec. The RST signal also remains active during this time (see Figure
19., page 25).
For a further more detailed review of lifetime calculations, please see Application Note AN1012.
SLAVE
ADDRESS
12/29
STOP
DATA n+X
P
ACK
DATA n+1
ACK
BUS ACTIVITY:
DATA n
ACK
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 12. WRITE Mode Sequence
AI00591
M41ST84W
CLOCK OPERATION
The eight byte clock register (see Table
3., page 14) is used to both set the clock and to
read the date and time from the clock, in a binary
coded decimal format. Tenths/Hundredths of Seconds, Seconds, Minutes, and Hours are contained
within the first four registers.
Note: A WRITE to any clock register will result in
the Tenths/Hundredths of Seconds being reset to
“00,” and Tenths/Hundredths of Seconds cannot
be written to any value other than “00.”
Bits D6 and D7 of Clock Register 03h (Century/
Hours Register) contain the CENTURY ENABLE
Bit (CEB) and the CENTURY Bit (CB). Setting
CEB to a '1' will cause CB to toggle, either from '0'
to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle. Bits D0 through D2 of Register
04h contain the Day (day of week). Registers 05h,
06h, and 07h contain the Date (day of month),
Month and Years. The ninth clock register is the
Control Register (this is described in the Clock
Calibration section). Bit D7 of Register 01h contains the STOP Bit (ST). Setting this bit to a '1' will
cause the oscillator to stop. If the device is expected to spend a significant amount of time on the
shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts
within one second.
The eight clock registers may be read one byte at
a time, or in a sequential block. The Control Register (Address location 08h) may be accessed independently. Provision has been made to assure
that a clock update does not occur while any of the
eight clock addresses are being read. If a clock address is being read, an update of the clock regis-
ters will be halted. This will prevent a transition of
data during the READ.
Power-down Time-Stamp
When a power failure occurs, the Halt Update Bit
(HT) will automatically be set to a '1.' This will prevent the clock from updating the TIMEKEEPER ®
registers, and will allow the user to read the exact
time of the power-down event. Resetting the HT
Bit to a '0' will allow the clock to update the TIMEKEEPER registers with the current time. For more
information, see Application Note AN1572.
TIMEKEEPER ® Registers
The M41ST84W offers 12 additional internal registers which contain the Alarm, Watchdog, Flag,
Square Wave and Control data. These registers
are memory locations which contain external (user
accessible) and internal copies of the data (usually
referred to as BiPORT™ TIMEKEEPER cells). The
external copies are independent of internal functions except that they are updated periodically by
the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will
be reset upon the completion of a WRITE to any
clock address.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer
increments to a non-clock or RAM address.
TIMEKEEPER and Alarm Registers store data in
BCD. Control, Watchdog and Square Wave Registers store data in Binary Format.
13/29
M41ST84W
Table 3. TIMEKEEPER® Register Map
Data
Address
D7
00h
D6
D5
D4
D3
D2
0.1 Seconds
D1
D0
Function/Range
BCD Format
0.01 Seconds
Seconds
00-99
01h
ST
10 Seconds
Seconds
Seconds
00-59
02h
0
10 Minutes
Minutes
Minutes
00-59
03h
CEB
CB
Hours (24 Hour Format)
Century/Hours
0-1/00-23
04h
TR
0
Day
01-7
05h
0
0
Date: Day of Month
Date
01-31
06h
0
0
Month
Month
01-12
Year
Year
00-99
07h
10 Hours
0
0
0
10 Date
0
Day of Week
10M
10 Years
08h
OUT
FT
S
09h
WDS
BMB4
BMB3
BMB2
0Ah
AFE
SQWE
ABE
Al 10M
0Bh
RPT4
RPT5
0Ch
RPT3
HT
0Dh
RPT2
0Eh
RPT1
0Fh
WDF
AF
0
BL
0
0
0
0
Flags
10h
0
0
0
0
0
0
0
0
Reserved
11h
0
0
0
0
0
0
0
0
Reserved
12h
0
0
0
0
0
0
0
0
Reserved
13h
RS3
RS2
RS1
RS0
0
0
0
0
SQW
BMB1
BMB0
Control
RB1
RB0
Watchdog
Alarm Month
Al Month
01-12
AI 10 Date
Alarm Date
Al Date
01-31
AI 10 Hour
Alarm Hour
Al Hour
00-23
Alarm 10 Minutes
Alarm Minutes
Al Min
00-59
Alarm 10 Seconds
Alarm Seconds
Al Sec
00-59
Keys: S = Sign Bit
FT = Frequency Test Bit
ST = Stop Bit
0 = Must be set to zero
BL = Battery Low Flag (Read only)
BMB0-BMB4 = Watchdog Multiplier Bits
CEB = Century Enable Bit
CB = Century Bit
OUT = Output level
AFE = Alarm Flag Enable Flag
14/29
Calibration
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog flag (Read only)
AF = Alarm flag (Read only)
SQWE = Square Wave Enable
RS0-RS3 = SQW Frequency
HT = Halt Update Bit
TR = trec Bit
M41ST84W
Calibrating the Clock
The M41ST84W is driven by a quartz controlled
oscillator with a nominal frequency of 32,768Hz.
The devices are tested not exceed +/–35 ppm
(parts per million) oscillator frequency error at
25oC, which equates to about +/–1.53 minutes per
month. When the Calibration circuit is properly employed, accuracy improves to better than ±2 ppm
at 25°C.
The oscillation rate of crystals changes with temperature (see Figure 13., page 16). Therefore, the
M41ST84W design employs periodic counter correction. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure
14., page 16. The number of times pulses which
are blanked (subtracted, negative calibration) or
split (added, positive calibration) depends upon
the value loaded into the five Calibration bits found
in the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration bits occupy the five lower order
bits (D4-D0) in the Control Register (08h). These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign Bit; '1' indicates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that
the oscillator is running at exactly 32,768Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month.
Two methods are available for ascertaining how
much calibration a given M41ST84W may require.
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate reference and recording deviation over a fixed period
of time. Calibration values, including the number of
seconds lost or gained in a given period, can be
found in Application Note AN934: TIMEKEEPER
CALIBRATION. This allows the designer to give
the end user the ability to calibrate the clock as the
environment requires, even if the final product is
packaged in a non-user serviceable enclosure.
The designer could provide a simple utility that accesses the Calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use of the
IRQ/FT/OUT pin. The pin will toggle at 512Hz,
when the Stop Bit (ST, D7 of 01h) is '0,' the Frequency Test Bit (FT, D6 of 08h) is '1,' the Alarm
Flag Enable Bit (AFE, D7 of 0Ah) is '0,' and the
Watchdog Steering Bit (WDS, D7 of 09h) is '1' or
the Watchdog Register (09h = 0) is reset.
Any deviation from 512Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of
512.010124Hz would indicate a +20 ppm oscillator
frequency error, requiring a –10 (XX001010) to be
loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency test output frequency.
The IRQ/FT/OUT pin is an open drain output
which requires a pull-up resistor to VCC for proper
operation. A 500 to 10k resistor is recommended
in order to control the rise time. The FT Bit is
cleared on power-down.
15/29
M41ST84W
Figure 13. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
∆F = K x (T –T )2
O
F
–100
K = –0.036 ppm/°C2 ± 0.006 ppm/°C2
–120
TO = 25°C ± 5°C
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999b
Figure 14. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
16/29
M41ST84W
Setting Alarm Clock Registers
Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second, or repeat every year, month,
day, hour, minute, or second. It can also be programmed to go off while the M41ST84W is in the
battery back-up to serve as a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode
of operation. Table 4., page 17 shows the possible
configurations. Codes not listed in the table default
to the once per second mode to quickly alert the
user of an incorrect alarm setting.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condition activates the IRQ/FT/OUT pin.
Note: If the address pointer is allowed to increment to the Flag Register address, an alarm condition will not cause the Interrupt/Flag to occur until
the address pointer is moved to a different ad-
dress. It should also be noted that if the last address written is the “Alarm Seconds,” the address
pointer will increment to the Flag address, causing
this situation to occur.
The IRQ/FT/OUT output is cleared by a READ to
the Flags Register as shown in Figure 15.. A subsequent READ of the Flags Register is necessary
to see that the value of the Alarm Flag has been
reset to '0.'
The IRQ/FT/OUT pin can also be activated in the
battery back-up mode. The IRQ/FT/OUT will go
low if an alarm occurs and both ABE (Alarm in Battery Back-up Mode Enable) and AFE are set. The
ABE and AFE Bits are reset during power-up,
therefore an alarm generated during power-up will
only set AF. The user can read the Flag Register
at system boot-up to determine if an alarm was
generated while the M41ST84W was in the deselect mode during power-up. Figure 16., page 18 illustrates the back-up mode alarm timing.
Figure 15. Alarm Interrupt Reset Waveform
0Eh
0Fh
10h
ACTIVE FLAG
HIGH-Z
IRQ/FT/OUT
AI03664
Table 4. Alarm Repeat Modes
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm Setting
1
1
1
1
1
Once per Second
1
1
1
1
0
Once per Minute
1
1
1
0
0
Once per Hour
1
1
0
0
0
Once per Day
1
0
0
0
0
Once per Month
0
0
0
0
0
Once per Year
17/29
M41ST84W
Figure 16. Back-Up Mode Alarm Waveform
VCC
VPFD
VSO
tREC
ABE, AFE Bits in Interrupt Register
AF bit in Flags Register
IRQ/FT/OUT
HIGH-Z
HIGH-Z
AI03920
Watchdog Timer
The watchdog timer can be used to detect an outof-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 09h.
Bits BMB4-BMB0 store a binary multiplier and the
two lower order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second,
10 = 1 second, and 11 = 4 seconds. The amount
of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the
Watchdog Register = 3*1, or 3 seconds).
Note: Accuracy of timer is within ± the selected
resolution.
If the processor does not reset the timer within the
specified period, the M41ST84W sets the WDF
(Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset.
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a '0,' the watchdog will activate the IRQ/FT/OUT
pin when timed-out. When WDS is set to a '1,' the
watchdog will output a negative pulse on the RST
pin for trec. The Watchdog register, FT, AFE, ABE
and SQWE Bits will reset to a '0' at the end of a
Watchdog time-out when the WDS Bit is set to a
'1.'
18/29
The watchdog timer can be reset by two methods:
1) a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI) or 2) the
microprocessor can perform a WRITE of the
Watchdog Register. The time-out period then
starts over.
Note: The WDI pin should be tied to VSS if not
used.
In order to perform a software reset of the watchdog timer, the original time-out period can be written into the Watchdog Register, effectively
restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS
Bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT/OUT pin. This will also
disable the watchdog function until it is again programmed correctly. A READ of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
0Fh).
The watchdog function is automatically disabled
upon power-up and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT/OUT pin and the Frequency Test (FT)
function is activated, the watchdog function prevails and the Frequency Test function is denied.
M41ST84W
Square Wave Output
The M41ST84W offers the user a programmable
square wave function which is output on the SQW
pin. The RS3-RS0 Bits located in 13h establish the
square wave output frequency. These frequencies
are listed in Table 5.. Once the selection of the
SQW frequency has been completed, the SQW
pin can be turned on and off under software control with the Square Wave Enable Bit (SQWE) located in Register 0Ah.
Table 5. Square Wave Output Frequency
Square Wave Bits
Square Wave
RS3
RS2
RS1
RS0
Frequency
Units
0
0
0
0
None
–
0
0
0
1
32.768
kHz
0
0
1
0
8.192
kHz
0
0
1
1
4.096
kHz
0
1
0
0
2.048
kHz
0
1
0
1
1.024
kHz
0
1
1
0
512
Hz
0
1
1
1
256
Hz
1
0
0
0
128
Hz
1
0
0
1
64
Hz
1
0
1
0
32
Hz
1
0
1
1
16
Hz
1
1
0
0
8
Hz
1
1
0
1
4
Hz
1
1
1
0
2
Hz
1
1
1
1
1
Hz
19/29
M41ST84W
Power-on Reset
Reset Input (RSTIN)
The M41ST84W continuously monitors VCC.
When VCC falls to the power fail detect trip point,
the RST pulls low (open drain) and remains low on
power-up for trec after VCC passes VPFD(max).
The RST pin is an open drain output and an appropriate pull-up resistor should be chosen to control
rise time.
The M41ST84W provides an independent input
which can generate an output reset. The duration
and function of this reset is identical to a reset generated by a power cycle. Table 6., page 20 and
Figure 17., page 20 illustrate the AC reset characteristics of this function. Pulses shorter than tRLRH
will not generate a reset condition. RSTIN is internally pulled up to VCC through a 100kΩ resistor.
Figure 17. RSTIN Timing Waveform
RSTIN
tRLRH
RST
(1)
tRHRSH
AI03682
Note: With pull-up resistor
Table 6. Reset AC Characteristics
Symbol
Parameter(1)
Min
tRLRH(2)
RSTIN Low to RSTIN High
200
RSTIN High to RST High
40
tRHRSH(3)
Max
ns
200
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V (except where noted).
2. Pulse width less than 50ns will result in no RESET (for noise immunity).
3. Programmable (see Table 8., page 22)
20/29
Unit
ms
M41ST84W
Power-fail INPUT/OUTPUT
The Power-Fail Input (PFI) is compared to an internal reference voltage (1.25V). If PFI is less than
the power-fail threshold (VPFI), the Power-Fail
Output (PFO) will go low. This function is intended
for use as an under-voltage detector to signal a
failing power supply. Typically PFI is connected
through an external voltage divider (see Figure
5., page 6) to either the unregulated DC input (if it
is available) or the regulated output of the VCC regulator. The voltage divider can be set up such that
the voltage at PFI falls below VPFI several milliseconds before the regulated VCC input to the
M41ST84W or the microprocessor drops below
the minimum operating voltage.
During battery back-up, the power-fail comparator
turns off and PFO goes (or remains) low. This occurs after VCC drops below VPFD(min). When power returns, PFO is forced high, irrespective of VPFI
for the write protect time (trec), which is the time
from VPFD(max) until the inputs are recognized. At
the end of this time, the power-fail comparator is
enabled and PFO follows PFI. If the comparator is
unused, PFI should be connected to VSS and PFO
left unconnected.
Century Bit
Bits D7 and D6 of Clock Register 03h contain the
CENTURY ENABLE Bit (CEB) and the CENTURY
Bit (CB). Setting CEB to a “1” will cause CB to toggle, either from a “0” to “1” or from “1” to “0” at the
turn of the century (depending upon its initial
state). If CEB is set to a “0”, CB will not toggle.
Output Driver Pin
When the FT Bit, AFE Bit and watchdog register
are not set, the IRQ/FT/OUT pin becomes an output driver that reflects the contents of D7 of the
Control Register. In other words, when D7 (OUT
Bit) and D6 (FT Bit) of address location 08h are a
'0,' then the IRQ/FT/OUT pin will be driven low.
Note: The IRQ/FT/OUT pin is an open drain which
requires an external pull-up resistor.
Battery Low Warning
The M41ST84W automatically performs battery
voltage monitoring upon power-up and at factoryprogrammed time intervals of approximately 24
hours. The Battery Low (BL) Bit, Bit D4 of Flags
Register 0Fh, will be asserted if the battery voltage
is found to be less than approximately 2.5V. The
BL Bit will remain asserted until completion of battery replacement and subsequent battery low
monitoring tests, either during the next power-up
sequence or the next scheduled 24-hour interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct. A
fresh battery should be installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The battery may be replaced while VCC is applied to the device.
The M41ST84W only monitors the battery when a
nominal VCC is applied to the device. Thus applications which require extensive durations in the
battery back-up mode should be powered-up periodically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
trec Bit
Bit D7 of Clock Register 04h contains the trec Bit
(TR). trec refers to the automatic continuation of
the deselect time after VCC reaches VPFD. This allows for a voltage setting time before WRITEs may
again be performed to the device after a powerdown condition. The trec Bit will allow the user to
set the length of this deselect time as defined by
Table 7., page 22.
Initial Power-on Defaults
Upon initial application of power to the device, the
following register bits are set to a '0' state: Watchdog Register, TR, FT, AFE, ABE, and SQWE. The
following bits are set to a '1' state: ST, OUT, and
HT (see Table 8., page 22).
21/29
M41ST84W
Table 7. trec Definitions
tREC Bit (TR)
trec Time
STOP Bit (ST)
Units
Min
Max
0
0
96
98
ms
0
1
40
200(1)
ms
1
X
50
2000
µs
Note: 1. Default Setting
Table 8. Default Values
Condition
Initial Power-up
(Battery Attach)(2)
Subsequent Power-up (with
battery back-up)(3)
TR
ST
HT
Out
FT
AFE
ABE
SQWE
WATCHDOG
Register(1)
0
1
1
1
0
0
0
0
0
UC
UC
1
UC
0
0
0
0
0
Note: 1. WDS, BMB0-BMB4, RB0, RB1.
2. State of other control bits undefined.
3. UC = Unchanged
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 9. Absolute Maximum Ratings
Symbol
TSTG
TSLD(1)
Parameter
Storage Temperature (VCC Off, Oscillator Off)
Lead Solder Temperature for 10 seconds
Value
Unit
–55 to 150
°C
260
°C
–0.3 to VCC + 0.3
V
VIO
Input or Output Voltages
VCC
Supply Voltage
–0.3 to 4.6
V
IO
Output Current
20
mA
PD
Power Dissipation
1
W
Note: 1. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget not to exceed 180°C for
between 90 to 150 seconds).
2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C
for greater than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
22/29
M41ST84W
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 10. DC and AC Measurement Conditions
Parameter
M41ST84W
VCC Supply Voltage
2.7 to 3.6V
Ambient Operating Temperature
–40 to 85°C
Load Capacitance (CL)
50pF
≤ 50ns
Input Rise and Fall Times
Input Pulse Voltages
0.2 to 0.8VCC
Input and Output Timing Ref. Voltages
0.3 to 0.7VCC
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 18. AC Testing Input/Output Waveforms
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02568
Note: 50pF for M41ST84W.
Table 11. Capacitance
Parameter(1,2)
Symbol
CIN
CIO(3)
tLP
Min
Max
Unit
Input Capacitance
7
pF
Input / Output Capacitance
10
pF
Low-pass filter input time constant (SDA and SCL)
50
ns
Note: 1. Effective capacitance measured with power supply at 3V. Sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
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M41ST84W
Table 12. DC Characteristics
Sym
Battery Current OSC ON
IBAT
Supply Current
ICC2
Supply Current (Standby)
Max
400
500
50
Unit
nA
nA
0.75
mA
SCL, SDA = VCC – 0.3V
or VSS + 0.3V
0.50
mA
0V ≤ VIN ≤ VCC
Input Leakage Current (PFI)
ILO(3)
Typ
f = 400kHz
Input Leakage Current
ILI(2)
Min
TA = 25°C, VCC = 0V,
VBAT = 3V
Battery Current OSC OFF
ICC1
M41ST84W
Test Condition(1)
Parameter
–25
2
0V ≤ VOUT ≤ VCC
Output Leakage Current
±1
µA
25
nA
±1
µA
VIH
Input High Voltage
0.7VCC
VCC + 0.3
V
VIL
Input Low Voltage
–0.3
0.3VCC
V
3.5(6)
V
VBAT
Battery Voltage
VOH
Output High Voltage(4)
2.5
IOH = –1.0mA
Output Low Voltage
VOL
Output Low Voltage (Open Drain)
(5)
Pull-up Supply Voltage (Open Drain)
VPFD
2.4
0.4
V
IOL = 10mA
0.4
V
RST, IRQ/FT/OUT
3.6
V
VCC = 3V(W)
PFI Input Threshold
PFI Hysteresis
VSO
V
IOL = 3.0mA
Power Fail Deselect
VPFI
3.0
2.55
2.60
2.70
V
1.225
1.250
1.275
V
20
70
mV
PFI Rising
Battery Back-up Switchover
2.5
V
Note: 1.
2.
3.
4.
5.
Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V (except where noted).
RSTIN internally pulled-up to VCC through 100KΩ resistor. WDI internally pulled-down to VSS through 100KΩ resistor.
Outputs deselected.
For PFO and SQW pins (CMOS).
For IRQ/FT/OUT, RST pins (Open Drain): if pulled-up to supply other than VCC, this supply must be equal to, or less than 3.0V when
VCC = 0V (during battery back-up mode).
6. For rechargeable back-up, VBAT (max) may be considered VCC.
Table 13. Crystal Electrical Characteristics (Externally Supplied)
Symbol
Parameter(1,2)
f0
Resonant Frequency
RS
Series Resistance
CL
Load Capacitance
Typ
Min
Max
32.768
kHz
50
12.5
Unit
kΩ
pF
Note: 1. Load capacitors are integrated within the M41ST84W. Circuit board layout considerations for the 32.768kHz crystal of minimum
trace lengths and isolation from RF generating signals should be taken into account.
2. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S:
1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at [email protected] or http://www.kdsj.co.jp for further information on this crystal type.
24/29
M41ST84W
Figure 19. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tFB
tRB
tDR
tREC
PFO
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
RST
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI03681
Table 14. Power Down/Up AC Characteristics
Symbol
Parameter(1)
Min
Typ
Max
Unit
tF(2)
VPFD(max) to VPFD(min) VCC Fall Time
300
µs
tFB(3)
VPFD(min) to VSS VCC Fall Time
10
µs
tPFD
PFI to PFO Propagation Delay
15
25
µs
tR
VPFD(min) to VPFD(max) VCC Rise Time
10
µs
tRB
VSS to VPFD(min) VCC Rise Time
1
µs
Power up Deselect Time
40
trec(4)
200
ms
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V (except where noted).
2. VPFD(max) to VPFD(min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes
VPFD(min).
3. VPFD(min) to VSS fall time of less than tFB may cause corruption of RAM data.
4. Programmable (see Table 7., page 22)
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M41ST84W
PACKAGE MECHANICAL INFORMATION
Figure 20. SO16 – 16-lead Plastic Small Outline, Package Outline
A2
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-b
Note: Drawing is not to scale.
Table 15. SO16 – 16-lead Plastic Small Outline, Package Mechanical Data
mm
inches
Symbol
Typ.
Min.
A
Typ.
Min.
1.75
A1
0.10
A2
Max.
0.069
0.25
0.004
1.60
0.010
0.063
B
0.35
0.46
0.014
0.018
C
0.19
0.25
0.007
0.010
D
9.80
10.00
0.386
0.394
E
3.80
4.00
0.150
0.158
–
–
–
–
H
5.80
6.20
0.228
0.244
L
0.40
1.27
0.016
0.050
a
0°
8°
0°
8°
N
16
e
CP
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Max.
1.27
0.050
16
0.10
0.004
M41ST84W
PART NUMBERING
Table 16. Ordering Information Scheme
Example:
M41ST
84W
MQ
6
E
Device Type
M41ST
Supply Voltage and Write Protect Voltage
84W = VCC = 2.7 to 3.6V; 2.55V ≤ VPFD ≤ 2.70V
Package
MQ = SO16
Temperature Range
6 = –40 to 85°C
Shipping Method
For SO16:
blank = Tubes (Not for New Design - Use E)
E = ECOPACK Package, Tubes
F = ECOPACK Package, Tape & Reel
TR = Tape & Reel (Not for New Design - Use F)
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
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M41ST84W
REVISION HISTORY
Table 17. Document Revision History
Date
Version
August 2000
1.0
First Issue
24-Aug-00
1.2
Block Diagram added (Figure 4)
08-Sep-00
1.3
SO16 package measures change
18-Dec-00
2.0
Reformatted, TOC added, and PFI Input Leakage Current added (Table 12)
18-Jun-01
2.1
Addition of trec information, table changed, one added (Tables 3, 7); changes to PFI/PFO
graphic (see Figure 4); change to DC and AC Characteristics, Order Information (Tables 12,
2, 16); note added to “Setting Alarm Clock Registers” section; added temp./voltage info. to
tables (Table 11, 12, 13, 2, 14); addition of Default Values (Table 8); textual improvements
25-Jun-01
2.2
Special note added in CLOCK OPERATION, page 13
26-Jul-01
3.0
Change in Product Maturity
07-Aug-01
3.1
Improve text for “Setting the Alarm Clock” section
20-Aug-01
3.2
Change VPFD values in document
06-Sep-01
3.3
DC Characteristics VBAT changed; PFI Hysteresis (PFI Rising) spec. added; and Crystal
Electrical Characteristics Series Resistance spec. changed (Tables 12, 13)
03-Dec-01
3.4
Change READ/WRITE Mode Sequence drawings (Figure 10, 12); change in VPFD lower
limit for 5V (M41ST84Y) part only (Table 12, 16)
14-Jan-02
3.5
Change Series Resistance (Table 13)
01-May-02
3.6
Change trec Definition (Table 7); modify reflow time and temperature footnote (Table 9)
03-Jul-02
3.7
Modify DC and Crystal Electrical Characteristics footnotes, Default Values (Tables 12, 13, 8)
01-Aug-02
3.8
Add marketing status (Figure 2; Table 16)
16-Jun-03
4.0
New Si changes (Table 14, 6, 7, 8)
15-Jun-04
5.0
Reformatted; added Lead-free information; update characteristics (Figure 13; Table 9, 12,
16)
18-Oct-04
6.0
Add Marketing Status (Figure 2; Table 16)
10-Jan-06
7.0
Updated template, Lead-free text, characteristics (Figure 2, 3, 6, 7; Table 1, 2, 6, 8, 9, 10,
11, 12, 13, 14, 16)
28/29
Revision Details
M41ST84W
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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