STMICROELECTRONICS M41T60

M41T60
Serial access real-time clock
Features summary
■
Counters for seconds, minutes, hours, day,
date, month, years, and century
■
32kHz crystal oscillator integrating load
capacitance and high crystal series resistance
operation
■
Oscillator stop detection monitors clock
operation
■
Serial interface supports I2C bus (400kHz)
■
350nA timekeeping current @ 3V
■
Low operating current of 35µA (@400KHz)
■
Timekeeping down to 1.0V
■
1.3V to 4.4V I2C bus operating voltage
■
Software clock calibration to compensate
deviation of crystal due to temperature
■
Software programmable output (OUT)
■
Operating temperature of –40 to 85°C
■
Automatic leap year compensation
■
Lead-free 16-pin QFN package
■
Li ION rechargeable operation
July 2006
QFN16 (Q)
3mm x 3mm
32KHz Crystal + QFN16 vs. VSOJ20
VSOJ20 (47.6mm2)
2
GND Plane Guard Ring (21.5mm )
SMT
CRYSTAL
1
XI
2
XO
3
4
ST QFN16
AI11107
Rev 11
1/24
www.st.com
24
Contents
M41T60
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
3
2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1
Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.2
Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.3
Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.4
Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.5
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2
Century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3
Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4
Oscillator stop detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5
Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/24
M41T60
Summary description
1
Summary description
The M41T60 is a low power Serial RTC with a built-in 32.768kHz oscillator (external crystal
controlled). Eight registers are used for the clock/calendar function and are configured in
binary coded decimal (BCD) format. Addresses and data are transferred serially via a twoline bi-directional bus. The built-in address register is increased automatically after each
WRITE or READ data byte.
The eight clock address locations contain the century, year, month, date, day, hour, minute,
and second; in 24-hour BCD format. Corrections for 28-, 29- (leap year), 30-, and 31-day
months are made automatically.
The M41T60 is supplied in 16-lead QFN package.
Figure 1.
Logic diagram
VCC
XI
FT(1)
XO
M41T60
SCL
OFIRQ/OUT(1)
SDA
VSS
AI08869
Open drain
Table 1. Signal names
XI
Oscillator Input
XO
Oscillator Output
FT
Serial Data Address Input / Output
SCL
Serial Clock
OFIRQ/OUT
Oscillator Fail Interrupt/OUT Output (Open Drain)
VCC
Supply Voltage
VSS
Ground
NC
VCC
NC
16-pin QFN connections
16
15
14
13
12
NC
XO
2
11
OFIRQ/OUT
VSS
3
10
SCL
(1)
4
9
SDA
FT
5
6
7
8
NC
1
NC
XI
NC
Figure 2.
Frequency Test Output (Open Drain)
SDA
NC
1
VSS
Note:
(1)
AI08870
3/24
Summary description
Figure 3.
M41T60
Block diagram
(1)
FT
FT
OUT
(1)
OFIRQ/OUT
OFIE
1 Hz
OSCILLATOR
FAIL DETECT
XI
OSCILLATOR
32.768 kHz
SECONDS
DIVIDER
XO
MINUTES
HOURS
CONTROL
LOGIC
VCC
VSS
DAY
DATE
SCL
CENTURY/
MONTH
SERIAL
BUS
INTERFACE
YEAR
ADDRESS
REGISTER
SDA
CALIBRATION
AI08871
Note:
1
Open drain output.
Figure 4.
Hardware hookup for SuperCap™ back-up operation
VCC
MCU
M41T60
VCC
XI
XO
VSS
VCC
(1)
OFIRQ/OUT
(1)
FT
Port
Port
SCL
Serial Clock Line
SDA
Serial Data Line
AI10476b
Note:
4/24
1
Open drain output.
M41T60
2
Operation
Operation
The M41T60 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 8 bytes
contained in the device can then be accessed sequentially in the following order:
2.1
1.
Seconds Register
2.
Minutes Register
3.
Hours Register
4.
Day Register
5.
Date Register
6.
Century/Month Register
7.
Years Register
8.
Calibration Register
2-wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one
bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the
SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●
Data transfer may be initiated only when the bus is not busy.
●
During data transfer, the data line must remain stable whenever the clock line is High.
Changes in the data line while the clock line is High will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain High.
2.1.2
Start data transfer
A change in the state of the data line, from High to Low, while the clock is High, defines the
START condition.
2.1.3
Stop data transfer
A change in the state of the data line, from Low to High, while the clock is High, defines the
STOP condition.
5/24
Operation
2.1.4
M41T60
Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the High period of the clock signal. The data on the line may be
changed during the Low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition, a device that gives out a message is called “transmitter”, the receiving device
that gets the message is called “receiver”. The device that controls the message is called
“master”. The devices that are controlled by the master are called “slaves”.
2.1.5
Acknowledge
Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low
level put on the bus by the receiver, whereas the master generates an extra acknowledge
related clock pulse.
A slave receiver which is addressed is obliged to generate an acknowledge after the
reception of each byte. Also, a master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable Low during the High period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case, the transmitter must leave the data line High to enable the master to generate the
STOP condition.
Figure 5.
6/24
Serial bus data transfer sequence
M41T60
Operation
Figure 6.
2.2
Acknowledgement sequence
READ mode
In this mode, the master reads the M41T60 slave after setting the slave address
(see Figure 7). Following the WRITE Mode Control Bit (R/W = 0) and the Acknowledge Bit,
the word address An is written to the on-chip address pointer. Next the START condition and
slave address are repeated, followed by the READ Mode Control Bit (R/W = 1). At this point,
the master transmitter becomes the master receiver. The data byte which was addressed
will be transmitted and the master receiver will send an Acknowledge Bit to the slave
transmitter. The address pointer is only increased on reception of an Acknowledge Bit. The
M41T60 slave transmitter will now place the data byte at address An+1 on the bus. The
master receiver reads and acknowledges the new byte and the address pointer is increased
to An+2.
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (0h to 6h). The update will resume due to a Stop Condition or when the
pointer increments to any non-clock address (7h).
An alternate READ Mode may also be implemented, whereby the master reads the M41T60
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer (see Figure 9 on page 9).
7/24
Operation
2.3
M41T60
WRITE mode
In this mode the master transmitter transmits to the M41T60 slave receiver. Bus protocol is
shown in Figure 10 on page 9. Following the START condition and slave address, a logic '0'
(R/W = 0) is placed on the bus and indicates to the addressed device that word address An
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is increased to the next
address location on the reception of an acknowledge clock. The M41T60 slave receiver will
send an acknowledge clock to the master transmitter after it has received the slave address
and again after it has received the word address and each data byte.
Figure 7.
Slave address location
R/W
START
A
1
LSB
MSB
SLAVE ADDRESS
1
0
1
0
0
0
AI00602
R/W
SLAVE
ADDRESS
DATA n+1
ACK
DATA n
ACK
BUS ACTIVITY:
S
ACK
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
READ mode sequence
START
Figure 8.
STOP
SLAVE
ADDRESS
P
NO ACK
DATA n+X
8/24
AI00899
M41T60
Operation
SLAVE
ADDRESS
P
NO ACK
BUS ACTIVITY:
DATA n+X
ACK
DATA n+1
ACK
DATA n
ACK
S
ACK
SDA LINE
R/W
BUS ACTIVITY:
MASTER
STOP
Alternate READ mode sequence
START
Figure 9.
AI00895
SLAVE
ADDRESS
STOP
DATA n+X
P
ACK
DATA n+1
ACK
BUS ACTIVITY:
DATA n
ACK
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 10. WRITE mode sequence
AI00591
9/24
Clock operation
3
M41T60
Clock operation
The M41T60 is driven by a quartz-controlled oscillator with a nominal frequency of
32.768KHz. The accuracy of the Real-Time Clock depends on the frequency of the quartz
crystal that is used as the time-base for the RTC. The eight-byte Clock Register (see Table 2
on page 12) is used to both set the clock and to read the date and time from the clock, in a
binary coded decimal format. Seconds, Minutes, and Hours are contained within the first
three registers.
Bits D6 and D7 of Clock Register 05h (Century/Month Register) contain the CENTURY Bit 0
(CB0) and the CENTURY Bit 1 (CB1). See Table 3 on page 14 for additional explanation.
Bits D0 through D2 of Register 03h contain the Day (day of the week). Registers 04h, 05h,
and 06h contain the Date (day of the month), Century/Month, and Years. the eighth clock
register is the Calibration Register (this is described in the Clock Calibration section). Bit D7
of Register 00h contains the STOP Bit (ST). Setting this bit to a '1' will cause the oscillator to
stop. When reset to a '0,' the oscillator restarts within one second (typical).
Note:
Upon initial power-up, the user should set the ST Bit to a '1,' then immediately reset the ST
Bit to '0.' This provides an additional “kick-start” to the oscillator circuit.
Bit D7 of Register 01h contains the Oscillator Fail Interrupt Enable Bit (OFIE - see the
description in the Oscillator Fail Detection section).
Note:
A WRITE to ANY location within the first seven bytes of the clock register (0h-6h), including
the OFIE and ST Bit, will result in an update of the system clock and a reset of the divider
chain. This could result in an inadvertent change of the current time. These non-clock
related bits should be written prior to setting the clock, and remain unchanged until such
time as a new clock time is also written.
The seven Clock Registers may be read one byte at a time, or in a sequential block. The
Calibration Register (Address location 7h) may be accessed independently. Provision has
been made to ensure that a clock update does not occur while any of the clock addresses
are being read. If a clock address is being read, an update of the clock registers will be
halted. this will prevent a transition of data during the READ.
3.1
Calibrating the clock
The M41T60 is driven by a quartz-controlled oscillator with a nominal frequency of
32,768Hz. The accuracy of the clock is dependent upon the accuracy of the crystal, and the
match between the capacitive load of the oscillator circuit and the capacitive load for which
the crystal was trimmed. The M41T60 oscillator is designed for use with a 6pF crystal load
capacitance. When the Calibration circuit is properly employed, accuracy improves to better
than ±2 ppm at 25°C.
The oscillation rate of crystals changes with temperature (see Figure 11 on page 12). The
M41T60 design employs periodic counter correction. The calibration circuit adds or
subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in
Figure 12 on page 13. The number of times pulses are blanked (subtracted, negative
calibration) or split (added, positive calibration) depends upon the value loaded into the five
Calibration Bits found in the Calibration Register. Adding counts speeds the clock up,
subtracting counts slows the clock down. The Calibration Bits occupy the five lower-order
bits (D4-D0) in the Calibration Register 07h.
10/24
M41T60
Clock operation
These bits can be set to represent any value between 0 and 31 in binary format. Bit D5 is a
Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration.
Calibration occurs within a 64-minute cycle. The first 62 minutes in the cycle may, once per
minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a
binary '1' is loaded into the register, only the first 2 minutes in the 64-minute cycle will be
modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each
calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every
125,829,120 actual oscillator cycles. That is, +4.068 or –2.034 ppm of adjustment per
calibration step in the calibration register. Assuming that the oscillator is running at exactly
32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or –5.35
seconds per day which corresponds to a total range of +5.5 or –2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M41T60 may
require:
Note:
●
The first involves setting the clock, letting it run for a month and comparing it to a known
accurate reference and recording deviation over a fixed period of time. Calibration
values, including the number of seconds lost or gained in a given period, can be found
in Application Note 934, “TIMEKEEPER® CALIBRATION.” This allows the designer to
give the end user the ability to calibrate the clock as the environment requires, even if
the final product is packaged in a non-user serviceable enclosure. The designer could
provide a simple utility that accesses the Calibration byte.
●
The second approach is better suited to a manufacturing environment, and involves the
use of the Frequency Test (FT) pin. The FT pin will toggle at 512Hz when the ST Bit is
set to '0,' and the OUT Bit and FT Bit are set to '1.' Any measured deviation from the
512Hz frequency indicates the degree and direction of oscillator frequency shift at the
test temperature. For example, a reading of 512.010124Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10 (XX001010) to be loaded into the Calibration
Byte for correction.
Setting or changing the Calibration Byte does not affect the Frequency Test output
frequency. the FT pin is an open drain pin which requires a pull-up resistor to VCC for proper
operation. A 500-10k resistor is recommended in order to control the rise time.
11/24
Clock operation
M41T60
Table 2. Register map
Data
Function/Range
BCD Format
Address
D7
D6
D5
D4
D3
D2
D1
D0
0
ST
10 Seconds
Seconds
Seconds
00-59
1
OFIE
10 Minutes
Minutes
Minutes
00-59
2
0
0
Hours
Hours
00-23
3
0
0
Day
01-07
4
0
0
Date
01-31
5
CB1
CB0
6
7
10 Hours
0
0
0
Day
10 Date
0
Date
10 M.
Month
10 Years
OUT
FT
Century/Month 0-3/01-12
Years
S
Year
Calibration
●
0 = Must be set to '0.'
●
CB0, CB1 = Century Bits
●
FT = Frequency Test Bits
●
OFIE = Oscillator Fail Interrupt Enable Bit
●
OUT = Output level
●
S = Sign Bit
●
ST = STOP Bit
00-99
Calibration
Figure 11. Crystal accuracy across temperature
Frequency (ppm)
20
0
–20
–40
–60
∆F = K x (T – T )2
O
F
–80
2
2
K = –0.036 ppm/°C ± 0.006 ppm/°C
–100
TO = 25°C ± 5°C
–120
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI07888
12/24
M41T60
Clock operation
Figure 12. Calibration waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
3.2
Century bits
These two bits will increment in a binary fashion at the turn of the century, and handle leap
years correctly. See Table 3 on page 14 for additional explanation.
3.3
Output driver pin
When the OFIE Bit is not set to generate an interrupt, the OFIRQ/OUT pin becomes an
output driver that reflects the contents of D7 of the Calibration Register. In other words,
when D7 (OUT Bit) is a '0,' then the OFIRQ/OUT pin will be driven low.
Note:
The OFIRQ/OUT pin is an open drain which requires an external pull-up resistor.
3.4
Oscillator stop detection
In the event that the oscillator has either stopped, or was stopped for some period of time,
and if the Oscillator Fail Interrupt Enable (OFIE) Bit is set to a '1,' an interrupt will be
generated. This interrupt can be used to judge the validity of the clock and date data.
The interrupt will be active any time the oscillator stops while VCC is ≥ 1.0V. The following
conditions will cause the OFIRQ pin to be active:
●
the ST Bit is set to '1.'
●
external interference or removal of the crystal.
The Oscillator Fail Interrupt (OFIRQ) will remain active until the OFIE Bit is reset to '0,' or the
oscillator restarts.
The oscillator must start and have run for at least 4 seconds before attempting to set the
OFIE Bit to '1.'
13/24
Clock operation
3.5
M41T60
Initial power-on defaults
Upon initial application of power to the device, the OUT Bit will be set to a '1,' while the ST,
OFIE, and FT Bits will be set to '0.' All other Register bits will initially power-on in a random
state.
Table 3. Century Bits Examples
CB0
CB1
Leap Year?
Example(1)
0
0
Yes
2000
0
1
No
2100
1
0
No
2200
1
1
No
2300
1. Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by
100. The only exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year
2100 is not).
14/24
M41T60
4
Maximum rating
Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4. Absolute maximum ratings
Symbol
Parameter
Conditions(1)
Value(2)
Unit
TSTG
Storage Temperature (VCC Off, Oscillator Off)
–55 to 125
°C
VCC
Supply Voltage
–0.3 to 5.0
V
260
°C
–0.2 to
Vcc+0.3
V
TSLD(3)
VIO
Lead Solder Temperature for 10 Seconds
Input or Output Voltages
IO
Output Current
20
mA
PD
Power Dissipation
1
W
TA = 25°C
>1500
V
TA = 25°C
>1000
V
VESD(HBM)
Electro-static discharge voltage
(Human Body Model)
VESD(RCDM) Electro-static discharge voltage
(Robotic Charged Device Model)
1. Test conforms to JEDEC standard
2. Data based on characterization results, not tested in production
3. Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C for greater than 30
seconds)
15/24
DC and AC parameters
5
M41T60
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC Characteristic
tables are derived from tests performed under the Measurement Conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 5. Operating and AC Measurement Conditions
Parameter
Note:
M41T60
Supply Voltage (VCC)
1.3V to 4.4V
Ambient Operating Temperature (TA)
–40 to 85°C
Load Capacitance (CL)
50pF
Input Rise and Fall Times
≤5ns
Input Pulse Voltages
0.2VCC to 0.8 VCC
Input and Output Timing Ref. Voltages
0.3VCC to 0.7 VCC
Output Hi-Z is defined as the point where data is no longer driven.
Figure 13. AC testing I/O waveform
Figure 14. Crystal isolation example
Local Grounding Plane
(Layer 2)
XI
Crystal
0.8VCC
XO
0.7VCC
GND
0.3VCC
0.2VCC
AI02568
AI09127
Note:
Substrate pad should be tied to VSS.
Table 6. Capacitance
Parameter (1)(2)
Symbol
CIN
COUT(3)
tLP
Min
Max
Unit
Input Capacitance (SCL)
7
pF
Output Capacitance (SDA, OUT)
10
pF
Low-pass filter input time constant (SDA and
SCL)
50
ns
1. Effective capacitance measured with power supply at 3.6V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
16/24
M41T60
DC and AC parameters
Table 7. DC Characteristics
Symbol
VCC(2)
ICC1
ICC2
Parameter
Test Condition(1)
Min
Clock (3)
I2C Bus (400kHz)
Operating Voltage
Supply Current
Supply Current
(Standby)
SCL = 400kHz
(No Load)
SCL = 0Hz
All inputs
≥ VCC – 0.2V
≤VSS + 0.2V
Typ
Max
Unit
1.0
4.4
V
1.3
4.4
V
100
µA
70
µA
VCC = 4.4V
VCC = 3.6V
50
VCC = 3.0V
35
µA
VCC = 2.5V
30
µA
VCC = 2.0V
20
µA
4.4V
3.6V
375
3.0V @ 25°C
350
2.0V @ 25°C
950
nA
700
nA
nA
310
nA
VIL
Input Low Voltage
–0.2
0.3 VCC
V
VIH
Input High Voltage
0.7 VCC
VCC + 0.3
V
VOL
Output Low Voltage
VCC = 4.4V, IOL = 3mA (SDA)
0.4
V
VCC = 4.4V, IOL = 1mA (OFIRQ/OUT)
0.4
V
FT, OFIRQ/OUT
4.4
V
Pull-up Supply
Voltage (Open Drain)
ILI
Input Leakage
Current
ILO
Output Leakage
Current
0V ≤VIN ≤VCC
–1.0
+1.0
µA
0V ≤VOUT ≤VCC
–1.0
+1.0
µA
Max
Unit
1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 1.3 to 4.4V (except where noted).
2. When using battery back-up, VCC fall time should not exceed 10mV/µs.
3. Oscillator start-up guaranteed at 1.5V only.
Table 8. Crystal electrical characteristics
Parameter (1)(2)
Symbol
fO
Resonant Frequency
RS
Series Resistance
(TA = –40 to 70°C, oscillator start-up at 2.0V)
CL
Load Capacitance
Min
Typ
32.768
kHz
75 (3)(4)
6
kΩ
pF
1. These values are externally supplied. STMicroelectronics recommends the Citizen CFS-145 (1.5x5mm) and the KDS DT38 (3x8mm) for thru-hole, or the KDS DMX-26S (3.2x8mm) for surface-mount, tuning fork-type quartz crystals.
KDS can be contacted at [email protected] or http://www.kdsj.co.jp.
Citizen can be contacted at [email protected] or http://www.citizencrystal.com.
2. Load capacitors are integrated within the M41T60. Circuit board layout considerations for the 32.768KHz crystal of
minimum trace lengths and isolation from RF generating signals should be taken into account.
3. Guaranteed by design.
4. RS (max) = 65kΩ for TA = –40 to 85°C and oscillator start-up at 1.5V.
17/24
DC and AC parameters
M41T60
Table 9. Oscillator characteristics
Symbol
Parameter
Conditions
Min
1.5
Typ
Max
Unit
VSTA
Oscillator Start Voltage
≤10 seconds
tSTA
Oscillator Start Time
VCC = 3.0V
Cg
XIN
12
pF
Cd
XOUT
12
pF
V
1
–10
IC-to-IC Frequency Variation (1)
s
+10
ppm
1. Reference value. TA = 25°C, VCC = 3.0V, CMJ-145 (CL = 6pF, 32,768Hz) manufactured by Citizen.
Figure 15. Bus timing requirements sequence
SDA
tBUF
tHD:STA
tHD:STA
tR
tF
SCL
tHIGH
P
S
tLOW
tSU:DAT
tHD:DAT
tSU:STA
SR
tSU:STO
P
AI00589
Note:
P = STOP and S = START
Table 10. AC characteristics
Parameter(1)
Symbol
Min
Typ
Max
Unit
400
kHz
fSCL
SCL Clock Frequency
tLOW
Clock Low Period
1.3
µs
tHIGH
Clock High Period
600
ns
0
tR
SDA and SCL Rise Time
300
ns
tF
SDA and SCL Fall Time
300
ns
tHD:STA
START Condition Hold Time
(after this period the first clock pulse is generated)
600
ns
tSU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
600
ns
tSU:DAT
Data Setup Time
100
ns
0
µs
STOP Condition Setup Time
600
ns
Time the bus must be free before a new transmission
can start
1.3
µs
tHD:DAT(2) Data Hold Time
tSU:STO
tBUF
1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 1.3 to 4.4V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling
edge of SCL.
18/24
M41T60
6
Package mechanical information
Package mechanical information
Figure 16. QFN16 – 16-lead, quad, flat package, no lead, 3x3mm body size, Outline
D
E
A3
A
A1
ddd C
e
b
L
K
1
2
E2
Ch
3
K
D2
QFN16-A
Note:
Drawing is not to scale.
19/24
Package mechanical information
M41T60
Table 11. QFN16 – 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Mechanical
Data
mm
inches
Dim
Typ
Min
Max
Typ
Min
Max
A
0.90
0.80
1.00
0.035
0.032
0.039
A1
0.02
0.00
0.05
0.001
0.000
0.002
A3
0.20
–
–
0.008
–
–
b
0.25
0.18
0.30
0.010
0.007
0.012
D
3.00
2.90
3.10
0.118
0.114
0.122
D2
1.70
1.55
1.80
0.067
0.061
0.071
E
3.00
2.90
3.10
0.118
0.114
0.122
E2
1.70
1.55
1.80
0.067
0.061
0.071
e
0.50
–
–
0.020
–
–
K
0.20
–
–
0.008
–
–
L
0.40
0.30
0.50
0.016
0.012
0.020
ddd
–
0.08
–
–
0.003
–
Ch
–
0.33
–
–
0.013
–
N
16
16
Figure 17. QFN16, quad, flat package, no lead, 3x3mm, recommended footprint
Note:
20/24
Substrate pad should be tied to VSS.
M41T60
Package mechanical information
Figure 18. 32KHz Crystal + QFN16 vs. VSOJ20 mechanical data
7.0 ± 0.3
VSOJ20
6.0 ± 0.2
3.2
SMT
CRYSTAL
1
XI
2
XO
2.9
3
4
1.5
ST QFN16
2.9
AI11146
Note:
Dimensions shown are in millimeters (mm).
21/24
Part numbering
7
M41T60
Part numbering
Table 12. Ordering Information Scheme
Example:
M41T
60
Q
6
F
Device Family
M41T
Device Type and Supply Voltage
60 = VCC = 1.3 to 4.4V
Package
Q = QFN16 (3mm x 3mm)
Temperature Range
6 = –40 to 85°C
Shipping Method
F = Lead-Free Package, Tape & Reel
For other options, or for more information on any aspect of this device, please contact the
ST Sales Office nearest you.
22/24
M41T60
8
Revision history
Revision history
Table 13. Revision history
Date
Version
Changes
13-Nov-2003
1.0
First Issue
20-Nov-2003
1.1
Update characteristics (Figure 2, 3, 4; Table 1, 2, 5, 7, 10)
25-Dec-2003
2.0
Reformatted; add crystal isolation, footprint (Figure 12)
13-Jan-2004
2.1
Update characteristics (Figure 9, 10, 12; Table 7, 12)
26-Feb-2004
2.2
Update characteristics and mechanical dimensions (Figure 14, 17;
Table 4 , 7, 11)
02-Mar-2004
2.3
Update characteristics (Table 7)
26-Apr-2004
3.0
Reformat and republish
13-May-2004
4.0
Update characteristics (Table 7 , 7, 8; Figure 14 , 17)
06-Aug-2004
5.0
Update characteristics (Figure 2; Table 7, 9)
25-Oct-2004
6.0
Document Status Promotion; update characteristics (Figure 1;
Table 4 ,7, 8, 9, 12)
20-Dec-2004
7.0
Corrected footprint; update characteristics (Figure 4, 17; Table 7 , 7)
05-May-2005
8.0
Add package comparison and mechanical data (Figure Figure 18)
31-Oct-2005
9.0
Update: bus operating voltage, characteristics (Figure 4;
Table 4, 7, 10, 12)
30-Nov-2005
10.0
Update ESD:HBM rating, crystal characteristics (Table 4 , 8)
06-Jul-2006
11.0
New template
23/24
M41T60
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