M54HCT138 RAD HARD 3 TO 8 LINE DECODER (INVERTING) ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 16ns (TYP.) at VCC = 4.5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN.) VIL = 0.8V (MAX) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 138 DEVICE FULLY COMPLIANT WITH SCC-9205-022 DESCRIPTION The M54HCT138 is an high speed CMOS 3 TO 8 LINE DECODER fabricated with silicon gate C2MOS technology. If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A or G2B is held high, the decoding function is DILC-16 FPC-16 ORDER CODES PACKAGE FM EM DILC FPC M54HC138D M54HC138K M54HC138D1 M54HC138K1 inhibited and all the 8 outputs go high. Three enable inputs are provided to ease cascade connection and application of address decoders for memory systems. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION June 2004 Rev. 1 1/10 M54HCT138 Figure 1: IEC Logic Symbols Figure 2: Input And Output Equivalent Circuit Table 1: Pin Description PIN N° SYMBOL 1, 2, 3 4, 5 6 9, 10, 11, 12, 13, 14, 15, 7 8 16 A, B, C G2A, G2B G1 Y0 to Y7 GND VCC NAME AND FUNCTION Address Inputs Enable Inputs Enable Input Data Outputs Ground (0V) Positive Supply Voltage Table 2: Truth Table INPUTS OUTPUTS ENABLE SELECT G2B G2A G1 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X H L L L L L L L L X H X L L L L L L L L L X X H H H H H H H H X X X L L L L H H H H X X X L L H H L L H H X X X L H L H L H L H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L X : Don’t Care 2/10 M54HCT138 Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays Table 3: Absolute Maximum Ratings Symbol VCC Parameter Supply Voltage VI DC Input Voltage VO DC Output Voltage Value Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V V IIK DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ICC or IGND DC VCC or Ground Current Power Dissipation PD Tstg Storage Temperature TL Lead Temperature (10 sec) ± 25 mA ± 50 mA 300 mW -65 to +150 °C 265 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied Table 4: Recommended Operating Conditions Symbol VCC Parameter Value Unit Supply Voltage 4.5 to 5.5 V VI Input Voltage 0 to VCC V VO Output Voltage 0 to VCC V Top Operating Temperature -55 to 125 °C tr, tf Input Rise and Fall Time (VCC = 4.5 to 5.5V) 0 to 500 ns 3/10 M54HCT138 Table 5: DC Specifications Test Condition Symbol VIH VIL VOH VOL II ICC ∆ ICC Parameter High Level Input Voltage Low Level Input Voltage Min. 4.5 to 5.5 4.5 to 5.5 4.5 Low Level Output Voltage 4.5 Input Leakage Current Quiescent Supply Current Additional Worst Case Supply Current TA = 25°C VCC (V) High Level Output Voltage Value Typ. Max. 2.0 -40 to 85°C -55 to 125°C Min. Min. Max. 2.0 0.8 Max. 2.0 0.8 V 0.8 IO=-20 µA 4.4 4.5 4.4 4.4 IO=-4.0 mA 4.18 4.31 4.13 4.10 Unit V V IO=20 µA 0.0 0.1 0.1 0.1 IO=4.0 mA 0.17 0.26 0.33 0.40 V 5.5 VI = VCC or GND ± 0.1 ±1 ±1 µA 5.5 VI = VCC or GND 4 40 80 µA 5.5 Per Input pin VI = 0.5V or VI = 2.4V Other Inputs at VCC or GND IO = 0 2.0 2.9 3.0 mA Table 6: AC Electrical Characteristics (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (A, B, C - Y) tPLH tPHL Propagation Delay Time (G1 - Y) tPLH tPHL Propagation Delay Time (G2 - Y) Value TA = 25°C VCC (V) Min. -40 to 85°C -55 to 125°C Min. Min. Max. Unit Typ. Max. Max. 4.5 8 15 19 22 ns 4.5 17 30 38 45 ns 4.5 16 30 38 45 ns 4.5 19 30 38 45 ns Table 7: Capacitive Characteristics Test Condition Symbol Parameter VCC (V) Value TA = 25°C Typ. Max. CIN Input Capacitance Min. 5 10 CPD Power Dissipation Capacitance (note 1) 52 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC 4/10 M54HCT138 Figure 4: Test Circuit CL = 50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) Figure 5: Waveform - Propagation Delays For Inverting Outputs (f=1MHz; 50% duty cycle) 5/10 M54HCT138 Figure 6: WAVEFORM - PROPAGATION DELAYS FOR NON-INVERTING OUTPUTS (f=1MHz; 50% duty cycle) 6/10 M54HCT138 DILC-16 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 2.1 2.71 0.083 0.107 a1 3.00 3.70 0.118 0.146 a2 0.63 1.14 0.025 B 1.82 2.39 0.072 b 0.40 0.45 0.50 0.016 0.018 0.020 b1 0.20 0.254 0.30 0.008 0.010 0.012 D 20.06 20.32 20.58 0.790 0.800 0.810 E 7.36 7.62 7.87 0.290 0.300 0.310 e 0.88 2.54 0.035 0.045 0.094 0.100 e1 17.65 17.78 17.90 0.695 0.700 0.705 e2 7.62 7.87 8.12 0.300 0.310 0.320 F 7.29 7.49 7.70 0.287 0.295 0.303 I 3.83 0.151 K 10.90 12.1 0.429 0.476 L 1.14 1.5 0.045 0.059 0056437F 7/10 M54HCT138 FPC-16 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 6.75 6.91 7.06 0.266 0.272 0.278 B 9.76 9.94 10.14 0.384 0.392 0.399 C 1.49 1.95 0.059 D 0.102 0.127 0.152 0.004 0.005 0.006 E 8.76 8.89 9.01 0.345 0.350 0.355 F 0.077 1.27 G 0.38 H 6.0 L 18.75 M 0.33 0.050 0.43 0.48 0.015 0.017 0.019 0.237 0.38 N 22.0 0.738 0.43 0.013 0.867 0.015 4.31 0.017 0.170 G F D H 9 16 A N L 8 1 H E B 8/10 M C 0016030E M54HCT138 Table 8: Revision History Date Revision 16-Jun-2004 1 Description of Changes First Release 9/10 M54HCT138 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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