STMICROELECTRONICS M65KA512AB8W3

M65KA512AB
512Mbit (4 Banks x 8M x 16), 133 MHz Clock Rate,
Bare Die, 1.8 V Supply, Low Power SDRAM
Features
■
512 Mbit Synchronous Dynamic Ram
– Organized as 4 Banks of 8 Mwords, each
16 bits wide
■
Supply voltage
– VDD = 1.7 to 1.9 V (1.8 V typical in
accordance with JEDEC standard)
– VDDQ = 1.7 to 1.9 V for Input/Output
■
Synchronous Burst Read and Write
– Fixed Burst Lengths: 1, 2, 4, 8 words or Full
Page
– Burst Types: Sequential and Interleaved.
– Clock Frequency: 133 MHz (7.5 ns speed
class)
– Clock Valid to Output Delay (CAS Latency):
3 at 133 MHz
– Burst Control by Burst Terminate and
Precharge Command
■
Automatic and controlled Precharge
■
Byte control by LDQM and UDQM
■
Low-power features:
– Partial Array Self Refresh (PASR),
– Automatic Temperature Compensated Self
Refresh (TCSR)
– Driver Strength (DS)
– Deep Power-Down Mode
■
Auto Refresh and Self Refresh
■
LVCMOS Interface compatible with
multiplexed addressing
■
Operating temperature range
– − 30to 85 °C
Wafer
M65KA512AB is only available as part of a multiple memory product
March 2007
Rev 3
1/55
www.st.com
1
Contents
M65KA512AB
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
4
2/55
2.1
Address Inputs (A0-A12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
Bank Select Address Inputs (BA0-BA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Data Inputs/Outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5
Column Address Strobe (CAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6
Row Address Strobe (RAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8
Clock Input (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9
Clock Enable (KE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.10
Lower/Upper Data Input/Output Mask (LDQM, UDQM) . . . . . . . . . . . . . . 10
2.11
VDD Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.12
VDDQ Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.13
VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.14
VSSQ Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4
Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5
Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.7
Deep Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
Mode Register Set command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2
Extended Mode Register Set command . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3
Bank (Row) Activate command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4
Write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
M65KA512AB
5
Contents
4.5
Read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6
Precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.7
Auto Precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.8
Burst Terminate command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.9
Data Mask command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.10
Clock Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.11
Auto Refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.12
Self Refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.13
Power-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14
Deep Power-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1
Mode Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2
Burst Length bits (MR0 to MR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3
Burst Type bit (MR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.4
CAS Latency bits (MR4 to MR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.5
Extended Mode Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.5.1
Partial Array Self Refresh bits (EMR0-EMR2) . . . . . . . . . . . . . . . . . . . . 22
5.5.2
Driver Strength bit (EMR5-EMR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.5.3
Automatic Temperature Compensated Self Refresh bits (EMR3-EMR4) .
22
6
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7
DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3/55
List of tables
M65KA512AB
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
4/55
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Extended mode Register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DC characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DC characteristics 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Self-Refresh current values in Normal Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC characteristics 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
M65KA512AB
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Chip Enable Signal during Read, Write and Precharge ac waveforms. . . . . . . . . . . . . . . . 30
Read with Precharge ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Read with Auto Precharge ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Clock Suspend during Burst Read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Random Column Read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Random Row Read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Column Interleaved Read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Burst Column Read followed by Auto Precharge ac waveforms . . . . . . . . . . . . . . . . . . . . 37
Write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Byte Write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Mode Register Set ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Clock Suspend during Burst Write ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Random Column Write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Random Row Write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Column Interleaved Write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Burst Column Write followed by Auto Precharge ac waveforms. . . . . . . . . . . . . . . . . . . . . 45
Precharge termination ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Power-On sequence ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Power-Down mode and Clock Masking ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Auto refresh ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Self refresh ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Deep Power-Down Entry ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Deep Power-Down Exit ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5/55
Description
1
M65KA512AB
Description
The M65KA512AB is a 512 Mbit Low Power Synchronous DRAM (SDRAM). The memory
array is organized as 4 Banks of 8,388,608 words of 16 bits each.
The LPSDRAM achieves low power consumption and high-speed data transfer using the
pipeline architecture.
The device architecture is illustrated in Figure 2: Functional block diagram. It uses Burst
mode to read and write data. It is capable of one, two, four, eight-word and full-page,
sequential and interleaved Burst.
To minimize current consumption during self-refresh operations, the M65KA512AB includes
three mechanisms configured via the Extended Mode Register:
●
Automatic Temperature Compensated Self Refresh (ATCSR) used to adapt the refresh
time according to the operating temperature (see Table 5: Extended mode Register
definition)
●
Partial Array Self Refresh (PASR) performs a limited refresh of part of the PSRAM
memory array. This area can be configured to half bank, a quarter of bank, one bank,
two banks or all banks. This mechanism allows to reduce the device Standby current by
refreshing only the part of the memory array that contains essential data.
●
The Deep Power-Down (DPD) mode completely halts the refresh operation and
achieves minimum current consumption by cutting off the supply voltage from the
whole memory array.
The device is programmable through two registers, the Mode Register and the Extended
Mode Register:
6/55
●
The Mode Register is used to select the CAS Latency, the Burst Type (sequential,
interleaved) and the Burst Length (1-, 2-, 4-, 8-word width or full page) through
programming the A6 to A4 bits, the A3 bit and the A2 to A0 bits, respectively (see
Table 4).
●
The Extended Mode Register is used to program the low-power features (PASR,
ATCSR) and Driver Strength) to reduce the current consumption during the Self
Refresh operations. For more details, refer to Table 5: Extended mode Register
definition, and to Section 4.2: Extended Mode Register Set command.
M65KA512AB
Figure 1.
Description
Logic diagram
VDD VDDQ
13
16
A0-A12
DQ0-DQ15
2
BA0-BA1
E
RAS
UDQM
M65KA512AB
LDQM
CAS
K
KE
W
VSS
Table 1.
VSSQ
AI12117
Signal names
Name
A0-A12
Description
Direction
Address Inputs
Inputs
BA0-BA1
Bank Select Inputs
Inputs
DQ0-DQ15
Data Inputs/Outputs
Input/Outputs
K
Clock Input
Input
KE
Clock Enable Input
Input
E
Chip Enable Input
Input
W
Write Enable Input
Input
RAS
Row Address Strobe Input
Input
CAS
Column Address Strobe Input
Input
UDQM
Upper Data Input/Output Mask
Input
LDQM
Lower Data Input/Output Mask
Input
VDD
VDDQ
VSS
VSSQ
Supply voltage
Supply
Input/Output Supply voltage
Supply
Ground
-
Input/Output Ground
-
7/55
Description
Figure 2.
M65KA512AB
Functional block diagram
TCSR, PASR
Extended
Mode
Register
Self Refresh
Logic & Timer
Internal Row
Counter
K
DQ0
...
I/O Buffer & Logic
Column Decoders
...
Column
PreDecoders
U/LDQM
Memory
Cell
Array
Sense AMP & I/O Gate
Column
Active
8 Mb x 16 Bank 0
...
W
8 Mb x 16 Bank 1
Row Decoders
CAS
Refresh
8 Mb x 16 Bank 2
Row Decoders
RAS
8 Mb x 16 Bank 3
Row Decoders
State Machine
E
Row
PreDecoders
Row Decoders
Row
Active
KE
DQ15
Column Add
Counter
Bank Select
A0
Address
Registers
A1
Burst Length
BA0
Address Buffers
BA1
...
...
A12
Mode
Register
Burst
Counter
CAS Latency
Data Out
Control
ai12118
8/55
M65KA512AB
2
Signal descriptions
Signal descriptions
See Figure 1: Logic diagram, and Table 1: Signal names, for a brief overview of the signals
connected to this device.
2.1
Address Inputs (A0-A12)
The A0-A12 Address Inputs are used to select the row or column to be made active. If a row
is selected, all thirteen A0-A12 Address Inputs are used. If a column is selected, only the ten
least significant Address Inputs, A0-A9, are used. In this latter case, A10 determines
whether Auto Precharge is used. If A10 is High (set to ‘1’) during Read or Write, the Read or
Write operation includes an Auto Precharge cycle. If A10 is Low (set to ‘0’) during Read or
Write, the Read or Write cycle does not include an Auto Precharge cycle.
2.2
Bank Select Address Inputs (BA0-BA1)
The BA0 and BA1 Banks Select Address Inputs are used to select the bank to be made
active.
The device must be enabled, the Row Address Strobe, RAS, must be Low, VIL, the Column
Address Strobe, CAS, and W must be High, VIH, when selecting the addresses. The
address inputs are latched on the rising edge of the clock signal, K.
2.3
Data Inputs/Outputs (DQ0-DQ15)
The Data Inputs/Outputs output the data stored at the selected address during a Read
operation, or are used to input the data during a write operation.
2.4
Chip Enable (E)
The Chip Enable input E activates the memory state machine, address buffers and
decoders when driven Low, VIL. When High, VIH, the device is not selected.
2.5
Column Address Strobe (CAS)
The Column Address Strobe, CAS, is used in conjunction with Address Inputs A0-A9 and
BA1-BA0, to select the starting column location prior to a Read or Write.
2.6
Row Address Strobe (RAS)
The Row Address Strobe, RAS, is used in conjunction with Address Inputs A0-A12 and
BA1-BA0, to select the starting address location prior to a Read or Write.
9/55
Signal descriptions
2.7
M65KA512AB
Write Enable (W)
The Write Enable input, W, controls writing.
2.8
Clock Input (K)
The Clock signal, K, is used to clock the Read and Write cycles. During normal operation,
the Clock Enable pin, KE, is High, VIH. The clock signal K can be suspended to switch the
device to the Self-Refresh, Power-Down or Deep Power-Down mode by driving KE Low, VIL.
2.9
Clock Enable (KE)
The Clock Enable, KE, pin is used to control the synchronizing of the signals with Clock
signal K. If KE is High, VIH, the next Clock rising edge is valid. When KE is Low, VIL, the
signals are no longer clocked and data Read and Write cycles are extended. KE is also
involved in switching the device to the Self-Refresh, Power-Down and Deep Power-Down
modes.
2.10
Lower/Upper Data Input/Output Mask (LDQM, UDQM)
Lower Data Input/Output Mask and Upper Data Input/Output Mask pins are input signals
used to mask the Read or Write data. The DQM latency is two clock cycles for read
operations and there is no latency for write operations.
2.11
VDD Supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main
power supply for all operations (Read and Write).
2.12
VDDQ Supply voltage
VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered
independently of VDD. VDDQ can be tied to VDD or can use a separate supply.
It is recommended to power-up and power-down VDD and VDDQ together to avoid certain
conditions that would result in data corruption.
2.13
VSS Ground
Ground, VSS, is the reference for the core power supply. It must be connected to the system
ground.
10/55
M65KA512AB
2.14
Signal descriptions
VSSQ Ground
VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be
connected to VSS.
Note:
Each device in a system should have VDD and VDDQ decoupled with a 0.1µF ceramic
capacitor close to the pin (high frequency, inherently low inductance capacitors should be as
close as possible to the package).
11/55
Operations
3
M65KA512AB
Operations
There are 7 operating modes that control the memory. Each of these is described in this
section, see Table 2: Operating mode, for a summary.
3.1
Power-Up
The Low-Power SDRAM has to be powered up and initialized in a well determined manner.
Power must be applied to VDD and VDDQ simultaneously and, at the same time, the clock
signal must be started. After Power-Up, a minimum initial pause of 200µs is required. From
power-up until the Precharge command is issued, the KE and DQM signals must be held
High. The Precharge command must then be issued to all banks, and 2 or more Auto
Refresh cycles must be executed after the precharge is completed and the minimum tRP is
satisfied. Once these cycles are completed, a Mode Register Set command must be issued
to program the specific operation mode (CAS Latency, Burst Length, etc.). After issuing the
Mode Register Set command, the device will not accept any other command for tRSC. After
issuing the Extended Mode Register Set command the device will not accept any other
command for tRSC.
The device is now ready for normal operation.
Refer to Figure 22 for a detailed description of the Power-Up ac waveforms.
3.2
Burst Read
The Read command is used to switch the device to Burst Read mode (see Section 4.5:
Read command for details). In Burst Read mode the data is output in bursts synchronized
with the clock. Burst Read opertions are initiated by driving E and CAS Low, VIL, W and
RAS High, and VIH, at the positive edge of the clock signal, K.
Burst Read can be accompanied by an Auto Precharge cycle depending on the state of the
A10 Address Input. If A10 is High (set to ‘1’) when the Burst Read command is issued, the
Burst Read operation is followed by an Auto Precharge cycle. If A10 is Low (set to ‘0’), the
row will remain active for subsequent accesses.
BA1 and BA0 are used to select the bank, and the A0-A9 address inputs are used to select
the starting column location. The Burst Length, Burst Type, and CAS Latency depend on the
values programmed by issuing a Mode Register Set command (see Section 5.1: Mode
Register description).
After a Burst Read operation is completed, data outputs become High-Z.
Refer to Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11 and Figure 12 for a
detailed description of Burst Read ac waveforms.
12/55
M65KA512AB
3.3
Operations
Burst Write
The Write command is used to switch the device to Burst Write mode (see Section 4.4:
Write command for details). In Burst Write mode the data is input in bursts synchronized
with the clock. Burst Write operations are initiated by driving E, CAS and W Low, VIL, and
RAS High, and VIH, at the positive edge of the clock signal, K.
Burst Write can be accompanied by an Auto Precharge cycle depending on the state of the
A10 Address Input. If A10 is High (set to ‘1’) when the Write command is issued, the Write
operation is followed by an Auto Precharge cycle. If A10 is Low (set to ‘0’), Auto Precharge
is not selected and the row will remain active for subsequent accesses.
BA1 and BA0 are used to select the bank, and the A0-A9 address inputs are used to select
the starting column location.
Refer to Figure 13, Figure 14, Figure 16, Figure 17, Figure 18, Figure 19 and Figure 20 for a
detailed description of Burst Write ac waveforms.
3.4
Self Refresh
In Self Refresh mode, the data contained in the Low-Power SDRAM memory array is
retained and refreshed. The Low-Power SDRAM refresh cycles are asynchronous.
All banks must be precharged prior to executing a Self-Refresh operation. The Self-Refresh
mode is entered by driving KE Low (set to ‘0’), with E, RAS, and CAS Low, and W High (set
to ‘1’). When in this mode, the device is not clocked any more.
The Self Refresh mode is exited by driving KE from Low to High, with E High, RAS, CAS
and W Don’t Care, or with E Low and RAS, CAS and W High.
The Self Refresh operation is performed according to the settings of Extended Mode
Register bits EMR0 to EMR2. They configure the amount of the memory to be refreshed
(Partial Array Self Refresh).
3.5
Auto Refresh
The Auto Refresh mode is used to refresh the Low-Power SDRAM in normal operation
mode whenever needed.
All banks must be precharged prior to executing an Auto Refresh operation.
During the Auto Refresh, the address bits are “Don’t Care”, because the specific address
bits are generated by the internal refresh address counter.
3.6
Power-Down
In Power-Down mode, the current is reduced to the standby current (IDD3P).
All banks must be precharged before entering Power-Down mode. For the memory to enter
the Power-Down mode, KE must be held Low (set to ‘0’), after the Precharge Time tRP, with
E High (set to ‘1’), RAS, CAS and W Don’t Care, or with E Low, RAS, CAS and W High.
13/55
Operations
3.7
M65KA512AB
Deep Power-Down
The purpose of this mode is to achieve maximum power reduction by cutting the power
supply to the whole memory array. Data is no longer retained when the device enters Deep
Power-Down Mode.
All banks must be precharged before entering Deep Power-Down mode. The
M65KA512ABM65KA512AB enters Deep Power Down Mode by holding E and W Low with
RAS and CAS High at the rising edge of the clock, K, while driving KE Low (see Figure 26:
Deep Power-Down Entry ac waveforms).
The M65KA512AB exits Deep Power-Down mode by asserting KE High. A special
sequence is then required before the device can take any new command into account:
1.
Maintain No Operation status conditions for a minimum of 200µs,
2.
Issue a Precharge command to all banks of the device (see Section 4.6: Precharge
command for details),
3.
Issue a Mode Register Set command to initialize the Mode Register bits,
4.
Issue an Extended Mode Register Set command to initialize the Extended Mode
Register bits,
5.
Issue 2 or more Auto Refresh commands.
The Deep Power-Down mode exit sequence is illustrated in Figure 27: Deep Power-Down
Exit ac waveforms.
Note:
14/55
The 2 Auto Refresh commands can be issued either after or before the configuration of the
Mode and Extended Mode Registers.
M65KA512AB
Table 2.
Operations
Operating mode(1)
Operating mode
KEn-1
KEn
E
RAS
CAS
W
A10
A11,
A12
A0-A9
BA0BA1
UDQM/L
DQM
Burst Read
VIH
X
VIL
VIH
VIL
VIH
VIL
Valid
Start
Column
Address
Bank
Select
Valid
Burst Write
VIH
X
VIL
VIH
VIL
VIL
VIL
Valid
Start
Column
Address
Bank
Select
X
Self Refresh
VIH
VIL
VIL
VIL
VIL
VIH
X
X
X
Auto Refresh
VIH
VIH
VIL
VIL
VIL
VIH
X
X
X
Power-Down with
Precharge
VIH
VIL
VIL
VIH
VIH
VIH
X
X
X
VIH
X
X
X
Deep PowerDown
VIH
VIL
VIL
VIH
VIH
VIL
X
X
X
Device Deselect
VIH
X
VIH
X
X
X
X
X
No operation
VIH
X
VIL
VIH
VIH
VIH
X
X
X
X
X
1. X = Don’t Care VIL or VIH.
15/55
Commands
4
M65KA512AB
Commands
There are 14 basic commands that control the memory. They can be combined to obtain 21
higher level commands shown in Table 3: Commands.
4.1
Mode Register Set command
The Mode Register Set command is issued by applying VIL to E, RAS, CAS and W and by
setting BA0 and BA1 to ‘0’.
The Mode Register Set command is used to configure the specific mode of operation of the
device by programming the Mode Register:
●
Burst Length (1, 2, 4, 8, Full Page),
●
CAS Latency (2, or 3),
●
Burst Type (sequential or interleaved).
The Mode Register Set command must be executed after the Power-Up sequence prior to
issuing a Bank(Row) Activate command (see Figure 15: Mode Register Set ac waveforms).
4.2
Extended Mode Register Set command
The Extended Mode Register Set command is issued by applying VIL to E, RAS, CAS and
W, and then by setting BA0 to ‘0’, and BA1 to ‘1’.
The Extended Mode Register Set command is used to configure the self refresh operation
of the device and the driver strength by programming the Extended Mode Register bits:
●
Partial arrays to be refreshed (all banks, two banks, one bank),
●
Driver strength (full, 1/2 strength, 1/4 strength, 1/8 strength).
The Extended Mode Register bit controlling the Automatic TSCR (A9) should always be
cleared to ‘0’ (A9 = ‘1’ is reserved).
The Extended Mode Register Set command must be executed after the Power-Up
sequence prior to issuing a Bank(Row) Activate command.
4.3
Bank (Row) Activate command
The Bank (Row) Activate command is used to activate a row in a specific bank of the device.
This command is initiated by driving E and RAS Low, and CAS and W High, VIH, at the
positive edge of the clock signal, K. The value on BA1 and BA0 selects the bank, and the
value on A0-A12 selects the row. The selected row remains active for column access until a
Precharge command is issued to that bank.
A minimum time of tRCD is required after issuing the Bank (Row) Active command prior to
initiating Read and Write operations from and to the activated bank.
16/55
M65KA512AB
4.4
Commands
Write command
The Write command is used to switch the Low-Power SDRAM to Burst Write mode (see
Section 3.3: Burst Write mode).
4.5
Read command
The Read command is used to switch the Low-Power SDRAM to Burst Read mode (see
Section 3.2: Burst Read).
4.6
Precharge command
The Precharge command is used to close the open row in a particular bank or the open row
in all banks. When the precharge command is issued with address A10 driven High, all
banks will be precharged. If A10 is driven Low, the open row in a particular bank will be
precharged. The bank(s) will be available when the minimum tRP time has elapsed after the
precharge command has been issued.
4.7
Auto Precharge command
The Auto Precharge command is used to close the open row in a specific bank after a Read
or Write operation. A10 is High, VIH, when a Read (or Write) command is issued.
4.8
Burst Terminate command
The Burst Terminate command is used to terminate a Burst operation. A Burst operation can
be interrupted by using the Precharge command (see Section 4.6: Precharge command for
details), or by issuing the Burst Terminate command. Issuing the Burst Terminate command
during a Burst Read or Write cycle will terminate the burst while leaving the bank open.
4.9
Data Mask command
The Data Mask command is used to mask Read or Write data.A Data Mask command
issued during a Read operation will disable the data outputs, switching them to the high
impedance state after a delay of two clock cycles. A Data Mask command issued during a
Write operation will disable the data inputs with no delay.
4.10
Clock Suspend command
The Clock Suspend command is used to interrupt the internal clock of the LPSDRAM. The
command is controlled by the Clock Enable input, KE, which is kept High, VIH, in normal
access mode.The Clock Suspend command is issued by driving KE Low,VIL, thus freezing
the internal clock, and extending data Read and Write operations.
17/55
Commands
4.11
M65KA512AB
Auto Refresh command
The Auto Refresh command is used to put the device in Auto refresh mode (see Section 3.5:
Auto Refresh and Figure 24: Auto refresh ac waveforms).
4.12
Self Refresh command
The purpose of the Self Refresh command is used to put the device in Self Refresh mode to
retain and refresh the data contained in the Low-Power SDRAM memory array. In Self
Refresh mode, the Low-Power SDRAM runs Refresh cycles asynchronously.
The Self Refresh cycle is performed according to the Extended Mode Register bits EMR0 to
EMR2 that configure the part of the memory array being refreshed (Partial Array Self
Refresh).
For more information on how the command is issued, refer to Figure 25: Self refresh ac
waveforms.
4.13
Power-Down command
The Power-Down command is used to put the device in Power-Down mode where the
operating current is reduced to the Standby current.
All banks must be precharged and a minimum time of tRP must elapse before issuing the
Power-Down command.
4.14
Deep Power-Down command
The Deep Power-Down command is used to switch the Low-Power SDRAM to Deep PowerDown Mode. This mode provides maximum power reduction as it cuts the power of the
entire memory array of the device. For more information on how the command is issued and
its exit sequence, see Section 3.7: Deep Power-Down, Figure 26: Deep Power-Down Entry
ac waveforms, and Figure 27: Deep Power-Down Exit ac waveforms.
18/55
M65KA512AB
Table 3.
Commands
Commands(1)
Command
KEn-1
KE
E
RAS
CAS
W
UDQM/
LDQM
DQ0DQ15
Mode Register Set
VIH
X
VIL
VIL
VIL
VIL
X
X
X
(3)
Extended Mode
Register Set
VIH
X
VIL
VIL
VIL
VIL
X
X
X
(4)
Bank (Row) Activate
VIH
X
VIL
VIL
VIH
VIH
X
X
Row address
V
Read
VIH
X
VIL
VIH
VIL
VIH
VIL
X
Column
VIL
V
Read with Auto
Precharge
VIH
X
VIL
VIH
VIL
VIH
VIL
X
Column
VIH
V
Write
VIH
X
VIL
VIH
VIL
VIL
VIL
X
Column
VIL
V
Write with Auto
Precharge
VIH
X
VIL
VIH
VIL
VIL
VIL
X
Column
VIH
V
Precharge all BANKS
VIH
X
VIL
VIL
VIH
VIL
X
X
X
VIH
X
Precharge selected
Bank
VIH
X
VIL
VIL
VIH
VIL
X
X
X
VIL
V
Burst Terminate
VIH
VIH
VIL
VIH
VIH
VIL
X
X
X
X
Clock Suspend Entry
VIH
VIL
X
X
X
X
X
X
X
X
Clock Suspend Exit
VIL
VIH
X
X
X
X
X
X
X
X
Data Mask / Output
Enable
VIH
X
X
X
X
X
VIL
X
X
X
Data Mask / Output
Disable
VIH
X
X
X
X
X
VIH
High-Z
X
X
Auto-Refresh
VIH
VIH
VIL
VIL
VIL
VIH
X
X
X
X
Self-Refresh Entry
VIH
VIL
VIL
VIL
VIL
VIH
X
X
X
X
Self-Refresh Exit(5)
X
X
X
VIH
VIH
X
VIL
X
X
X
VIL
VIH
VIH
VIH
X
X
X
X
VIL
VIH
X
VIH
X
X
X
VIL
VIH
VIH
VIH
X
X
X
X
VIH
VIH
X
VIL
X
X
X
VIL
VIH
VIH
VIH
X
Deep Power-down
Entry
VIH
VIL
VIL
VIH
VIH
VIL
X
X
X
X
Deep Power-down Exit
VIL
VIH
X
X
X
X
X
X
X
X
Power-down Entry
Power-down Exit
Addr.
A10
(2)
BA0BA1
1. X = Don’t Care (VIL or VIH), V = Valid Data.
2. Addresses AO to A12 except A10.
3. BA1 and BA0 must both be set to ‘0’ to issue the Mode Register Set Command.
4. BA1 and BA0 must be set to ‘1’ and ‘0’, respectively, to issue the Extended Mode Register Set Command.
5. The Self-Refresh mode is exited by asynchronously driving KE from Low to High
19/55
Register descriptions
M65KA512AB
5
Register descriptions
5.1
Mode Register description
The Mode Register is used to select the CAS Latency (2 or 3), the Burst Type (sequential,
interleaved), the Burst Length (1-, 2-, 4-, 8-word width or full page).
It is loaded by issuing a Mode Register Set command that programs A0 to A12 address bits.
The values placed on the address lines are then latched into the Mode Register. BA0-BA1
must be set to ‘0’.
See Table 4: Mode Register Definition, for more details.
5.2
Burst Length bits (MR0 to MR2)
Bits 0 to 2 (MR0 to MR2) of the Mode Register are used to configure the Burst Length. The
burst Length is the number of words that are output or input during a read or a write
operation, respectively. It can be set to 1, 2, 4, 8 words or full page.
5.3
Burst Type bit (MR3)
Bit 3 (MR3) of the Mode Register is used to set the Burst Type. The Burst Type defines the
order in which the address locations are accessed during a burst operation. It can be either
sequential or interleaved.
The type of application microprocessor must be taken into account when selecting the Burst
Type: some microprocessor cache systems are optimized for sequential addressing and
others for interleaved addressing.
Both Burst Types support burst length of 1, 2, 4 or 8 words. Full page burst is also available
when the sequential burst type is selected.
5.4
CAS Latency bits (MR4 to MR6)
The CAS latency is the most critical of the Mode Register parameters. It defines the number
of clocks cycles between the detection of a Read command to the first data output valid. It
can be set to two or three clock cycles.
The value of this parameter is determined by the frequency of the clock and the speed grade
of the device.
Table 4.
Mode Register Definition
Address
Bits
Mode
Register bit
Register
description
A12-A7
-
-
A6-A4
MR6-MR4
CAS Latency bits
Value
Description
0000000
010
2 clock cycles
011
3 clock cycles(1)
Other configurations reserved
20/55
M65KA512AB
Register descriptions
Table 4.
Mode Register Definition
Address
Bits
Mode
Register bit
Register
description
A3
MR3
Burst type
A2-A0
MR2-MR0
Burst Length bit
Value
Description
0
Sequential
1
Interleaved
000
1 word (A3 is Don’t Care)
001
2 words (A3 is Don’t Care)
010
4 words (A3 is Don’t Care)
011
8 words (A3 is Don’t Care)
111
Full Page if A3 = 0
Reserved if A3 = 1
Other configurations reserved
BA1-BA0
-
-
00
1. At 133MHz, the CAS Latency must be set to 3.
21/55
Register descriptions
5.5
M65KA512AB
Extended Mode Register description
The Extended Mode Register is used to configure the low-power self-refresh operation of
the device (PASR, DS). It is used to select the area of the memory array refreshed during
Partial Array Self Refresh operations, and the driver strength.
It is loaded by issuing a Extended Mode Register Set command that programs A0 to A12
address bits. The values placed on the address lines are then latched into the Extended
Mode Register. BA0 and BA1 must be set to ‘0’ and ‘1’ respectively.
See Table 5: Extended mode Register definition, for more details.
5.5.1
Partial Array Self Refresh bits (EMR0-EMR2)
Bits EMR0 to EMR2 of the Extended Mode Register allow to configure the amount of
memory that will be refreshed during a Self Refresh operation (see Section 3.4: Self
Refresh). It can be set to:
●
All Banks (banks 0, 1, 2, and 3)
●
Two Banks (banks 0 and 1)
●
One Bank (bank 0).
It is important to note that the data stored in the banks or portion of banks which are not
refreshed, are lost. As an example, data stored in banks 1, 2 and 3 are lost when the PASR
is set to one bank (bank 0 refreshed).
5.5.2
Driver Strength bit (EMR5-EMR6)
Extended Mode Register bits, EMR5 and EMR6, can be used to select the driver strength of
data outputs. This value should be set according to the application requirements.
5.5.3
Automatic Temperature Compensated Self Refresh bits (EMR3-EMR4)
The M65KA512ABM65KA512ABhas a built-in temperature sensor that controls
automatically the internal self refresh rate.
22/55
M65KA512AB
Register descriptions
Table 5.
Extended mode Register definition
Address
bits
Mode
Register bit
Description
A12-A10
-
-
0
Enabled
EMR9
Automatic
Temperature
Compensated
Self-Refresh
(ATCSR)
1
Reserved
-
00
A9
A8-A7
A6-A5
A4-A3
-
EMR6-EMR5
-
Driver strength
bits
-
Value
0000
00
Full strength
01
1/2 strength
10
1/4 strength
11
1/8 strength
00
000
A2-A0
EMR2-EMR0
Description
Partial Array Self- 001
Refresh bits
010
All Banks
Two Banks (BA1=0)
One Bank (BA0 and BA1 =0)
Other configurations reserved
BA1-BA0
-
-
10
23/55
Maximum rating
6
M65KA512AB
Maximum rating
Stressing the device above the ratings listed in Table 6: Absolute maximum ratings, may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 6.
Absolute maximum ratings
Value
Symbol
Unit
Min
Max
TJ
Junction temperature
− 30
85
°C
TSTG
Storage temperature
− 55
125
°C
Input or Output voltage
− 0.5
2.3
V
Supply voltage
− 0.5
2.3
V
VIO
VDD, VDDQ
IOS
24/55
Parameter
Short Circuit Output current
50
mA
M65KA512AB
7
DC and ac parameters
DC and ac parameters
This section summarizes the operating and measurement conditions, and the dc and ac
characteristics of the device. The parameters in the dc and ac characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 7: Operating and ac measurement conditions. Designers should check that the
operating conditions in their circuit match the measurement conditions when relying on the
quoted parameters.
Table 7.
Operating and ac measurement conditions
Parameter(1)
Symbol
M65KA512AB
Units
Min
Max
Supply voltage
1.7
1.9
V
Input/Output supply voltage
1.7
1.9
V
TJ
Junction temperature
− 30
85
°C
CL
Load capacitance
30
pF
Input Transition Time between VIL and VIH
Input Rise/Fall time
0.5
ns
VIL
Input Pulses Low voltage
0.2
V
VIH
Input Pulses High voltage
1.6
V
Input and Output Timing ref. voltages
0.9
V
VDD
VDDQ
tT,
tR, tF
VREF
1. All voltages are referenced to VSS = 0 V.
Figure 3.
AC measurement I/O waveform
Input Timing Reference Voltage
1.6V
VDDQ/2
0.2V
Output Transition Timing Reference Voltage
VDDQ
VDDQ/2
0V
AI08009c
25/55
DC and ac parameters
Figure 4.
M65KA512AB
AC measurement load circuit
Output
CL
AI12109
Table 8.
Symbol
Capacitance
Parameter
Signal
Input capacitance
CIO
Unit
Min
Max
K
2.0
4.5
pF
A0-A11, BA0, BA1, KE, E, RAS,
CAS, W, UDQM, LDQM
2.0
4.5
pF
DQ0-DQ15
3.5
6.0
pF
CI1
CI2
M65KA512ABM65
KA512AB(1)
Data I/O capacitance
1. TJ = 25 °C, f = 1 MHz
Table 9.
DC characteristics 1
Symbol
Parameter
M65KA512ABM65KA5
12AB
Min
Max
Unit
ILI
Input Leakage current
0V≤ VIN ≤ 1.8V
−2
2
µA
ILO
Output Leakage current
0V≤ VOUT ≤1.8V
− 1.5
1.5
µA
(2)
Input Low voltage
VIN = 0V
− 0.3
0.3
V
VIH(3)
Input High voltage
VIN = 0V
0.8 VDDQ
VDDQ + 0.3
V
VOL
Output Low voltage
IOUT = 100µA VIN = 0V
0.2
V
VOH
Output High voltage
IOUT = –100µA VIN = 0V VDDQ− 0.2
VIL
1. TJ = –30 to 85 °C.
2. VIL (min.) = −0.5 V (pulse width ≤ 5 ns)
3. VIH (max.) = 2.3 V (pulse width ≤ 5 ns).
26/55
Test
condition(1)
V
M65KA512AB
Table 10.
DC and ac parameters
DC characteristics 2
Symbol
M65KA512AB
Test condition(1)
Parameter
Unit
Max
Operating current
IDD2P
Precharge Standby current in
Power-Down Mode
IDD2PS
IDD2N
Precharge Standby current in
Non Power-Down Mode
IDD2NS
IDD3P
IDD3PS
IDD3N
Active Standby current in
Power-Down Mode
Active Standby current in
Non Power-Down Mode
IDD3NS
IDD4(2)
70
CAS Latency = 2 Burst length = 1, one bank active
CAS Latency = 3 tRC ≥ tRC(min), IOL = 0 mA
IDD1(2)
Burst Mode current
mA
70
KE ≤ VIL(max), tK = tK(min)
0.8
KE ≤ VIL(max), tK = ∞
0.6
KE ≥ VIH (min), E ≥ VIH (min), tK =
tK(min)
Input signals changed once in 30 ns
All other pins ≥ VDD − 0.2 V or ≤ 0.2 V
4.0
KE ≥ VIH (min), tK = ∞
Input signals are stable
2.0
KE ≤ VIL(max), tK = tK(min)
3.0
KE ≤ VIL(max), tK = ∞
1.2
KE ≥ VIH (min), E ≥ VIH (min), tK= tK(min)
Input signals changed once in 30 ns
All other pins ≥ VDD − 0.2 V or ≤ 0.2 V
10
KE ≥ VIH (min), tK = ∞
Input signals are stable
7
mA
mA
mA
mA
CAS Latency = 2 tK ≥ tK (min), IOL = 0 mA
CAS Latency = 3 All banks active
50
mA
85
IDD5
Auto-Refresh current
tRRC ≥ tRRC (min), All banks active
IDD6
Self-Refresh current
IDD7
Standby current in Deep
Power-Down Mode
90
mA
KE ≤ 0.2 V
See Table 11
µA
KE ≤ 0.2 V
10
µA
1. TJ = –30 to 85 °C.
2. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.
Table 11.
Self-Refresh current values in Normal Operating Mode
Memory array(1)
Temperature in °C
4 Banks
Typ
2 Banks
Max
Typ
1 Bank
Max
Typ
Unit
Max
70 ≤ TJ ≤ 85
800
650
490
µA
40 ≤ TJ ≤ 70
550
380
290
µA
–30 ≤ TJ ≤ 40
300
240
210
µA
1. VDD = 1.8 ± 0.1 V, VDDQ = 1.8 ± 0.1 V, VSSQ = 0 V.
27/55
DC and ac parameters
M65KA512AB
Table 12.
AC characteristics 1
Symbol
Alt.
tAC
M65KA512AB
M65KA512AB
Parameter
Min.
Max.
CAS Latency=3
-
6
ns
CAS Latency=2
-
8
ns
Access Time from clock
tAS(1)
Address Setup Time
1.9
-
ns
tAH(1)
Address Hold Time
0.9
-
ns
CAS Latency=3
7.5
-
ns
CAS Latency=2
15
-
ns
tCK
Clock Cycle Time
tCHW
tCH
Clock High Pulse Width
2.5
-
ns
tCLW
tCL
Clock Low Pulse Width
2.5
-
ns
tCKS(1)
Clock Enable Setup Time
1.9
-
ns
tCKSP(1)
Clock Enable Setup Time (Power-Down Exit)
1.9
-
ns
tCKH(1)
Clock enable Hold Time
0.9
-
ns
tCS
tCMS(1) Command Setup Time
1.9
-
ns
tCH
tCMH(1)
Command Hold Time
0.9
-
ns
tDS(1)
Data-Input Setup Time
1.9
-
ns
tDH(1)
Data-Input Hold Time
0.9
-
ns
Data-out Hold Time
2
-
ns
0
-
ns
CAS Latency=3
0
6
ns
CAS Latency=2
0
8
ns
tOH
tOLZ
tLZ
Clock to Data Output in Low-Z Time
tOHZ
tHZ
Clock to Data Output in High-Z
Time
1. If tT is greater than 0.5 ns, (tT− 0.5) or ((tR + tF)/2 − 0.5) should be added.
28/55
Unit
M65KA512AB
Table 13.
Symbol
DC and ac parameters
AC characteristics 2
Alt.
M65KA512ABM65KA51
2AB
Parameter
tDPL
Delay Time, Write Command to Data Input
tDAL
Data Input Valid to Precharge
Command
Min.
Max.
2
-
(1)
-
ns
-
ns
CAS Latency = 2
CAS Latency = 3
Unit
2*tCK + 22.5
Mode Register Set Cycle Time
2
-
(1)
tRC(2)
RAS Cycle Time (normal operation)
90
-
ns
tRC
RAS Cycle Time (refresh operation)
112.5
-
ns
tRC2
RAS Cycle Time (Self Refresh Exit to Refresh or
Bank/Row Activate Command)
120
-
ns
tRCD
Delay Time, RAS Active to CAS Active
27.5
-
ns
tRAS
RAS Active Time
60
120000
ns
tRP
RAS Precharge Time
22.5
-
ns
tRSC
tMRD
tRRD
Delay Time, RAS Active to RAS Bank Active
2
-
(1)
tREF
Refresh Time
-
64
ms
0.5
30
ns
tT
Input Transition Time between VIL and VIH
1. The unit is the system Clock cycle time.
2. A new command can be issued tRC after the Self Refresh mode is exited.
29/55
DC and ac parameters
AI09959b
Chip Enable Signal during Read, Write and Precharge ac waveforms
Write
in Bank A
Bank/Row Activate
in Bank A
DQ0-DQ15
Low
LDQM/
UDQM
Address
A10
Hi-Z
RAa
RAa
Low
BA1
BA0
W
CAS
RAS
E
KE
K
High
T0
T1
Low
T2
T3
T4
T5
Read
from Bank A
T6
CAa
T7
QAa1
T8
QAa2
T9
QAa3
T10
QAa4
DQN
T11
T12
DAb1
T13
DAb2
T14
DAb3
T15
DAb4
T16
CAb
T17
T18
Precharge
Bank A
T19
T20
T21
Figure 5.
M65KA512AB
1. The Chip Enable signal, E, must be issued at a minimum rate with respect to the other signals.
2. Burst Length = 4 words, Latency = 3 clock cycles.
3. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAan= Data n read from
Column a in Bank A, DAan= Data n written to Column a in Bank A.
30/55
M65KA512AB
DC and ac parameters
Figure 6.
Read with Precharge ac waveforms
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
tCK
K
tCLW
tCHW
KE
tCH
tCKS
tCKH
E
tCS
RAS
CAS
W
BA0
BA1
A10
Address
tAS
LDQM/
UDQM
tAH
Low
tAC
DQ0-DQ15
tOHZ
Hi-Z
DQN
tRCD
DQN+1
tOLZ
DQN+2
DQN+3
tOH
tRAS
tRP
tRC
Bank/Row Activate
in Bank A
Read
from Bank A
Precharge
in Bank A
Bank/Row Activate
in Bank A
AI09934b
1. Burst Length = 4 words, Latency = 3 clock cycles.
31/55
DC and ac parameters
M65KA512AB
Figure 7.
Read with Auto Precharge ac waveforms
Auto Precharge
Start from Bank C
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
tCK
K
tCLW
tCHW
KE
tCH
tCKS
tCKH
E
tCS
RAS
CAS
W
BA0
BA1
A10
Address
tAS
LDQM/
UDQM
Low
DQ0-DQ15
tAH
tOH
tAC
Hi-Z
DQN
tRCD
DQN+1
DQN+2
DQN+3
tOHZ
tOLZ
tRAS, tRRD
tRC
Bank/Row Activate
in Bank C
Read with Auto Precharge
from Bank C
Bank/Row Activate
in Bank D
Bank/Row Activate
in Bank C
AI09935b
1. Burst Length = 4 words, Latency = 3 clock cycles.
32/55
Hi-Z
Low
RAa
RAa
Bank/Row Activate
in Bank A
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
T1
T2
CAa
T4
Read
from Bank A
T3
T5
T6
QAa1
T7
T9
Clock Suspended
during 1 cycle
QAa2
T8
QAa3
T11
T12
Clock Suspended
during 2 cycles
T10
T13
T15
T16
Clock Suspended
during 3 cycles
QAa4
T14
AI09949
End of
Read
Hi-Z
T17
Figure 8.
KE
K
T0
M65KA512AB
DC and ac parameters
Clock Suspend during Burst Read ac waveforms
1. Burst Length = 4 words, Latency = 3 clock cycles.
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAan= Data n read from
Column a in Bank A.
33/55
34/55
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
T5
QAa1
T6
T7
CAb
QAa3
T8
CAc
T9
QAc2
T13
QAc1
T12
QAb2
T11
QAb1
T10
QAc3
T14
QAc4
T15
T16
Read
from Bank A
Read
from Bank A
QAa2
Read
from Bank A
QAa4
DQN
Precharge
in Bank A
T17
Bank/Row Activate
in Bank A
RAa
CAa
T4
RAa
T3
RAa
T2
RAa
Bank/Row Activate
in Bank A
Hi-Z
Low
High
T1
T18
CAa
T20
Read
from Bank A
T19
AI09955
T21
Figure 9.
KE
K
T0
DC and ac parameters
M65KA512AB
Random Column Read ac waveforms
1. Burst Length = 4 words, Latency = 3 clock cycles.
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAmn= Data n read from
Column m in Bank A.
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
T5
T6
QBa1
T7
QBa2
T8
Read
from Bank B
T9
T10
Bank/Row Activate
in Bank A
QBa3 QBa4
RAa
CBa
T4
RBa
T3
RAa
T2
RBa
T1
Bank/Row Activate
in Bank B
Hi-Z
Low
High
T0
T12
T13
Read
from Bank A
QBa8
T14
Precharge
in Bank B
QBa5 QBa6 QBa7
CAa
T11
QAa1
T15
T17
T18
T19
CBb
T20
T21
Bank/Row Activate
in Bank B
Read
from Bank A
AI09957
QAa2 QAa3 QAa4 QAa5 QAa6 QAa7
RBb
RBb
T16
M65KA512AB
DC and ac parameters
Figure 10. Random Row Read ac waveforms
1. Burst Length = 8 words, Latency = 3 clock cycles.
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAmn= Data n read from row
m in Bank A.
35/55
36/55
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
1. Burst Length = 4 words, Latency = 3 clock cycles.
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAmn= Data n read from
Column m in Bank A.
T5
Bank/Row Activate
in Bank D
Read
from Bank A
RDa
CAa
T4
RAa
T3
RDa
T2
RAa
T1
Bank/Row Activate
in Bank A
Hi-Z
Low
High
T0
T6
QAa2
CDa
T8
T9
Read
from Bank D
Read
from Bank A
Precharge
in Bank D
Precharge
in Bank A
T20
QAb4
T19
QAb3
T18
QAb2
T17
QAb1
T16
QDc2
T15
QDc1
T14
QDb2
CAb
T13
QDb1
T12
QDa2
CDc
T11
QAa4 QDa1
CDb
T10
Read
from Bank D
QAa3
Read
from Bank D
QAa1
DQN
T7
AI09520
T21
DC and ac parameters
M65KA512AB
Figure 11. Column Interleaved Read ac waveforms
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
T5
Bank/Row Activate
in Bank D
Read
from Bank A
RDa
CAa
T4
RAa
T3
RDa
T2
RAa
T1
Bank/Row Activate
in Bank A
Hi-Z
Low
High
T0
T6
CDa
T8
Read +
Auto Precharge
from Bank D
DQN
T7
T9
T11
T12
CAb
Auto Precharge
from Bank D
Read +
Auto Precharge
from Bank A
T10
T14
RDb
RDb
T15
T16
Autoprecharge Start
from Bank A
Bank/Row Activate
in Bank D
T13
T17
CDb
T19
Read +
Auto Precharge
from Bank D
T18
T20
AI09961b
T21
M65KA512AB
DC and ac parameters
Figure 12. Burst Column Read followed by Auto Precharge ac waveforms
1. Burst Length = 4 words, Latency = 3 clock cycles.
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A.
37/55
38/55
1. Burst Length = 4 words.
Hi-Z
Low
T1
T2
T3
T4
tDH
T6
Bank/Row
Activate
in Bank B
T5
Write
+ Auto
Precharge
to Bank C
tRRD
tDS
tRCD
tCH, tAH
Bank/Row Activate
in Bank C
tCS, tAS
tCKS
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
T0
T10
tDAL
tRAS
T9
Write to Bank B
T8
Auto Precharge
Start from Bank C
tRC
tRCD
DQN
T7
tDPL
T13
Precharge
in Bank B
T12
Bank/Row
Activate
in Bank C
tRC
T11
tCKH
T14
tRP
T16
Bank/Row
Activate
in Bank B
T15
AI09947
T17
DC and ac parameters
M65KA512AB
Figure 13. Write ac waveforms
Hi-Z
Hi-Z
High
T1
T2
Bank/Row Activate
Read
in Bank D
from Bank D
DQ8-DQ15
DQ0-DQ7
UDQM
LDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
T0
T3
T5
Lower Byte
Read
T4
T6
T8
Upper Byte
Read
T7
T10
Upper Byte
Write
T9
T12
T13
T14
Lower Byte
Read from
Write
Bank D
Upper Byte
Write
T11
T15
T17
Upper Byte
Read
T16
T18
T20
Upper Byte
Read
T19
AI09963b
T21
M65KA512AB
DC and ac parameters
Figure 14. Byte Write ac waveforms
1. Burst Length = 4 words.
39/55
DC and ac parameters
M65KA512AB
Figure 15. Mode Register Set ac waveforms
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
K
High
KE
tMRD, 2 Clock Cycles (min)
E
RAS
CAS
W
BA0
BA1
A10
MR
Address
Data (2)
LDQM/
UDQM
DQ0-DQ15
Hi-Z
tRP
Precharge
All Banks
Mode Register
Set
Bank/Row
Activate
Valid
AI09948
1. To program the Extended Mode Register, BA0 and BA1 must be set to ‘0’ and ‘1’ respectively, and A0 to
A11 to the Extended Mode Register Data.
2. MR Data is the value to be written to the Mode Register.
40/55
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
T1
Bank/Row Activate
in Bank A
Hi-Z
Low
RAa
RAa
T0
T2
T4
T5
T6
DAa2
Clock
Suspended
during 1 cycle
Write
to Bank A
DAa1
CAa
T3
T8
T9
DAa3
Clock Suspended
during 2 cycles
T7
T10
T12
T13
DAa4
Clock Suspended
during 3 cycles
T11
T14
T15
T16
AI09950b
T17
M65KA512AB
DC and ac parameters
Figure 16. Clock Suspend during Burst Write ac waveforms
1. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, DAan= Data n Written to
Column a in Bank A.
41/55
42/55
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
DDa2
T7
DDa4
DQN
T6
DDa3
T5
CDb
CDc
T9
DDb2
T8
T14
Precharge
in Bank D
T13
DDc4
T12
DDc3
T11
DDc2
T10
T15
T16
Write
to Bank D
DDa1
Write
to Bank D
DDb1
Write
to Bank D
DDc1
T17
Bank/Row Activate
in Bank D
RDd
CDa
T4
RDa
T3
RDd
T2
RDa
T1
Bank/Row Activate
in Bank D
Hi-Z
Low
High
T0
T18
CDd
Write
to Bank D
T21
AI09956
DDd2
T20
DDd1
T19
DC and ac parameters
M65KA512AB
Figure 17. Random Column Write ac waveforms
1. Burst Length = 4 words.
2. RDa = Address of Row a in Bank D, CDa = Address of Column a in Bank D, DDmn= Data n written to
Column m in Bank D.
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
DAa2
T5
DAa3
T6
DAa4 DAa5
T7
T8
Write
to Bank A
DAa1
T9
T10
T12
Write
to Bank D
DDa4
T14
Precharge
in Bank A
DDa3
T13
DDa1 DDa2
CDa
T11
DAa7 DAa8
Bank/Row Activate
in Bank D
DAa6
RDa
CAa
T4
RAa
T3
RDa
T2
RAa
T1
Bank/Row Activate
in Bank A
Hi-Z
Low
High
T0
T18
CAb
T20
Write
to Bank A
T21
AI09958
DAb1 DAb2
T19
DDa7 DDa8
T17
DDa6
RAb
RAb
T16
Bank/Row Activate
in Bank A
DDa5
T15
M65KA512AB
DC and ac parameters
Figure 18. Random Row Write ac waveforms
1. Burst Length = 8 words.
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, DAmn= Data n written to row
m in Bank A.
43/55
44/55
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
DAa2
Write
to Bank B
DBa2
T8
CBa
DBa1
T7
DAa4
T6
DAa3
T5
Bank/Row Activate
in Bank B
Write
to Bank A
DQN
DAa1
RBa
CAa
T4
RAa
T3
RBa
T2
RAa
T1
Bank/Row Activate
in Bank A
Hi-Z
Low
High
T0
CBb
Write
to Bank B
Write
to Bank B
DAb2
T14
Write
to Bank A
DAb1
CAb
T13
DBc2
T12
DBc1
CBc
T11
DBb2
T10
DBb1
T9
T17
DBb4
T18
Precharge
in Bank A
DBb2 DBb3
T16
Write
to Bank B
DBb1
CBd
T15
T20
Precharge
in Bank B
T19
AI09521
T21
DC and ac parameters
M65KA512AB
Figure 19. Column Interleaved Write ac waveforms
1. Burst Length = 4 words.
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, DAmn= Data n written to
Column m in Bank A.
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
T5
Bank/Row
Activate
in Bank D
Write
to Bank A
DQN
RDa
CAa
T4
RAa
T3
RDa
T2
RAa
T1
Bank/Row Activate
in Bank A
Hi-Z
Low
High
T0
T6
CDa
T8
Write +
Auto Precharge
from Bank D
T7
T9
T10
CAb
T12
T13
Write +
Auto Precharge
from Bank A
Auto Precharge Start
from Bank D
T11
T14
T16
T17
T18
CDb
T19
Bank/Row
Write +
Activate
Auto Precharge
in Bank D
from Bank D
Auto Precharge Start
from Bank A
RDb
RDb
T15
T20
AI09962
T21
M65KA512AB
DC and ac parameters
Figure 20. Burst Column Write followed by Auto Precharge ac waveforms
1. Burst Length = 4 words
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A.
45/55
46/55
DQ0-DQ15
LDWM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
1. Burst Length = 8 words, Latency = 3 clock cycles.
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAan= Data n read from
Column a in Bank A, DAan= Data n written to Column a in Bank A.
DAa2
T5
T6
T8
Write Masking
T7
T9
T10
T11
tRAS
Write to Bank A
DAa1
tDPL
DAa5
Precharge in Bank A
+
Write Terminated
DAa3 DQDAa4
N
Bank/Row Activate
in Bank A
tRP
RAb
CAa
T4
RAa
T3
RAb
tRCD
T2
RAa
T1
Bank/Row Activate
in Bank A
Hi-Z
High
T0
T12
CAb
tRAS
T14
Read from
Bank A
T13
T15
QAb2
T17
T19
T21
AI09524
Bank/Row Activate
in Bank A
RAc
RAc
T20
QAb3 DQQAb4
N
T18
Precharge in Bank A
+
Read Terminated
QAb1
T16
DC and ac parameters
M65KA512AB
Figure 21. Precharge termination ac waveforms
High
DQ0-DQ15 Hi-Z
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
T1
T2
Precharge
All Banks
High Level nedeed
1 Clock Cycle needed
T0
T6
EMR
Data (1)
T5
T7
tMRD
T8
Mode
Extended Mode
CBR
Register Set Register Set Auto Refresh
tRP
T4
MR
Data (1)
tMRD
T3
T9
tRC1
T10
T11
T13
CBR
Auto Refresh
T12
T14
T16
T17
T18
tRC1
T19
T20
T21
AI09960b
Bank/Row Activate
2 Refresh Cycles needed
T15
M65KA512AB
DC and ac parameters
Figure 22. Power-On sequence ac waveforms
1. MR Data and EMR data are the values to be written to the Mode Register and the Extended Mode
Register, respectively.
47/55
48/55
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
T1
T2
T4
CAa
T6
Read
from Bank A
T5
Power-Down
Exit
tCKSP
T3
ACTIVE STANDBY
Bank/Row
Activate
in Bank A
Power-Down
Entry
Hi-Z
Low
RAa
RAa
T0
T7
T8
QAa2
T10
Start of
Clock Masking
QAa1
T9
T12
End of
Clock Masking
QAa3
T11
T14
T15
Power-Down
Entry
Precharge
in Bank A
QAa4
T13
T17
T19
tCKSP
T18
PRECHARGE STANDBY
T16
T21
AI09951
Power-Down
Exit
T20
DC and ac parameters
M65KA512AB
Figure 23. Power-Down mode and Clock Masking ac waveforms
1. Burst Length = 4 words, Latency = 3 clock cycles.
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAan= Data n read from Column a in Bank A.
Hi-Z
DQ0-DQ15
T1
Precharge
(optional)
Low
High
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
T0
T3
Auto Refresh
tRP
T2
T4
T5
tRC1
T6
Tn
Tn+1
Tn+3
Auto Refresh
Tn+2
Tn+4
Tn+5
tRC1
Tn+6
Tm
Bank/Row Activate
Read
Tm+7
AI09952c
Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6
M65KA512AB
DC and ac parameters
Figure 24. Auto refresh ac waveforms
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Low
Hi-Z
LDQM/
UDQM
DQ0-DQ15
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
T0
T2
Precharge
(optional)
T1
T4
Self Refresh
Entry
tRP
T3
Tn+1
Self Refresh
Exit
Tn
tRC2
Tn+2
Tm+1
Self Refresh
Entry
(or Bank/Row
Activate)
Next Clock
Enable
Tm
Self Refresh
Exit
Tk+2
Bank/Row
Activate
Tk+1
Next Clock
Enable
tRC2
Tk
Tk+3
AI09953b
Tk+4
DC and ac parameters
M65KA512AB
Figure 25. Self refresh ac waveforms
M65KA512AB
DC and ac parameters
Figure 26. Deep Power-Down Entry ac waveforms
T0
T1
T3
T2
T4
T5
K
KE
E
RAS
CAS
W
A10
DQ0-DQ15
Hi-Z
tRP
Precharge All Banks
(optional)
Deep Power-Down
Entry
ai07720c
1. BA0, BA1 and address bits A0 to A12 are ‘Don’t Care’.
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W
CAS
RAS
E
KE
K
High
1. MR Data and EMR data are the values to be written to the Mode Register and the Extended Mode
Register, respectively.
T2
1 Clock Cycle needed
T1
Precharge
All Banks
200µs
High Level nedeed
Deep
Power-Down
Exit
DQ0-DQ15 Hi-Z
LDQM/
UDQM
Address
A10
BA1
BA0
1
T0
T6
EMR
Data (1)
T5
T7
tMRD
T8
Mode
Extended Mode Auto Refresh
Register Set Register Set
tRP
T4
MR
Data (1)
tMRD
T3
T9
tRC1
T10
T11
T13
Auto Refresh
T12
T14
T16
T17
T18
tRC1
T19
T20
T21
AI09954c
Bank/Row Activate
2 Refresh Cycles needed
T15
DC and ac parameters
M65KA512AB
Figure 27. Deep Power-Down Exit ac waveforms
M65KA512AB
8
Part numbering
Part numbering
Table 14.
Ordering information scheme
Example:
M65KA512A
B 8
W 3
Device type
M65 = Low- Power SDRAM
Architecture
K = Bare Die
Operating voltage
A = VDD = VDDQ = 1.8V, Standard LPSDRAM, x16
Array organization
512 = 4 Banks x 8 Mbit x 16
Option 1
A = One Chip Enable
Option 2
B = B Die
Speed
8 = 7.5ns
Package
W = Unsawn wafer
Temperature range
8 = –30 to 85 °C
For a list of available options (Speed, Package, etc.) or for further information on any aspect
of this device, please contact the ST Sales Office nearest to you.
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Revision history
9
Revision history
Date
Revision
18-Nov-2005
0.1
Initial release.
1.0
Table 8: Capacitance and Table 11: Self-Refresh current values in
Normal Operating Mode filled-in.
Table 10: DC characteristics 2 and Table 12: AC characteristics 1
updated.
Wafer and Die specifications section removed.
31-Jan-2006
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M65KA512AB
Changes
12-Sep-2006
2
Changed Burst Stop to Burst Terminate in Features; changed the
Operating Temperature Range from − 25 to − 30 in Features, Table 6,
Table 7, Table 9, Table 10, Table 11, and Table 14; updated footnotes in
Table 7, Table 9, Table 10, and Table 12; updated tT value in Table 7:
Operating and ac measurement conditions; updated package
information and removed option ‘T’ in Table 14: Ordering information
scheme.
20-Mar-2007
3
tRCD minimum value updated in Table 13: AC characteristics 2.
M65KA512AB
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