M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR ■ ■ ■ ■ ■ ■ ■ HIGH SPEED : fMAX = 79MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 112 DESCRIPTION The M74HC112 is an high speed CMOS DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR fabricated with silicon gate C2MOS technology. The M74HC112 dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs for each flip-flop. When the clock goes high, the inputs are enabled and data will be accepted. The logic level of the J and K inputs DIP SOP TSSOP ORDER CODES PACKAGE TUBE DIP SOP TSSOP M74HC112B1R M74HC112M1R T&R M74HC112RM13TR M74HC112TTR may be allowed to change when the clock pulse is high and the bistable will function as shown in the truth table. Input data is transferred to the input on the negative going edge of the clock pulse. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/12 M74HC112 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION Clock Input(HIGH to LOW edge triggered) Data Inputs: Flip-Flop 1 1K, 2K and 2 Data Inputs: Flip-Flop 1 1J, 2J and 2 1PR, 2PR Set Inputs 1Q, 2Q True Flip-Flop Outputs Complement Flip-Flop 1Q, 2Q Outputs 1CLR, 2CLR Reset Inputs GND Ground (0V) Vcc Positive Supply Voltage 1CK, 2CK 1, 13 2, 12 3, 11 4, 10 5, 9 6, 7 15, 14 8 16 TRUTH TABLE INPUTS OUTPUTS FUNCTION CLR PR J K CK Q Q L H L H L L X X X X X X X X X L H H H L H CLEAR PRESET ---- H H L L Qn Qn NO CHANGE H H H L H L ---- H H L H L H ---- H H H H Qn Qn TOGGLE H H X X Qn Qn NO CHANGE X : Don’t Care LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/12 M74HC112 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Value Supply Voltage Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ± 50 mA VI DC Input Voltage VO DC Output Voltage IIK ICC or IGND DC VCC or Ground Current PD Power Dissipation Tstg Storage Temperature TL Lead Temperature (10 sec) V 500(*) mW -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Value Supply Voltage Unit 2 to 6 V VI Input Voltage 0 to VCC V VO Output Voltage 0 to VCC V Top Operating Temperature -55 to 125 °C Input Rise and Fall Time tr, tf VCC = 2.0V 0 to 1000 ns VCC = 4.5V 0 to 500 ns VCC = 6.0V 0 to 400 ns 3/12 M74HC112 DC SPECIFICATIONS Test Condition Symbol VIH VIL VOH VOL II ICC 4/12 Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current Value TA = 25°C VCC (V) Min. 2.0 4.5 6.0 2.0 4.5 6.0 Typ. Max. 1.5 3.15 4.2 -40 to 85°C -55 to 125°C Min. Min. Max. 1.5 3.15 4.2 0.5 1.35 1.8 Max. 1.5 3.15 4.2 0.5 1.35 1.8 V 0.5 1.35 1.8 2.0 IO=-20 µA 1.9 2.0 1.9 1.9 4.5 IO=-20 µA 4.4 4.5 4.4 4.4 6.0 IO=-20 µA 5.9 6.0 5.9 5.9 4.5 IO=-4.0 mA 4.18 4.31 4.13 4.10 5.68 Unit V V 6.0 IO=-5.2 mA 2.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=20 µA 0.0 0.1 0.1 0.1 6.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=4.0 mA 0.17 0.26 0.33 0.40 6.0 IO=5.2 mA 0.18 0.26 0.33 0.40 6.0 VI = VCC or GND ± 0.1 ±1 ±1 µA 6.0 VI = VCC or GND 2 20 40 µA 5.8 5.63 5.60 V M74HC112 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (CK - Q, Q) tPLH tPHL Propagation Delay Time (CLR, PR Q, Q) fMAX Maximum Clock Frequency tW(H) tW(L) Minimum Pulse Width (CLOCK) tW(L) Minimum Pulse Width (CLR, PR) ts th tREM Minimum Set-up Time Minimum Hold Time Minimum Removal Time (CLR, PR) Value TA = 25°C VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Min. Typ. Max. 75 15 13 125 25 21 135 27 23 8 40 47 30 8 7 52 16 14 68 17 14 16 68 79 20 5 4 20 5 4 28 7 6 -40 to 85°C -55 to 125°C Min. Min. Max. 95 19 16 155 31 26 170 34 29 6.4 32 38 75 15 13 75 15 13 75 15 13 0 0 0 50 10 9 24 4 3 Max. 110 22 19 190 38 32 205 41 35 5.4 27 32 95 19 16 95 19 16 95 19 16 0 0 0 60 12 10 Unit ns ns ns MHz 110 22 19 110 22 19 110 22 19 0 0 0 70 14 12 ns ns ns ns ns CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) Value TA = 25°C Min. Typ. Max. 10 CIN Input Capacitance 5.0 5 CPD Power Dissipation Capacitance (note 1) 5.0 33 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + I CC/2 (per FLIP/ FLOP) 5/12 M74HC112 TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (CK), SETUP AND HOLD TIME (J to CK) (f=1MHz; 50% duty cycle) 6/12 M74HC112 WAVEFORM 2 : PROPAGATIONS DELAY TIME, MINIMUM PULSE WIDTH (CLR, PR) (f=1MHz; 50% duty cycle) 7/12 M74HC112 WAVEFORM 3 : MINIMUM REMOVAL TIME (CLR to CK) (f=1MHz; 50% duty cycle) WAVEFORM 4 : MINIMUM REMOVAL TIME (PR to CK) (f=1MHz; 50% duty cycle) 8/12 M74HC112 Plastic DIP-16 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 0.77 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 P001C 9/12 M74HC112 SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45° (typ.) D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 0.024 8° (max.) PO13H 10/12 M74HC112 TSSOP16 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 4.9 5 5.1 0.193 0.197 0.201 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0° L 0.45 A 0.60 0.0256 BSC 8° 0° 0.75 0.018 8° 0.024 0.030 A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080338D 11/12 M74HC112 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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