STMICROELECTRONICS M95160-W

M95160
M95080
16 Kbit and 8 Kbit serial SPI bus EEPROM
with high speed clock
Features
Figure 1.
■
Compatible with SPI bus serial interface
(positive clock SPI modes)
■
Single supply voltage:
– 4.5 V to 5.5 V for M95xxx
– 2.5 V to 5.5 V for M95xxx-W
– 1.8 V to 5.5 V for M95xxx-R
■
High Speed: 10 MHz
■
Status Register
■
Hardware Protection of the Status Register
■
Byte and page write (up to 32 bytes)
■
Self-timed programming cycle
■
Adjustable size read-only EEPROM area
■
Enhanced ESD protection
■
More than 1 million Erase/Write cycles
■
More than 40-year data retention
■
Packages
– ECOPACK® (RoHS compliant)
Table 1.
Packages
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
UFDFPN8 (MB)
2 x 3 mm (MLP)
Device summary
Reference
Part number
M95160
M95160
M95160-W
M95160-R
M95080
M95080
M95080-W
M95080-R
May 2007
Rev 6
1/45
www.st.com
1
Contents
M95160, M95080
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
2.1
Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
4
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.1
4.1.2
Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.3
Power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.4
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2
Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5
Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1
2/45
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
M95160, M95080
7
Contents
6.3.2
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.3
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.4
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.6
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3/45
List of tables
M95160, M95080
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
4/45
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write-Protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Operating conditions (M95160 and M95080) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating conditions (M95160-W and M95080-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating conditions (M95160-R and M95080-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics (M95160 and M95080, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics (M95160 and M95080, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics (M95160-W and M95080-W, device grade 3). . . . . . . . . . . . . . . . . . . . 29
DC characteristics (M95160-W and M95080-W, device grade 6). . . . . . . . . . . . . . . . . . . . 29
DC characteristics (M95160-R and M95080-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AC characteristics (M95160 and M95080, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . 31
AC characteristics (M95160 and M95080, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . 32
AC characteristics (M95160-W and M95080-W, device grade 3). . . . . . . . . . . . . . . . . . . . 33
AC characteristics (M95160-W and M95080-W, device grade 6). . . . . . . . . . . . . . . . . . . . 34
AC characteristics (M95160-R and M95080-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead
2 x 3 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data . . . . . . . . . . . . . . 40
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Available M95160 products (package, voltage range, temperature grade) . . . . . . . . . . . . 42
Available M95080 products (package, voltage range, temperature grade) . . . . . . . . . . . . 42
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
M95160, M95080
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, package outline . . . . . . 38
UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead
2 x 3 mm², package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TSSOP8 – 8 lead Thin Shrink Small Outline, package outline . . . . . . . . . . . . . . . . . . . . . . 40
5/45
Description
1
M95160, M95080
Description
These electrically erasable programmable memory (EEPROM) devices are accessed by a
high speed SPI-compatible bus. The memory array is organized as 2048 x 8 bit (M95160),
and 1024 x 8 bit (M95080).
The device is accessed by a simple serial interface that is SPI-compatible. The bus signals
are C, D and Q, as shown in Table 2. and Figure 2.
The device is selected when Chip Select (S) is taken Low. Communications with the device
can be interrupted using Hold (HOLD).
In order to meet environmental requirements, ST offers the M95xxx in ECOPACK®
packages. ECOPACK® packages are Lead-free and RoHS compliant.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 2.
Logic diagram
VCC
D
Q
C
S
M95xxx
W
HOLD
VSS
AI01789C
Table 2.
Signal names
Signal name
6/45
Function
Direction
C
Serial Clock
Input
D
Serial Data input
Input
Q
Serial Data output
Output
S
Chip Select
Input
W
Write Protect
Input
HOLD
Hold
Input
VCC
Supply voltage
VSS
Ground
M95160, M95080
Figure 3.
Description
8-pin package connections (top view)
M95xxx
S
Q
W
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
C
D
AI01790D
1. See Package mechanical section for package dimensions, and how to identify pin-1.
7/45
Signal description
2
M95160, M95080
Signal description
During all operations, VCC must be held stable and within the specified valid range:
VCC(min) to VCC(max).
All of the input and output signals must be held High or Low (according to voltages of VIH,
VOH, VIL or VOL, as specified in Table 13. to Table 18.). These signals are described next.
2.1
Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2
Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Write cycle is in progress, the device will be in the Standby
Power mode. Driving Chip Select (S) Low selects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
8/45
M95160, M95080
2.6
Signal description
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either High or Low, and must be stable during all write instructions.
2.7
VCC supply voltage
VCC is the supply voltage.
2.8
VSS ground
VSS is the reference for the VCC supply voltage.
9/45
Connecting to the SPI bus
3
M95160, M95080
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes Low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 4. shows three devices, connected to an MCU, on an SPI bus. Only one device is
selected at a time, so only one device drives the Serial Data Output (Q) line at a time, all the
others being high impedance.
Figure 4.
Bus master and memory devices on the SPI bus
VSS
VCC
R
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
VCC
C Q D
SPI Bus Master
SPI Memory
Device
R
CS3
VCC
C Q D
VSS
C Q D
VCC
VSS
SPI Memory
Device
R
VSS
SPI Memory
Device
R
CS2 CS1
S
W
HOLD
S
W
HOLD
S
W
HOLD
AI12836b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 4 shows an example of three memory devices connected to an MCU, on an SPI bus.
Only one memory device is selected at a time, so only one memory device drives the Serial
Data Output (Q) line at a time, the other memory devices are high impedance.
The pull-up resistor R (represented in Figure 4) ensures that a device is not selected if the
Bus Master leaves the S line in the high impedance state.
In applications where the Bus Master may be in a state where all input/output SPI buses are
high impedance at the same time (for example, if the Bus Master is reset during the
transmission of an instruction), the clock line (C) must be connected to an external pulldown resistor so that, if all inputs/outputs become high impedance, the C line is pulled Low
(while the S line is pulled High): this ensures that S and C do not become High at the same
time, and so, that the tSHCH requirement is met. The typical value of R is 100 kΩ.
10/45
M95160, M95080
3.1
Connecting to the SPI bus
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
●
CPOL=0, CPHA=0
●
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 5., is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
●
C remains at 0 for (CPOL=0, CPHA=0)
●
C remains at 1 for (CPOL=1, CPHA=1)
Figure 5.
SPI modes supported
CPOL CPHA
0
0
C
1
1
C
D
Q
MSB
MSB
AI01438B
11/45
Operating features
4
Operating features
4.1
Supply voltage (VCC)
4.1.1
Operating supply voltage VCC
M95160, M95080
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 9, Table 10 and
Table 11). In order to secure a stable dc supply voltage, it is recommended to decouple the
VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the
VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (tW).
4.1.2
Power-up conditions
When the power supply is turned on, VCC rises from VSS to VCC. During this time, the Chip
Select (S) line is not allowed to float but should follow the VCC voltage, it is therefore
recommended to connect the S line to VCC via a suitable pull-up resistor.
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge
sensitive as well as level sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been High, prior to going Low to start the first operation.
The VCC rise time must not vary faster than 1 V/µs.
4.1.3
Power-up and device reset
In order to prevent inadvertent Write operations during power-up, a power on reset (POR)
circuit is included. At power-up (continuous rise of VCC), the device does not respond to any
instruction until VCC has reached the power on reset threshold voltage (this threshold is
lower than the minimum VCC operating voltage defined in Table 9, Table 10 and Table 11).
Once VCC has passed the POR threshold, the device is reset and is in the following state:
●
Standby Power mode
●
deselected (at next power-up, a falling edge is required on Chip Select (S) before any
instructions can be started)
●
not in the Hold condition
Status Register state:
12/45
●
the Write Enable Latch (WEL) is reset to 0
●
Write In Progress (WIP) is reset to 0. The SRWD, BP1 and BP0 bits of the Status
Register are unchanged from the previous power-down (they are non-volatile bits).
M95160, M95080
4.1.4
Operating features
Power-down
At Power-down (continuous decrease of VCC), as soon as VCC drops from the normal
operating voltage to below the power on reset threshold voltage, the device stops
responding to any instruction sent to it.
During Power-down, the device must be deselected and in Standby Power mode (that is
there should be no internal Write cycle in progress). Chip Select (S) should be allowed to
follow the voltage applied on VCC.
4.2
Active Power and Standby Power Modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode. The
device consumes ICC, as specified in Table 13. to Table 18.
When Chip Select (S) is High, the device is deselected. If a Write cycle is not currently in
progress, the device then goes into the Standby Power mode, and the device consumption
drops to ICC1.
4.3
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition, has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven Low at the same time as
Serial Clock (C) already being Low.
The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as
Serial Clock (C) already being Low.
4.4
Status Register
Figure 6. shows the position of the Status Register in the control logic of the device. The
Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits
13/45
Operating features
4.5
M95160, M95080
Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and
within applications that could experience problems if memory bytes are corrupted.
Consequently, the device features the following data protection mechanisms:
●
Write and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
●
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
Power-up
–
Write Disable (WRDI) instruction completion
–
Write Status Register (WRSR) instruction completion
–
Write (WRITE) instruction completion
●
The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be
configured as read-only.
●
The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits of the Status
Register to be protected.
For any instruction to be accepted, and executed, Chip Select (S) must be driven High after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points need to be noted in the previous sentence:
●
The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
●
The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 3.
Write-Protected block size
Status Register Bits
Array Addresses Protected
Protected Block
14/45
BP1
BP0
M95160
M95080
0
0
none
none
none
0
1
Upper quarter
0600h - 07FFh
0300h - 03FFh
1
0
Upper half
0400h - 07FFh
0200h - 03FFh
1
1
Whole memory
0000h - 07FFh
0000h - 03FFh
M95160, M95080
5
Memory organization
Memory organization
The memory is organized as shown in Figure 6.
Figure 6.
Block diagram
HOLD
W
High Voltage
Generator
Control Logic
S
C
D
I/O Shift Register
Q
Address Register
and Counter
Data
Register
Size of the
Read only
EEPROM
area
Y Decoder
Status
Register
1 Page
X Decoder
AI01272C
15/45
Instructions
6
M95160, M95080
Instructions
Each instruction starts with a single-byte code, as summarized in Table 4.
If an invalid instruction is sent (one not contained in Table 4.), the device automatically
deselects itself.
Table 4.
Instruction set
Instruction
6.1
Description
Instruction Format
WREN
Write Enable
0000 0110
WRDI
Write Disable
0000 0100
RDSR
Read Status Register
0000 0101
WRSR
Write Status Register
0000 0001
READ
Read from Memory Array
0000 0011
WRITE
Write to Memory Array
0000 0010
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7., to send this instruction to the device, Chip Select (S) is driven Low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven
High.
Figure 7.
Write Enable (WREN) sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI02281E
16/45
M95160, M95080
6.2
Instructions
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 8., to send this instruction to the device, Chip Select (S) is driven Low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven High.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●
Power-up
●
WRDI instruction execution
●
WRSR instruction completion
●
WRITE instruction completion.
Figure 8.
Write Disable (WRDI) sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI03750D
17/45
Instructions
6.3
M95160, M95080
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 9.
The status and control bits of the Status Register are as follows:
6.3.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
6.3.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
6.3.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 5.) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
6.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 5.
Status Register format
b7
SRWD
b0
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
18/45
M95160, M95080
Figure 9.
Instructions
Read Status Register (RDSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
D
Status Register Out
Status Register Out
High Impedance
Q
7
MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
AI02031E
19/45
Instructions
6.4
M95160, M95080
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data Input (D). The instruction is
terminated by driving Chip Select (S) High at a byte boundary of the input data. The selftimed Write cycle then starts, and continues for a period tW (as specified in Table 19,
Table 20, Table 21, Table 22 and Table 23), at the end of which the Write in Progress (WIP)
bit is reset to 0. The instruction sequence is shown in Figure 10.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the
Status Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is
driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated.
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle, and is 0 when it is completed. When the
cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as readonly, as defined in Table 5.
The Write Status Register (WRSR) instruction also allows the user to set or reset the Status
Register Write Disable (SRWD) bit in accordance with the Write Protect (W) signal. The
Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to
be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR)
instruction is not executed once the Hardware Protected Mode (HPM) is entered.
The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0)
bits are frozen at their current values from just before the start of the execution of Write
Status Register (WRSR) instruction. The new, updated, values take effect at the moment of
completion of the execution of Write Status Register (WRSR) instruction.
20/45
M95160, M95080
Instructions
Table 6.
Protection modes
W
Signal
SRWD
Bit
1
0
0
0
1
0
1
1
Mode
Write Protection of the
Status Register
Status Register is
Writable (if the WREN
Software instruction has set the
Protected WEL bit)
(SPM)
The values in the BP1
and BP0 bits can be
changed
Memory content
Protected area(1)
Unprotected area(1)
Write Protected
Ready to accept
Write instructions
Status Register is
Hardware write
Hardware
protected
Protected
Write Protected
The values in the BP1
(HPM)
and BP0 bits cannot be
changed
Ready to accept
Write instructions
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 6.
The protection features of the device are summarized in Table 3.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of whether Write Protect (W) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W):
●
If Write Protect (W) is driven High, it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
●
If Write Protect (W) is driven Low, it is not possible to write to the Status Register even
if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction. (Attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register,
are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
●
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
●
or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP1, BP0) bits of the Status Register, can be used.
21/45
Instructions
M95160, M95080
Table 7.
Address range bits(1)
Device
Address Bits
M95160
M95080
A10-A0
A9-A0
1. b15 to b11 are Don’t Care on the M95160.
b15 to b10 are Don’t Care on the M95080.
Figure 10. Write Status Register (WRSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
Status
Register In
7
D
High Impedance
6
5
4
3
2
1
0
MSB
Q
AI02282D
22/45
M95160, M95080
6.5
Instructions
Read from Memory Array (READ)
As shown in Figure 11., to send this instruction to the device, Chip Select (S) is first driven
Low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
If Chip Select (S) continues to be driven Low, the internal address register is automatically
incremented, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) High. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Figure 11. Read from Memory Array (READ) sequence
S
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
D
3
2
1
0
MSB
Data Out 1
High Impedance
Q
7
6
5
4
3
2
Data Out 2
1
0
7
MSB
AI01793D
1. Depending on the memory size, as shown in Table 7., the most significant address bits are Don’t Care.
23/45
Instructions
6.6
M95160, M95080
Write to Memory Array (WRITE)
As shown in Figure 12., to send this instruction to the device, Chip Select (S) is first driven
Low. The bits of the instruction byte, address byte, and at least one data byte are then
shifted in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) High at a byte boundary of the input
data. In the case of Figure 12., this occurs after the eighth bit of the data byte has been
latched in, indicating that the instruction is being used to write a single byte. The self-timed
Write cycle starts, and continues for a period tWC (as specified in Table 20. to Table 23.), at
the end of which the Write in Progress (WIP) bit is reset to 0.
If, though, Chip Select (S) continues to be driven Low, as shown in Figure 13., the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 32 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
●
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
●
if a Write cycle is already in progress
●
if the device has not been deselected, by Chip Select (S) being driven High, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
●
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Figure 12. Byte Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
D
3
2
Data Byte
1
0
7
6
5
4
3
2
1
0
High Impedance
Q
AI01795D
1. Depending on the memory size, as shown in Table 7., the most significant address bits are Don’t Care.
24/45
M95160, M95080
Instructions
Figure 13. Page Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
D
3
2
Data Byte 1
1
0
7
6
5
4
3
2
0
1
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Data Byte 2
D
7
6
5
4
3
2
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte N
1
0
6
5
4
3
2
1
0
AI01796D
1. Depending on the memory size, as shown in Table 7., the most significant address bits are Don’t Care.
25/45
Delivery state
M95160, M95080
7
Delivery state
7.1
Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write
Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
8
Maximum rating
Stressing the device outside the ratings listed in Table 8. may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the Operating sections of this specification, is not
implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 8.
Absolute maximum ratings
Symbol
Min.
Max.
Ambient operating temperature
–40
130
TSTG
Storage temperature
–65
150
TLEAD
Lead temperature during soldering
TA
Parameter
Unit
°C
See note (1)
°C
VO
Output voltage
–0.50
VCC+0.6
V
VI
Input voltage
–0.50
6.5
V
VCC
Supply voltage
–0.50
6.5
V
VESD
Electrostatic discharge voltage (human body model)(2)
–4000
4000
V
®
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100 pF, R1=1500 Ω, R2=500 Ω)
26/45
M95160, M95080
9
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, and the dc and ac
characteristics of the device. The parameters in the dc and ac characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 9.
Operating conditions (M95160 and M95080)
Symbol
VCC
TA
Table 10.
Parameter
Min.
Max.
Unit
Supply voltage
4.5
5.5
V
Ambient operating temperature (device grade 6)
–40
85
°C
Ambient operating temperature (device grade 3)
–40
125
°C
Min.
Max.
Unit
Supply voltage
2.5
5.5
V
Ambient operating temperature (device grade 6)
–40
85
°C
Ambient operating temperature (device grade 3)
–40
125
°C
Operating conditions (M95160-W and M95080-W)
Symbol
VCC
TA
Table 11.
Parameter
Operating conditions (M95160-R and M95080-R)
Min.(1)
Max.(1)
Unit
Supply voltage
1.8
5.5
V
Ambient operating temperature
–40
85
°C
Symbol
VCC
TA
Parameter
1. This product is under development. For more information, please contact your nearest ST sales office.
Table 12.
AC measurement conditions(1)
Symbol
CL
Parameter
Min.
Load capacitance
Typ.
Max.
30
Input rise and fall times
Unit
pF
50
ns
Input pulse voltages
0.2VCC to 0.8VCC
V
Input and output timing reference voltages
0.3VCC to 0.7VCC
V
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 14. AC measurement I/O waveform
Input Levels
0.8VCC
0.2VCC
Input and Output
Timing Reference Levels
0.7VCC
0.3VCC
AI00825B
27/45
DC and AC parameters
Table 13.
M95160, M95080
Capacitance(1)
Symbol
COUT
CIN
Parameter
Test condition
Output capacitance (Q)
Min.
Max.
Unit
VOUT = 0 V
8
pF
Input capacitance (D)
VIN = 0 V
8
pF
Input capacitance (other pins)
VIN = 0 V
6
pF
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz.
Table 14.
Symbol
DC characteristics (M95160 and M95080, device grade 3)
Parameter
Test condition
Min.
Max.
Unit
ILI
Input leakage current
VIN = VSS or VCC
±2
µA
ILO
Output leakage current
S = VCC, VOUT = VSS or VCC
±2
µA
ICC
Supply current
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 5 V, Q = open
3
mA
ICC1
Supply current
(Standby)
S = VCC, VCC = 5 V,
VIN = VSS or VCC
5
µA
VIL
Input low voltage
–0.45
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+1
V
VOL (1)
Output low voltage
IOL = 2 mA, VCC = 5 V
0.4
V
Output high voltage
IOH = –2 mA, VCC = 5 V
VOH
(1)
0.8 VCC
V
1. For all 5 V range devices, the device meets the output requirements for both TTL and CMOS standards.
Table 15.
Symbol
DC characteristics (M95160 and M95080, device grade 6)
Parameter
Test condition
Min.
Max.
Unit
ILI
Input leakage
current
VIN = VSS or VCC
±2
µA
ILO
Output leakage
current
S = VCC, VOUT = VSS or VCC
±2
µA
ICC
Supply current
C = 0.1VCC/0.9VCC at 10 MHz,
VCC = 5 V, Q = open
5
mA
ICC1
Supply current
(Standby)
S = VCC, VCC = 5 V,
VIN = VSS or VCC
2
µA
VIL
Input low voltage
–0.45
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+1
V
0.4
V
VOL(1)
Output low voltage IOL = 2 mA, VCC = 5 V
VOH (1)
Output high
voltage
IOH = –2 mA, VCC = 5 V
0.8 VCC
1. For all 5 V range devices, the device meets the output requirements for both TTL and CMOS standards.
28/45
V
M95160, M95080
Table 16.
Symbol
DC and AC parameters
DC characteristics (M95160-W and M95080-W, device grade 3)
Parameter
Test condition
Min.
Max.
Unit
ILI
Input leakage
current
VIN = VSS or VCC
±2
µA
ILO
Output leakage
current
S = VCC, VOUT = VSS or VCC
±2
µA
ICC
Supply current
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 2.5 V, Q = open
2
mA
ICC1
Supply current
(Standby)
S = VCC, VCC = 2.5 V, VIN = VSS or VCC
2
µA
VIL
Input low voltage
–0.45
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+1
V
VOL
Output low voltage
0.4
V
VOH
Output high voltage IOH = –0.4 mA, VCC = 2.5 V
Table 17.
Symbol
IOL = 1.5 mA, VCC = 2.5 V
0.8 VCC
V
DC characteristics (M95160-W and M95080-W, device grade 6)
Parameter
Test condition
Min.
Max.
Unit
ILI
Input leakage
current
VIN = VSS or VCC
±2
µA
ILO
Output leakage
current
S = VCC, VOUT = VSS or VCC
±2
µA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 2.5V, Q = open, Process SA
2
mA
C = 0.1VCC/0.9VCC at 10 MHz,
VCC = 2.5 V, Q = open, Process GB or
SB
5
mA
S = VCC, 2.5 V <VCC < 5.5 V
VIN = VSS or VCC
2
µA
ICC
Supply current
ICC1
Supply current
(Standby)
VIL
Input low voltage
–0.45
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+1
V
VOL
Output low voltage
0.4
V
VOH
Output high voltage IOH = –0.4 mA, VCC = 2.5 V
IOL = 1.5 mA, VCC = 2.5 V
0.8 VCC
V
29/45
DC and AC parameters
Table 18.
Symbol
30/45
M95160, M95080
DC characteristics (M95160-R and M95080-R)
Parameter
Test Condition
Min.
Max.
Unit
ILI
Input leakage current
VIN = VSS or VCC
±2
µA
ILO
Output leakage current
S = VCC, VOUT = VSS or VCC
±2
µA
ICC
Supply current
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 1.8 V, Q = open
3
mA
ICC1
Supply current
(Standby)
S = VCC, VIN = VSS or VCC,
1.8 < VCC < 2.5 V
1
µA
VIL
Input low voltage
–0.45
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+1
V
VOL
Output low voltage
IOL = 0.15 mA, VCC = 1.8 V
0.3
V
VOH
Output high voltage
IOH = –0.1 mA, VCC = 1.8 V
0.8 VCC
V
M95160, M95080
DC and AC parameters
Table 19.
AC characteristics (M95160 and M95080, device grade 3)
Test conditions specified in Table 12. and Table 9.
Symbol
Alt.
fC
fSCK
Clock frequency
tSLCH
tCSS1
S active setup time
90
ns
tSHCH
tCSS2
S not active setup time
90
ns
tSHSL
tCS
S deselect time
100
ns
tCHSH
tCSH
S active hold time
90
ns
S not active hold time
90
ns
tCHSL
Parameter
Min.
Max.
Unit
D.C.
5
MHz
tCH(1)
tCLH
Clock high time
90
ns
(1))
90
ns
tCLL
Clock low time
tCLCH
(2)
tRC
Clock rise time
1
µs
tCHCL
(2)
tFC
Clock fall time
1
µs
tCL
tDVCH
tDSU
Data in setup time
20
ns
tCHDX
tDH
Data in hold time
30
ns
tHHCH
Clock low hold time after HOLD not active
70
ns
tHLCH
Clock low hold time after HOLD active
40
ns
tCLHL
Clock low set-up time before HOLD active
0
ns
tCLHH
Clock low set-up time before HOLD not active
0
ns
tSHQZ(2)
tDIS
tCLQV
tV
tCLQX
Output disable time
100
ns
Clock low to output valid
60
ns
tHO
Output hold time
tQLQH
(2)
0
ns
tRO
Output rise time
50
ns
tQHQL
(2)
tFO
Output fall time
50
ns
tHHQV
tLZ
HOLD high to output valid
50
ns
tHLQZ(2)
tHZ
HOLD low to output High-Z
100
ns
tW
tWC
Write time
5
ms
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterization, not 100% tested in production.
31/45
DC and AC parameters
Table 20.
M95160, M95080
AC characteristics (M95160 and M95080, device grade 6)
Test conditions specified in Table 12. and Table 9.
Symbol
Alt.
fC
fSCK
Clock frequency
tSLCH
tCSS1
S active setup time
15
ns
tSHCH
tCSS2
S not active setup time
15
ns
tSHSL
tCS
S deselect time
40
ns
tCHSH
tCSH
S active hold time
25
ns
S not active hold time
15
ns
tCHSL
Parameter
Max.
Unit
D.C.
10
MHz
tCH(1)
tCLH
Clock high time
40
ns
(1)
40
ns
tCLL
Clock low time
tCLCH(2)
tRC
Clock rise time
1
µs
tCHCL(2)
tFC
Clock fall time
1
µs
tDVCH
tDSU
Data in setup time
15
ns
tCHDX
tDH
Data in hold time
15
ns
tHHCH
Clock low hold time after HOLD not active
15
ns
tHLCH
Clock low hold time after HOLD active
20
ns
tCLHL
Clock low set-up time before HOLD active
0
ns
tCLHH
Clock low set-up time before HOLD not active
0
ns
tCL
tSHQZ(2)
tDIS
tCLQV
tV
tCLQX
Output disable time
25
ns
Clock low to output valid
35
ns
tHO
Output hold time
tQLQH
(2)
tRO
Output rise time
20
ns
tQHQL
(2)
tFO
Output Fall Time
20
ns
tHHQV
tLZ
HOLD High to Output Valid
25
ns
tHLQZ ((2))
tHZ
HOLD Low to Output High-Z
35
ns
tW
tWC
Write Time
5
ms
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterization, not 100% tested in production.
32/45
Min.
0
ns
M95160, M95080
DC and AC parameters
Table 21.
AC characteristics (M95160-W and M95080-W, device grade 3)
Test conditions specified in Table 12. and Table 10.
Symbol
Alt.
fC
fSCK
Clock frequency
tSLCH
tCSS1
S active setup time
90
ns
tSHCH
tCSS2
S not active setup time
90
ns
tSHSL
tCS
S deselect time
100
ns
tCHSH
tCSH
S active hold time
90
ns
S not active hold time
90
ns
tCHSL
Parameter
Min.
Max.
Unit
D.C.
5
MHz
tCH(1)
tCLH
Clock high time
90
ns
tCL(1)
90
ns
tCLL
Clock low time
tCLCH
(2)
tRC
Clock rise time
1
µs
tCHCL
(2)
tFC
Clock fall time
1
µs
tDVCH
tDSU
Data in setup time
20
ns
tCHDX
tDH
Data in hold time
30
ns
tHHCH
Clock low hold time after HOLD not active
70
ns
tHLCH
Clock low hold time after HOLD active
40
ns
tCLHL
Clock low set-up time before HOLD active
0
ns
tCLHH
Clock low set-up time before HOLD not active
0
ns
tSHQZ(2)
tDIS
tCLQV
tV
tCLQX
Output disable time
100
ns
Clock low to output valid
60
ns
tHO
Output hold time
tQLQH
(2)
0
ns
tRO
Output rise time
50
ns
tQHQL
(2)
tFO
Output fall time
50
ns
tHHQV
tLZ
HOLD high to output valid
50
ns
tHLQZ(2)
tHZ
HOLD low to output High-Z
100
ns
tW
tWC
Write time
5
ms
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterization, not 100% tested in production.
33/45
DC and AC parameters
Table 22.
M95160, M95080
AC characteristics (M95160-W and M95080-W, device grade 6)
Test conditions specified in Table 12. and Table 10.
Process SA
Symbol
fC
Alt.
Process GB or SB (1)
Parameter
fSCK Clock frequency
Unit
Min.
Max.
Min.
Max.
D.C.
5
D.C.
10
tSLCH
tCSS1 S active setup time
90
30
ns
tSHCH
tCSS2 S not active setup time
90
30
ns
100
40
ns
90
30
ns
S not active hold time
90
30
ns
tSHSL
tCS
tCHSH
tCSH S active hold time
tCHSL
S deselect time
tCH(2)
tCLH
Clock high time
90
40
ns
(2)
90
40
ns
tCLL
Clock low time
tCLCH(3)
tRC
Clock rise time
1
2
µs
tCHCL(3)
tFC
Clock fall time
1
2
µs
tCL
tDVCH
tDSU Data in setup time
20
10
ns
tCHDX
tDH
Data in hold time
30
10
ns
tHHCH
Clock low hold time after
HOLD not active
70
30
ns
tHLCH
Clock low hold time after
HOLD active
40
30
ns
tCLHL
Clock low set-up time before
HOLD active
0
0
ns
tCLHH
Clock low set-up time before
HOLD not active
0
0
ns
tSHQZ(3)
tDIS
tCLQV
tV
tCLQX
Output disable time
100
40
ns
Clock low to output valid
60
40
ns
tHO
Output hold time
tQLQH
(3)
0
0
tRO
Output rise time
50
40
ns
tQHQL
(3)
tFO
Output fall time
50
40
ns
tHHQV
tLZ
HOLD high to output valid
50
40
ns
tHLQZ(3)
tHZ
HOLD low to output High-Z
100
40
ns
tW
tWC
Write time
5
5
ms
1. Preliminary data
2. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
3. Value guaranteed by characterization, not 100% tested in production.
34/45
MHz
ns
M95160, M95080
DC and AC parameters
Table 23.
AC characteristics (M95160-R and M95080-R)
Test conditions specified in Table 12. and Table 11.
Symbol
fC
Alt.
Parameter
fSCK Clock frequency
Min.
Max.
Unit
D.C.
5
MHz
tSLCH
tCSS1 S active setup time
60
ns
tSHCH
tCSS2 S not active setup time
60
ns
90
ns
60
ns
60
ns
tCLH Clock high time
80
ns
tCLL Clock low time
80
ns
tSHSL
tCS
tCHSH
tCSH S active hold time
S not active hold time
tCHSL
tCH(1)
tCL
(1)
S deselect time
tCLCH(2)
tRC
Clock rise time
2
µs
tCHCL(2)
tFC
Clock fall time
2
µs
tDVCH
tDSU Data in setup time
20
ns
tCHDX
tDH
Data in hold time
20
ns
tHHCH
Clock low hold time after HOLD not active
60
ns
tHLCH
Clock low hold time after HOLD active
60
ns
tCLHL
Clock low set-up time before HOLD active
0
0
tCLHH
Clock low set-up time before HOLD not active
0
0
tSHQZ(2)
tDIS
tCLQV
tV
tCLQX
Output disable time
80
ns
Clock low to output valid
80
ns
tHO
Output hold time
tQLQH
(2)
0
ns
tRO
Output rise time
80
ns
tQHQL
(2)
tFO
Output fall time
80
ns
tHHQV
tLZ
HOLD high to output valid
80
ns
tHLQZ(2)
tHZ
HOLD low to output High-Z
80
ns
tW
tWC
Write time
5
ms
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterization, not 100% tested in production.
35/45
DC and AC parameters
M95160, M95080
Figure 15. Serial input timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
LSB IN
MSB IN
D
Q
tCLCH
High Impedance
AI01447C
Figure 16. Hold timing
S
tHLCH
tCLHL
tHHCH
C
tCLHH
tHLQZ
tHHQV
Q
D
HOLD
AI01448B
36/45
M95160, M95080
DC and AC parameters
Figure 17. Output timing
S
tCH
C
tCLQV
tCLQX
tCLQV
tCL
tSHQZ
tCLQX
LSB OUT
Q
tQLQH
tQHQL
D
ADDR.LSB IN
AI01449e
37/45
Package mechanical
10
M95160, M95080
Package mechanical
Figure 18. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, package
outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 24.
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,
mechanical data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
1.75
Max
0.069
A1
0.10
A2
1.25
b
0.28
0.48
0.011
0.019
c
0.17
0.23
0.007
0.009
ccc
0.25
0.004
0.010
0.049
0.10
0.004
D
4.90
4.80
5.00
0.193
0.189
0.197
E
6.00
5.80
6.20
0.236
0.228
0.244
E1
3.90
3.80
4.00
0.154
0.150
0.157
e
1.27
–
–
0.050
–
–
h
0.25
0.50
0.010
0.020
k
0°
8°
0°
8°
L
0.40
1.27
0.016
0.050
L1
38/45
Max
1.04
0.041
M95160, M95080
Package mechanical
Figure 19. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead
2 x 3 mm², package outline
e
D
b
L1
L3
E
E2
L
A
D2
ddd
A1
UFDFPN-01
1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be
allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering
process.
Table 25.
UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead
2 x 3 mm, package mechanical data
millimeters
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
0.55
0.50
0.60
0.022
0.020
0.024
A1
0.02
0.00
0.05
0.001
0.000
0.002
b
0.25
0.20
0.30
0.010
0.008
0.012
D
2.00
1.90
2.10
0.079
0.075
0.083
D2
1.60
1.50
1.70
0.063
0.059
0.067
ddd
0.08
0.003
E
3.00
2.90
3.10
0.118
0.114
0.122
E2
0.20
0.10
0.30
0.008
0.004
0.012
e
0.50
–
–
0.020
–
–
L
0.45
0.40
0.50
0.018
0.016
0.020
L1
L3
0.15
0.30
0.006
0.012
39/45
Package mechanical
M95160, M95080
Figure 20. TSSOP8 – 8 lead Thin Shrink Small Outline, package outline
D
8
5
c
E1
1
E
4
α
A1
A
L
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 26.
TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data
millimeters
inches
Symbol
Typ
Min
A
0.050
0.150
0.800
1.050
b
0.190
c
0.090
A2
Typ
Min
1.200
A1
1.000
CP
40/45
Max
Max
0.0472
0.0020
0.0059
0.0315
0.0413
0.300
0.0075
0.0118
0.200
0.0035
0.0079
0.0394
0.100
0.0039
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
–
–
0.0256
–
–
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.450
0.750
0.0236
0.0177
0.0295
L1
1.000
0°
8°
0.0394
α
0°
N
8
8°
8
M95160, M95080
11
Part numbering
Part numbering
Table 27.
Ordering information scheme
Example:
M95160
–
W MN 6
T
P /S
Device type
M95 = SPI serial access EEPROM
Device function
160 = 16 Kbit (2048 x 8)
080 = 8 Kbit (1024 x 8)
Operating voltage
blank = VCC = 4.5 to 5.5 V
W = VCC = 2.5 to 5.5 V
R = VCC = 1.8 to 5.5 V
Package
MN = SO8 (150 mil width)
DW = TSSOP8
MB = MLP8 (UFDFPN8)
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3 = Device tested with High Reliability Certified Flow(1).
Automotive temperature range (–40 to 125 °C)
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating technology
G or P = ECOPACK® (RoHS compliant)
Process(2)
/G or /S = F6SP36%
1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.
The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your
nearest ST sales office for a copy.
2. The Process letter (/G or /S) applies only to Range 3 devices. For Range 6 devices, the process letters do
not appear in the Ordering Information but only appear on the device package (marking) and on the
shipment box. Please contact your nearest ST Sales Office. For more information on how to identify
products by the Process Identification Letter, please refer to AN2043: Serial EEPROM Device Marking.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST Sales Office.
The category of second Level Interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to
soldering conditions are also marked on the inner box label.
41/45
Part numbering
M95160, M95080
Table 28.
Available M95160 products (package, voltage range, temperature grade)
Package
M95160
4.5 V to 5.5 V
M95160-W
2.5 V to 5.5 V
M95160-R
1.8 V to 5.5 V
SO8 (MN)
Range 6
Range3
Range 6
Range3
Range 6
TSSOP (DW)
NA(1)
Range 6
Range3
Range 6
MLP 2x3mm (MB)
NA(1)
NA(1)
Range 6
1. NA = Not available
Table 29.
Available M95080 products (package, voltage range, temperature grade)
Package
M95080
4.5 V to 5.5 V
M95080-W
2.5 V to 5.5 V
M95080-R
1.8 V to 5.5 V
SO8 (MN)
Range 6
Range3
Range 6
Range3
Range 6
TSSOP (DW)
NA(1)
Range 6
Range3
Range 6
MLP 2x3mm (MB)
NA(1)
Range 6
Range 6
1. NA = Not available
42/45
M95160, M95080
12
Revision history
Revision history
Table 30.
Document revision history
Date
Revision
19-Jul-2001
1.0
Document written from previous M95640/320/160/080 datasheet
06-Feb-2002
1.1
Announcement made of planned upgrade to 10MHz clock for the 5V, –40
to 85°C, range
18-Oct-2002
1.2
TSSOP8 (3x3mm body size, MSOP8) package added
04-Nov-2002
1.3
New products, identified by the process letter W, added
13-Nov-2002
1.4
Correction to footnote in Ordering Information table
21-Nov-2003
2.0
Table of contents, and Pb-free options added. VIL(min) improved to –
0.45V
3.0
MLP8 package added. Absolute Maximum Ratings for VIO(min) and
VCC(min) improved. Soldering temperature information clarified for RoHS
compliant devices. Device Grade 3 clarified, with reference to HRCF and
automotive environments. Process identification letter “G” information
added. SO8 narrow and TSSOP8 Package mechanical specifications
updated.
4.0
Product List summary table added. AEC-Q100-002 compliance. tHHQX
corrected to tHHQV.
10MHz, 5ms Write is now the present product. tCH+tCL<1/fC constraint
clarified
5.0
Added 20MHz and -S product information. Removed DIP package. Info on
Pull-up resistors, VCC lines and Note 2. added to Figure 4.: Bus master
and memory devices on the SPI bus. Device internal reset paragraph
clarified. Packages compliant with the JEDEC Std J-STD-020C. Process
info updated in DC and AC parameters and Table 27.: Ordering
information scheme.
08-Jun-2004
07-Oct-2004
21-Sep-2005
Changes
43/45
Revision history
Table 30.
Date
24-May-2007
44/45
M95160, M95080
Document revision history
Revision
Changes
6
Document reformatted. Small text changes.
TSSOP8 3 x 3 mm (DS) package removed, 1.65 V to 5.5 V operating
voltage range removed (M95080-S and M95160-S removed).
Figure 4: Bus master and memory devices on the SPI bus updated, note 2
removed and explanatory paragraph added (see Section 3: Connecting to
the SPI bus).
Section 2.7: VCC supply voltage and Section 2.8: VSS ground added.
Power-up, Device Internal Reset and Power-down replaced by
Section 4.1: Supply voltage (VCC).
Command termination specified in Section 6.4: Write Status Register
(WRSR).
Blank process no longer available for M95160, M95080, M95160-W and
M95080-W in the device grade 3 range.
L, GB and SB processes no longer available for M95160 and M95080, in
the device grade 6 range.
L process no longer available for M95160-W and M95080-W in the device
grade 6 range.
ICC1 value and test conditions modified in Table 18: DC characteristics
(M95160-R and M95080-R).
End timing line of tSHQZ modified in Figure 17: Output timing.
SO8N and UFDFPN8 package specifications updated. All packages are
ECOPACK® compliant.
Blank option removed below Plating technology and Note 2 modified in
Table 27: Ordering information scheme.
Table 28: Available M95160 products (package, voltage range,
temperature grade) and Table 29: Available M95080 products (package,
voltage range, temperature grade) added.
M95160, M95080
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