STMICROELECTRONICS RHFXH162373K-01V

54VCXH162373
Rad hard low voltage CMOS 16-bit D-type latch (3-state)
with 3.6V tolerant inputs and outputs
Features
■
1.65 to 3.6V inputs and outputs
■
High speed:
– tPD = 3.3ns (Max) at VCC = 3.0 to 3.6V
– tPD = 4.5ns (Max) at VCC = 2.3 to 2.7V
■
Symmetrical impedance outputs:
– |IOH| = IOL = 12mA (Min) at VCC = 3.0V
– |IOH| = IOL = 8mA (Min) at VCC = 2.3V
■
Power down protection on inputs and outputs
■
26Ω serie resistors in outputs
■
Operating voltage range:
– VCC(Opr) = 1.65V to 3.6V
■
Pin and function compatible with 54 SERIES
HR162373
■
Bus hold provided on both sides
■
Cold spare function
■
Latch-up performance exceeds
300mA (JESD 17)
■
ESD performance:
– HBM > 2000V
(MIL STD 883 method 3015); MM > 200V
■
300KRad Mil1019.6 Condition A, (RHA QML
qualification extension undergone)
■
No SEL, no SEU under 72 Mev/cm2/mg LET
heavy ions irradiation
■
QML qualified product
■
Device fully compliant with
DSCC SMD 5962-05211
Flat-48
Description
The 54VCXH162373 is a low voltage CMOS 16
bit d-type latch with 3 state outputs non inverting
fabricated with sub-micron silicon gate and fivelayer metal wiring C2MOS technology. It is ideal
for low power and very high speed 1.65 to 3.6V
applications; it can be interfaced to 3.6V signal
environment for both inputs and outputs.
These 16 bit D-TYPE latches are bite controlled
by two latch enable inputs (nLE) and two output
enable inputs (OE).
While the nLE input is held at a high level, the nQ
outputs will follow the data input precisely.
When the nLE is taken low, the nQ outputs will be
in a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state. Bus hold on data inputs is
provided in order to eliminate the need for
external pull-up or pull-down resistor. The device
circuits is including 26Ω series resistance in the
outputs. These resistors permit to reduce line
noise in high speed applications.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
July 2007
Rev 4
1/17
www.st.com
17
Contents
54VCXH162373
Contents
1
Logic symbols and I/O equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
2.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8
Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
54VCXH162373
1
Logic symbols and I/O equivalent circuit
Logic symbols and I/O equivalent circuit
Figure 1.
IEC logic symbols
Figure 2.
Input and output equivalent circuit
3/17
Logic symbols and I/O equivalent circuit
Figure 3.
Logic diagram
Note:
This logic diagram has not to be used to estimate propagation delays
4/17
54VCXH162373
54VCXH162373
Pin settings
2
Pin settings
2.1
Pin connection
Figure 4.
Pin connection (top through view)
5/17
Pin settings
2.2
54VCXH162373
Pin description
Table 1. Pin description
2.3
Pin N°
Symbol
Name and function
1
1OE
3 state output enable input (Active
LOW)
2, 3, 5, 6, 8, 9, 11, 12
1Q0 to 1Q7
3-state outputs
13, 14, 16, 17, 19, 20, 22, 23
2Q0 to 2Q7
3-state outputs
24
2OE
3 state output enable input (Active
LOW)
25
2LE
Latch enable input
36, 35, 33, 32, 30, 29, 27, 26
2D0 to 2D7
Data inputs
47, 46, 44, 43, 41, 40, 38, 37
1D0 to 1D7
Data inputs
48
1LE
Latch enable input
4, 10, 15, 21, 28, 34, 39, 45
GND
Ground (0V)
7, 18, 31, 42
VCC
Positive supply voltage
Truth table
Table 2. Truth table
Inputs
Output
OE
LE
D
Q
H
X
X
Z
L
L
X
No change (1)
L
H
L
L
L
H
H
H
1. Q outputs are latched at the time when the LE input is taken low logic level.
Note:
6/17
X = Do not care; Z = High Impedance
54VCXH162373
3
Maximum rating
Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 3. Absolute maximum ratings
Symbol
Value
Unit
Supply voltage
-0.5 to +4.6
V
VI
DC input voltage
-0.5 to +4.6
V
VO
DC output voltage (OFF state)
-0.5 to +4.6
V
VO
DC output voltage (High or Low state) (1)
-0.5 to VCC + 0.5
V
IIK
DC input diode current
- 50
mA
IOK
DC output diode current (2)
- 50
mA
IO
DC output current
± 50
mA
DC VCC or ground current per supply pin
± 100
mA
400
mW
-65 to +150
°C
260
°C
VCC
ICC or
IGND
Parameter
PD
Power dissipation
Tstg
Storage temperature
TL
Lead temperature (10 sec)
1. IO absolute maximum rating must be observed
2. VO < GND, VO > VCC
3.1
Recommended operating conditions
Table 4. Recommended operating conditions
Symbol
Value
Unit
Supply voltage
1.8 to 3.6
V
VI
Input voltage
-0.3 to 3.6
V
VO
Output voltage (OFF State)
0 to 3.6
V
VO
Output voltage (High or Low State)
0 to VCC
V
VCC
Parameter
IOH, IOL
High or low level output current (VCC = 3.0 to 3.6V)
± 12
mA
IOH, IOL
High or low level output current (VCC = 2.3 to 2.7V)
±8
mA
-55 to 125
°C
0 to 10
ns/V
Top
dt/dv
Operating temperature
Input rise and fall time (1)
1. VIN from 0.8V to 2V at VCC = 3.0V
7/17
Electrical characteristics
4
54VCXH162373
Electrical characteristics
Table 5. DC specifications (2.7V < VCC < 3.6V unless otherwise specified)
Test condition
Symbol
Parameter
VIH
High level input voltage
VIL
Low level input voltage
VOH
High level output
voltage
Low level output
voltage
Input leakage current
Unit
Max
2.0
V
0.8
2.7 to 3.6
IO=-100 µA
VCC-0.2
2.7
IO=-6 mA
2.2
IO=-8 mA
2.4
IO=-12 mA
2.2
V
2.7 to 3.6
IO=100 µA
0.2
2.7
IO=6 mA
0.4
IO=8 mA
0.55
IO=12 mA
0.8
VI = 0 to 3.6V
±5
2.7 to 3.6
3.0
II(HOLD) Input hold current
8/17
Min
2.7 to 3.6
3.0
II
-55 to 125°C
VCC
(V)
3.0
VOL
Value
V
VI = 0.8V
75
VI = 2V
-75
µA
µA
3.6
VI = 0 to 3.6V
± 500
0
VI or VO = 0 to 3.6V
10
µA
VI = VIH or VIL
VO = 0 to 3.6V
± 10
µA
VI = VCC or GND
20
VI or VO = VCC to 3.6V
± 20
VIH = VCC - 0.6V
750
Ioff
Power Off leakage
current
IOZ
High impedance output
leakage current
2.7 to 3.6
ICC
Quiescent supply
current
2.7 to 3.6
∆ICC
ICC incr. per Input
2.7 to 3.6
µA
µA
54VCXH162373
Electrical characteristics
Table 6. DC specifications (2.3V < VCC < 2.7V unless otherwise specified)
Test condition
Symbol
Parameter
VIH
High level input voltage
VIL
Low level input voltage
Min
II
Max
1.6
2.3 to 2.7
V
0.7
High level output voltage
2.3
2.3 to 2.7
VOL
Unit
-55 to 125 °C
VCC
(V)
2.3 to 2.7
VOH
Value
Low level output voltage
2.3
Input leakage current
2.3 to 2.7
II(HOLD) Input hold current
Ioff
Power Off leakage
current
IOZ
ICC
2.3
IO=-100 µA
VCC-0.2
IO=-4 mA
2.0
IO=-6 mA
1.8
IO=-8 mA
1.7
V
IO=100 µA
0.2
IO=6 mA
0.4
IO=8 mA
0.6
VI = VCC or GND
±5
VI = 0.7V
45
VI = 1.7V
-45
V
µA
µA
0
VI or VO = 0 to 3.6V
10
µA
High impedance output
leakage current
2.3 to 2.7
VI = VIH or VIL
VO = 0 to 3.6V
± 10
µA
Quiescent supply
current
VI = VCC or GND
20
2.3 to 2.7
VI or VO = VCC to 3.6V
± 20
µA
Table 7. Dynamic switching characteristics
(TA = 25°C, Input tr = tf = 2.0ns, CL = 30pF, RL = 500Ω)
Test condition
Symbol
Parameter
TA = 25 °C
VCC
(V)
2.5
VOLV
Dynamic valley low voltage
quiet output (1) (2)
VOHV
Dynamic valley high voltage
quiet output (2) (3)
2.5
VOHV
Dynamic valley high voltage
quiet output (2) (3)
2.5
3.3
3.3
3.3
Value
Min
VIL = 0V
VIH = VCC
VIL = 0V
VIH = VCC
VIL = 0V
VIH = VCC
Typ
Unit
Max
0.25
V
0.35
-0.25
V
-0.35
2.05
V
2.65
1. Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to
HIGH. The remaining output is measured in the LOW state.
2. Parameters guaranteed by design.
3. Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to
HIGH. The remaining output is measured in the HIGH state.
9/17
Electrical characteristics
54VCXH162373
Table 8. AC electrical characteristics (CL = 30pF, RL = 500Ω, Input tr = tf = 2.0ns)
Symbol
Test condition
Value
VCC
(V)
-55 to 125 °C
Min
Max
Parameter
tPLH tPHL
Propagation delay
time Dn to Qn
2.3 to 2.7
1.0
5.2
3.0 to 3.6
0.8
4.0
tPLH tPHL
Propagation delay
time LE to Qn
2.3 to 2.7
1.0
5.7
3.0 to 3.6
0.8
4.2
tPZL tPZH
2.3 to 2.7
1.0
6.2
Output enable time
3.0 to 3.6
0.8
4.7
tPLZ tPHZ
2.3 to 2.7
1.0
5.1
Output disable time
3.0 to 3.6
0.8
4.8
ts
Setup tIme, HIGH or
LOW level Dn to LE
2.3 to 2.7
1.0
3.0 to 3.6
1.0
th
Hold time HIGH or
LOW level Dn to LE
2.3 to 2.7
1.5
3.0 to 3.6
1.5
tw
2.3 to 2.7
1.5
LE pulse width, HIGH
3.0 to 3.6
1.5
tOSLH tOSHL
Output to output skew
time (1) (2)
Unit
ns
ns
ns
ns
ns
ns
ns
2.3 to 2.7
0.5
3.0 to 3.6
0.5
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|,
tOSHL = | tPHLm - tPHLn|)
2. Parameter guaranteed by design
Table 9. Capacitive characteristics
Test condition
Symbol
Parameter
Value
TA = 25 °C
VCC
(V)
Min
Typ
Unit
Max
Input capacitance
2.5 or 3.3
VIN = 0 or VCC
6
pF
COUT
Output capacitance
2.5 or 3.3
VIN = 0 or VCC
7
pF
CPD
Power dissipation
capacitance (1)
2.5 or 3.3
fIN = 10MHz
VIN = 0 or VCC
20
pF
CIN
1. CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the
operating current consumption without load. (Refer to Test Circuit). Average operating current can be
obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per circuit)
10/17
54VCXH162373
5
Test circuit
Test circuit
Figure 5.
Test circuit
Table 10. Test circuit
Test
tPLH, tPHL
Switch
Open
tPZL, tPLZ (VCC = 3.0 to 3.6V)
6V
tPZL, tPLZ (VCC = 2.3 to 2.7V)
2VCC
tPZH, tPHZ
GND
CL = 30pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
11/17
Waveforms
6
54VCXH162373
Waveforms
Table 11. Waveform symbol value
VCC
Symbol
Figure 6.
12/17
3.0 to 3.6V
2.3 to 2.7V
VIH
2.7V
VCC
VM
1.5V
VCC/2
VX
VOL +0.3V
VOL +0.15V
VY
VOH -0.3V
VOH -0.15V
Waveform - LE TO Qnpropagation delays, LE minimum pulse width, Dn to
LE setup and hold times (f = 1MHz; 50% duty cycle)
54VCXH162373
Waveforms
Figure 7.
Waveform - output enable and disable time (f = 1MHz; 50% duty cycle)
Figure 8.
Waveform - propagation delay time (f = 1MHz; 50% duty cycle)
13/17
Package mechanical data
7
54VCXH162373
Package mechanical data
54VCXH162373 Products are supplied into ceramic body / metal lid hermetic Flat 48-pin
space package
Table 12. Flat-48 (MIL-STD-1835) mechanical data
Dim.
mm
inch
Min
Typ
Max
Min
Typ
Max
A
2.18
2.47
2.72
0.086
0.097
0.107
b
0.20
0.254
0.30
0.008
0.010
0.012
c
0.12
0.15
0.18
0.005
0.006
0.007
D
15.57
15.75
15.92
0.613
0.620
0.627
E
9.52
9.65
9.78
0.375
0.380
0.385
E2
6.22
6.35
6.48
0.245
0.250
0.255
E3
1.52
1.65
1.78
0.060
0.065
0.070
e
0.635
0.025
f
0.20
0.008
L
6.85
8.38
9.40
0.270
0.330
0.370
Q
0.66
0.79
0.92
0.026
0.031
0.036
S1
0.25
0.43
0.61
0.010
0.017
0.024
Figure 9.
Package dimension
7330585B
14/17
54VCXH162373
8
Order code
Order code
Table 13. Order code
Flight model
Package Lead finish
Flat-48
QML-V
QML-Q
Engineering
model
Radiation level
Gold
300kRad
RHFXH162373K-01V
RHFXH162373K-01Q
RHRXH162373K1
Gold
100kRad
RHRXH162373K-01V
RHRXH162373K-01Q
RHRXH162373K1
Solder dip
100kRad
RHRXH162373K-02V
RHRXH162373K-02Q
Use the above one
15/17
Revision history
9
54VCXH162373
Revision history
Table 14. Revision history
16/17
Date
Revision
Changes
09-Jul-2004
1
First release
17-May-2005
2
SMD qualified
19-Jun-2006
3
300Krad bullet updated, new template, mechanical data updated
30-Jul-2007
4
Typo in Table 12 on page 14.
54VCXH162373
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17/17