ST755C Adjustable inverting negative output current mode PWM regulators Features ■ 2.7V to 11V input to adjustable negative output conversion ■ 1W guaranteed output power (VI > 4.5V, TA ≤ 70°C) ■ 68% typ. efficiency at 6V ■ Very low quiescent current: 1.2mA in on mode, 10µA in shut down mode ■ Soft start ■ Very low noise output ■ 160KHz fixed frequency oscillator ■ Mixed bipolar-CMOS technology SO-8 and TA = 0°C to 70°C) and 275mA (typical value at TA = 25°C, VO = -5V). A logic controlled shut down pin that interfaces directly with microprocessor reduces supply current to only 10mA. Input to Output differential voltage is limited to VI+|VO|<12.7V. No load supply current is 1.2mA Description The ST755 is an adjustable inverting switch-mode DC-DC regulator with internal Power MOSFET that generators an adjustable negative output from a voltage input of 2.7V to 11V, output current guaranteed at 200mA (for VI > 4.5V, VO = -5V Table 1. July 2007 Device summary Part number Package Packaging ST755C ST755CD-TR SO-8 (tape & reel) Rev. 5 1/16 www.st.com 16 ST755C Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/16 ST755C Diagram 1 Diagram Figure 1. Schematic diagram 3/16 Pin configuration ST755C 2 Pin configuration Figure 2. Pin connections (top view) Table 2. Pin description Pin N° Symbol 1 SHDN SHUT-DOWN control (VCC = ON, GND = Shutdown) 2 VREF Reference output voltage: (1.25V) 3 SS Soft start 4 CC Compensation input 5 VO Negative output voltage 6 GND 7 LX 8 VCC 4/16 Name and function Ground Switch output Supply voltage input ST755C Maximum ratings 3 Maximum ratings Table 3. Absolute maximum ratings Symbol VCC VSHDN Parameter DC input voltage to GND (1) Shutdown voltage, SS Voltage, CC Voltage VLX Switch voltage (LX to VCC) VFB Feedback voltage (VO to GND) ILX Peak switch current PTOT Continuous power dissipation at TA = 70°C (SO-8) Value Unit -0.3 to 12 V -0.3 to (VCC + 0.3) V -12.5 to + 0.3 V -11 to + 0.9 V 2 A 470 mW Top Operating junction temperature range (C series) -40 to 185 °C Tstg Storage temperature range -55 to +150 °C 1. The input to output differential voltage is limited to VCC+|VO|<12.7V Note: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied Table 4. Thermal data Symbol RthJA Parameter Thermal resistance junction-ambient (1) SO-8 Unit 160 °C/W 1. This value depends from thermal design of PCB on which the device is mounted. 5/16 Electrical characteristics ST755C 4 Electrical characteristics Table 5. Electrical characteristics (Refer to the test circuits, VCC = 5V, VO = -5.25 to -4.75V, ILOAD = 0mA, TA = TMIN to TMAX, unless otherwise specified. Typical value are referred at TA = 25°C) Symbol Parameter VI Input voltage VO Output voltage IO Output current Test conditions Min. Typ. 4 VCC = 4.5 to 6.2V, IO =0 to 200mA 4.75 5 VCC = 4.5 to 6.2V, TA = 0 to 70°C 200 275 VCC = 4.5 to 6.2V, TA = -40 to 85°C 175 Max. Unit 11 V 5.25 V mA VCC = 4V, VO = -5V 175 VCC = 2.7V, VO = -5V 125 Supply current (including switching current) No Load, VSHDN = VCC 1.2 3.5 mA IOFF Standby current) No Load, VSHDN = 0V 10 100 µA ISC Short circuit current) ΔVO Line regulation ΔVO ISUPPLY 1.2 A VCC = 4 to 6.2V 0.1 %/V Load regulation IO = 0 to 200mA 0.003 %/mA VREF Reference voltage TA = 25°C ΔVREF Reference drift TA = TMIN to TMAX 1.18 RDSON LX on resistance ILEAK LX leakage current) ISH Shutdown pin current) VIH SHDN input high threshold VIL SHDN input low threshold fOSC h CC Note: 6/16 VDS = 10V Compensation pin impedance 1.32 ppm/°C 0.7 Ω 1 µA 2 µA V 0.25 IO =100mA V 50 1 Oscillator frequency Power efficiency 1.25 V 160 KHz 68 % 7.5 KΩ Do not overload or short the Output to Ground. If the above conditions are observed, the device may be damaged. ST755C 5 Application information Application information The ST755 is an IC developed for voltage conversion from an input voltage ranging from +2.4V to 11V to a regulated adjustable negative output limited by |VO| ≤12.7V - VI. The circuit adopts a current-mode PWM control scheme to achieve good efficiency, high stability and low noise performance. The figure in the first page shown the detailed block diagram of the device. ST755 is realized in a BCD technology in order to achieve high temperature stability, the best REFERENCE precision, a very low quiescent current and jitter free operations. The final stage is built around a 0.7Ω - 2A P-Channel Power MOS. A fraction of the output current is splitted out for current detection.Internal clock frequency is fixed to 160KHz. Error amplifier drives the PWM comparator in order to keep 0V on the CC input. So R3 and R4 resistors are calculated by the following formulae R4 = (|VO|/VREF)*R3 (see Figure 3.). For R3 can be choose any value between 2KΩ and 20KΩ. Soft-Start (SS) input is a voltage dependent-output current limit (see Figure 11., Switch Current Limit vs. SS Input Voltage). SS pin is internally pulled to VREF through a 1.2 MΩ resistor. Applying an appropriate capacitor at SS input is possible to obtain a soft-start current imitation during power up. Forcing Soft-Start (SS) input to a lower voltage through a resistive voltage driver (R1 and R2), the maximum LX current limit can be lowered according the diagram showed in Figure 11. When SHDN input is low, the total current consumption is reduced to 10µA. 7/16 Application circuit 6 ST755C Application circuit To achieve the best performances from switching power supply topology, particular care to layout drawing is needed, in order to minimize EMI and obtain low noise, jitter free operation moreover, it ensures the full device functionality. Layout design proposed on demoboard (see Figure 4.) helps to lower the developing time. Wire lengths must be minimized, filter and by-pass capacitors C1, C2 and C3 must be low ESR type, placed as close possible to the integrated circuit. The 10µH inductor must be chosen built on a core, taking care that saturation current should be higher than the peak LX switch current. See the Peak inductor current vs. load current graph (Figure 6.). Figure 3. Typical application circuit (*) R1 and R2 can be omitted for IO<200mA. (**) C6: Very low noise but poor transient and load response speed. (***) C3 (alternative to C6): faster transient and load response. 8/16 ST755C Application circuit Figure 4. Printed demoboard Pin 1 = VCC Pin 2 = VO Pin 3 = SHDN Pin 4 = GND Note: Drawings not in scale Table 6. Component values Capacitor Value Unit Resistor Value Unit C1 47 µF R1 130 KΩ C2 100 µF R2 300 KΩ C3 82 pF R3 10 KΩ C4 1 µF R4 40.7 KΩ C5 10 µF R5 10 KΩ C6 47 pF 9/16 Typical performance characteristics ST755C 7 Typical performance characteristics Figure 5. (Unless otherwise specified TJ = 25°C) Load current vs supply voltage Figure 6. Peak inductor current vs load curr. Figure 7. Load current vs supply voltage Figure 8. Switch ON resist. vs supply voltage Figure 9. Efficiency vs load current Figure 10. Oscillator frequency vs temperature & supply voltage 10/16 ST755C Figure 11. Switch current limit vs soft start voltage Typical performance characteristics Figure 12. Reference voltage vs temperature Figure 13. Soft start delay time 11/16 Package mechanical data 8 ST755C Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 12/16 ST755C Package mechanical data SO-8 MECHANICAL DATA DIM. mm. MIN. TYP inch MAX. MIN. TYP. MAX. A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.04 0.010 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.00 0.150 0.157 e 1.27 0.050 H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 k ddd 8˚ (max.) 0.1 0.04 0016023/C 13/16 Package mechanical data ST755C Tape & Reel SO-8 MECHANICAL DATA mm. inch DIM. MIN. A MAX. MIN. 330 13.2 TYP. MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 14/16 TYP 0.504 22.4 0.519 0.882 Ao 8.1 8.5 0.319 0.335 Bo 5.5 5.9 0.216 0.232 Ko 2.1 2.3 0.082 0.090 Po 3.9 4.1 0.153 0.161 P 7.9 8.1 0.311 0.319 ST755C Revision history 9 Revision history Table 7. Revision history Date Revision 06-Jul-2007 5 Changes Device summary updated and the document has been reformatted. 15/16 ST755C Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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