STMICROELECTRONICS ST7PLITEUS2M6TR

ST7LITEUSx
8-bit MCU with single voltage Flash memory,
ADC, timers
Features
■
■
■
■
■
Memories
– 1K bytes single voltage Flash Program memory with read-out protection, In-Circuit and InApplication Programming (ICP and IAP). 10K
write/erase cycles guaranteed, data retention:
20 years at 55°C.
– 128 bytes RAM.
Clock, Reset and Supply Management
– 3-level low voltage supervisor (LVD) and auxiliary voltage detector (AVD) for safe poweron/off procedures
– Clock sources: internal trimmable 8MHz RC
oscillator, internal low power, low frequency
RC oscillator or external clock
– Five Power Saving Modes: Halt, Auto Wake
Up from Halt, Active-Halt, Wait and Slow
Interrupt Management
– 11 interrupt vectors plus TRAP and RESET
– 5 external interrupt lines (on 5 vectors)
I/O Ports
– 5 multifunctional bidirectional I/O lines
– 1 additional Output line
– 6 alternate function lines
– 5 high sink outputs
2 Timers
– One 8-bit Lite Timer (LT) with prescaler including: watchdog, one realtime base and one
8-bit input capture.
– One 12-bit Auto-reload Timer (AT) with output
compare function and PWM
SO8
150”
DIP8
DFN8
■
■
■
A/D Converter
– 10-bit resolution for 0 to VDD
– 5 input channels
Instruction Set
– 8-bit data manipulation
– 63 basic instructions with illegal opcode detection
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
Development Tools
– Full hardware/software development package
– Debug Module
Table 1. Device summary
Features
Program memory - bytes
RAM (stack) - bytes
Peripherals
ADC
Operating Supply
CPU Frequency
Operating Temperature
Packages
ST7ULTRALITE
ST7LITEUS2
ST7LITEUS5
1K
128 (64)
LT Timer w/ Wdg, AT Timer w/ 1 PWM
10-bit
2.4V to 3.3V @fCPU=4MHz, 3.3V to 5.5V @fCPU=8MHz
up to 8MHz RC
-40°C to +85°C / -40°C to 125°C
SO8 150”, DIP8, DFN8, DIP161)
Note 1: For development or tool prototyping purposes only. Not orderable in production quantities.
Rev. 4
January 2007
1/108
1
ST7LITEUSx
ST7LITEUSx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
ST7LITEUSx
1 INTRODUCTION . . .. ... .. ... .. ... .. ... .. ... .. ... .. ... .. ... .. ... .. ... .. ... .. ... .. ... .. ... .. ... .. ... .. ... .. ... .. ... .. ... 1
4
2
DESCRIPTION
5
1 PIN
INTRODUCTION
.............................................................. 4
3 REGISTER
& MEMORY
8
2
PIN DESCRIPTION
. . . .MAP
........................................................ 5
4
FLASH
PROGRAM
MEMORY
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11
3 REGISTER & MEMORY MAP .
. 8
4.1 INTRODUCTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 FLASH
PROGRAM MEMORY
4.2 INTRODUCTION
MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
4.3
4.2 PROGRAMMING
MAIN FEATURESMODES
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4
INTERFACE MODES
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
12
4.3 ICC
PROGRAMMING
4.5
MEMORY
PROTECTION
4.4 ICC
INTERFACE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
12
4.6
RELATED PROTECTION
DOCUMENTATION
4.5 MEMORY
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.7
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.6 REGISTER
RELATED DOCUMENTATION
5 CENTRAL
PROCESSING
UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.7 REGISTER
DESCRIPTION
13
5.1
INTRODUCTION
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14
5 CENTRAL PROCESSING UNIT
5.2
MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 INTRODUCTION
5.3
5.2 CPU
MAINREGISTERS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 SUPPLY,
AND CLOCK
5.3 CPURESET
REGISTERS
. . . . . .MANAGEMENT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
14
6.1 INTERNAL
OSCILLATOR
ADJUSTMENT
6 SUPPLY,
RESET RC
AND
CLOCK MANAGEMENT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2
DESCRIPTION
. .ADJUSTMENT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
19
6.1 REGISTER
INTERNAL RC
OSCILLATOR
6.3
RESET SEQUENCE
MANAGER
22
6.2 REGISTER
DESCRIPTION
. . . . (RSM)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4
DESCRIPTION
. . . . (RSM)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3 REGISTER
RESET SEQUENCE
MANAGER
22
7 INTERRUPTS
. . DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
25
6.4 REGISTER
7.1 NON MASKABLE
7 INTERRUPTS
. . . . . . . SOFTWARE
. . . . . . . . . . .INTERRUPT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2
EXTERNAL
INTERRUPTS
. . .INTERRUPT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1 NON
MASKABLE
SOFTWARE
7.3
PERIPHERAL
INTERRUPTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2 EXTERNAL
INTERRUPTS
7.4
INTEGRITY
MANAGEMENT
7.3 SYSTEM
PERIPHERAL
INTERRUPTS
. . . . . . . .(SI)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
25
8 POWER
SAVING
MODES .MANAGEMENT
. . . . . . . . . . . . .(SI)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
33
7.4 SYSTEM
INTEGRITY
8.1 INTRODUCTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8 POWER
SAVING MODES
34
8.2
MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
33
8.1 SLOW
INTRODUCTION
8.3
WAIT MODE
8.2 SLOW
MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.4
ACTIVE-HALT
8.3 WAIT
MODE .AND
. . . . HALT
. . . . . MODES
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.5
WAKE UP
FROM
HALT
MODE
37
8.4 AUTO
ACTIVE-HALT
AND
HALT
MODES
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9 I/O
. . . . . .UP
. . .FROM
. . . . . .HALT
. . . . .MODE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
41
8.5PORTS
AUTO. WAKE
9.1PORTS
INTRODUCTION
41
9 I/O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.2
FUNCTIONAL DESCRIPTION
9.1 INTRODUCTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
42
9.3
I/O PINS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
45
9.2 UNUSED
FUNCTIONAL
DESCRIPTION
9.4
LOW POWER
MODES
9.3 UNUSED
I/O PINS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
46
9.5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
45
9.4 INTERRUPTS
LOW POWER MODES
9.6
I/O PORT IMPLEMENTATION
9.5 INTERRUPTS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
46
10 ON-CHIP
PERIPHERALS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
47
9.6 I/O PORT
IMPLEMENTATION
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ST7LITEUSx
10.1 LITE TIMER (LT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.2 12-BIT AUTORELOAD TIMER (AT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.3 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
11.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.1010-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
13.2 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
14 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 95
14.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
14.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
15 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
15.1 LIMITATIONS IN USER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
15.2 LIMITATIONS IN ICC MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Please pay special attention to the Section “KNOWN LIMITATIONS” on page 104
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ST7LITEUSx
1 INTRODUCTION
The ST7ULTRALITE is a member of the ST7 microcontroller family. All ST7 devices are based on
a common industry-standard 8-bit core, featuring
an enhanced instruction set.
The ST7ULTRALITE features FLASH memory
with byte-by-byte In-Circuit Programming (ICP)
and In-Application Programming (IAP) capability.
Under software control, the ST7ULTRALITE device can be placed in WAIT, SLOW, or HALT
mode, reducing power consumption when the application is in idle or standby state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing
modes.
For easy reference, all parametric data are located
in section 12 on page 67.
The devices feature an on-chip Debug Module
(DM) to support in-circuit debugging (ICD). For a
description of the DM registers, refer to the ST7
ICC Protocol Reference Manual.
Figure 1. General block diagram
AWU RC OSC
Internal
Clock
8-MHz RC OSC
External
Clock
VDD
VSS
LVD
POWER
SUPPLY
PORT A
CONTROL
8-BIT CORE
ALU
1K Byte
FLASH
MEMORY
RAM
(128 Bytes)
4/108
1
ADDRESS AND DATA BUS
PA3 / RESET
LITE TIMER
with WATCHDOG
12-BIT AUTORELOAD TIMER
10-BIT ADC
PA5:0
(6 bits)
ST7LITEUSx
2 PIN DESCRIPTION
Figure 2. 8-pin SO and DIP package pinout
VDD
1
8
VSS
PA5 (HS) / AIN4 / CLKIN
2 ei4
ei0 7
PA0 (HS) / AIN0 / ATPWM / ICCDATA
PA4 (HS) / AIN3
3 ei3
ei1 6
PA1 (HS) / AIN1 / ICCCLK
4
ei2 5
PA2 (HS) / LTIC / AIN2
PA3 / RESET
(HS) : High sink capability
eix : associated external interrupt vector
Figure 3. 8-pin DFN package pinout
VDD
1
8
VSS
PA5 (HS) / AIN4 / CLKIN
2 ei4
ei0 7
PA0 (HS) / AIN0 / ATPWM / ICCDATA
PA4 (HS) / AIN3
3 ei3
ei1 6
PA1 (HS) / AIN1 / ICCCLK
4
ei2 5
PA2 (HS) / LTIC / AIN2
PA3 / RESET
(HS) : High sink capability
eix : associated external interrupt vector
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ST7LITEUSx
PIN DESCRIPTION (Cont’d)
Figure 4. 16-pin package pinout (For development or tool prototyping purposes only. Package not
orderable in production quantities.)
Reserved 1)
1
16
NC
VDD
2
15
VSS
RESET
3
ei0 14
PA0 (HS) / AIN0 / ATPWM
ICCCLK
4
ei1 13
PA1 (HS) / AIN1
PA5 (HS) / AIN4 / CLKIN
5 ei4
12
NC
PA4 (HS) / AIN3
6 ei3
11
ICCDATA
PA3
7
ei2 10
NC
8
9
PA2 (HS) / LTIC / AIN2
NC
Note 1: must be tied to ground
Notes:
The differences versus the 8-pin packages are listed below:
1. The ICC signals (ICCCLK and ICCDATA) are
mapped on dedicated pins.
2. The RESET signal is mapped on a dedicated
pin. It is not multiplexed with PA3.
6/108
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3. PA3 pin is always configured as output. Any
change on multiplexed IO reset control registers
(MUXCR1 and MUXCR2) will have no effect on
PA3 functionality. Refer to “REGISTER DESCRIPTION” on page 24.
ST7LITEUSx
PIN DESCRIPTION (Cont’d)
Legend / Abbreviations for Table 1:
Type: I = input, O = output, S = supply
In/Output level: CT= CMOS 0.3VDD/0.7VDD with
input trigger
Output level: HS = High sink (on N-buffer only)
Port and control configuration:
– Input:float = floating, wpu = weak pull-up, int = interrupt, ana = analog
– Output: OD = open drain, PP = push-pull
The RESET configuration of each pin is shown in
bold which is valid as long as the device is in reset
state.
Table 1. Device Pin Description
Alternate Function
PP
OD
ana
int
Port / Control
Main
Input
Output Function
(after
reset)
wpu
float
Output
Input
Pin Name
Type
Level
Pin
No.
1
VDD
S
Main power supply
2
PA5/AIN4/
CLKIN
I/O CT HS
X
ei4
X
X
X
Port A5
Analog input 4 or External Clock Input
3
PA4/AIN3
I/O CT HS
X
ei3
X
X
X
Port A4
Analog input 3
4
PA3/RESET 1)
O
X
X
Port A3
RESET 1)
5
PA2/AIN2/LTIC I/O CT HS
X
X
Port A2
X
X
ei2
X
6
PA1/AIN1/
ICCCLK
I/O CT HS
X
ei1
X
X
X
Port A1
7
PA0/AIN0/ATPI/O CT HS
WM/ICCDATA
X
ei0
X
X
X
Port A0
8
VSS
S
Analog input 2 or Lite Timer Input Capture
Analog input 1 or In Circuit Communication Clock
Caution: During normal operation this
pin must be pulled-up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to
avoid entering ICC mode unexpectedly
during a reset. In the application, even if
the pin is configured as output, any reset will put it back in pull-up
Analog input 0 or Auto-Reload Timer
PWM or In Circuit Communication Data
Ground
Note:
1. After a reset, the multiplexed PA3/RESET pin will act as RESET. To configure this pin as output (Port
A3), write 55h to MUXCR0 and AAh to MUXCR1. For further details, please refer to section 6.4 on page
24.
7/108
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ST7LITEUSx
3 REGISTER & MEMORY MAP
As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers.
The available memory locations consist of 128
bytes of register locations, 128 bytes of RAM and
1 Kbytes of user program memory. The RAM
space includes up to 64 bytes for the stack from
00C0h to 00FFh.
The highest address bytes contain the user reset
and interrupt vectors.
The Flash memory contains two sectors (see Figure 5) mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors
are located in Sector 0 (FE00h-FFFFh).
The size of Flash Sector 0 and other device options are configurable by Option byte.
IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reseved area can have unpredictable effects on the
device.
Figure 5. Memory Map
0000h
007Fh
0080h
HW Registers
0080h
Short Addressing
RAM (zero page)
(see Table 2)
00C0h
RAM
(128 Bytes)
64-Byte Stack
00FFh
00FFh
0100h
DEE0h
DEE1h
DEE2h
Reserved
1K FLASH
PROGRAM MEMORY
RCCRL0
RCCRH1
RCCRL1
see section 6.1 on page 17
FBFFh
FC00h
FC00h
FDFFh
FE00h
Flash Memory
(1K)
FFDFh
FFE0h
DEE3h
RCCRH0
FFFFh
0.5 Kbytes
SECTOR 1
0.5 Kbytes
SECTOR 0
Interrupt & Reset Vectors
(see Table 7)
FFFFh
Note:
1. DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area but are special bytes
containing also the RC calibration values which are read-accessible only in user mode. If all the EEPROM
data or Flash space (including the RC calibration values locations) has been erased (after the read-out
protection removal), then the RC calibration values can still be obtained through these addresses.
8/108
1
ST7LITEUSx
Table 2. Hardware Register Map
Address
0000h
0001h
0002h
Block
Port A
Register
Label
PADR
PADDR
PAOR
0003h000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
LITE
TIMER
00h 1)
08h
02h 2)
Remarks
R/W
R/W
R/W
AUTORELOAD
TIMER
LTCSR
LTICR
Lite Timer Control/Status Register
Lite Timer Input Capture Register
0xh
00h
R/W
Read Only
ATCSR
CNTRH
CNTRL
ATRH
ATRL
PWMCR
PWM0CSR
Timer Control/Status Register
Counter Register High
Counter Register Low
Auto-Reload Register High
Auto-Reload Register Low
PWM Output Control Register
PWM 0 Control/Status Register
00h
00h
00h
00h
00h
00h
00h
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
00h
00h
R/W
R/W
00h
R/W
Reserved area (3 bytes)
AUTORELOAD
TIMER
DCR0H
DCR0L
0019h to
002Eh
0002Fh
Port A Data Register
Port A Data Direction Register
Port A Option Register
Reset Status
Reserved area (8 bytes)
0014h to
0016h
0017h
0018h
Register Name
PWM 0 Duty Cycle Register High
PWM 0 Duty Cycle Register Low
Reserved area (22 bytes)
FLASH
FCSR
0030h to
0033h
Flash Control/Status Register
Reserved area (4 bytes)
0034h
0035h
0036h
ADC
ADCCSR
ADCDRH
ADCDRL
A/D Control Status Register
A/D Data Register High
A/D Data Register Low
00h
xxh
00h
R/W
Read Only
R/W
0037h
ITC
EICR1
External Interrupt Control Register 1
00h
R/W
0038h
MCC
MCCSR
Main Clock Control/Status Register
00h
R/W
0039h
003Ah
Clock and
Reset
RCCR
SICSR
RC oscillator Control Register
System Integrity Control/Status Register
FFh
0000 0x00b
R/W
R/W
003Bh to
003Ch
Reserved area (2 bytes)
003Dh
ITC
EICR2
External Interrupt Control Register 2
00h
R/W
003Eh
AVD
AVDTHCR
AVD Threshold Selection Register
03h
R/W
003Fh
Clock
controller
CKCNTCSR
Clock Controller Control/Status Register
09h
R/W
0040h to
0046h
Reserved area (7 bytes)
9/108
1
ST7LITEUSx
Register
Label
Address
Block
0047h
0048h
MuxIOreset
MUXCR0
MUXCR1
Mux IO-Reset Control Register 0
Mux IO-Reset Control Register 1
00h
00h
R/W
R/W
0049h
004Ah
AWU
AWUPR
AWUCSR
AWU Prescaler Register
AWU Control/Status Register
FFh
00h
R/W
R/W
DM 3)
DMCR
DMSR
DMBK1H
DMBK1L
DMBK2H
DMBK2L
DM Control Register
DM Status Register
DM Breakpoint Register 1 High
DM Breakpoint Register 1 Low
DM Breakpoint Register 2 High
DM Breakpoint Register 2 Low
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h to
007Fh
Register Name
Reset Status
Remarks
Reserved area (47 bytes)
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
3. For a description of the DM registers, see the ST7 ICC Protocol Reference Manual.
10/108
1
ST7LITEUSx
4 FLASH PROGRAM MEMORY
4.1 Introduction
The ST7 single voltage extended Flash (XFlash) is
a non-volatile memory that can be electrically
erased and programmed either on a byte-by-byte
basis or up to 32 bytes in parallel.
The XFlash devices can be programmed off-board
(plugged in a programming tool) or on-board using
In-Circuit Programming or In-Application Programming.
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
4.2 Main Features
■
■
■
■
■
ICP (In-Circuit Programming)
IAP (In-Application Programming)
ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
Sector 0 size configurable by option byte
Read-out and write protection
4.3 PROGRAMMING MODES
The ST7 can be programmed in three different
ways:
– Insertion in a programming tool. In this mode,
FLASH sectors 0 and 1 and option byte row
can be programmed or erased.
– In-Circuit Programming. In this mode, FLASH
sectors 0 and 1 and option byte row can be
programmed or erased without removing the
device from the application board.
– In-Application Programming. In this mode,
sector 1 can be programmed or erased without removing the device from the application
board and while the application is running.
4.3.1 In-Circuit Programming (ICP)
ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable.
ICP is performed in three steps:
– Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while
the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 System Memory
containing the ICC protocol routine. This routine
enables the ST7 to receive bytes from the ICC interface.
– Download ICP Driver code in RAM from the ICCDATA pin
– Execute ICP Driver code in RAM to program the
FLASH memory
Depending on the ICP Driver code downloaded in
RAM, FLASH memory programming can be fully
customized (number of bytes to program, program
locations, or selection of the serial communication
interface for downloading).
4.3.2 In Application Programming (IAP)
This mode uses an IAP Driver program previously
programmed in Sector 0 by the user (in ICP
mode).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (user-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored etc.)
IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during
the programming operation.
11/108
1
ST7LITEUSx
FLASH PROGRAM MEMORY (Cont’d)
4.4 ICC interface
ICP needs a minimum of 4 and up to 6 pins to be
connected to the programming tool. These pins
are:
– RESET: device reset
– VSS: device power supply ground
– ICCCLK: ICC output serial clock pin (see note
1)
– ICCDATA: ICC input serial data pin
– CLKIN: main clock input for external source
– VDD: application board power supply (see
Note 3)
Figure 6. Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICC CONNECTOR
HE10 CONNECTOR TYPE
(See Note 3)
OPTIONAL
(See Note 4)
9
7
5
3
1
10
8
6
4
2
APPLICATION BOARD
APPLICATION
RESET SOURCE
See Note 2
3.3kΩ
(See Note 5)
APPLICATION
POWER SUPPLY
See Note 1 and Caution
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to be implemented in case another device forces the signal. Refer to the Programming
Tool documentation for recommended resistor values.
2. During the ICP session, the programming tool
must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the application RESET circuit in this case. When using a
classical RC network with R>1K or a reset management IC with open drain output and pull-up re-
12/108
1
APPLICATION
I/O
ICCDATA
ICCCLK
ST7
RESET
CLKIN
VDD
See Note 1
sistor>1K, no additional components are needed.
In all cases the user must ensure that no external
reset is generated by the application during the
ICC session.
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Programming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
4. Pin 9 has to be connected to the CLKIN pin of
the ST7 when ICC mode is selected with option
bytes disabled (35-pulse ICC entry mode). When
option bytes are enabled (38-pulse ICC entry
mode), the internal RC clock (internal RC or AWU
RC) is forced. If internal RC is selected in the option byte, the internal RC is provided. If AWU RC
or external clock is selected, the AWU RC oscillator is provided.
ST7LITEUSx
FLASH PROGRAM MEMORY (Cont’d)
5. A serial resistor must be connected to ICC connector pin 6 in order to prevent contention on PA3/
RESET pin. Contention may occur if a tool forces a
state on RESET pin while PA3 pin forces the opposite state in output mode. The resistor value is
defined to limit the current below 2mA at 5V. If PA3
is used as output push-pull, then the application
must be switched off to allow the tool to take control of the RESET pin (PA3). To allow the programming tool to drive the RESET pin below VIL, special care must also be taken when a pull-up is
placed on PA3 for application reasons.
Caution: During normal operation, ICCCLK pin
must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if
the pin is configured as output, any reset will put it
back in input pull-up.
4.5.2 Flash Write/Erase Protection
Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. Its purpose is to provide advanced security to
applications and prevent any change being made
to the memory content.
Warning: Once set, Write/erase protection can
never be removed. A write-protected flash device
is no longer reprogrammable.
Write/erase protection is enabled through the
FMP_W bit in the option byte.
4.5 Memory Protection
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write
Reset Value: 000 0000 (00h)
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
There are two different types of memory protection: read-out protection and Write/Erase Protection which can be applied individually.
4.5.1 Read-out Protection
Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory.
Even if no protection can be considered as totally
unbreakable, the feature provides a very high level
of protection for a general purpose microcontroller.
Program memory is protected.
In flash devices, this protection is removed by reprogramming the option. In this case, program
memory is automatically erased, and the device
can be reprogrammed.
Read-out protection selection depends on the device type:
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
– In ROM devices it is enabled by mask option
specified in the Option List.
4.6 Related Documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual.
4.7 Register Description
7
0
0
0
0
0
0
OPT
LAT
PGM
Note: This register is reserved for programming
using ICP, IAP or other programming methods. It
controls the XFlash programming and erasing operations.
When an EPB or another programming tool is
used (in socket or ICP mode), the RASS keys are
sent automatically.
Table 3. FLASH Register Map and Reset Values
Address
(Hex.)
002Fh
Register
Label
7
6
5
4
3
2
1
0
0
0
0
0
0
OPT
0
LAT
0
PGM
0
FCSR
Reset Value
13/108
1
ST7LITEUSx
5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
5.2 MAIN FEATURES
■
■
■
■
■
■
■
■
63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes
Two 8-bit index registers
16-bit stack pointer
Low power modes
Maskable hardware interrupts
Non-maskable software interrupt
5.3 CPU REGISTERS
The six CPU registers shown in Figure 7 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
Index Registers (X and Y)
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from
the stack).
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 7. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
X INDEX REGISTER
RESET VALUE = XXh
7
0
Y INDEX REGISTER
RESET VALUE = XXh
15
PCH
8 7
PCL
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1 1 1 H I
0
N Z C
CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X
15
8 7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
14/108
1
ST7LITEUSx
CPU REGISTERS (cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Reset Value: 111x1xxx
7
1
0
1
1
H
I
N
Z
because the I bit is set by hardware at the start of
the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the current interrupt routine.
C
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Bit 4 = H Half carry
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 2 = N Negative
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7th
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(that is, the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 3 = I Interrupt mask
This bit is set by hardware when entering in interrupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptible
Bit 0 = C Carry/borrow
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
15/108
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ST7LITEUSx
CPU REGISTERS (Cont’d)
Stack Pointer (SP)
Read/Write
Reset Value: 00 FFh
15
0
8
0
0
0
0
0
0
7
1
0
0
1
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 8).
Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP5 to SP0 bits are set) which is the stack
higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously
stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 8.
– When an interrupt is received, the SP is decremented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 8. . Stack Manipulation Example
CALL
Subroutine
PUSH Y
Interrupt
event
POP Y
RET
or RSP
IRET
@ 00C0h
SP
SP
CC
A
1
CC
A
X
X
X
PCH
PCH
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PCL
PCL
PCL
PCL
PCL
Stack Higher Address = 00FFh
Stack Lower Address = 00C0h
16/108
SP
PCH
SP
@ 00FFh
Y
CC
A
SP
SP
ST7LITEUSx
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and reducing the number of external components.
Main features
■ Clock Management
– 8 MHz internal RC oscillator (enabled by option byte)
– External Clock Input (enabled by option byte)
■ Reset Sequence Manager (RSM)
■ System Integrity Management (SI)
– Main supply Low voltage detection (LVD) with
reset generation (enabled by option byte)
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply
6.1 INTERNAL RC OSCILLATOR ADJUSTMENT
The ST7 contains an internal RC oscillator with a
specific accuracy for a given device, temperature
and voltage. It can be selected as the start up
clock through the CKSEL[1:0] option bits (see section 14.1 on page 95). It must be calibrated to obtain the frequency required in the application. This
is done by software writing a 10-bit calibration value in the RCCR (RC Control Register) and in the
bits [6:5] in the SICSR (SI Control Status Register).
Whenever the microcontroller is reset, the RCCR
returns to its default value (FFh), i.e. each time the
device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are
stored in Flash memory for 3.3 and 5V VDD supply
voltages at 25°C, as shown in the following table.
RCCR
RCCRH0
RCCRL0
RCCRH1
RCCRL1
Conditions
VDD=5V
TA=25°C
fRC=8MHz
VDD=3.3V
TA=25°C
fRC=8MHz
ST7LITEUS2/
ST7LITEUS5
Address
DEE0h 1) (CR[9:2] bits)
DEE1h 1) (CR[1:0] bits)
DEE2h 1) (CR[9:2] bits)
DEE3h 1) (CR[1:0] bits)
1. DEE0h, DEE1h, DEE2h and DEE3h are located
in a reserved area but are special bytes containing
also the RC calibration values which are read-accessible only in user mode. If all the Flash space
(including the RC calibration value locations) has
been erased (after the read-out protection remov-
al), then the RC calibration values can still be obtained through these two address.
Notes:
– In ICC mode, the internal RC oscillator is forced
as a clock source, regardless of the selection in
the option byte. Refer to note 5 in section 4.4 on
page 12 for further details.
– See “ELECTRICAL CHARACTERISTICS” on
page 67. for more information on the frequency
and accuracy of the RC oscillator.
– To improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and
VSS pins as close as possible to the ST7 device.
Caution: If the voltage or temperature conditions
change in the application, the frequency may need
to be recalibrated.
Refer to application note AN2326 for information
on how to calibrate the RC frequency using an external reference signal.
The ST7ULTRALITE also contains an Auto Wake
Up RC oscillator. This RC oscillator should be enabled to enter Auto Wake-up from Halt mode.
The Auto Wake Up RC oscillator can also be configured as the startup clock through the CKSEL[1:0] option bits (see section 14.1 on page 95).
This is recommended for applications where very
low power consumption is required.
Switching from one startup clock to another can be
done in run mode as follows (see Figure 9):
Case 1: Switching from internal RC to AWU:
– 1. Set the RC/AWU bit in the CKCNTCSR register to enable the AWU RC oscillator
– 2. The RC_FLAG is cleared and the clock output
is at 1.
– 3. Wait 3 AWU RC cycles till the AWU_FLAG is
set
– 4. The switch to the AWU clock is made at the
positive edge of the AWU clock signal
– 5. Once the switch is made, the internal RC is
stopped
Case 2: Switching from AWU RC to internal RC:
– 1. Reset the RC/AWU bit to enable the internal
RC oscillator
17/108
1
ST7LITEUSx
SUPPLY, RESET AND CLOCK MANAGEMENT (Cont’d)
– 2. Using a 4-bit counter, wait until 8 internal RC
3. When the external clock is selected, the AWU
cycles have elapsed. The counter is running on
RC oscillator is always on.
internal RC clock.
Figure 9. Clock Switching
– 3. Wait till the AWU_FLAG is cleared (1AWU RC
cycle) and the RC_FLAG is set (2 RC cycles)
Internal RC Set RC/AWU
– 4. The switch to the internal RC clock is made at
AWU RC
Poll AWU_FLAG until set
the positive edge of the internal RC clock signal
– 5. Once the switch is made, the AWU RC is
stopped
Reset RC/AWU
Notes:
AWU RC
Internal RC
Poll RC_FLAG until set
1. When the internal RC is not selected, it is
stopped so as to save power consumption.
2. When the internal RC is selected, the AWU RC
is turned on by hardware when entering Auto
Wake-Up from Halt mode.
18/108
1
ST7LITEUSx
6.2 REGISTER DESCRIPTION
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
0
SMS
Bits 7:1 = Reserved, must be kept cleared.
RC CONTROL REGISTER (RCCR)
Read / Write
Reset Value: 1111 1111 (FFh)
CR9
0
CR8
CR7
CR6
CR5
CR4
CR3
7
0
0
CR1 CR0
0
0
LVDR
F
AVD
F
AVDI
E
Bit 7 = Reserved, must be kept cleared.
Bit 0 = SMS Slow Mode select
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the input
clock fOSC or fOSC/32.
0: Normal mode (fCPU = fOSC
1: Slow mode (fCPU = fOSC/32)
7
SYSTEM INTEGRITY (SI) CONTROL/STATUS
REGISTER (SICSR)
Read/Write
Reset Value: 0000 0x00 (0xh)
Bits 6:5 = CR[1:0] RC Oscillator Frequency Adjustment bits
These bits, as well as CR[9:2] bits in the RCCR
register must be written immediately after reset to
adjust the RC oscillator frequency and to obtain
the required accuracy. Refer to section 6.1 on
page 17.
Bits 4:3 = Reserved, must be kept cleared.
Bits 2:0 = System Integrity bits. Refer to Section
7.4 SYSTEM INTEGRITY MANAGEMENT (SI).
CR2
Bits 7:0 = CR[9:2] RC Oscillator Frequency Adjustment Bits
These bits, as well as CR[1:0] bits in the SICSR
register must be written immediately after reset to
adjust the RC oscillator frequency and to obtain
the required accuracy. The application can store
the correct value for each voltage range in Flash
memory and write it to this register at start-up.
00h = maximum available frequency
FFh = lowest available frequency
Note: To tune the oscillator, write a series of different values in the register until the correct frequency is reached. The fastest method is to use a dichotomy starting with 80h.
19/108
1
ST7LITEUSx
REGISTER DESCRIPTION (Cont’d)
CLOCK CONTROLLER CONTROL/STATUS
REGISTER (CKCNTCSR)
Read/Write
Reset Value: 0000 1001 (09h)
AVD THRESHOLD SELECTION REGISTER
(AVDTHCR)
Read/Write
Reset Value: 0000 0011 (03h)
7
7
0
0
0
0
CK1 CK0
0
0
0
0
0
0
AWU_
FLAG
RC_
FLAG
RC/
AWU
0
AVD1 AVD0
Bits 7:4 = Reserved, must be kept cleared.
Bit 7 = Reserved, must be kept cleared.
Bits 6:5 = CK[1:0] internal RC Prescaler Selection
These bits are set by software and cleared by
hardware after a reset. These bits select the prescaler of the internal RC oscillator. See Figure 10
on page 21 and the following table and note:
Bit 3 = AWU_FLAG AWU Selection
This bit is set and cleared by hardware
0: No switch from AWU to RC requested
1: AWU clock activated and temporization completed
Table 4. Internal RC Prescaler Selection bits
CK1 CK0
fOSC
0
0
fRC
0
1
fRC/2
1
0
fRC/4
1
1
fRC/8
Bit 2 = RC_FLAG RC Selection
This bit is set and cleared by hardware
0: No switch from RC to AWU requested
1: RC clock activated and temporization completed
Note: If the internal RC is used with a supply operating range below 3.3V, a division ratio of at least 2
must be enabled in the RC prescaler.
Bits 4:2 = Reserved, must be kept cleared.
Bits 1:0 = AVD Threshold Selection bits. Refer to
Section 7.4 SYSTEM INTEGRITY MANAGEMENT (SI).
Bit 1 = Reserved, must be kept cleared.
Bit 0 = RC/AWU RC/AWU Selection
0: RC enabled
1: AWU enabled (default value)
Table 5. Clock Register Map and Reset Values
Address
(Hex.)
0038h
0039h
003Ah
003Eh
003Fh
20/108
1
Register
Label
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
SMS
0
CR9
1
CR8
1
CR7
1
CR6
1
CR5
1
CR4
1
CR3
1
CR2
1
0
CR1
CR0
0
0
LVDRF
x
AVDF
0
AVDIE
0
0
CK1
0
CK0
0
0
0
0
AVD1
1
AVD2
1
0
0
0
0
0
RC/AWU
1
MCCSR
Reset Value
RCCR
Reset Value
SICSR
Reset Value
AVDTHCR
Reset Value
CKCNTCSR
Reset Value
AWU_FLAG RC_FLAG
1
0
ST7LITEUSx
SUPPLY, RESET AND CLOCK MANAGEMENT (Cont’d)
Figure 10. Clock Management Block Diagram
CR9
CR8
CR7
CR6
CR5
CR1
CR4
CR3
CR2
RCCR
SICSR
CR0
Tunable
internal RC Oscillator
RC/AWU CKCNTCSR
Clock
Controller
8MHz(fRC)
Prescaler
AWU
RC
CLKIN
fCLKIN
RC OSC
Ext Clock
8MHz
4MHz
2MHz
1MHz
33kHz
CKSEL[1:0]
Option bits
/2
DIVIDER
13-BIT
LITE TIMER COUNTER
fOSC
fOSC
fOSC
AWU CK
/32 DIVIDER
fOSC/32
0
1
fLTIMER
(1ms timebase @ 8 MHz fOSC)
fCPU
TO CPU AND
PERIPHERALS
SMS MCCSR
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6.3 RESET SEQUENCE MANAGER (RSM)
6.3.1 Introduction
The reset sequence manager includes three RESET sources as shown in Figure 12:
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Refer to Figure 12.
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 11:
Active Phase depending on the RESET source
■ 64 CPU clock cycle delay
■ RESET vector fetch
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed. For this reason, it is recommended to keep the RESET pin in low state until
programming mode is entered, in order to avoid
unwanted behavior.
The 64 CPU clock cycle delay allows the oscillator
to stabilise and ensures that recovery has taken
place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
■
Figure 11. RESET Sequence Phases
RESET
Active Phase
INTERNAL RESET
64 CLOCK CYCLES
FETCH
VECTOR
Figure 12. Reset Block Diagram
VDD
RON
RESET
INTERNAL
RESET
FILTER
WATCHDOG RESET
PULSE
GENERATOR
ILLEGAL OPCODE RESET 1)
LVD RESET
Note 1: See “Illegal Opcode Reset” on page 64. for more details on illegal opcode reset conditions.
22/108
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ST7LITEUSx
RESET SEQUENCE MANAGER (Cont’d)
6.3.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated RON weak pull-up resistor.
This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
A RESET signal originating from an external
source must have a duration of at least th(RSTL)in in
order to be recognized (see Figure 13). This detection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteristics section.
6.3.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until VDD is over the minimum
level specified for the selected fCLKIN frequency.
A proper reset signal for a slow rising VDD supply
can generally be provided by an external RC network connected to the RESET pin.
6.3.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
■ Power-On RESET
■ Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when VDD<VIT+ (rising edge) or
VDD<VIT- (falling edge) as shown in Figure 13.
The LVD filters spikes on VDD larger than tg(VDD) to
avoid parasitic resets.
6.3.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 13.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least tw(RSTL)out.
Figure 13. RESET Sequences
VDD
VIT+(LVD)
VIT-(LVD)
LVD
RESET
RUN
EXTERNAL
RESET
RUN
ACTIVE PHASE
ACTIVE
PHASE
WATCHDOG
RESET
RUN
ACTIVE
PHASE
RUN
tw(RSTL)out
th(RSTL)in
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (64 TCPU)
VECTOR FETCH
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ST7LITEUSx
6.4 REGISTER DESCRIPTION
MULTIPLEXED IO RESET CONTROL REGISTER 1 (MUXCR1)
Read / Write once only
Reset Value: 0000 0000 (00h)
7
0
MIR1 MIR1 MIR1 MIR1 MIR1 MIR1 MIR
5
4
3
2
1
0
9
MIR
8
MULTIPLEXED IO RESET CONTROL REGISTER 0 (MUXCR0)
Read / Write once only
Reset Value: 0000 0000 (00h)
7
0
MIR7 MIR6 MIR5 MIR4 MIR3 MIR2 MIR1 MIR0
Bits 15:0 = MIR[15:0]
This 16-bit register is read/write by software but
can be written only once between two reset
events. It is cleared by hardware after a reset;
When both MUXCR0 and MUXCR1 registers are
at 00h, the multiplexed PA3/RESET pin will act as
RESET. To configure this pin as output (Port A3),
write 55h to MUXCR0 and AAh to MUXCR1.
These registers are one-time writable only.
– To configure PA3 as general purpose output:
After power-on / reset, the application program
has to configure the I/O port by writing to these
registers as described above. Once the pin is
configured as an I/O output, it cannot be
changed back to a reset pin by the application
code.
– To configure PA3 as RESET:
An internally generated reset (such as POR,
LVD, WDG, illegal opcode) will clear the two registers and the pin will act again as a reset function. Otherwise, a power-down is required to put
the pin back in reset configuration.
Table 6. Multiplexed IO Register Map and Reset Values
Address
(Hex.)
0047h
0048h
24/108
1
Register
Label
MUXCR0
Reset Value
MUXCR1
Reset Value
7
6
5
4
3
2
1
0
MIR7
0
MIR6
0
MIR5
0
MIR4
0
MIR3
0
MIR2
0
MIR1
0
MIR0
0
MIR15
0
MIR14
0
MIR13
0
MIR12
0
MIR11
0
MIR10
0
MIR9
0
MIR8
0
ST7LITEUSx
7 INTERRUPTS
The ST7 core may be interrupted by one of two different methods: Maskable hardware interrupts as
listed in Table 7, “Interrupt Mapping,” on page 26
and a non-maskable software interrupt (TRAP).
The Interrupt processing flowchart is shown in Figure 14.
The maskable interrupts must be enabled by
clearing the I bit in order to be serviced. However,
disabled interrupts may be latched and processed
when they are enabled (see external interrupts
subsection).
Note: After reset, all interrupts are disabled.
When an interrupt has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– The I bit of the CC register is set to prevent additional interrupts.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping table for vector addresses).
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I bit is cleared and the main program resumes.
Priority Management
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine.
In the case when several interrupts are simultaneously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Mapping table).
Interrupts and Low Power Mode
All interrupts allow the processor to leave the
WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to
leave the HALT low power mode (refer to the “Exit
from HALT” column in the Interrupt Mapping table).
7.1 NON MASKABLE SOFTWARE INTERRUPT
This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit.
It is serviced according to the flowchart in Figure
14.
7.2 EXTERNAL INTERRUPTS
External interrupt vectors can be loaded into the
PC register if the corresponding external interrupt
occurred and if the I bit is cleared. These interrupts
allow the processor to leave the HALT low power
mode.
The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).
An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of a NANDed source
(as described in the I/O ports section), a low level
on an I/O pin, configured as input with interrupt,
masks the interrupt request even in case of risingedge sensitivity.
7.3 PERIPHERAL INTERRUPTS
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control
register.
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Clearing an interrupt request is done by:
– Writing “0” to the corresponding bit in the status
register or
– Access to the status register while the flag is set
followed by a read or write of an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (that is, waiting for being
enabled) will therefore be lost if the clear sequence is executed.
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ST7LITEUSx
INTERRUPTS (cont’d)
Figure 14. Interrupt Processing Flowchart
FROM RESET
I BIT SET?
N
N
Y
INTERRUPT
PENDING?
Y
FETCH NEXT INSTRUCTION
N
IRET?
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTOR
Y
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Table 7. Interrupt Mapping
N°
Source
Block
RESET
Description
Reset
TRAP
Software Interrupt
0
AWU
Auto Wakeup Interrupt
1
ei0
External Interrupt 0
2
ei1
External Interrupt 1
3
ei2
External Interrupt 2
4
5
6
2)
7
8
ei4
2)
SI
AT TIMER
9
10
11
LITE TIMER
Priority
Order
N/A
Highest
Priority
AWUCSR
Address
Vector
yes
FFFEh-FFFFh
no
FFFCh-FFFDh
yes 1)
FFFAh-FFFBh
yes
2)
AVD interrupt
FFF6h-FFF7h
FFF4h-FFF5h
N/A
External Interrupt 3
External Interrupt 4
Exit
from
HALT
FFF8h-FFF9h
Not used
ei3
Register
Label
no
FFF2h-FFF3h
yes
FFF0h-FFF1h
no
2)
FFEEh-FFEFh
SICSR
no
FFECh-FFEDh
PWMxCSR
or ATCSR
no
FFEAh-FFEBh
AT TIMER Overflow Interrupt
ATCSR
yes 3)
FFE8h-FFE9h
LITE TIMER Input Capture Interrupt
LTCSR
no
FFE6h-FFE7h
LITE TIMER RTC1 Interrupt
LTCSR
yes 3)
FFE4h-FFE5h
no
FFE2h-FFE3h
no
FFE0h-FFE1h
AT TIMER Output Compare Interrupt
12
Not used
13
Not used
Lowest
Priority
Notes:
1. This interrupt exits the MCU from “Auto Wake-up from HALT” mode only.
2. This interrupt exits the MCU from “WAIT” and “ACTIVE-HALT” modes only. Moreover, IS4[1:0] = 01 is the only safe
configuration to avoid spurious interrupt in HALT and AWUFH mode
3. These interrupts exit the MCU from “ACTIVE-HALT” mode only.
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ST7LITEUSx
INTERRUPTS (Cont’d)
EXTERNAL INTERRUPT CONTROL REGISTER
1 (EICR1)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
IS21
IS20
IS11
IS10
IS01
EXTERNAL INTERRUPT CONTROL REGISTER
2 (EICR2)
Read/Write
Reset Value: 0000 0000 (00h)
0
7
IS00
0
0
0
0
0
IS41
IS40
IS31
IS30
Bits 7:6 = Reserved
Bits 7:4 = Reserved
Bits 5:4 = IS2[1:0] ei2 sensitivity
These bits define the interrupt sensitivity for ei2
according to Table 8.
Bits 3:2 = IS4[1:0] ei4 sensitivity
These bits define the interrupt sensitivity for ei1
according to Table 8.
Bits 3:2 = IS1[1:0] ei1 sensitivity
These bits define the interrupt sensitivity for ei1
according to Table 8.
Bits 1:0 = IS3[1:0] ei3 sensitivity
These bits define the interrupt sensitivity for ei0
according to Table 8.
Notes:
1. These 8 bits can be written only when the I bit in
the CC register is set.
2. Changing the sensitivity of a particular external
interrupt clears this pending interrupt. This can be
used to clear unwanted pending interrupts. Refer
to section “External interrupt function” on page 41.
3. IS4[1:0] = 01 is the only safe configuration to
avoid spurious interrupt in HALT and AWUFH
modes.
Bits 1:0 = IS0[1:0] ei0 sensitivity
These bits define the interrupt sensitivity for ei0
according to Table 8.
Notes:
1. These 8 bits can be written only when the I bit in
the CC register is set.
2. Changing the sensitivity of a particular external
interrupt clears this pending interrupt. This can be
used to clear unwanted pending interrupts. Refer
to section “External interrupt function” on page 41.
Table 8. Interrupt Sensitivity Bits
ISx1 ISx0
External Interrupt Sensitivity
0
0
Falling edge & low level
0
1
Rising edge only
1
0
Falling edge only
1
1
Rising and falling edge
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ST7LITEUSx
7.4 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by
the SICSR register.
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Refer to “Illegal Opcode Reset” on page 64 for further
details.
7.4.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is
below a VIT-(LVD) reference value. This means that
it secures the power-up as well as the power-down
keeping the ST7 in reset.
The VIT-(LVD) reference value for a voltage drop is
lower than the VIT+(LVD) reference value for poweron in order to avoid a parasitic reset when the
MCU starts running and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when
VDD is below:
– VIT+(LVD) when VDD is rising
– VIT-(LVD) when VDD is falling
The LVD function is illustrated in Figure 15.
The voltage threshold can be configured by option
byte to be low, medium or high. See section 14.1
on page 95.
Provided the minimum VDD value (guaranteed for
the oscillator frequency) is above VIT-(LVD), the
MCU can only be in two modes:
– under full software control
– in static safe reset
In these conditions, secure operation is always ensured for the application without the need for external reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Notes:
Use of LVD with capacitive power supply: with this
type of power supply, if power cuts occur in the application, it is recommended to pull VDD down to
0V to ensure optimum restart conditions. Refer to
circuit example in Figure 63 on page 87 and note
4.
The LVD is an optional function which can be selected by option byte. See section 14.1 on page
95. It allows the device to be used without any external RESET circuitry. If the LVD is disabled, an
external circuitry must be used to ensure a proper
power-on reset.
It is recommended to make sure that the VDD supply voltage rises monotonously when the device is
exiting from Reset, to ensure the application functions properly.
Make sure the right combination of LVD and AVD
thresholds is used as LVD and AVD levels are not
correlated. Refer to section 12.3.2 on page 70 and
section 12.3.3 on page 70 for more details.
Caution: If an LVD reset occurs after a watchdog
reset has occurred, the LVD will take priority and
will clear the watchdog flag.
Figure 15. Low Voltage Detector vs Reset
VDD
Vhys
VIT+(LVD)
VIT-(LVD)
RESET
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ST7LITEUSx
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
Figure 16. Reset and Supply Management Block Diagram
WATCHDOG
STATUS FLAG
TIMER (WDG)
SYSTEM INTEGRITY MANAGEMENT
RESET SEQUENCE
RESET
MANAGER
(RSM)
AVD Interrupt Request
SICSR
0
7
1
1
0
0
LVD AVD AVD
RF F IE
0
LOW VOLTAGE
VSS
DETECTOR
VDD
(LVD)
AUXILIARY VOLTAGE
DETECTOR
(AVD)
7.4.2 Auxiliary Voltage Detector (AVD)
The Voltage Detector function (AVD) is based on
an analog comparison between a VIT-(AVD) and
VIT+(AVD) reference value and the VDD main supply voltage (VAVD). The VIT-(AVD) reference value
for falling voltage is lower than the VIT+(AVD) reference value for rising voltage in order to avoid parasitic detection (hysteresis).
The output of the AVD comparator is directly readable by the application software through a real
time status bit (AVDF) in the SICSR register. This
bit is read only.
7.4.2.1 Monitoring the VDD Main Supply.
The AVD threshold is selected by the AVD[1:0]
bits in the AVDTHCR register.
If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the VIT+(AVD) or
VIT-(AVD) threshold (AVDF bit is set).
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
down safely before the LVD resets the microcontroller. See Figure 17.
The interrupt on the rising edge is used to inform
the application that the VDD warning state is over
Note: Make sure the right combination of LVD and
AVD thresholds is used as LVD and AVD levels
are not correlated. Refer to section 12.3.2 on page
70 and section 12.3.3 on page 70 for more details.
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ST7LITEUSx
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
Figure 17. Using the AVD to Monitor VDD
VDD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
Vhyst
VIT+(AVD)
VIT-(AVD)
VIT+(LVD)
VIT-(LVD)
AVDF bit
0
1
1
RESET
0
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT Cleared by
reset
INTERRUPT Cleared by
hardware
LVD RESET
7.4.3 Low Power Modes
Mode
WAIT
HALT
Description
No effect on SI. AVD interrupts cause the
device to exit from Wait mode.
The SICSR register is frozen.
The AVD remains active but the AVD interrupt cannot be used to exit from Halt mode.
7.4.3.1 Interrupts
The AVD interrupt event generates an interrupt if
the corresponding Enable Control Bit (AVDIE) is
set and the interrupt mask in the CC register is reset (RIM instruction).
Interrupt Event
AVD event
30/108
1
Enable
Event
Control
Flag
Bit
AVDF AVDIE
Exit
from
Wait
Yes
Exit
from
Halt
No
ST7LITEUSx
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
7.4.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS
REGISTER (SICSR)
Read/Write
Reset Value: 0000 0x00 (0xh)
7
0
0
CR1 CR0
0
0
LVDRF AVDF AVDIE
Bit 7 = Reserved, must be kept cleared.
Bit 0 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag is
set. The pending interrupt information is automatically cleared when software enters the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
AVD THRESHOLD SELECTION REGISTER
(AVDTHCR)
Read/Write
Reset Value: 0000 0011 (03h)
7
Bits 6:5 = CR[1:0] RC Oscillator Frequency Adjustment bits
These bits, as well as CR[9:2] bits in the RCCR
register must be written immediately after reset to
adjust the RC oscillator frequency and to obtain
the required accuracy. Refer to section 6.1 on
page 17.
Bits 4:3 = Reserved, must be kept cleared.
Bit 2 = LVDRF LVD reset flag
This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared when read. See WDGRF flag description in Section 10.1 for more details. When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Note:
If the selected clock source is one of the two internal ones, and if VDD remains below the selected
LVD threshold during less than TAWU (33us typ.),
the LVDRF flag cannot be set even if the device is
reset by the LVD.
If the selected clock source is the external clock
(CLKIN), the flag is never set if the reset occurs
during Halt mode. In run mode the flag is set only
if fCLKIN is greater than 10MHz.
Bit 1 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is generated when the AVDF bit is set. Refer to Figure
17 for additional details
0: VDD over AVD threshold
1: VDD under AVD threshold
0
0
CK1 CK0
0
0
0
AVD1 AVD0
Bit 7 = Reserved, must be kept cleared.
Bits 6:5 = CK[1:0] internal RC Prescaler Selection
Refer to Section 6.1 INTERNAL RC OSCILLATOR
ADJUSTMENT on page 17.
Bits 4:2 = Reserved, must be kept cleared.
Bits 1:0 = AVD[1:0] AVD Threshold Selection
These bits are set and cleared by software and set
by hardware after a reset. They select the AVD
threshold.
Table 9. AVD Threshold Selection bits
AVD1 AVD0
Functionality
0
0
Low
0
1
Medium
1
0
High
1
1
AVD off
Application notes
The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
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REGISTER DESCRIPTION (Cont’d)
Table 10. System Integrity Register Map and Reset Values
Address
(Hex.)
003Ah
003Eh
32/108
1
Register
Label
SICSR
Reset Value
AVDTHCR
Reset Value
7
6
5
4
3
2
1
0
0
1
1
0
0
LVDRF
x
AVDF
0
AVDIE
0
0
CK1
0
CK0
0
0
0
0
AVD1
1
AVD2
1
ST7LITEUSx
8 POWER SAVING MODES
8.1 INTRODUCTION
To give a large measure of flexibility to the application in terms of power consumption, four main
power saving modes are implemented in the ST7
(see Figure 18):
■ Slow
■ Wait (and Slow-Wait)
■ Active Halt
■ Auto Wake up From Halt (AWUFH)
■ Halt
After a RESET the normal operating mode is selected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency (fOSC).
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
Figure 18. Power Saving Mode Transitions
8.2 SLOW MODE
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (fCPU) to
the available supply voltage.
SLOW mode is controlled by the SMS bit in the
MCCSR register which enables or disables Slow
mode.
In this mode, the oscillator frequency is divided by
32. The CPU and peripherals are clocked at this
lower frequency.
Notes:
SLOW-WAIT mode is activated when entering
WAIT mode while the device is already in SLOW
mode.
Figure 19. SLOW Mode Clock Transition
fOSC/32
fOSC
fCPU
High
fOSC
RUN
SMS
SLOW
NORMAL RUN MODE
REQUEST
WAIT
SLOW WAIT
ACTIVE HALT
HALT
Low
POWER CONSUMPTION
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POWER SAVING MODES (Cont’d)
8.3 WAIT MODE
WAIT mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the
‘WFI’ instruction.
All peripherals remain active. During WAIT mode,
the I bit of the CC register is cleared, to enable all
interrupts. All other registers and memory remain
unchanged. The MCU remains in WAIT mode until
an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of
the interrupt or Reset service routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Refer to Figure 20.
Figure 20. WAIT Mode Flow-chart
WFI INSTRUCTION
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
ON
OFF
0
N
RESET
Y
N
INTERRUPT
Y
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
OFF
ON
0
64 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
ON
ON
X 1)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
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POWER SAVING MODES (Cont’d)
8.4 ACTIVE-HALT AND HALT MODES
ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the LTCSR/ATCSR register status as shown in the following table:.
ATCSR
LTCSR
ATCSR ATCSR
OVFIE
TBIE bit
CK1 bit CK0 bit
bit
0
x
x
0
0
0
x
x
0
1
1
1
1
x
x
x
x
1
0
1
Meaning
ACTIVE-HALT
mode disabled
ACTIVE-HALT
mode enabled
8.4.1 ACTIVE-HALT MODE
ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ instruction when active halt mode is enabled.
The MCU can exit ACTIVE-HALT mode on reception of a Lite Timer / AT Timer interrupt or a RESET.
– When exiting ACTIVE-HALT mode by means of
a RESET, a 64 CPU cycle delay occurs. After the
start up delay, the CPU resumes operation by
fetching the reset vector which woke it up (see
Figure 22).
– When exiting ACTIVE-HALT mode by means of
an interrupt, the CPU immediately resumes operation by servicing the interrupt vector which woke
it up (see Figure 22).
When entering ACTIVE-HALT mode, the I bit in
the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
In ACTIVE-HALT mode, only the main oscillator
and the selected timer counter (LT/AT) are running
to keep a wake-up time base. All other peripherals
are not clocked except those which get their clock
supply from another clock generator (such as external or auxiliary oscillator).
Caution: As soon as ACTIVE-HALT is enabled,
executing a HALT instruction while the Watchdog
is active does not generate a RESET if the
WDGHALT bit is reset.
This means that the device cannot spend more
than a defined delay in this power saving mode.
Figure 21. ACTIVE-HALT Timing Overview
RUN
ACTIVE
HALT
64 CPU
CYCLE DELAY 1)
RESET
OR
HALT
INTERRUPT
INSTRUCTION
[Active Halt Enabled]
RUN
FETCH
VECTOR
Figure 22. ACTIVE-HALT Mode Flow-chart
HALT INSTRUCTION
(Active Halt enabled)
OSCILLATOR
ON
PERIPHERALS 2) OFF
CPU
OFF
I BIT
0
N
RESET
N
Y
INTERRUPT 3)
Y
OSCILLATOR
ON
PERIPHERALS 2) OFF
CPU
ON
I BIT
X 4)
64 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
I BITS
ON
ON
ON
X 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. This delay occurs only if the MCU exits ACTIVEHALT mode by means of a RESET.
2. Peripherals clocked with an external clock
source can still be active.
3. Only the Lite Timer RTC and AT Timer interrupts
can exit the MCU from ACTIVE-HALT mode.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
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POWER SAVING MODES (Cont’d)
8.4.2 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when active halt mode is disabled.
The MCU can exit HALT mode on reception of either a specific interrupt (see Table 7, “Interrupt
Mapping,” on page 26) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the main oscillator is immediately turned on and
the 64 CPU cycle delay is used to stabilize it. After
the start up delay, the CPU resumes operation by
servicing the interrupt or by fetching the reset vector which woke it up (see Figure 24).
When entering HALT mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes immediately.
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, including the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscillator).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” option bit of the option byte. The HALT instruction
when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see section 14.1 on page 95 for more details).
Figure 23. HALT Timing Overview
RUN
HALT
HALT
INSTRUCTION
[Active Halt disabled]
64 CPU CYCLE
DELAY
RUN
RESET
OR
INTERRUPT
FETCH
VECTOR
Note:
1. A reset pulse of at least 42µs must be applied
when exiting from HALT mode.
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Figure 24. HALT Mode Flow-chart
HALT INSTRUCTION
(Active Halt disabled)
ENABLE
WDGHALT 1)
WATCHDOG
0
DISABLE
1
WATCHDOG
RESET
OSCILLATOR
OFF
PERIPHERALS 2) OFF
CPU
OFF
I BIT
0
N
RESET
N
Y
INTERRUPT 3)
Y
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
OFF
ON
X 4)
64 CPU CLOCK CYCLE
DELAY 5)
OSCILLATOR
PERIPHERALS
CPU
I BITS
ON
ON
ON
X 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Refer to Table 7, “Interrupt Mapping,” on page 26 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
5. The CPU clock must be switched to 1MHz
(RC/8) or AWU RC before entering HALT mode.
ST7LITEUSx
POWER SAVING MODES (Cont’d)
8.4.2.1 HALT Mode Recommendations
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configured due to external interference or by an unforeseen logical
condition.
– For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure.
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memory. For example, avoid defining a constant in
ROM with the value 0x8E.
– As the HALT instruction clears the I bit in the CC
register to allow interrupts, the user may choose
to clear all pending interrupt bits before executing the HALT instruction. This avoids entering
other peripheral interrupt routines after executing
the external interrupt routine corresponding to
the wake-up event (reset or external interrupt).
8.5 AUTO WAKE UP FROM HALT MODE
Auto Wake Up From Halt (AWUFH) mode is similar to Halt mode with the addition of a specific internal RC oscillator for wake-up (Auto Wake-Up
from Halt oscillator) which replaces the main clock
which was active before entering HALT mode.
Compared to ACTIVE-HALT mode, AWUFH has
lower power consumption (the main clock is not
kept running), but there is no accurate realtime
clock available.
It is entered by executing the HALT instruction
when the AWUEN bit in the AWUCSR register has
been set.
Figure 25. AWUFH Mode Block Diagram
AWU RC
oscillator
fAWU_RC
/64
divider
to 8-bit Timer input capture
AWUFH
prescaler/1 .. 255
AWUFH
interrupt
(ei0 source)
As soon as HALT mode is entered, and if the
AWUEN bit has been set in the AWUCSR register,
the AWU RC oscillator provides a clock signal
(fAWU_RC). Its frequency is divided by a fixed divider and a programmable prescaler controlled by the
AWUPR register. The output of this prescaler provides the delay time. When the delay has elapsed,
the following actions are performed:
– the AWUF flag is set by hardware,
– an interrupt wakes-up the MCU from Halt mode,
– the main oscillator is immediately turned on and
the 64 CPU cycle delay is used to stabilize it.
After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The AWU
flag and its associated interrupt are cleared by
software reading the AWUCSR register.
To compensate for any frequency dispersion of
the AWU RC oscillator, it can be calibrated by
measuring the clock frequency fAWU_RC and then
calculating the right prescaler value. Measurement
mode is enabled by setting the AWUM bit in the
AWUCSR register in Run mode. This connects
fAWU_RC to the input capture of the 8-bit lite timer,
allowing the fAWU_RC to be measured using the
main oscillator clock as a reference timebase.
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POWER SAVING MODES (Cont’d)
Similarities with Halt mode
The following AWUFH mode behaviour is the
same as normal Halt mode:
– The MCU can exit AWUFH mode by means of
any interrupt with exit from Halt capability or a reset (see Section 8.4 ACTIVE-HALT AND HALT
MODES).
– When entering AWUFH mode, the I bit in the CC
register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes
up immediately.
– In AWUFH mode, the main oscillator is turned off
causing all internal processing to be stopped, including the operation of the on-chip peripherals.
None of the peripherals are clocked except those
which get their clock supply from another clock
generator (such as an external or auxiliary oscillator like the AWU oscillator).
– The compatibility of watchdog operation with
AWUFH mode is configured by the WDGHALT
option bit in the option byte. Depending on this
setting, the HALT instruction when executed
while the watchdog system is enabled, can generate a watchdog RESET.
Figure 26. AWUF Halt Timing Diagram
tAWU
RUN MODE
HALT MODE
64 tCPU
RUN MODE
fCPU
fAWU_RC
Clear
by software
AWUFH interrupt
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Figure 27. AWUFH Mode Flow-chart
HALT INSTRUCTION
(Active-Halt disabled)
(AWUCSR.AWUEN=1)
ENABLE
WDGHALT 1)
WATCHDOG
0
DISABLE
1
WATCHDOG
RESET
AWU RC OSC
ON
MAIN OSC
OFF
PERIPHERALS 2) OFF
CPU
OFF
I[1:0] BITS
10
Notes:
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from HALT mode (such
as external interrupt). Refer to Table 7, “Interrupt
Mapping,” on page 26 for more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
N
RESET
N
Y
INTERRUPT 3)
Y
AWU RC OSC
OFF
MAIN OSC
ON
PERIPHERALS OFF
CPU
ON
I[1:0] BITS
XX 4)
64 CPU CLOCK
CYCLE DELAY
AWU RC OSC
OFF
MAIN OSC
ON
PERIPHERALS ON
CPU
ON
I[1:0] BITS
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
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POWER SAVING MODES (Cont’d)
8.5.1 Register Description
AWUFH PRESCALER REGISTER (AWUPR)
Read/Write
Reset Value: 1111 1111 (FFh)
AWUFH CONTROL/STATUS REGISTER
(AWUCSR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
7
0
0
0
0
0
AWU AWU AWU
F
M
EN
Bits 7:3 = Reserved.
Bit 2= AWUF Auto Wake Up Flag
This bit is set by hardware when the AWU module
generates an interrupt and cleared by software on
reading AWUCSR. Writing to this bit does not
change its value.
0: No AWU interrupt occurred
1: AWU interrupt occurred
Bit 1= AWUM Auto Wake Up Measurement
This bit enables the AWU RC oscillator and connects its output to the input capture of the 8-bit Lite
timer. This allows the timer to be used to measure
the AWU RC oscillator dispersion and then compensate this dispersion by providing the right value
in the AWUPRE register.
0: Measurement disabled
1: Measurement enabled
Bit 0 = AWUEN Auto Wake Up From Halt Enabled
This bit enables the Auto Wake Up From Halt feature: once HALT mode is entered, the AWUFH
wakes up the microcontroller after a time delay dependent on the AWU prescaler value. It is set and
cleared by software.
0: AWUFH (Auto Wake Up From Halt) mode disabled
1: AWUFH (Auto Wake Up From Halt) mode enabled
Note: whatever the clock source, this bit should be
set to enable the AWUFH mode once the HALT instruction has been executed.
0
AWU AWU AWU AWU AWU AWU AWU AWU
PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0
Bits 7:0= AWUPR[7:0] Auto Wake Up Prescaler
These 8 bits define the AWUPR Dividing factor (as
explained below:
AWUPR[7:0]
Dividing factor
00h
Forbidden
01h
1
...
...
FEh
254
FFh
255
In AWU mode, the period that the MCU stays in
Halt Mode (tAWU in Figure 26 on page 38) is defined by
t
AWU
1
= 64 × AWUPR × -------------------------- + t
RCSTRT
f
AWURC
This prescaler register can be programmed to
modify the time that the MCU stays in Halt mode
before waking up automatically.
Note: If 00h is written to AWUPR, depending on
the product, an interrupt is generated immediately
after a HALT instruction, or the AWUPR remains
unchanged.
Table 11. AWU Register Map and Reset Values
Address
(Hex.)
0049h
004Ah
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1
Register
7
6
5
4
3
2
1
0
Label
AWUPR
AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
Reset Value
1
1
1
1
1
1
1
1
AWUCSR
0
0
0
0
0
AWUF
AWUM
AWUEN
Reset Value
ST7LITEUSx
9 I/O PORTS
9.1 INTRODUCTION
The I/O port offers different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
– external interrupt generation
– alternate signal input/output for the on-chip peripherals.
An I/O port contains up to 6 pins. Each pin (except
PA3/RESET) can be programmed independently
as digital input (with or without interrupt generation) or digital output.
9.2 FUNCTIONAL DESCRIPTION
Each port has 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
The following description takes into account the
OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is
shown in Figure 28
9.2.1 Input Modes
The input configuration is selected by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Different input modes can be selected by software
through the OR register.
Notes:
1. Writing the DR register modifies the latch value
but does not affect the pin status.
2. PA3 cannot be configured as input.
9.2.1.1 External interrupt function
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate an external interrupt request to the CPU.
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
programmable using the sensitivity bits in the
EICR register.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description
and interrupt section). If several I/O interrupt pins
on the same interrupt vector are selected simultaneously, they are logically combined. For this reason if one of the interrupt pins is tied low, it may
mask the others.
External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Changing the sensitivity
of a particular external interrupt clears this pending
interrupt. This can be used to clear unwanted
pending interrupts.
Spurious interrupts
When enabling/disabling an external interrupt by
setting/resetting the related OR register bit, a spurious interrupt is generated if the pin level is low
and its edge sensitivity includes falling/rising edge.
This is due to the edge detector input which is
switched to '1' when the external interrupt is disabled by the OR register.
To avoid this unwanted interrupt, a "safe" edge
sensitivity (rising edge for enabling and falling
edge for disabling) has to be selected before
changing the OR register bit and configuring the
appropriate sensitivity again.
Caution: In case a pin level change occurs during
these operations (asynchronous signal input), as
interrupts are generated according to the current
sensitivity, it is advised to disable all interrupts before and to reenable them after the complete previous sequence in order to avoid an external interrupt occurring on the unwanted edge.
This corresponds to the following steps:
1. To enable an external interrupt:
– set the interrupt mask with the SIM instruction
(in cases where a pin level change could occur)
– select rising edge
– enable the external interrupt through the OR
register
– select the desired sensitivity if different from
rising edge
– reset the interrupt mask with the RIM instruction (in cases where a pin level change could
occur)
2. To disable an external interrupt:
– set the interrupt mask with the SIM instruction
SIM (in cases where a pin level change could
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occur)
– select falling edge
– disable the external interrupt through the OR
register
– select rising edge
9.2.2 Output Modes
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR register returns the previously stored value.
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
DR register value and output pin status:
DR
0
1
Push-pull
VSS
VDD
Open-drain
Vss
Floating
Note: When switching from input to output mode,
the DR register has to be written first to drive the
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correct level on the pin as soon as the port is configured as an output.
9.2.3 Alternate Functions
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically selected. This alternate function takes priority over the
standard I/O programming under the following
conditions:
– When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in
output mode (push-pull or open drain according
to the peripheral).
– When the signal is going to an on-chip peripheral, the I/O pin must be configured in floating input
mode. In this case, the pin state is also digitally
readable by addressing the DR register.
Notes:
– Input pull-up configuration can cause unexpected value at the input of the alternate peripheral
input.
– When an on-chip peripheral use a pin as input
and output, this pin has to be configured in input
floating mode.
ST7LITEUSx
Figure 28. I/O Port General Block Diagram
ALTERNATE
OUTPUT
REGISTER
ACCESS
1
VDD
0
P-BUFFER
(see table below)
ALTERNATE
ENABLE
PULL-UP
(see table below)
DR
VDD
DDR
PULL-UP
CONDITION
DATA BUS
OR
PAD
If implemented
OR SEL
N-BUFFER
DIODES
(see table below)
DDR SEL
DR SEL
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
EXTERNAL
INTERRUPT
SOURCE (eix)
POLARITY
SELECTION
ALTERNATE
INPUT
FROM
OTHER
BITS
Table 12. I/O Port Mode Options
Configuration Mode
Input
Output
Floating with/without Interrupt
Pull-up with/without Interrupt
Push-pull
Open Drain (logic level)
Pull-Up
P-Buffer
Off
On
Off
Off
On
Off
Diodes
to VDD
to VSS
On
On
Legend:NI - not implemented
Off - implemented not activated
On - implemented and activated
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I/O PORTS (Cont’d)
Table 13. I/O Port Configurations
Hardware Configuration
DR REGISTER ACCESS
VDD
RPU
PULL-UP
CONDITION
DR
REGISTER
PAD
W
DATA BUS
R
ALTERNATE INPUT
FROM
OTHER
PINS
INPUT 1)
INTERRUPT
CONDITION
EXTERNAL INTERRUPT
SOURCE (eix)
POLARITY
SELECTION
ANALOG INPUT
DR REGISTER ACCESS
OPEN-DRAIN OUTPUT 2)
VDD
RPU
DR
REGISTER
PAD
ALTERNATE
ENABLE
DATA BUS
ALTERNATE
OUTPUT
DR REGISTER ACCESS
VDD
PUSH-PULL OUTPUT 2)
R/W
RPU
PAD
DR
REGISTER
ALTERNATE
ENABLE
R/W
DATA BUS
ALTERNATE
OUTPUT
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
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I/O PORTS (Cont’d)
CAUTION: The alternate function must not be activated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
Analog alternate function
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected analog pin.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maximum ratings.
9.3 UNUSED I/O PINS
Unused I/O pins must be connected to fixed voltage levels. Refer to Section 12.8.
9.4 LOW POWER MODES
Mode
WAIT
HALT
Description
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
9.5 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the interrupt mask in
the CC register is not active (RIM instruction).
Enable
Event
Control
Flag
Bit
Interrupt Event
External interrupt on
selected external
event
-
DDRx
ORx
Exit
from
Wait
Exit
from
Halt
Yes
Yes
9.6 I/O PORT IMPLEMENTATION
The hardware implementation on each I/O port depends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC Input or true open drain.
Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 29. Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
Figure 29. Interrupt I/O Port State Transitions
01
00
10
11
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
XX
= DDR, OR
The I/O port register configurations are summarised in the following table:
Table 14. Port Configuration
Port
Pin name
Port A
PA0:2, PA4:5
PA3
Input (DDR=0)
OR = 0
OR = 1
floating
pull-up interrupt
-
Output (DDR=1)
OR = 0
OR = 1
open drain
push-pull
open drain
push-pull
Note: after reset, to configure PA3 as a general purpose output, the application has to program the
MUXCR0 and MUXCR1 registers. See section 6.4 on page 24
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I/O PORTS (Cont’d)
Table 15. I/O Port Register Map and Reset Values
Address
Register
Label
7
6
5
4
3
2
1
0
0000h
PADR
Reset Value
MSB
0
0
0
0
0
0
0
LSB
0
0001h
PADDR
Reset Value
MSB
0
0
0
0
1
0
0
LSB
0
0002h
PAOR
Reset Value
MSB
0
0
0
0
0
0
1
LSB
0
(Hex.)
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10 ON-CHIP PERIPHERALS
10.1 LITE TIMER (LT)
10.1.1 Introduction
■
The Lite Timer can be used for general-purpose
timing functions. It is based on a free-running 13bit upcounter with two software-selectable timebase periods, an 8-bit input capture register and
watchdog function.
10.1.2 Main Features
■ Realtime Clock
– 13-bit upcounter
– 1 ms or 2 ms timebase period (@ 8 MHz fOSC)
– Maskable timebase interrupt
■ Input Capture
– 8-bit input capture register (LTICR)
– Maskable interrupt with wakeup from Halt
Mode capability
Watchdog
– Enabled by hardware or software (configurable by option byte)
– Optional reset on HALT instruction (configurable by option byte)
– Automatically resets the device unless disable
bit is refreshed
– Software reset (Forced Watchdog reset)
– Watchdog reset status flag
Figure 30. Lite Timer Block Diagram
fLTIMER
To 12-bit AT TImer
fWDG
fOSC
/2
13-bit UPCOUNTER
LTICR
LTIC
fLTIMER
WATCHDOG
WATCHDOG RESET
1
Timebase
1 or 2 ms
0
(@ 8MHz
fOSC)
8 MSB
8-bit
INPUT CAPTURE
REGISTER
LTCSR
ICIE
7
ICF
TB
TBIE
TBF WDG
RF
WDGE WDGD
0
LTTB INTERRUPT REQUEST
LTIC INTERRUPT REQUEST
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1
ST7LITEUSx
LITE TIMER (Cont’d)
10.1.3 Functional Description
The value of the 13-bit counter cannot be read or
written by software. After an MCU reset, it starts
incrementing from 0 at a frequency of fOSC. A
counter overflow event occurs when the counter
rolls over from 1F39h to 00h. If fOSC = 8 MHz, then
the time period between two counter overflow
events is 1 ms. This period can be doubled by setting the TB bit in the LTCSR register.
When the timer overflows, the TBF bit is set by
hardware and an interrupt request is generated if
the TBIE is set. The TBF bit is cleared by software
reading the LTCSR register.
10.1.3.1 Watchdog
The watchdog is enabled using the WDGE bit.
The normal Watchdog timeout is 2ms (@ fosc = 8
MHz ), after which it then generates a reset.
To prevent this watchdog reset occuring, software
must set the WDGD bit. The WDGD bit is cleared
by hardware after tWDG. This means that software
must write to the WDGD bit at regular intervals to
prevent a watchdog reset occurring. Refer to Figure 31.
If the watchdog is not enabled immediately after
reset, the first watchdog timeout will be shorter
than 2ms, because this period is counted starting
from reset. Moreover, if a 2ms period has already
elapsed after the last MCU reset, the watchdog reset will take place as soon as the WDGE bit is set.
For these reasons, it is recommended to enable
the Watchdog immediately after reset or else to
set the WDGD bit before the WGDE bit so a
watchdog reset will not occur for at least 2ms.
Note: Software can use the timebase feature to
set the WDGD bit at 1 or 2 ms intervals.
A Watchdog reset can be forced at any time by
setting the WDGRF bit. To generate a forced
watchdog reset, first watchdog has to be activated
by setting the WDGE bit and then the WDGRF bit
has to be set.
The WDGRF bit also acts as a flag, indicating that
the Watchdog was the source of the reset. It is automatically cleared after it has been read.
Caution: When the WDGRF bit is set, software
must clear it, otherwise the next time the watchdog
is enabled (by hardware or software), the microcontroller will be immediately reset.
Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGE bit in
the LTCSR is not used.
Refer to the Option Byte description in the "device
configuration and ordering information" section.
Using Halt Mode with the Watchdog (option)
If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be used
when the watchdog is enabled.
In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the Lite Timer
stops counting and is no longer able to generate a
Watchdog reset until the microcontroller receives
an external interrupt or a reset.
If an external interrupt is received, the WDG restarts counting after 64 CPU clocks. If a reset is
generated, the Watchdog is disabled (reset state).
If Halt mode with Watchdog is enabled by option
byte (No watchdog reset on HALT instruction), it is
recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up
the microcontroller.
Figure 31. Watchdog Timing Diagram
HARDWARE CLEARS
WDGD BIT
fWDG
tWDG
(2ms @ 8MHz fOSC)
WDGD BIT
INTERNAL
WATCHDOG
RESET
SOFTWARE SETS
WDGD BIT
WATCHDOG RESET
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1
ST7LITEUSx
LITE TIMER (Cont’d)
Input Capture
10.1.5 Interrupts
The 8-bit input capture register is used to latch the
free-running upcounter after a rising or falling edge
is detected on the LTIC pin. When an input capture
occurs, the ICF bit is set and the LTICR register
contains the MSB of the free-running upcounter.
An interrupt is generated if the ICIE bit is set. The
ICF bit is cleared by reading the LTICR register.
The LTICR is a read only register and always contains the data from the last input capture. Input
capture is inhibited if the ICF bit is set.
Interrupt
Event
Timebase
Event
IC Event
Exit Exit
from from
Wait Halt
Exit
from
ActiveHalt
Event
Flag
Enable
Control
Bit
TBF
TBIE
Yes
No
Yes
ICF
ICIE
Yes
No
No
Note: The TBF and ICF interrupt events are connected to separate interrupt vectors (see Interrupts chapter).
10.1.4 Low Power Modes
Mode
WAIT
ACTIVE-HALT
HALT
They generate an interrupt if the enable bit is set in
the LTCSR register and the interrupt mask in the
CC register is reset (RIM instruction).
Description
No effect on Lite timer
No effect on Lite timer
Lite timer stops counting
Figure 32. Input Capture Timing Diagram
125ns
(@ 8MHz fOSC)
fCPU
fOSC
13-bit COUNTER
0001h
0002h
0003h
0004h
0005h
0006h
0007h
CLEARED
BY S/W
READING
LTIC REGISTER
LTIC PIN
ICF FLAG
LTICR REGISTER
xxh
04h
07h
t
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1
ST7LITEUSx
LITE TIMER (Cont’d)
10.1.6 Register Description
LITE TIMER CONTROL/STATUS REGISTER
(LTCSR)
Read / Write
Reset Value: 0000 0x00 (0xh)
7
ICIE
Bit 2 = WDGRF Force Reset/ Reset Status Flag
This bit is used in two ways: it is set by software to
force a watchdog reset. It is set by hardware when
a watchdog reset occurs and cleared by hardware
or by software. It is cleared by hardware only when
an LVD reset occurs. It can be cleared by software
after a read access to the LTCSR register.
0: No watchdog reset occurred.
1: Force a watchdog reset (write), or, a watchdog
reset occurred (read).
0
ICF
TB
TBIE
TBF
WDG
WDG
WDGE
R
D
Bit 7 = ICIE Interrupt Enable.
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
Bit 1 = WDGE Watchdog Enable
This bit is set and cleared by software.
0: Watchdog disabled
1: Watchdog enabled
Bit 6 = ICF Input Capture Flag.
This bit is set by hardware and cleared by software
by reading the LTICR register. Writing to this bit
does not change the bit value.
0: No input capture
1: An input capture has occurred
Note: After an MCU reset, software must initialise
the ICF bit by reading the LTICR register
Bit 0 = WDGD Watchdog Reset Delay
This bit is set by software. It is cleared by hardware at the end of each tWDG period.
0: Watchdog reset not delayed
1: Watchdog reset delayed
LITE TIMER INPUT CAPTURE REGISTER
(LTICR)
Read only
Reset Value: 0000 0000 (00h)
Bit 5 = TB Timebase period selection.
This bit is set and cleared by software.
0: Timebase period = tOSC * 8000 (1ms @ 8 MHz)
1: Timebase period = tOSC * 16000 (2ms @ 8
MHz)
7
0
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
Bit 4 = TBIE Timebase Interrupt enable.
This bit is set and cleared by software.
0: Timebase (TB) interrupt disabled
1: Timebase (TB) interrupt enabled
Bits 7:0 = ICR[7:0] Input Capture Value
These bits are read by software and cleared by
hardware after a reset. If the ICF bit in the LTCSR
is cleared, the value of the 8-bit up-counter will be
captured when a rising or falling edge occurs on
the LTIC pin.
Bit 3 = TBF Timebase Interrupt Flag.
This bit is set by hardware and cleared by software
reading the LTCSR register. Writing to this bit has
no effect.
0: No counter overflow
1: A counter overflow has occurred
Table 16. Lite Timer Register Map and Reset Values
Address (Hex.) Register Label
50/108
1
7
6
5
4
3
2
1
0
0B
LTCSR
Reset Value
ICIE
0
ICF
0
TB
0
TBIE
0
TBF
0
WDGRF
x
WDGE
0
WDGD
0
0C
LTICR
Reset Value
ICR7
0
ICR6
0
ICR5
0
ICR4
0
ICR3
0
ICR2
0
ICR1
0
ICR0
0
ST7LITEUSx
10.2 12-BIT AUTORELOAD TIMER (AT)
10.2.1 Introduction
■
The 12-bit Autoreload Timer can be used for general-purpose timing functions. It is based on a freerunning 12-bit upcounter with a PWM output channel.
10.2.2 Main Features
■ 12-bit upcounter with 12-bit autoreload register
(ATR)
■ Maskable overflow interrupt
■
■
PWM signal generator
Frequency range 2KHz-4MHz (@ 8 MHz fCPU)
– Programmable duty-cycle
– Polarity control
– Maskable Compare interrupt
Output Compare Function
Figure 33. Block Diagram
7 ATCSR
0
0
fLTIMER
(1 ms timebase
@ 8MHz)
OVF INTERRUPT
REQUEST
0
0
CK1
CK0
OVF OVFIE CMPIE
CMP INTERRUPT
REQUEST
CMPF0
fCOUNTER
12-BIT UPCOUNTER
Update on OVF Event
CNTR
fCPU
12-BIT AUTORELOAD VALUE
ATR
DCR0L
Preload
Preload
OE0 bit CMPF0 bit
0
on OVF Event
IF OE0=1
12-BIT DUTY CYCLE VALUE (shadow)
1
COMPPARE
OP0 bit
fPWM POLARITY
OUTPUT CONTROL
DCR0H
PWM GENERATION
OE0 bit
PWM0
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ST7LITEUSx
12-BIT AUTORELOAD TIMER (Cont’d)
10.2.3 Functional Description
PWM Mode
This mode allows a Pulse Width Modulated signals to be generated on the PWM0 output pin with
minimum core processing overhead. The PWM0
output signal can be enabled or disabled using the
OE0 bit in the PWMCR register. When this bit is
set the PWM I/O pin is configured as output pushpull alternate function.
Note: CMPF0 is available in PWM mode (see
PWM0CSR description on page 55).
PWM Frequency and Duty Cycle
The PWM signal frequency (fPWM) is controlled by
the counter period and the ATR register value.
fPWM = fCOUNTER / (4096 - ATR)
Following the above formula, if fCPU is 8 MHz, the
maximum value of fPWM is 4 Mhz (ATR register
value = 4094), and the minimum value is 2 kHz
(ATR register value = 0).
Note: The maximum value of ATR is 4094 because it must be lower than the DCR value which
must be 4095 in this case.
At reset, the counter starts counting from 0.
Software must write the duty cycle value in the
DCR0H and DCR0L preload registers. The
DCR0H register must be written first. See caution
below.
When a upcounter overflow occurs (OVF event),
the ATR value is loaded in the upcounter, the
preloaded Duty cycle value is transferred to the
Duty Cycle register and the PWM0 signal is set to
a high level. When the upcounter matches the
DCRx value the PWM0 signals is set to a low level.
To obtain a signal on the PWM0 pin, the contents
of the DCR0 register must be greater than the contents of the ATR register.
The polarity bit can be used to invert the output
signal.
The maximum available resolution for the PWM0
duty cycle is:
Resolution = 1 / (4096 - ATR)
Note: To get the maximum resolution (1/4096), the
ATR register must be 0. With this maximum resolution and assuming that DCR=ATR, a 0% or
100% duty cycle can be obtained by changing the
polarity .
Caution: As soon as the DCR0H is written, the
compare function is disabled and will start only
when the DCR0L value is written. If the DCR0H
write occurs just before the compare event, the
signal on the PWM output may not be set to a low
level. In this case, the DCRx register should be updated just after an OVF event. If the DCR and ATR
values are close, then the DCRx register shouldbe
updated just before an OVF event, in order not to
miss a compare event and to have the right signal
applied on the PWM output.
Figure 34. PWM Function
COUNTER
4095
DUTY CYCLE
REGISTER
(DCR0)
AUTO-RELOAD
REGISTER
(ATR)
PWM0 OUTPUT
000
52/108
1
WITH OE0=1
AND OP0=0
WITH OE0=1
AND OP0=1
t
ST7LITEUSx
12-BIT AUTORELOAD TIMER (Cont’d)
Figure 35. PWM Signal Example
fCOUNTER
PWM0 OUTPUT
WITH OE0=1
AND OP0=0
ATR= FFDh
COUNTER
FFDh
FFEh
FFFh
FFDh
FFEh
FFFh
FFDh
FFEh
DCR0=FFEh
Output Compare Mode
To use this function, the OE bit must be 0, otherwise the compare is done with the shadow register
instead of the DCRx register. Software must then
write a 12-bit value in the DCR0H and DCR0L registers. This value will be loaded immediately (without waiting for an OVF event).
The DCR0H must be written first, the output compare function starts only when the DCR0L value is
written.
When the 12-bit upcounter (CNTR) reaches the
value stored in the DCR0H and DCR0L registers,
the CMPF0 bit in the PWM0CSR register is set
and an interrupt request is generated if the CMPIE
bit is set.
Note: The output compare function is only available for DCRx values other than 0 (reset value).
Caution: At each OVF event, the DCRx value is
written in a shadow register, even if the DCR0L
value has not yet been written (in this case, the
shadow register will contain the new DCR0H value
and the old DCR0L value), then:
– If OE=1 (PWM mode): the compare is done between the timer counter and the shadow register
(and not DCRx)
– if OE=0 (OCMP mode): the compare is done between the timer counter and DCRx. There is no
PWM signal.
t
The compare between DCRx or the shadow register and the timer counter is locked until DCR0L is
written.
10.2.4 Low Power Modes
Mode
Description
The input frequency is divided
SLOW
by 32
WAIT
No effect on AT timer
AT timer halted except if CK0=1,
ACTIVE-HALT
CK1=0 and OVFIE=1
HALT
AT timer halted
10.2.5 Interrupts
Interrupt
Event 1)
Overflow
Event
CMP Event
Enable Exit Exit
Event
Control from from
Flag
Bit
Wait Halt
Exit
from
ActiveHalt
Yes
No
Yes2)
CMPFx CMPIE Yes
No
No
OVF
OVFIE
Note 1: The interrupt events are connected to separate interrupt vectors (see Interrupts chapter).
They generate an interrupt if the enable bit is set in
the ATCSR register and the interrupt mask in the
CC register is reset (RIM instruction).
Note 2: only if CK0=1and CK1=0
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ST7LITEUSx
12-BIT AUTORELOAD TIMER (Cont’d)
10.2.6 Register Description
TIMER CONTROL STATUS REGISTER (ATCSR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
CK1
CK0
OVF
OVFIE CMPIE
Bits 7:5 = Reserved, must be kept cleared.
Counter Clock Selection
CK1
CK0
0
OFF
0
fLTIMER (1 ms timebase @ 8 MHz)
0
1
fCPU
1
0
Reserved
1
1
Bit 2 = OVF Overflow Flag.
This bit is set by hardware and cleared by software
by reading the ATCSR register. It indicates the
transition of the counter from FFFh to ATR value.
0: No counter overflow occurred
1: Counter overflow occurred
Caution:
When set, the OVF bit stays high for 1 fCOUNTER
cycle (up to 1ms depending on the clock selection)
after it has been cleared by software.
Bit 1 = OVFIE Overflow Interrupt Enable.
This bit is read/write by software and cleared by
hardware after a reset.
0: OVF interrupt disabled
1: OVF interrupt enabled
1
COUNTER REGISTER HIGH (CNTRH)
Read only
Reset Value: 0000 0000 (00h)
15
Bits 4:3 = CK[1:0] Counter Clock Selection.
These bits are set and cleared by software and
cleared by hardware after a reset. They select the
clock frequency of the counter.
54/108
Bit 0 = CMPIE Compare Interrupt Enable.
This bit is read/write by software and clear by
hardware after a reset. It allows to mask the interrupt generation when CMPF bit is set.
0: CMPF interrupt disabled
1: CMPF interrupt enabled
0
8
0
0
0
CN11
CN10
CN9
CN8
COUNTER REGISTER LOW (CNTRL)
Read only
Reset Value: 0000 0000 (00h)
7
CN7
0
CN6
CN5
CN4
CN3
CN2
CN1
CN0
Bits 15:12 = Reserved, must be kept cleared.
Bits 11:0 = CNTR[11:0] Counter Value.
This 12-bit register is read by software and cleared
by hardware after a reset. The counter is incremented continuously as soon as a counter clock is
selected. To obtain the 12-bit value, software
should read the counter value in two consecutive
read operations. As there is no latch, it is recommended to read LSB first. In this case, CNTRH
can be incremented between the two read operations and to have an accurate result when
ftimer=fCPU, special care must be taken when CNTRL values close to FFh are read.
When a counter overflow occurs, the counter restarts from the value specified in the ATR register.
ST7LITEUSx
12-BIT AUTORELOAD TIMER (Cont’d)
AUTO RELOAD REGISTER (ATRH)
Read / Write
Reset Value: 0000 0000 (00h)
PWM0 DUTY CYCLE REGISTER LOW (DCR0L)
Read / Write
Reset Value: 0000 0000 (00h)
15
0
8
0
0
0
ATR11 ATR10 ATR9
ATR8
AUTO RELOAD REGISTER (ATRL)
Read / Write
Reset Value: 0000 0000 (00h)
0
ATR6
ATR5
ATR4
ATR3
ATR2
ATR1
DCR7 DCR6 DCR5 DCR4 DCR3
DCR2
DCR1 DCR0
Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value
This 12-bit value is written by software. The high
register must be written first.
ATR0
Bits 15:12 = Reserved, must be kept cleared.
Bits 11:0 = ATR[11:0] Autoreload Register.
This is a 12-bit register which is written by software. The ATR register value is automatically
loaded into the upcounter when an overflow occurs. The register value is used to set the PWM
frequency.
PWM0 DUTY CYCLE REGISTER HIGH (DCR0H)
Read / Write
Reset Value: 0000 0000 (00h)
15
0
Bits 15:12 = Reserved, must be kept cleared.
7
ATR7
7
In PWM mode (OE0=1 in the PWMCR register)
the DCR[11:0] bits define the duty cycle of the
PWM0 output signal (see Figure 34). In Output
Compare mode, (OE0=0 in the PWMCR register)
they define the value to be compared with the 12bit upcounter value.
PWM0
CONTROL/STATUS
(PWM0CSR)
Read / Write
Reset Value: 0000 0000 (00h)
REGISTER
7
0
0
0
0
0
0
0
OP0 CMPF0
8
Bit 7:2= Reserved, must be kept cleared.
0
0
0
0
DCR11 DCR10 DCR9 DCR8
Bit 1 = OP0 PWM0 Output Polarity.
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the polarity
of the PWM0 signal.
0: The PWM0 signal is not inverted.
1: The PWM0 signal is inverted.
Bit 0 = CMPF0 PWM0 Compare Flag.
This bit is set by hardware and cleared by software
by reading the PWM0CSR register. It indicates
that the upcounter value matches the DCR0 register value.
0: Upcounter value does not match DCR value.
1: Upcounter value matches DCR value.
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1
ST7LITEUSx
12-BIT AUTORELOAD TIMER (Cont’d)
PWM OUTPUT CONTROL REGISTER (PWMCR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
0
OE0
Bits 7:1 = Reserved, must be kept cleared.
Bit 0 = OE0 PWM0 Output enable.
This bit is set and cleared by software.
0: PWM0 output Alternate Function disabled (I/O
pin free for general purpose I/O)
1: PWM0 output enabled
Table 17. Register Map and Reset Values
Address
Register
Label
7
6
5
4
3
2
1
0
0D
ATCSR
Reset Value
0
0
0
CK1
0
CK0
0
OVF
0
OVFIE
0
CMPIE
0
0E
CNTRH
Reset Value
0
0
0
0
CN11
0
CN10
0
CN9
0
CN8
0
0F
CNTRL
Reset Value
CN7
0
CN6
0
CN5
0
CN4
0
CN3
0
CN2
0
CN1
0
CN0
0
10
ATRH
Reset Value
0
0
0
0
ATR11
0
ATR10
0
ATR9
0
ATR8
0
11
ATRL
Reset Value
ATR7
0
ATR6
0
ATR5
0
ATR4
0
ATR3
0
ATR2
0
ATR1
0
ATR0
0
12
PWMCR
Reset Value
0
0
0
0
0
0
0
OE0
0
13
PWM0CSR
Reset Value
0
0
0
0
0
0
OP
0
CMPF0
0
17
DCR0H
Reset Value
0
0
0
0
DCR11
0
DCR10
0
DCR9
0
DCR8
0
18
DCR0L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
(Hex.)
56/108
1
ST7LITEUSx
10.3 10-BIT A/D CONVERTER (ADC)
10.3.1 Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This
peripheral has up to 5 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 5 different sources.
The result of the conversion is stored in a 10-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
10.3.2 Main Features
■ 10-bit conversion
■ Up to 5 channels with multiplexed input
■ Linear successive approximation
Data register (DR) which contains the results
■ Conversion complete status flag
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 36.
10.3.3 Functional Description
10.3.3.1 Analog Power Supply
VDDA and VSSA are the high and low level reference
voltage pins. In some devices (refer to device pin
out description) they are internally connected to
the VDD and VSS pins.
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
■
Figure 36. ADC Block Diagram
fCPU
DIV 4
DIV 2
1
fADC
0
0
1
EOC SPEED ADON
SLOW
bit
0
0
CH2
CH1
ADCCSR
CH0
3
AIN0
HOLD CONTROL
RADC
AIN1
ANALOG TO DIGITAL
ANALOG
MUX
CONVERTER
CADC
AINx
ADCDRH
D9
D8
ADCDRL
D7
D6
0
D5
0
D4
0
D3
0
D2
SLOW
0
D1
D0
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1
ST7LITEUSx
10-BIT A/D CONVERTER (ADC) (Cont’d)
10.3.3.2 Digital A/D Conversion Result
The conversion is monotonic, meaning that the result never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (VAIN) is greater than VDDA (highlevel voltage reference) then the conversion result
is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication).
If the input voltage (VAIN) is lower than VSSA (lowlevel voltage reference) then the conversion result
in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and ADCDRL registers. The accuracy of the conversion is
described in the Electrical Characteristics Section.
RAIN is the maximum recommended impedance
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
10.3.3.3 A/D Conversion Phases
The A/D conversion is based on two conversion
phases:
■ Sample capacitor loading [duration: tSAMPLE]
During this phase, the VAIN input voltage to be
measured is loaded into the CADC sample
capacitor.
■ A/D conversion [duration: tHOLD]
During this phase, the A/D conversion is
computed (8 successive approximations cycles)
and the CADC sample capacitor is disconnected
from the analog input pin to get the optimum
analog to digital conversion accuracy.
■ The total conversion time:
tCONV = tSAMPLE + tHOLD
While the ADC is on, these two phases are continuously repeated.
At the end of each conversion, the sample capacitor is kept loaded with the previous measurement
load. The advantage of this behaviour is that it
minimizes the current consumption on the analog
pin in case of single input channel measurement.
chapter. Using these pins as analog inputs does
not affect the ability of the port to be read as a logic
input.
In the ADCCSR register:
– Select the CS[2:0] bits to assign the analog
channel to convert.
ADC Conversion mode
In the ADCCSR register:
Set the ADON bit to enable the A/D converter and
to start the conversion. From this time on, the ADC
performs a continuous conversion of the selected
channel.
When a conversion is complete:
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH resets the EOC bit.
To read the 10 bits, perform the following steps:
1. Poll EOC bit
2. Read ADCDRL
3. Read ADCDRH. This clears EOC automatically.
To read only 8 bits, perform the following steps:
1. Poll EOC bit
2. Read ADCDRH. This clears EOC automatically.
10.3.4 Low Power Modes
Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
Mode
WAIT
HALT
Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D Converter requires a stabilization time tSTAB (see
Electrical Characteristics) before accurate
conversions can be performed.
10.3.5 Interrupts
None.
10.3.3.4 A/D Conversion
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the “I/O ports”
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ST7LITEUSx
10-BIT A/D CONVERTER (ADC) (Cont’d)
10.3.6 Register Description
Note: A write to the ADCCSR register (with ADON
set) aborts the current conversion, resets the EOC
bit and starts a new conversion.
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
7
EOC
0
SPEE ADO
D
N
0
0
CH2
CH1
CH0
DATA REGISTER HIGH (ADCDRH)
Read Only
Reset Value: 0000 0000 (00h)
7
D9
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by software reading the ADCDRH register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software. It is used
together with the SLOW bit to configure the ADC
clock speed. Refer to the table in the SLOW bit description.
AIN0
AIN1
AIN2
AIN3
AIN4
CH1
0
0
1
1
0
D6
D5
D4
D3
D2
DATA REGISTER LOW (ADCDRL)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
SLOW
0
D1
D0
Bit 4 = Reserved. Forced by hardware to 0.
Bits 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
CH2
0
0
0
0
1
D7
Bits 7:5 = Reserved. Forced by hardware to 0.
Bits 4:3 = Reserved. Must be kept cleared.
Channel Pin
D8
Bits 7:0 = D[9:2] MSB of Analog Converted Value
0
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
0
CH0
0
1
0
1
0
Bit 3 = SLOW Slow mode
This bit is set and cleared by software. It is used
together with the SPEED bit to configure the ADC
clock speed as shown on the table below.
fADC
fCPU/2
fCPU
fCPU/4
SLOW
0
0
1
SPEED
0
1
x
Bit 2 = Reserved. Forced by hardware to 0.
Bits 1:0 = D[1:0] LSB of Analog Converted Value
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ST7LITEUSx
Table 18. ADC Register Map and Reset Values
Address
(Hex.)
7
6
5
4
3
2
1
0
0034h
ADCCSR
Reset Value
EOC
0
SPEED
0
ADON
0
0
0
0
0
CH2
0
CH1
0
CH0
0
0035h
ADCDRH
Reset Value
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
0036h
ADCDRL
Reset Value
0
0
0
0
0
0
0
0
SLOW
0
0
0
D1
0
D0
0
60/108
1
Register
Label
ST7LITEUSx
11 INSTRUCTION SET
11.1 ST7 ADDRESSING MODES
The ST7 Core features 17 different addressing
modes which can be classified in seven main
groups:
Addressing Mode
Example
Inherent
nop
Immediate
ld A,#$55
Direct
ld A,$55
Indexed
ld A,($55,X)
Indirect
ld A,([$55],X)
Relative
jrne loop
Bit operation
bset
byte,#5
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
so, most of the addressing modes may be subdivided in two submodes called long and short:
– Long addressing mode is more powerful because it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cycles.
– Short addressing mode is less powerful because
it can generally only access page zero (0000h 00FFh range), but the instruction size is more
compact, and faster. All memory to memory instructions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and
short addressing modes.
Table 19. ST7 Addressing Mode Overview
Mode
Syntax
Pointer
Address
(Hex.)
Destination/
Source
Pointer
Size
(Hex.)
Length
(Bytes)
Inherent
nop
+0
Immediate
ld A,#$55
+1
Short
Direct
ld A,$10
00..FF
+1
Long
Direct
ld A,$1000
0000..FFFF
+2
No Offset
Direct
Indexed
ld A,(X)
00..FF
+ 0 (with X register)
+ 1 (with Y register)
Short
Direct
Indexed
ld A,($10,X)
00..1FE
+1
Long
Direct
Indexed
Short
Indirect
ld A,($1000,X)
0000..FFFF
ld A,[$10]
00..FF
+2
00..FF
byte
+2
Long
Indirect
ld A,[$10.w]
0000..FFFF
00..FF
word
+2
Short
Indirect
Indexed
ld A,([$10],X)
00..1FE
00..FF
byte
+2
Long
Indirect
Indexed
ld A,([$10.w],X)
0000..FFFF
00..FF
word
+2
byte
+2
1)
+1
Relative
Direct
jrne loop
PC-128/PC+127
Relative
Indirect
jrne [$10]
PC-128/PC+1271) 00..FF
Bit
Direct
bset $10,#7
00..FF
Bit
Indirect
bset [$10],#7
00..FF
Bit
Direct
btjt $10,#7,skip
00..FF
Relative
+1
00..FF
byte
+2
+2
Bit
Indirect Relative btjt [$10],#7,skip 00..FF
00..FF
byte
+3
Note:
1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
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ST7 ADDRESSING MODES (cont’d)
11.1.1 Inherent
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction
Function
NOP
No operation
TRAP
S/W Interrupt
WFI
Wait For Interrupt (Low Power
Mode)
HALT
Halt Oscillator (Lowest Power
Mode)
RET
Subroutine Return
IRET
Interrupt Subroutine Return
SIM
Set Interrupt Mask
RIM
Reset Interrupt Mask
SCF
Set Carry Flag
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
LD
Load
CLR
Clear
PUSH/POP
Push/Pop to/from the stack
INC/DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
MUL
Byte Multiplication
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
11.1.2 Immediate
Immediate instructions have 2 bytes, the first byte
contains the opcode, the second byte contains the
operand value.
Immediate Instruction
Function
LD
Load
CP
Compare
BCP
Bit Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Operations
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11.1.3 Direct
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two submodes:
Direct (Short)
The address is a byte, thus requires only 1 byte after the opcode, but only allows 00 - FF addressing
space.
Direct (Long)
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode.
11.1.4 Indexed (No Offset, Short, Long)
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three
submodes:
Indexed (No Offset)
There is no offset (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
The offset is a byte, thus requires only 1 byte after
the opcode and allows 00 - 1FE addressing space.
Indexed (Long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode.
11.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two submodes:
Indirect (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
ST7LITEUSx
ST7 ADDRESSING MODES (cont’d)
11.1.6 Indirect Indexed (Short, Long)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the unsigned addition of an index register value (X or Y)
with a pointer value located in memory. The pointer address follows the opcode.
The indirect indexed addressing mode consists of
two submodes:
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
11.1.7 Relative Mode (Direct, Indirect)
This addressing mode is used to modify the PC
register value by adding an 8-bit signed offset to it.
Available Relative Direct/
Indirect Instructions
Function
JRxx
Conditional Jump
CALLR
Call Relative
The relative addressing mode consists of two submodes:
Relative (Direct)
The offset follows the opcode.
Relative (Indirect)
The offset is defined in memory, of which the address follows the opcode.
Table 20. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Instructions
Function
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Addition/subtraction operations
BCP
Bit Compare
Short Instructions Only
Function
CLR
Clear
INC, DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
BSET, BRES
Bit Operations
BTJT, BTJF
Bit Test and Jump Operations
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
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11.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
Stack operation
PUSH
POP
Increment/Decrement
INC
DEC
Compare and Tests
CP
TNZ
BCP
Logical operations
AND
OR
XOR
CPL
NEG
Bit Operation
BSET
BRES
Conditional Bit Test and Branch
BTJT
BTJF
Arithmetic operations
ADC
ADD
SUB
SBC
MUL
Shift and Rotates
SLL
SRL
SRA
RLC
RRC
SWAP
SLA
Unconditional Jump or Call
JRA
JRT
JRF
JP
CALL
CALLR
NOP
Conditional Branch
JRxx
Interruption management
TRAP
WFI
HALT
IRET
Condition Code Flag modification
SIM
RIM
SCF
RCF
Using a prebyte
The instructions are described with 1 to 4 bytes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they precede.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PC
Opcode
PC+1 Additional word (0 to 2) according to the
number of bytes required to compute the
effective address
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
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1
RSP
RET
PDY 90 Replace an X based instruction using
immediate, direct, indexed, or inherent
addressing mode by a Y one.
PIX 92 Replace an instruction using direct, direct bit or direct relative addressing
mode to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X
indexed addressing mode to an instruction using indirect X indexed addressing
mode.
PIY 91 Replace an instruction using X indirect
indexed addressing mode by a Y one.
11.2.1 Illegal Opcode Reset
In order to provide enhanced robustness to the device against unexpected behavior, a system of illegal opcode detection is implemented. If a code to
be executed does not correspond to any opcode
or prebyte value, a reset is generated. This, combined with the Watchdog, allows the detection and
recovery from an unexpected fault or interference.
Note: A valid prebyte associated with a valid opcode forming an unauthorized combination does
not generate a reset.
ST7LITEUSx
INSTRUCTION GROUPS (cont’d)
Mnemo
Description
Function/Example
Dst
Src
H
I
N
Z
C
ADC
Add with Carry
A=A+M+C
A
M
H
N
Z
C
ADD
Addition
A=A+M
A
M
H
N
Z
C
AND
Logical And
A=A.M
A
M
N
Z
BCP
Bit compare A, Memory
tst (A . M)
A
M
N
Z
BRES
Bit Reset
bres Byte, #3
M
BSET
Bit Set
bset Byte, #3
M
BTJF
Jump if bit is false (0)
btjf Byte, #3, Jmp1
M
C
BTJT
Jump if bit is true (1)
btjt Byte, #3, Jmp1
M
C
CALL
Call subroutine
CALLR
Call subroutine relative
CLR
Clear
CP
Arithmetic Compare
tst(Reg - M)
reg
CPL
One Complement
A = FFH-A
DEC
Decrement
dec Y
reg, M
HALT
Halt
IRET
Interrupt routine return
Pop CC, A, X, PC
INC
Increment
inc X
JP
Absolute Jump
jp [TBL.w]
JRA
Jump relative always
JRT
Jump relative
JRF
Never jump
JRIH
Jump if ext. interrupt = 1
0
1
N
Z
C
reg, M
N
Z
1
reg, M
N
Z
N
Z
N
Z
M
0
H
reg, M
I
C
jrf *
JRIL
Jump if ext. interrupt = 0
JRH
Jump if H = 1
H=1?
JRNH
Jump if H = 0
H=0?
JRM
Jump if I = 1
I=1?
JRNM
Jump if I = 0
I=0?
JRMI
Jump if N = 1 (minus)
N=1?
JRPL
Jump if N = 0 (plus)
N=0?
JREQ
Jump if Z = 1 (equal)
Z=1?
JRNE
Jump if Z = 0 (not equal)
Z=0?
JRC
Jump if C = 1
C=1?
JRNC
Jump if C = 0
C=0?
JRULT
Jump if C = 1
Unsigned <
JRUGE
Jump if C = 0
Jmp if unsigned >=
JRUGT
Jump if (C + Z = 0)
Unsigned >
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INSTRUCTION GROUPS (cont’d)
Mnemo
Description
Function/Example
Dst
Src
JRULE
Jump if (C + Z = 1)
Unsigned <=
LD
Load
dst <= src
reg, M
M, reg
MUL
Multiply
X,A = X * A
A, X, Y
X, Y, A
NEG
Negate (2's compl)
neg $10
reg, M
NOP
No Operation
OR
OR operation
A=A+M
A
M
POP
Pop from the Stack
pop reg
reg
M
pop CC
CC
M
M
reg, CC
H
I
N
Z
N
Z
0
H
C
0
I
N
Z
N
Z
N
Z
C
C
PUSH
Push onto the Stack
push Y
RCF
Reset carry flag
C=0
RET
Subroutine Return
RIM
Enable Interrupts
I=0
RLC
Rotate left true C
C <= Dst <= C
reg, M
N
Z
C
RRC
Rotate right true C
C => Dst => C
reg, M
N
Z
C
RSP
Reset Stack Pointer
S = Max allowed
SBC
Subtract with Carry
A=A-M-C
N
Z
C
SCF
Set carry flag
C=1
SIM
Disable Interrupts
I=1
SLA
Shift left Arithmetic
C <= Dst <= 0
reg, M
N
Z
C
SLL
Shift left Logic
C <= Dst <= 0
reg, M
N
Z
C
SRL
Shift right Logic
0 => Dst => C
reg, M
0
Z
C
SRA
Shift right Arithmetic
Dst7 => Dst => C
reg, M
N
Z
C
SUB
Subtraction
A=A-M
A
N
Z
C
SWAP
SWAP nibbles
Dst[7..4] <=> Dst[3..0] reg, M
N
Z
TNZ
Test for Neg & Zero
tnz lbl1
N
Z
TRAP
S/W trap
S/W interrupt
WFI
Wait for Interrupt
XOR
Exclusive OR
N
Z
66/108
1
0
0
A
M
1
1
M
1
0
A = A XOR M
A
M
ST7LITEUSx
12 ELECTRICAL CHARACTERISTICS
12.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are referred to VSS.
12.1.1 Minimum and Maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
devices with an ambient temperature at TA=25°C
and TA=TAmax (given by the selected temperature
range).
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the minimum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
12.1.2 Typical values
Unless otherwise specified, typical data are based
on TA=25°C, VDD=5V (for the 4.5V≤VDD≤5.5V voltage range), VDD=3.75V (for the 3V≤VDD≤4.5V
voltage range) and VDD=2.7V (for the
2.4V≤VDD≤3V voltage range). They are given only
as design guidelines and are not tested.
12.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
12.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 37.
12.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 38.
Figure 38. Pin input voltage
ST7 PIN
VIN
Figure 37. Pin loading conditions
ST7 PIN
CL
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12.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device under these condi12.2.1 Voltage Characteristics
Symbol
VDD - VSS
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
Ratings
Supply voltage
Maximum value
7.0
Unit
V
Input voltage on any pin 1) & 2)
VSS-0.3 to VDD+0.3
VESD(HBM)
Electrostatic discharge voltage (Human Body Model)
see section 12.7.2 on page 79
VESD(MM)
Electrostatic discharge voltage (Machine Model)
see section 12.7.2 on page 79
VIN
12.2.2 Current Characteristics
Symbol
Ratings
Maximum value
IVDD
Total current into VDD power lines (source) 3)
75
IVSS
Total current out of VSS ground lines (sink) 3)
150
Output current sunk by any standard I/O and control pin
20
IIO
IINJ(PIN) 2) & 4)
ΣIINJ(PIN) 2)
Output current sunk by any high sink I/O pin
40
Output current source by any I/Os and control pin
-25
Injected current on RESET pin
±5
Injected current on any other pin 5)
±5
Total injected current (sum of all I/O and control pins) 5)
± 20
Unit
mA
12.2.3 Thermal Characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Value
Unit
-65 to +150
°C
Maximum junction temperature (see Section PACKAGE CHARACTERISTICS (Cont’d))
Notes:
1. Directly connecting the I/O pins to VDD or VSS could damage the device if an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be
done through a pull-up or pull-down resistor (typical: 10kΩ for I/Os). Unused I/O pins must be tied in the same way to VDD
or VSS according to their reset configuration.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be
respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD
while a negative injection is induced by VIN<VSS.
3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive
and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
68/108
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ST7LITEUSx
12.3 OPERATING CONDITIONS
12.3.1 General Operating Conditions
TA = -40 to +125°C unless otherwise specified.
Symbol
Parameter
VDD
Supply voltage
fCPU
CPU clock frequency
Conditions
Min
Max
fCPU = 4 MHz. max.
2.4
5.5
fCPU = 8 MHz. max.
3.3
5.5
3.3V≤ VDD≤5.5V
up to 8
2.4V≤VDD<3.3V
up to 4
Unit
V
MHz
Figure 39. fCPU Maximum Operating Frequency Versus VDD Supply Voltage
FUNCTIONALITY
GUARANTEED
IN THIS AREA
(UNLESS OTHERWISE
STATED IN THE
TABLES OF
PARAMETRIC DATA)
fCPU [MHz]
8
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
4
2
SUPPLY VOLTAGE [V]
0
2.0
2.4 2.7
3.3
3.5
4.0
4.5
5.0
5.5
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ST7LITEUSx
12.3.2 Operating Conditions with Low Voltage Detector (LVD)
TA = -40 to 125°C, unless otherwise specified
Symbol
Parameter
VIT+(LVD)
Reset release threshold
(VDD rise)
VIT-(LVD)
Reset generation threshold
(VDD fall)
LVD voltage threshold hysteresis
Vhys
VDD rise time rate 2) 4)
VtPOR
1)
LVD/AVD current consumption
IDD(LVD)
Conditions 3)
High Threshold
Med. Threshold
Low Threshold
High Threshold
Med. Threshold
Low Threshold
VIT+(LVD)-VIT-(LVD)
Min
3.50
3.30
2.50
3.30
3.20
2.40
20
VDD = 5V
Typ
4.00
3.70
2.65
3.80
3.50
2.70
150
220
Max
4.50
4.30
3.30
4.40
4.20
3.20
Unit
V
mV
µs/V
µA
Notes:
1. Not tested in production.
2. Not tested in production. The VDD rise time rate condition is needed to ensure a correct device power-on and LVD reset
release. When the VDD slope is outside these values, the LVD may not release properly the reset of the MCU.
3. LVD and AVD high thresholds must not be selected at the same time.
4. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is
recommended to pull VDD down to 0V to ensure optimum restart conditions. Refer to circuit example in Figure 62 on page
87.
12.3.3 Auxiliary Voltage Detector (AVD) Thresholds
TA = -40 to 125°C, unless otherwise specified
Symbol
Parameter
VIT+(AVD)
1=>0 AVDF flag toggle threshold
(VDD rise)
VIT-(AVD)
0=>1 AVDF flag toggle threshold
(VDD fall)
Vhys
∆VIT-
AVD voltage threshold hysteresis
Voltage drop between AVD flag set
and LVD reset activation
Conditions 1)
High Threshold
Med. Threshold
Low Threshold
High Threshold
Med. Threshold
Low Threshold
VIT+(AVD)-VIT-(AVD)
VDD fall
Notes:
1. LVD and AVD high thresholds must not be selected at the same time.
2. Not tested in production, guaranteed by characterization.
Note: Refer to section 7.4.2.1 on page 29
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1
Min 2)
3.50
3.30
2.50
3.40
3.20
2.40
Typ 2)
4.10
3.90
3.00
4.00
3.80
2.90
100
0.45
Max 2)
4.80
4.60
3.50
4.70
4.50
3.40
Unit
V
mV
V
ST7LITEUSx
OPERATING CONDITIONS (Cont’d)
12.3.4 Voltage drop between AVD flag set and LVD reset generation
Parameter
AVD med. Threshold - AVD low. threshold
AVD high. Threshold - AVD low threshold
AVD high. Threshold - AVD med. threshold
AVD low Threshold - LVD low threshold
AVD med. Threshold - LVD low threshold
AVD med. Threshold - LVD med. threshold
AVD high. Threshold - LVD low threshold
AVD high. Threshold - LVD med. threshold
Min 1)
700
900
100
0
800
50
850
200
Typ 1)
950
1150
200
100
1000
200
1250
400
Max 1)
1200
1400
300
300
1300
300
1700
600
Unit
mV
Note:
1. Not tested in production, guaranteed by characterization.
12.3.5 Internal RC oscillator
12.3.5.1 Internal RC oscillator calibrated at 5.0V
The ST7 internal clock can be supplied by an internal RC oscillator (selectable by option byte).
Symbol
fRC
ACCRC
IDD(RC)
tsu(RC)
Parameter
Conditions
RCCR = FF (reset value),
TA=25°C,VDD=5V
Internal RC oscillator frequency
RCCR = RCCR01),TA=25°C,VDD=5V
TA=25°C, VDD=5V
TA=25°C, VDD=4.5 to 5.5V
Accuracy of Internal RC oscillator TA=0 to +85°C, VDD=5V
with
TA=0 to +85°C, VDD=4.5 to 5.5V
RCCR=RCCR01)
TA=0 to +125°C, VDD=5V
TA=0 to +125°C, VDD=4.5 to 5.5V
TA=-40°C to 0°C, VDD=4.5 to 5.5V
RC oscillator current consumption TA=25°C, VDD=5V
RC oscillator setup time
TA=25°C, VDD=5V
Min
Typ
Max
4.5
Unit
MHz
8
-2
-3
-3.5
-4
-3.5
-5
-6
+2
+3
+4.5
+5
+6
+7
+5
900 2)
4 2)
%
%
%
%
%
%
%
µA
µs
Notes:
1. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 17
2. Guaranteed by Design.
To improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF,
between the VDD and VSS pins as close as possible to the ST7 device
71/108
1
ST7LITEUSx
12.3.5.2 Internal RC oscillator calibrated at 3.3V
The ST7 internal clock can be supplied by an internal RC oscillator (selectable by option byte).
Symbol
fRC
ACCRC
IDD(RC)
tsu(RC)
Parameter
Conditions
RCCR = FF (reset value),
TA=25°C,VDD=3.3V
Internal RC oscillator frequency
RCCR = RCCR11 ),TA=25°C,VDD=3.3V
TA=25°C, VDD=3.3V
TA=25°C, VDD=3.0 to 3.6V
Accuracy of Internal RC oscillator TA=0 to +85°C, VDD=3.3V
with
TA=0 to +85°C, VDD=3.0 to 3.6V
RCCR=RCCR11)
TA=0 to +125°C, VDD=3.3V
TA=0 to +125°C, VDD=3.0 to 3.6V
TA=-40°C to 0°C, VDD=3.0 to 3.6V
RC oscillator current consumption TA=25°C, VDD=3.3V
RC oscillator setup time
TA=25°C, VDD=3.3V
Min
Typ
Max
4.4
MHz
8
-2
-4
-4
-6
-5.5
-7
-6
+2
+4
+3.5
+5
+4.5
+5.5
+6
900 2)
4 2)
Notes:
1. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 17
2. Guaranteed by Design.
Figure 40. Internal RC oscillator frequency vs. temperature (RCCR=RCCR0) at VDD = 5.0V
fRC (MHz)
8.25
8
4.5V
5.0V
5.5V
7.75
-60
-40
-20
0
20
40
60
80
100
120
140
TA (°C)
Figure 41. Internal RC oscillator frequency vs. temperature (RCCR=RCCR1) at VDD = 3.3V
8.25
fRC (MHz)
8
7.75
3.0V
3.3V
3.6V
7.5
-60
-40
-20
0
20
40
TA (°C)
72/108
1
60
80
100
120
140
Unit
%
%
%
%
%
%
%
µA
µs
ST7LITEUSx
12.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST7 functional operating modes over temperature range does not take into account the clock
source current consumption. To get the total de12.4.1 Supply Current
TA = -40 to +125°C unless otherwise specified
Parameter
Supply current in WAIT mode
IDD
2)
Supply current in SLOW mode 3)
Supply current in SLOW-WAIT mode 4)
Supply current in AWUFH mode 5)6)
Supply current in ACTIVE HALT mode
Supply current in HALT mode 7)
Supply current in RUN mode 1)
Supply current in WAIT mode 2)
Supply current in SLOW mode 3)
Supply current in SLOW-WAIT mode 4)
Supply current in AWUFH mode 5)6)
Supply current in ACTIVE HALT mode
Supply current in HALT mode 7)
VDD=5V
Supply current in RUN mode
1)
VDD=3V
Symbol
vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped).
Conditions
fCPU = 4MHz
fCPU = 8MHz
fCPU = 4MHz
fCPU = 8MHz
fCPU/32 = 250kHz
fCPU/32 = 250kHz
fCPU = 4MHz
fCPU = 4MHz
fCPU/32 = 250kHz
fCPU/32 = 250kHz
Typ
2.5
5.0
1.0
1.5
650
500
40
100
0.5
1.5
0.5
350
285
15
70
0.25
Max
5.0
9.0
2.5
4.0
1100
900
120 8)
250
3
4.0 8)
2.5 8)
700 8)
600 8)
80 8)
200
3 8)
Unit
mA
µA
mA
µA
Notes:
1. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals
in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
2. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN)
driven by external square wave, LVD disabled.
3. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or
VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
4. SLOW-WAIT mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at
VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
5. All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max. and fCPU
max.
6. This consumption refers to the Halt period only and not the associated run period which is software dependent.
7. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results,
tested in production at VDD max and fCPU max.
8. Data based on characterization, not tested in production.
73/108
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ST7LITEUSx
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
Figure 42. Typical IDD in run mode vs. fCPU
Figure 45. Typical IDD in slow-wait mode
vs. fCPU
6.00
0.70
5.00
2MHz
0.60
4MHZ
2MHz
8MHz
4MHZ
0.50
8MHz
3.00
Idd [mA]
Idd [mA]
4.00
2.00
0.40
0.30
0.20
1.00
0.10
0.00
2.4 2.6 2.8 3
3.2 3.4 3.6 3.8 4
4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8
0.00
2.4 2.6 2.8 3
Vdd [V]
3.2 3.4 3.6 3.8 4
4.2 4.4 4.6 4.8 5
5.2 5.4 5.6 5.8
Vdd [V]
Figure 43. Typical IDD in slow mode vs. fCPU
0.80
Figure 46. Typical IDD vs. temperature
at VDD = 5V and fCPU = 8MHz
0.70
5.00
2MHz
0.60
4.50
8MHz
4.00
RUN
WAIT
3.50
0.40
Idd [mA]
Idd [mA]
0.50
4MHZ
0.30
0.20
0.10
SLOW
3.00
SLOWWAIT
2.50
2.00
1.50
1.00
0.00
2.4 2.6 2.8 3
3.2 3.4 3.6 3.8 4
4.2 4.4 4.6 4.8 5
5.2 5.4 5.6 5.8
0.50
Vdd [V]
0.00
-45
Figure 44. Typical IDD in wait mode vs. fCPU
1.80
1.60
Idd [mA]
2MHz
1.40
4MHZ
1.20
8MHz
1.00
0.80
0.60
0.40
0.20
0.00
2.4 2.6 2.8 3
3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5
Vdd [V]
74/108
1
5.2 5.4 5.6 5.8
25
Vdd [V]
90
ST7LITEUSx
12.4.2 On-chip peripherals
Symbol
IDD(AT)
IDD(ADC)
Parameter
12-bit Auto-Reload Timer supply current 1)
ADC supply current when converting 2)
Conditions
fCPU=4MHz
VDD=3.0V
VDD=5.0V
fCPU=8MHz
fADC=2MHz
VDD=3.0V
VDD=5.0V
fADC=4MHz
Typ 3)
15
30
450
750
Unit
µA
Notes:
1. Data based on a differential IDD measurement between reset configuration (timer stopped) and the timer running in
PWM mode at fcpu=8MHz.
2. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions with amplifier off.
3. Not tested in production, guaranteed by characterization.
75/108
1
ST7LITEUSx
12.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for VDD, fOSC, and TA.
12.5.1 General Timings
Parameter 1)
Symbol
tc(INST)
tv(IT)
Instruction cycle time
Interrupt reaction time
tv(IT) = ∆tc(INST) + 10
Conditions
fCPU=8MHz
3)
fCPU=8MHz
Min
Typ 2)
Max
Unit
2
3
12
tCPU
250
375
1500
ns
10
22
tCPU
1.25
2.75
µs
Notes:
1. Data based on characterization. Not tested in production.
2. Data based on typical application software.
3. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish the current instruction execution.
12.5.2 Auto Wakeup RC Oscillator
Parameter
Conditions
Min
Typ
Supply Voltage Range
2.4
5.0
5.5
V
Operating Temperature Range
-40
25
125
°C
2.0
8.0
14.0
Current Consumption 1)
Without prescaler
Consumption 1)
AWU RC switched off
Output Frequency 1)
Note:
1. Data guaranteed by Design.
76/108
1
Max
0
20
33
Unit
µA
µA
60
kHz
ST7LITEUSx
12.6 MEMORY CHARACTERISTICS
TA = -40°C to 125°C, unless otherwise specified
12.6.1 RAM and Hardware Registers
Symbol
VRM
Parameter
Data retention mode
1)
Conditions
HALT mode (or RESET)
Min
Typ
Max
1.6
Unit
V
12.6.2 FLASH Program Memory
Symbol
VDD
tprog
tRET
NRW
IDD
Parameter
Operating voltage for Flash write/erase
Programming time for 1~32 bytes 2)
Programming time for 1 kByte
Data retention 4)
Write erase cycles
Supply current 6)
Conditions
Min
2.4
TA=−40 to +125°C
TA=+25°C
TA=+55°C 3)
20
TA=+25°C
10k 7)
Read / Write / Erase
modes
fCPU = 8MHz, VDD = 5.5V
No Read/No Write Mode
Power down mode / HALT
Typ
5
0.16
Max
5.5
10
0.32
2.6
0
100
0.1
Unit
V
ms
s
years
cycles
mA
µA
µA
Notes:
1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware registers (only in HALT mode). Guaranteed by construction, not tested in production.
2. Up to 32 bytes can be programmed at a time.
3. The data retention time increases when the TA decreases.
4. Data based on reliability test results and monitored in production.
5. Data based on characterization results, not tested in production.
6. Guaranteed by Design. Not tested in production.
7. Design target value pending full product characterization.
77/108
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ST7LITEUSx
12.7 EMC CHARACTERISTICS
Susceptibility tests are performed on a sample basis during product characterization.
12.7.1 Functional EMS (Electro Magnetic
Susceptibility)
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
■ FTB: A Burst of Fast Transient voltage (positive
and negative) is applied to VDD and VSS through
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-44 standard.
A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined
in application note AN1709.
12.7.1.1 Designing hardened software to avoid
noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It
Symbol
VFESD
VFFTB
78/108
1
Parameter
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
Software recommendations:
The software flowchart must include the management of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical Data corruption (control registers...)
Prequalification trials:
Most of the common failures (unexpected reset
and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behaviour
is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Conditions
VDD=5V, TA=+25°C, fOSC=8MHz,
Voltage limits to be applied on any I/O pin to induce a
SO8 package,
functional disturbance
conforms to IEC 1000-4-2
VDD=5V, TA=+25°C, fOSC=8MHz,
Fast transient voltage burst limits to be applied
through 100pF on VDD and VDD pins to induce a func- SO8 package,
tional disturbance
conforms to IEC 1000-4-4
Level/
Class
3B
4B
ST7LITEUSx
EMC CHARACTERISTICS (Cont’d)
12.7.2 Electro Magnetic Interference (EMI)
Based on a simple application running on the
product (toggling 2 LEDs through the I/O ports),
the product is monitored in terms of emission. This
emission test is in line with the norm SAE J 1752/
3 which specifies the board and the loading of
each pin.
Symbol
SEMI
Parameter
Monitored
Frequency Band
Conditions
0.1MHz to 30MHz
VDD=5V, TA=+25°C,
30MHz to 130MHz
SO8 package,
conforming to SAE J 1752/3 130MHz to 1GHz
SAE EMI Level
Peak level
Max vs. [fOSC/fCPU]
-/8MHz
21
23
10
3
Unit
dBµV
-
Note:
1. Data based on characterization results, not tested in production.
12.7.3 Absolute Maximum Ratings (Electrical
Sensitivity)
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, refer to the application note AN1181.
12.7.3.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends on the
number of supply pins in the device (3 parts*(n+1)
supply pin). One model can be simulated: Human
Body Model. This test conforms to the JESD22A114A/A115A standard.
Absolute Maximum Ratings
Symbol
VESD(HBM)
Ratings
Electro-static discharge voltage
(Human Body Model)
Conditions
TA=+25°C
Maximum value 1) Unit
> 4000
V
Note:
1. Data based on characterization results, not tested in production.
79/108
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ST7LITEUSx
EMC CHARACTERISTICS (Cont’d)
12.7.3.2 Static and Dynamic Latch-Up
■ LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin) and a current injection (applied to
each input, output and configurable I/O pin) are
performed on each sample. This test conforms
to the EIA/JESD 78 IC latch-up standard. For
more details, refer to the application note
AN1181.
■
DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards. For more details, refer to the
application note AN1181.
Electrical Sensitivities
Symbol
LU
DLU
Parameter
Conditions
Class 1)
Static latch-up class
TA=+125°C
A
Dynamic latch-up class
VDD=5.5V, fOSC=4MHz, TA=+25°C
A
Note:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
80/108
1
ST7LITEUSx
12.8 I/O PORT PIN CHARACTERISTICS
12.8.1 General Characteristics
Subject to general operating conditions for VDD,
fOSC, and TA unless otherwise specified.
Symbol
Parameter
Conditions
VIL
Input low level voltage
VIH
Input high level voltage
Vhys
Schmitt trigger voltage
hysteresis 1)
IL
Input leakage current
IS
Static current consumption induced by each floating input Floating input mode
pin2)
RPU
Weak pull-up equivalent
resistor 3) 5)
CIO
I/O pin capacitance
Min
-40°C to 125°C
Typ
Max
Unit
0.3xVDD
V
0.7 x VDD
400
VSS≤VIN≤VDD
VIN=VSS
tf(IO)out
Output high to low level fall
time 1)
tr(IO)out
Output low to high level rise
time 1)
tw(IT)in
External interrupt pulse time 4)
mV
±1
µA
400
VDD=5V
80
VDD=3V
120
170
200 1)
kΩ
5
pF
25
CL=50pF
Between 10% and 90%
ns
25
1
tCPU
Notes:
1. Data based on characterization results, not tested in production.
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 51). Static peak current value taken at a fixed VIN value,
based on design simulation and technology characteristics, not tested in production. This value depends on VDD and temperature values.
3. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in Figure 48).
4. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
5. RPU not applicable on PA3 because it is multiplexed on RESET pin
Figure 47. Two typical Applications with unused I/O Pin
VDD
ST7XXX
10kΩ
10kΩ
UNUSED I/O PORT
UNUSED I/O PORT
ST7XXX
Caution: During normal operation the ICCCLK pin must be pulled- up, internally or externally
(external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset.
Note: I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC
robustness and lower cost.
81/108
1
ST7LITEUSx
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure
48. Typical IPU vs. VDD with VIN=VSS
l
IPU [uA]
90
80
-45°C
70
25°C
60
90°C
50
40
30
20
10
6
5.
6
5.
2
4.
8
4.
4
4
3.
6
3.
2
2.
8
2.
4
0
VDD [V]
12.8.2 Output Driving Current
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Symbol
Parameter
Conditions
VOL 1)3)
VOH 2)3)
VOL 1)3)
VOH 2)3)
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 58)
Output low level voltage for PA3/RESET standard
I/O pin
(see Figure 50)
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 53)
VDD=3V
VOH 2)
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 54)
Min
Max
IIO=+5mA,TA≤125°C
1200
IIO=+2mA,TA≤125°C
400
IIO=+20mA,
TA≤125°C
1300
IIO=+8mA,TA≤125°C
VDD-1500
IIO=-2mA,TA≤125°C
VDD-800
IIO=+2mA,TA≤125°C
250
IIO=+2mA,TA≤125°C
150
IIO=+8mA,TA≤125°C
500
IIO=-2mA,TA≤125°C
Output low level voltage for PA3/RESET standard
I/O pin (see Figure 49)
IIO=+2mA,TA≤125°C
500
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 52)
IIO=+2mA,TA≤125°C
200
IIO=+8mA,TA≤125°C
600
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 55)
IIO=-2mA,TA≤125°C
Unit
750
IIO=-5mA,TA≤125°C
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 56)
VDD=2.4V
VOL 1)
VDD=5V
Output low level voltage for PA3/RESET standard
I/O pin (see Figure 51)
mV
VDD-800
VDD-900
Notes:
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of
IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins do not have VOH.
3. Not tested in production, based on characterization results.
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ST7LITEUSx
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 49. Typical vOL at vDD = 2.4V (standard
pins)
Figure 52. Typical VOL at VDD = 2.4V (HS pins)
1200
1000
-45°C
VOL (mV) at VDD=2.4 V(STD)
25°C
1000
25°C
-45°C
90°C
800
90°C
Vol [mV]
800
600
600
400
400
200
200
0
0
2
4
6
8
0
0
2
4
10
12
14
16
18
20
ILOAD[mA]
6
ILOAD (mA)
Figure 50. Typical vol at vdd = 3V (standard
pins)
Figure 53. Typical VOL at VDD = 3V (HS pins)
1200
1000
-45°C
25°C
90°C
800
Vol [mV]
VOL (mV) at VDD=3 V(STD)
1000
25°C
800
600
-45°C
90°C
600
400
400
200
200
0
0
2
4
6
8
0
10
12
14
16
18
20
ILOAD[mA]
0
2
4
6
ILOAD (mA)
Figure 51. Typical VOL at VDD = 5V (standard
pins)
Figure 54. Typical VOL at VDD = 5V (HS pins)
1000
800
-45°C
900
25°C
-45°C
700
Vol [mV]
VOL (mV) at VDD=5V(STD)
25°C
800
90°C
600
400
90°C
600
500
400
300
200
200
100
0
0
0
2
4
6
8
10
12
14
16
18
20
ILOAD[mA]
0
2
4
6
ILOAD (mA)
83/108
1
ST7LITEUSx
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 55. Typical VDD-VOH at VDD = 2.4V (HS
pins)
Figure 57. Typical VDD-VOH at VDD = 4V (HS
pins)
700
1200
1000
-45°C
25°C
-45°C
25°C
90°C
600
90°C
500
VDD-VOH [mV]
VDD-VOH [mV]
800
600
400
400
300
200
200
100
0
0
-2
-4
-6
-8
-10
0
-12
0
ILOAD [mA]
-2
-4
-6
-8
-10
-12
ILOAD [mA]
Figure 56. Typical VDD-VOH at VDD = 3V (HS
pins)
Figure 58. Typical VDD-VOH at VDD = 5V (HS
pins)
600
1000
900
-45°C
25°C
90°C
800
700
400
VDD-VOH [mV]
VDD-VOH [mV]
-45°C
25°C
90°C
500
600
500
400
300
200
300
200
100
100
0
0
0
-2
-4
-6
-8
-10
-12
0
-2
-4
-6
Iload [mA]
-8
-10
-12
Iload [mA]
Figure 59. Typical VOL vs. VDD (standard I/Os)
500
-45°C
450
25°C
VOL [mV] at Iload=2mA
400
90°C
350
300
250
200
150
100
50
0
2.4
3
3.4
4
4.4
VDD [V}
84/108
1
5
5.4
6
ST7LITEUSx
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 60. Typical VOL vs. VDD (HS pins)
900
500
-45°C
25°C
90°C
450
700
Vol [mV] at ILOAD = 12mA
Vol [mV] at ILOAD = 8mA
400
-45°C
25°C
90°C
800
350
300
250
200
150
600
500
400
300
100
200
50
100
0
0
2.4
3
3.4
4
4.4
5
5.4
6
2.4
3
3.4
4
Vdd [V]
4.4
5
5.4
6
Vdd [V]
Figure 61. Typical VDD-VOH vs. VDD (HS pins)
600
180
160
VDD-VOH [mV] at ILOAD = 6mA
VDD-VOH [mV] at ILOAD=2 mA
500
140
120
100
80
60
-45°C
40
25°C
300
200
-45°C
25°C
100
90°C
20
400
90°C
0
2.4
3
3.4
4
4.4
VDD [V]
5
5.4
6
0
2.4
3
3.4
4
4.4
5
5.4
6
VDD [V]
85/108
1
ST7LITEUSx
12.9 CONTROL PIN CHARACTERISTICS
12.9.1 Asynchronous RESET Pin
TA = -40°C to 125°C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
VIL
Input low level voltage
VSS - 0.3
0.3xVDD
VIH
Input high level voltage
0.7xVDD
VDD + 0.3
Vhys
Schmitt trigger voltage hysteresis 1)
VOL
Output low level voltage 2)
VDD=5V IIO=+2mA
RON
Pull-up equivalent resistor 3)
VIN=VSS
tw(RSTL)out Generated reset pulse duration
th(RSTL)in
External reset pulse hold time
tg(RSTL)in
Filtered glitch duration
4)
2
VDD=5V
VDD=3V
50
90
1)
90 1)
Internal reset sources
V
V
400
30
Unit
70
mV
kΩ
µs
µs
20
200
ns
Notes:
1. Data based on characterization results, not tested in production.
2. The IIO current sunk must always respect the absolute maximum rating specified in section 12.2.2 on page 68 and the
sum of IIO (I/O ports and control pins) must not exceed IVSS.
3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between
VILmax and VDD
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.
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1
ST7LITEUSx
CONTROL PIN CHARACTERISTICS (Cont’d)
Figure 62. RESET pin protection when LVD is enabled.1)2)3)4)
ST72XXX
VDD
Optional
(note 3)
Required
RON
EXTERNAL
RESET
INTERNAL
RESET
Filter
0.01µF
1MΩ
PULSE
GENERATOR
WATCHDOG
ILLEGAL OPCODE 5)
LVD RESET
Figure 63. RESET pin protection when LVD is disabled.1)
VDD
ST72XXX
RON
USER
EXTERNAL
RESET
CIRCUIT
INTERNAL
RESET
Filter
0.01µF
Required
PULSE
GENERATOR
WATCHDOG
ILLEGAL OPCODE 5)
Note 1:
– The reset network protects the device against parasitic resets.
– The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the
device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
– Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go
below the VIL max. level specified in section 12.9.1 on page 86. Otherwise the reset will not be taken into account
internally.
– Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for IINJ(RESET) in
section 12.2.2 on page 68.
Note 2: When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down
capacitor is required to filter noise on the reset line.
Note 3: In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the RESET
pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power
consumption of the MCU).
Note 4: Tips when using the LVD:
– 1. Check that all recommendations related to ICCCLK and reset circuit have been applied (see caution in Table 1
on page 7 and notes above)
– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and
AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin.
– 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality.
In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the
RESET pin with a 5µF to 20µF capacitor.”
Note 5: Please refer to “Illegal Opcode Reset” on page 64 for more details on illegal opcode reset conditions
87/108
1
ST7LITEUSx
12.10 10-BIT ADC CHARACTERISTICS
Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
Symbol
Parameter
fADC
ADC clock frequency
VAIN
Conversion voltage range 3)
RAIN
Conditions
Min
Typ 1)
2)
VSSA
External input resistor
8k
7k 4)
2.7V ≤ VDD ≤5.5V, fADC=2MHz
10k 4)
2.4V ≤ VDD ≤2.7V, fADC=1MHz
TBD 4)
3
Stabilization time after ADC enable
0 5)
3.5
fCPU=8MHz, fADC=4MHz
4
10
V
4)
VDD = 5V, fADC=4MHz
Internal sample and hold capacitor
- Sample capacitor loading time
- Hold conversion time
MHz
VDD = 3.3V, fADC=4MHz
tSTAB
tADC
Unit
4
VDDA
CADC
Conversion time (Sample+Hold)
Max
Ω
pF
µs
1/fADC
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guidelines and are not tested.
2. The maximum ADC clock frequency allowed within VDD = 2.4V to 2.7V operating range is 1MHz.
3. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.
4. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
5. The stabilization time of the A/D converter is masked by the first tLOAD. The first conversion after the enable is then
always valid.
Figure 64. Typical Application with ADC
VDD
VT
0.6V
RAIN
AINx
10-Bit A/D
Conversion
VAIN
VT
0.6V
IL
±1µA
CADC
ST7LITEUSx
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ST7LITEUSx
ADC CHARACTERISTICS (Cont’d)
ADC Accuracy with VDD = 3.3V to 5.5V
Symbol 1)
Parameter
Conditions
Typ
Max
2.1
5.0
|ET|
Total unadjusted error
|EO|
Offset error
|EG|
Gain Error
|ED|
Differential linearity error
1.9
3.5
|EL|
Integral linearity error
1.9
4.5
Typ
Max
fCPU=8MHz, fADC=4MHz 1)
0.2
2.5
0.3
1.5
Unit
LSB
Note:
1. Data based on characterization results over the whole temperature range.
ADC Accuracy with VDD = 2.7V to 3.3V
Symbol 1)
Parameter
Conditions
|ET|
Total unadjusted error
2.0
3.0
|EO|
Offset error
0.1
1.5
1)
|EG|
Gain Error
0.4
1.4
|ED|
Differential linearity error
1.8
2.5
|EL|
Integral linearity error
1.7
2.5
Typ
Max
2.2
3.5
fCPU=4MHz, fADC=2MHz
Unit
LSB
Note:
1. Data based on characterization results over the whole temperature range.
ADC Accuracy with VDD = 2.4V to 2.7V
Symbol 1)
Parameter
|ET|
Total unadjusted error
|EO|
Offset error
|EG|
Gain Error
Conditions
fCPU=2MHz, fADC=1MHz 1)
0.5
1.5
0.5
1.5
|ED|
Differential linearity error
1.8
2.5
|EL|
Integral linearity error
1.8
2.5
Unit
LSB
Note:
1. Data based on characterization results at a temperature range ≥ 25°C.
89/108
1
ST7LITEUSx
ADC CHARACTERISTICS (Cont’d)
Figure 65. ADC Accuracy Characteristics
Digital Result ADCDR
EG
1023
1022
1LSB
1021
IDEAL
V
–V
DD
SS
= --------------------------------
1024
(2)
ET
(3)
7
(1)
6
5
EO
4
EL
3
ED
2
1 LSBIDEAL
1
0
1
VSS
90/108
1
2
3
4
5
6
7
1021 1022 1023 1024
VDD
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
ET=Total Unadjusted Error: maximum deviation between the actual and the ideal
transfer curves.
EO=Offset Error: deviation between the first
actual transition and the first ideal one.
EG=Gain Error: deviation between the last
ideal transition and the last actual one.
ED=Differential Linearity Error: maximum
deviation between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation between any actual transition and the
end point correlation line.
Vin (LSBIDEAL)
ST7LITEUSx
13 PACKAGE CHARACTERISTICS
In order to meet environmental requirements, ST
offers these devices in ECOPACK® packages.
These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
13.1 PACKAGE MECHANICAL DATA
Figure 66. 8-Lead Very thin Fine pitch Dual Flat No-Lead Package
D
Dim.
INDEX AREA
(D/2 x E/2)
E
Min
Typ
Max
A
0.80
0.90
1.00
0.031 0.035 0.039
A1
0.00
0.02
0.05
0.000 0.001 0.002
A3
b
TOP VIEW
0.20
0.25
D
A3
D2
A
3.50
L
b
3.65
2.11
0.30
0.40
Typ
Max
0.35
0.010 0.012 0.014
3.75
0.138 0.144 0.148
2.21
0.077 0.083 0.087
0.50
0.012 0.016 0.020
0.177
3.50
1.96
e
e
0.30
Min
0.008
4.50
E
E2
A1
SIDE VIEW
inches1)
mm
0.138
0.80
0.031
Number of Pins
E2
INDEX AREA
(D/2 x E/2)
N
8
Note 1. Values in inches are converted from mm
and rounded to 3 decimal digits.
L
D2
BOTTOM VIEW
91/108
1
ST7LITEUSx
PACKAGE CHARACTERISTICS (Cont’d)
Figure 67. 8-Pin Plastic Small Outline Package, 150-mil Width
D
h x 45°
Dim.
A2 A
A1
α
B
C
L
Min
H
Typ
Max
Min
Typ
Max
A
1.35
1.75 0.053
0.069
A1
0.10
0.25 0.004
0.010
A2
1.10
1.65 0.043
0.065
B
0.33
0.51 0.013
0.020
C
0.19
0.25 0.007
0.010
D
4.80
5.00 0.189
0.197
E
3.80
4.00 0.150
e
E
inches1)
mm
1.27
0.158
0.050
H
5.80
6.20 0.228
0.244
0.50 0.010
0.020
h
0.25
α
0d
L
0.40
8d
1.27 0.016
0.050
Number of Pins
N
8
Note 1. Values in inches are converted from
mm and rounded to 3 decimal digits.
e
Figure 68. 8-Pin Plastic Dual In-Line Package, 300-mil Width
E
Dim.
A2
A
L
b2
eB
e
D1
D
c
b3
b
D
Min
Typ
A
A1
E1
1
4
Min
Typ
Max
0.210
A1
0.38
A2
2.92
3.30
4.95 0.115 0.130 0.195
0.015
b
0.36
0.46
0.56 0.014 0.018 0.022
b2
1.14
1.52
1.78 0.045 0.060 0.070
b3
0.76
0.99
1.14 0.030 0.039 0.045
c
0.20
0.25
0.36 0.008 0.010 0.014
D
9.02
9.27 10.16 0.355 0.365 0.400
D1
0.13
0.005
2.54
eB
5
Max
5.33
e
8
inches1)
mm
0.100
10.92
0.430
E
7.62
7.87
8.26 0.300 0.310 0.325
E1
6.10
6.35
7.11 0.240 0.250 0.280
L
2.92
3.30
3.81 0.115 0.130 0.150
Number of Pins
N
8
Note 1. Values in inches are converted from
mm and rounded to 3 decimal digits.
92/108
1
ST7LITEUSx
PACKAGE CHARACTERISTICS (Cont’d)
Figure 69. 16-Pin Plastic Dual In-Line Package, 300-mil Width
Dim.
E
inches1)
mm
Min
Typ
Max
A
A2
A1
A
L
b2
D1
Typ
Max
0.210
A1
0.38
A2
2.92
3.30
4.95 0.115 0.130 0.195
0.015
b
0.36
0.46
0.56 0.014 0.018 0.022
E1
b2
1.14
1.52
1.78 0.045 0.060 0.070
eB
b3
0.76
0.99
1.14 0.030 0.039 0.045
c
0.20
0.25
0.36 0.008 0.010 0.014
D
18.67 19.18 19.69 0.735 0.755 0.775
D1
0.13
c
b
e
b3
Min
5.33
D
e
0.005
2.54
0.100
E
7.62
7.87
8.26 0.300 0.310 0.325
E1
6.10
6.35
7.11 0.240 0.250 0.280
L
2.92
3.30
eB
3.81 0.115 0.130 0.150
10.92
0.430
Number of Pins
N
16
Note 1. Values in inches are converted from
mm and rounded to 3 decimal digits.
Table 21. THERMAL CHARACTERISTICS
Symbol
Ratings
RthJA
Package thermal resistance
(junction to ambient)
TJmax
Maximum junction temperature 1)
PDmax
Power dissipation 2)
Value
DIP8
82
SO8
130
DFN8 (on 4-layer PCB)
DFN8 (on 2-layer PCB)
50
106
150
DIP8
300
SO8
180
DFN8 (on 4-layer PCB)
500
DFN8 (on 2-layer PCB)
250
Unit
°C/W
°C
mW
Notes:
1. The maximum chip-junction temperature is based on technology characteristics.
2. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA.
The power dissipation of an application can be defined by the user with the formula: PD=PINT+PPORT where PINT is the
chip internal power (IDD x VDD) and PPORT is the port power dissipation depending on the ports used in the application.
93/108
1
ST7LITEUSx
13.2 SOLDERING INFORMATION
In accordance with the RoHS European directive,
all STMicroelectronics packages have been converted to lead-free technology, named ECOPACKTM.
TM packages are qualified according
■ ECOPACK
to the JEDEC STD-020C compliant soldering
profile.
■ Detailed information on the STMicroelectronics
ECOPACKTM transition program is available on
www.st.com/stonline/leadfree/, with specific
technical Application notes covering the main
technical aspects related to lead-free
conversion (AN2033, AN2034, AN2035,
AN2036).
Backward and forward compatibility:
The main difference between Pb and Pb-free soldering process is the temperature range.
– ECOPACKTM LQFP, SDIP, SO and DFN8 packages are fully compatible with Lead (Pb) containing soldering process (see application note
AN2034)
– LQFP, SDIP and SO Pb-packages are compatible with Lead-free soldering process, nevertheless it's the customer's duty to verify that the Pbpackages maximum temperature (mentioned on
the Inner box label) is compatible with their Leadfree soldering temperature.
Table 22. Soldering Compatibility (wave and reflow soldering process)
Package
SDIP & PDIP
DFN8
TQFP and SO
Plating material devices
Sn (pure Tin)
Sn (pure Tin)
NiPdAu (Nickel-palladium-Gold)
Pb solder paste
Yes
Yes
Yes
Pb-free solder paste
Yes *
Yes *
Yes *
* Assemblers must verify that the Pb-package maximum temperature (mentioned on the Inner box label)
is compatible with their Lead-free soldering process.
94/108
1
ST7LITEUSx
14 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user programmable versions (FLASH) as well as in factory
coded versions (FASTROM).
ST7PLITEUS2 and ST7PLITEUS5 devices are
Factory Advanced Service Technique ROM (FASTROM) versions: they are factory-programmed
XFlash devices.
ST7FLITEUS2 and ST7FLITEUS5 XFlash devices
are shipped to customers with a default program
memory content (FFh).
The FASTROM factory coded parts contain the
code supplied by the customer. This implies that
FLASH devices have to be configured by the customer using the Option Bytes while the FASTROM
devices are factory-configured.
14.1 OPTION BYTES
The two option bytes allow the hardware configuration of the microcontroller to be selected.
The option bytes can be accessed only in programming mode (for example using a standard
ST7 programming tool).
OPTION BYTE 1
Bit 7:6 = CKSEL[1:0] Start-up clock selection.
This bit is used to select the startup frequency. By
default, the Internal RC is selected.
Configuration
Internal RC as Startup Clock
OPTION BYTE 0
Bits 7:4 = Reserved, must always be 1.
CKSEL1 CKSEL0
0
Bit 3 = Reserved, must always be 0.
0
AWU RC as a Startup Clock
0
1
Reserved
1
0
External Clock on pin PA5
1
1
Bit 2 = SEC0 Sector 0 size definition
This option bit indicates the size of sector 0 according to the following table.
Bit 5 = Reserved, must always be 1.
Bit 4 = Reserved, must always be 0.
Bits 3:2 = LVD[1:0] Low Voltage Detection selection
These option bits enable the LVD block with a selected threshold as shown in Table 23.
Table 23. LVD Threshold Configuration
Configuration
Bit 0 = WDG HALT Watchdog Reset on Halt
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
LVD1 LVD0
LVD Off
1
1
Highest Voltage Threshold
1
0
Medium Voltage Threshold
0
1
Lowest Voltage Threshold
0
0
Bit 1 = WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
Sector 0 Size
SEC0
0.5k
0
1k
1
Bit 1 = FMP_R Read-out protection
Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory.
Erasing the option bytes when the FMP_R option
is selected will cause the whole memory to be
erased first, and the device can be reprogrammed.
Refer to Section 4.5 and the ST7 Flash Programming Reference Manual for more details.
0: Read-out protection off
1: Read-out protection on
Bit 0 = FMP_W FLASH write protection
This option indicates if the FLASH program memory is write protected.
Warning: When this option is selected, the program memory (and the option bit itself) can never
be erased or programmed again.
0: Write protection off
1: Write protection on
95/108
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ST7LITEUSx
OPTION BYTES (Cont’d)
OPTION BYTE 0
OPTION BYTE 1
7
0
96/108
1
1
1
1
0
SEC FMP FMP CKS CKS
0
R
W
EL1 EL0
Reserved
Default
Value
7
1
0
0
0
0
0
0
Res
1
WDG WDG
Res LVD1 LVD0
SW HALT
0
1
1
1
1
ST7LITEUSx
14.2 ORDERING INFORMATION
Customer code is made up of the FASTROM contents and the list of the selected options (if any).
The FASTROM contents are to be sent on diskette, or by electronic means, with the S19 hexadecimal file generated by the development tool. All
unused bytes must be set to FFh. The selected options are communicated to STMicroelectronics us-
ing the correctly completed OPTION LIST appended.
Refer to application note AN1635 for information
on the counter listing returned by ST after code
has been transferred.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on contractual points.
Table 24. Supported part numbers
Part Number
Program
Memory
(Bytes)
RAM
(Bytes)
ADC
Temp.
Range
Package
Conditioning
ST7FLITEUS2B6
-
DIP8
Tube
ST7FLITEUS2M6
-
SO8
Tube
ST7FLITEUS2M6TR
1K FLASH
128
SO8
Tape & Reel
-
DFN8
Tape & Reel
ST7FLITEUS5B6
10-bit
DIP8
Tube
ST7FLITEUS5M6
10-bit
SO8
Tube
ST7FLITEUS2U6TR
ST7FLITEUS5M6TR
1K FLASH
128
ST7FLITEUS5U6
10-bit
-40°C +85°C
10-bit
ST7FLITEUS5U6TR
ST7FLITEUSICD
-
-40°C +85°C
10-bit
1K FLASH
128
-
-40°C +125°C
SO8
Tape & Reel
DFN8
Tray
DFN8
Tape & Reel
DIP16 1)
Tube
ST7PLITEUS2B6
-
DIP8
Tube
ST7PLITEUS2M6
-
SO8
Tube
SO8
Tape & Reel
-
DFN8
Tape & Reel
10-bit
DIP8
Tube
ST7PLITEUS2M6TR
1K FASTROM
128
ST7PLITEUS2U6TR
ST7PLITEUS5B6
ST7PLITEUS5M6
ST7PLITEUS5M6TR
-
-40°C +85°C
10-bit
1K FASTROM
128
10-bit
-40°C +85°C
SO8
Tube
SO8
Tape & Reel
ST7PLITEUS5U6
10-bit
DFN8
Tray
ST7PLITEUS5U6TR
10-bit
DFN8
Tape & Reel
ST7FLITEUS2B3
-
DIP8
Tube
ST7FLITEUS2M3
-
SO8
Tube
ST7FLITEUS2M3TR
1K FLASH
128
ST7FLITEUS2U3TR
ST7FLITEUS5B3
ST7FLITEUS5M3
ST7FLITEUS5M3TR
-
-40°C +125°C
SO8
Tape & Reel
-
DFN8
Tape & Reel
10-bit
DIP8
Tube
10-bit
1K FLASH
128
10-bit
-40°C +125°C
SO8
Tube
SO8
Tape & Reel
ST7FLITEUS5U3
10-bit
DFN8
Tray
ST7FLITEUS5U3TR
10-bit
DFN8
Tape & Reel
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1
ST7LITEUSx
ST7PLITEUS2B3
-
DIP8
Tube
ST7PLITEUS2M3
-
SO8
Tube
ST7PLITEUS2M3TR
1K FASTROM
128
SO8
Tape & Reel
-
DFN8
Tape & Reel
ST7PLITEUS5B3
10-bit
DIP8
Tube
ST7PLITEUS5M3
10-bit
SO8
Tube
ST7PLITEUS2U3TR
ST7PLITEUS5M3TR
1K FASTROM
128
-
-40°C +125°C
SO8
Tape & Reel
ST7PLITEUS5U3
10-bit
10-bit
-40°C +125°C
DFN8
Tray
ST7PLITEUS5U3TR
10-bit
DFN8
Tape & Reel
Contact ST sales office for product availability
Note:
1. For development or tool prototyping purposes only, not orderable in production quantities.
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ST7LITEUSx
ST7LITEUS FASTROM MICROCONTROLLER OPTION LIST
(Last update: January 2007)
Customer
Address
..........................................................................
..........................................................................
..........................................................................
Contact
..........................................................................
Phone No
..........................................................................
Reference FASTROM Code*: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
*FASTROM code name is assigned by STMicroelectronics.
FASTROM code must be sent in .S19 format. .Hex extension cannot be processed.
Device Type/Memory Size/Package (check only one option):
--------------------------------- | | ----------------------------------------FASTROM DEVICE:
1K FASTROM
--------------------------------- | | ----------------------------------------PDIP8:
||
[]
SO8:
||
[]
DFN8:
||
[]
Conditioning (check only one option):
DIP package:
SO package:
DFN package:
[ ] Tube
[ ] Tape & Reel
[ ] Tape & Reel
[ ] Tube
[ ] Tray (for ST7PLITEUS5U6 and ST7PLITEUS5U3 only)
Special Marking:
[ ] No
[ ] Yes "_ _ _ _ _ _ _ _ "
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Maximum character count:
PDIP8/SO8/DFN8 (8 char. max) : _ _ _ _ _ _ _ _
Temperature range:
Clock Source Selection:
[ ] -40°C to +85°C
[ ] -40°C to +125°C
[ ] External Clock
[ ] AWU RC Oscillator
[ ] Internal RC Oscillator
Sector 0 size:
[ ] 0.5K
[ ] 1K
Readout Protection:
FLASH Write Protection
LVD Reset
[ ] Disabled
[ ] Disabled
[ ] Disabled
[ ] Enabled
[ ] Enabled
[ ] Highest threshold
[ ] Medium threshold
[ ] Lowest threshold
Watchdog Selection:
[ ] Software Activation
[ ] Hardware Activation
Watchdog Reset on Halt:
[ ] Disabled
[ ] Enabled
Comments : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes
..........................................................................
Date:
..........................................................................
Signature:
..........................................................................
Important note: Not all configurations are available. See section 14.1 on page 95 for authorized option byte
combinations.
Please download the latest version of this option list from:
http://www.st.com/mcu > downloads > ST7 microcontrollers > Option list
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ST7LITEUSx
14.3 DEVELOPMENT TOOLS
Development tools for the ST7 microcontrollers include a complete range of hardware systems and
software tools from STMicroelectronics and thirdparty tool suppliers. The range of tools includes
solutions to help you evaluate microcontroller peripherals, develop and debug your application, and
program your microcontrollers.
14.3.1 Starter kits
ST offers complete, affordable starter kits. Starter
kits are complete, affordable hardware/software
tool packages that include features and samples
to help you quickly start developing your application.
14.3.2 Development and debugging tools
Application development for ST7 is supported by
fully optimizing C Compilers and the ST7 Assembler-Linker toolchain, which are all seamlessly integrated in the ST7 integrated development environments in order to facilitate the debugging and
fine-tuning of your application. The Cosmic C
Compiler is available in a free version that outputs
up to 16KBytes of code.
The range of hardware tools includes full-featured
ST7-EMU3 series emulators, cost effective ST7DVP3 series emulators and the low-cost RLink
in-circuit debugger/programmer. These tools are
supported by the ST7 Toolset from STMicroelectronics, which includes the STVD7 integrated development environment (IDE) with high-level lan-
guage debugger, editor, project manager and integrated programming interface.
14.3.3 Programming tools
During the development cycle, the ST7-DVP3 and
ST7-EMU3 series emulators and the RLink provide in-circuit programming capability for programming the Flash microcontroller on your application
board.
ST also provides a low-cost dedicated in-circuit
programmer, the ST7-STICK, as well as ST7
Socket Boards which provide all the sockets required for programming any of the devices in a
specific ST7 sub-family on a platform that can be
used with any tool with in-circuit programming capability for ST7.
For production programming of ST7 devices, ST’s
third-party tool partners also provide a complete
range of gang and automated programming solutions, which are ready to integrate into your production environment.
14.3.4 Order Codes for Development and
Programming Tools
Table 25 below lists the ordering codes for the
ST7LITEUSx development and programming
tools. For additional ordering codes for spare parts
and accessories, refer to the online product selector at www.st.com/mcu.
14.3.5 Order codes for ST7LITEUSx development tools
Table 25. Development tool order codes for the ST7LITEUSx family
In-circuit Debugger, RLink Series1)
Emulator
Programming tool
Supported
Products
Starter Kit
without Demo
Board
Starter Kit with
Demo Board
DVP Series
EMU Series
ST7FLITEUS2
ST7FLITEUS5
STX-RLINK2)
STFLITESK/RAIS2)
ST7MDT10DVP34)
ST7MDT10- STX-RLINK
EMU3
ST7-STICK3)5)
In-circuit
Programmer
ST Socket
Boards and
EPBs
ST7SB10SU03)
Notes:
1. Available from ST or from Raisonance, www.raisonance.com
2. USB connection to PC
3. Add suffix /EU, /UK or /US for the power supply for your region
4. Includes connection kit for DIP16/SO16 only. See “How to order an EMU or DVP” in ST product and tool selection guide
for connection kit ordering information
5. Parallel port connection to PC
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ST7LITEUSx
14.4 ST7 APPLICATION NOTES
Table 26. ST7 Application Notes
IDENTIFICATION DESCRIPTION
APPLICATION EXAMPLES
AN1658
SERIAL NUMBERING IMPLEMENTATION
AN1720
MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS
AN1755
A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555
AN1756
CHOOSING A DALI IMPLEMENTATION STRATEGY WITH ST7DALI
A HIGH PRECISION, LOW COST, SINGLE SUPPLY ADC FOR POSITIVE AND NEGATIVE INAN1812
PUT VOLTAGES
EXAMPLE DRIVERS
AN 969
SCI COMMUNICATION BETWEEN ST7 AND PC
AN 970
SPI COMMUNICATION BETWEEN ST7 AND EEPROM
AN 971
I²C COMMUNICATION BETWEEN ST7 AND M24CXX EEPROM
AN 972
ST7 SOFTWARE SPI MASTER COMMUNICATION
AN 973
SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
AN 974
REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
AN 976
DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
AN 979
DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
AN 980
ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
AN1017
USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
AN1041
USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOÏD)
AN1042
ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT
AN1044
MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
AN1045
ST7 S/W IMPLEMENTATION OF I²C BUS MASTER
AN1046
UART EMULATION SOFTWARE
AN1047
MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
AN1048
ST7 SOFTWARE LCD DRIVER
AN1078
PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
AN1082
DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERALS REGISTERS
AN1083
ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
AN1105
ST7 PCAN PERIPHERAL DRIVER
AN1129
PWM MANAGEMENT FOR BLDC MOTOR DRIVES USING THE ST72141
AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
AN1130
WITH THE ST72141
AN1148
USING THE ST7263 FOR DESIGNING A USB MOUSE
AN1149
HANDLING SUSPEND MODE ON A USB MOUSE
AN1180
USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
AN1276
BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
AN1321
USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
AN1325
USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
AN1445
EMULATED 16-BIT SLAVE SPI
AN1475
DEVELOPING AN ST7265X MASS STORAGE APPLICATION
AN1504
STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
AN1602
16-BIT TIMING OPERATIONS USING ST7262 OR ST7263B ST7 USB MCUS
AN1633
DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION IN ST7 NON-USB APPLICATIONS
AN1712
GENERATING A HIGH RESOLUTION SINEWAVE USING ST7 PWMART
AN1713
SMBUS SLAVE DRIVER FOR ST7 I2C PERIPHERALS
AN1753
SOFTWARE UART USING 12-BIT ART
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ST7LITEUSx
Table 26. ST7 Application Notes
IDENTIFICATION DESCRIPTION
AN1947
ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY
GENERAL PURPOSE
AN1476
LOW COST POWER SUPPLY FOR HOME APPLIANCES
AN1526
ST7FLITE0 QUICK REFERENCE NOTE
AN1709
EMC DESIGN FOR ST MICROCONTROLLERS
AN1752
ST72324 QUICK REFERENCE NOTE
PRODUCT EVALUATION
AN 910
PERFORMANCE BENCHMARKING
AN 990
ST7 BENEFITS VS INDUSTRY STANDARD
AN1077
OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
AN1086
U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
AN1103
IMPROVED B-EMF DETECTION FOR LOW SPEED, LOW VOLTAGE WITH ST72141
AN1150
BENCHMARK ST72 VS PC16
AN1151
PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
AN1278
LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131
MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
AN1322
MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
AN1365
GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264
AN1604
HOW TO USE ST7MDT1-TRAIN WITH ST72F264
AN2200
GUIDELINES FOR MIGRATING ST7LITE1X APPLICATIONS TO ST7FLITE1XB
PRODUCT OPTIMIZATION
AN 982
USING ST7 WITH CERAMIC RESONATOR
AN1014
HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
AN1015
SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
AN1040
MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
AN1070
ST7 CHECKSUM SELF-CHECKING CAPABILITY
AN1181
ELECTROSTATIC DISCHARGE SENSITIVE MEASUREMENT
AN1324
CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
AN1502
EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
AN1529
EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLAAN1530
TOR
AN1605
USING AN ACTIVE RC TO WAKEUP THE ST7LITE0 FROM POWER SAVING MODE
AN1636
UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS
AN1828
PIR (PASSIVE INFRARED) DETECTOR USING THE ST7FLITE05/09/SUPERLITE
AN1946
SENSORLESS BLDC MOTOR CONTROL AND BEMF SAMPLING METHODS WITH ST7MC
AN1953
PFC FOR ST7MC STARTER KIT
AN1971
ST7LITE0 MICROCONTROLLED BALLAST
PROGRAMMING AND TOOLS
AN 978
ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES
AN 983
KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
AN 985
EXECUTING CODE IN ST7 RAM
AN 986
USING THE INDIRECT ADDRESSING MODE WITH ST7
AN 987
ST7 SERIAL TEST CONTROLLER PROGRAMMING
AN 988
STARTING WITH ST7 ASSEMBLY TOOL CHAIN
AN1039
ST7 MATH UTILITY ROUTINES
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Table 26. ST7 Application Notes
IDENTIFICATION
AN1071
AN1106
DESCRIPTION
HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER
TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PROAN1179
GRAMMING)
AN1446
USING THE ST72521 EMULATOR TO DEBUG AN ST72324 TARGET APPLICATION
AN1477
EMULATED DATA EEPROM WITH XFLASH MEMORY
AN1527
DEVELOPING A USB SMARTCARD READER WITH ST7SCR
AN1575
ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
AN1576
IN-APPLICATION PROGRAMMING (IAP) DRIVERS FOR ST7 HDFLASH OR XFLASH MCUS
AN1577
DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION FOR ST7 USB APPLICATIONS
AN1601
SOFTWARE IMPLEMENTATION FOR ST7DALI-EVAL
AN1603
USING THE ST7 USB DEVICE FIRMWARE UPGRADE DEVELOPMENT KIT (DFU-DK)
AN1635
ST7 CUSTOMER ROM CODE RELEASE INFORMATION
AN1754
DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC
AN1796
FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT
AN1900
HARDWARE IMPLEMENTATION FOR ST7DALI-EVAL
AN1904
ST7MC THREE-PHASE AC INDUCTION MOTOR CONTROL SOFTWARE LIBRARY
AN1905
ST7MC THREE-PHASE BLDC MOTOR CONTROL SOFTWARE LIBRARY
SYSTEM OPTIMIZATION
AN1711
SOFTWARE TECHNIQUES FOR COMPENSATING ST7 ADC ERRORS
AN1827
IMPLEMENTATION OF SIGMA-DELTA ADC WITH ST7FLITE05/09
AN2009
PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7FMC
AN2030
BACK EMF DETECTION DURING PWM ON TIME BY ST7MC
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15 KNOWN LIMITATIONS
15.1 LIMITATIONS IN USER MODE
15.1.1 Flash Memory Access when Exiting
from HALT Mode
Description
When exiting from HALT mode, the CPU starts to
run after 64 cycles.
However, to work properly and to be accessed
safely, the Flash memory needs a delay of 42 µs.
This problem occurs only with a CPU frequency
from 2MHz to 8MHz (i.e. with a wake-up time from
Halt mode respectively from 32µs to 8µs).
This limitation is NOT present in the following
cases:
– at power-on (as an additional delay of 34µs is always applied)
– for internal reset as Flash memory cells are not
stopped.
Workaround
The CPU frequency must be set by software at
1MHz before entering HALT mode.
When the CPU exits from HALT mode by an external reset, the reset pulse of at least 42µs must be
applied.
15.1.2 Spurious AVD Interrupt when AVD
Switches ON and LVD is OFF
Description
If LVD is selected OFF by the option bytes, when
the AVD is turned ON by selecting one of the three
levels with the AVDTHCR register, a spurious
AVD interrupt is generated.
Workaround
In the application using an AVD threshold with
LVD OFF, the user can insure that the AVD interrupt is not a spurious one by checking if AVDF is
ON when entering the AVD interrupt subroutine.
15.2 LIMITATIONS IN ICC MODE
These limitations can concern ICP (programming)
and/or ICD (debugging) and a workaround (when
available) should be implemented in any programming or debugging tool, as described in the following sections.
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15.2.1 Spurious LVD Reset after Programming
the Option Bytes
Description
When programming the LVD option from OFF to
ON in ICC mode with Option Bytes enabled (38pulse mode) and if the AVD is OFF, a spurious reset is generated and ICC communication is lost.
Workaround
At the user level, using the ICC mode with Option
Bytes disabled (35-pulse mode), no spurious reset
is generated.
At the programming tool designer level, either by
generating a reset after or by setting the AVD ON
before programming the Option Bytes, a spurious
LVD reset is avoided.
15.2.2 In-Circuit Programming of Devices
Previously Programmed with Hardware
Watchdog Option
Description
In-Circuit Programming of devices configured with
hardware watchdog (WDGSW bit in option byte 1
programmed to 0) requires certain precautions
(see below).
In-Circuit Programming uses ICC mode. In this
mode, the hardware watchdog is not automatically
deactivated as one might expect. As a consequence, internal resets are generated by the
watchdog, thus preventing programming.
The device factory configuration is software
watchdog so this issue is not seen with devices
that are programmed for the first time. For the
same reason, devices programmed by the user
with the software watchdog option are not impacted.
The only devices impacted are those that have
previously been programmed with the hardware
watchdog option.
Workaround
Devices configured with Hardware Watchdog
must be programmed using a specific programming mode that ignores the option byte settings. In
this mode, an external clock, normally provided by
the programming tool, has to be used. In ST tools,
this mode is called "ICP OPTIONS DISABLED".
Sockets on ST programming tools are controlled
using "ICP OPTIONS DISABLED" mode. Devices
can therefore be reprogrammed by plugging them
in the ST Programming Board socket, whatever
the watchdog configuration.
ST7LITEUSx
When using third-party tools, please refer the
manufacturer's documentation to check how to access specific programming modes. If a tool does
not have a mode that ignores the option byte settings, devices programmed with the Hardware
watchdog option cannot be reprogrammed using
this tool.
15.2.3 In-Circuit Debugging with Hardware
Watchdog
In-Circuit Debugging is impacted in the same way
as In-Circuit Programming by the activation of the
hardware watchdog in ICC mode. Please refer to
Section 15.2.2.
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ST7LITEUSx
16 REVISION HISTORY
Date
Revision
06-Feb-06
1
Initial release
2
Removed references to 3% RC
Added note below Figure 4 on page 6
Modified presentation of section 4.3.1 on page 11
Added notes to section 6.1 on page 17 (above Figure 9), replaced 8-bit calibration value
to 10-bit calibration value and changed application note reference (AN2326 instead of
AN1324)
Modifed Table 5, “Clock Register Map and Reset Values,” on page 20 and added bit 1
in the description of CKCNTCSR register
Modified Figure 10 on page 21 (added CKCNTCSR register)
Added note 2 to EICRx description on page 27
Modified caution in section 7.2 on page 25
Replaced VIT+(LVD) by VIT+(LVD) in section 7.4.2.1 on page 29
Modified LVDRF bit description in section 7.4.4 on page 31
Replaced “oscillator” by “main oscillator” in the second paragraph of section 8.4.2 on
page 36
Added note 1 to Figure 23 on page 36 and added note 5 to Figure 24 on page 36
Modified section 8.5 on page 37
Replaced bit 1 by bit 2 for AWUF bit in section 8.5.1 on page 40
Modified section 9.1 on page 41
Modified section 9.2.1.1 on page 41
Updated section 9.5 on page 45
Modified section 12.3.2 on page 70
Modified section 12.3.3 on page 70
Modified section 12.3.4 on page 71
Modified section 12.3.5 on page 71
Modified section 12.4.1 on page 73
Modified section 12.4.2 on page 75
Modified section 12.5.2 on page 76
Modified section 12.8.1 on page 81
Modified section 12.8.2 on page 82
Modified section 12.9.1 on page 86
Modified section 12.10 on page 88
Added Figure 48 on page 82
Modified Figure 62 on page 87
Removed EMC protection circuitry in Figure 63 on page 87 (device works correctly without these components)
Added ECOPACK text in section 13 on page 91
Modified first paragraph in section 13.2 on page 94
Modified Table 24 on page 97
Modified conditioning option in option list on page 99
Modified “DEVELOPMENT TOOLS” on page 100
Added section 14.4 on page 101
Added “KNOWN LIMITATIONS” on page 104
Added erratasheet at the end of the document
18-Apr-06
Main changes
Revision History continued overleaf ...
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ST7LITEUSx
18-Sep-06
26-Jan-07
3
Modified description of AVD[1:0] bits in the AVDTRH register in section 7.4.4 on page 31
Modified description of CNTR[11:0] bits in section 10.2.6 on page 54
Modified values in section 12.2.2 on page 68
LVD and AVD tables updated, Section 12.3.2, Section 12.3.3 and section 12.3.4 on
page 71
Internal RC oscillator data modified in Section 12.3.5.1 and new table added section
12.3.5.2 on page 72
Typical data in section 12.4.2 on page 75 (on chip peripherals) modified
EMC characteristics updated, section 12.7 on page 78
RPU data corrected in section 12.8.1 on page 81 including additional notes
Output driving current table updated, section 12.8.2 on page 82
RON data corrected in section 12.9.1 on page 86
Modified ADC accuracy tables in Section 12.10 on page 89
“KNOWN LIMITATIONS” on page 104 updated
Errata sheet removed from document
Notes modified for Low Voltage Detector section 7.4.1 on page 28
Notes updated in section 4.4 on page 12 (ICC Interface)
Thermal characteristics table updated, Table 21 on page 93
Modified option list on page 99
Modified “DEVELOPMENT TOOLS” on page 100
Modified text in section 15.2 on page 104
4
Added -40°C to 125°C temperature range
Added caution to section 6.3.1 on page 22
Modified note on ei4 in Table 7, “Interrupt Mapping,” on page 26
Added note 3 to “EXTERNAL INTERRUPT CONTROL REGISTER 2 (EICR2)” on
page 27
Added a note to LVDRF in section 7.4.4 on page 31
Added Figure 41 on page 72 and Figure 40 on page 72
Modified section 12.3.2 on page 70 and section 12.3.3 on page 70
Modified section 12.3.5 on page 71
Updated section 12.4.1 on page 73
Updated section 12.8.2 on page 82
Modified RAIN and ADC accuracy tables in section 12.10 on page 88
Modified Table 25 on page 100
Modified Table 24 on page 97
Modified option list on page 99
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Please Read Carefully:
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right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
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