STMICROELECTRONICS STA2416

STA2416
Bluetooth™ Baseband with integrated flash
Target Specification
Features
■
Bluetooth™ specification compliance: V1.1
and V1.2
■
SW compatible with STLC2416
■
2 layer class 4 PCB compatible
– Point-to-point, point-to-multi-point (up to 7
slaves) and scatternet capability
■
Asynchronous connection oriented (ACL)
logical transport link
■
Synchronous connection oriented (SCO) links:
2 simultaneous SCO channels
■
Supports pitch-period error concealment
(PPEC)
– Improves speech quality in the vicinity of
interference
– Improves coexistence with WLAN
– Works at receiver, no Bluetooth implication
■
Adaptive frequency hopping (AFH): hopping
kernel, channel assessment as master and as
slave
■
Faster connection: interlaced scan for page
and inquiry scan, first FHS without random
backoff, RSSI used to limit range
■
Extended SCO (eSCO) links
■
Standard BlueRF bus interface
■
QoS flush
■
Clock support
– System clock input: any integer value from
12 to 33 MHz
– LPO clock input at 3.2 and 32 kHz or via
the embedded 32 kHz crystal oscillator cell
■
ARM7TDMI 32-bit CPU
■
Memory
– Integrated 4 Mbit flash
LFBGA120 (10x10x1.4mm)
– 64 KByte on-chip RAM
– 4 KByte on-chip boot ROM
■
Low power architecture with sleep mode
■
HW support for packet types
– ACL: DM1, 3, 5 and DH1, 3, 5
– SCO: HV1, 3 and DV
– eSCO: EV3, 5
■
Communication interfaces
– Synchronous serial interface, supporting up
to 32-bit data
– Two enhanced 16550 UARTs with 128-byte
FIFO depth
– 12 Mbps USB interface
– Fast master I2C bus interface
– Multi slot PCM interface
– 15 programmable GPIOs
– 2 external interrupts and various interrupt
possibilities through other interfaces
■
32 KHz clock out
■
Efficient support for WLAN coexistence
■
Ciphering support for up to 128-bit key
■
Receiver signal strength indication (RSSI)
support for power-controlled links
■
Separate control for external power amplifier
(PA) for class1 power support
■
Software support: low level (up to HCI) stack or
embedded stack with profiles
– Support of UART and USB HCI transport
layers
Part number
Package
Packing
STA2416
LFBGA120 (10x10x1.4mm)
Tube
December 2006
Rev 1
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
1/38
www.st.com
1
Contents
STA2416
Contents
1
Application features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
3.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3
Pin description and assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2
Operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3
I/O specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4
5
4.3.1
Specifications for 3.3 V I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3.2
Specifications for 1.8 V I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1
5.2
Baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.1
Baseband 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.2
Baseband 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Integrated Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.1
6
General specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1
System clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.1
2/38
Flash signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Slow clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2
Boot procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.3
Clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.4
Master reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.5
Interrupts/wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6
V1.2 detailed functionality - extended SCO . . . . . . . . . . . . . . . . . . . . . . . 22
6.7
V1.2 detailed functionality - adaptive frequency hopping . . . . . . . . . . . . . 23
STA2416
7
8
Contents
6.8
V1.2 detailed functionality - faster connection . . . . . . . . . . . . . . . . . . . . . 23
6.9
V1.2 detailed functionality - quality of service . . . . . . . . . . . . . . . . . . . . . 24
6.10
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.10.1
Sniff or park . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.10.2
Inquiry/page scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.10.3
No connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.10.4
Active link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.11
SW initiated low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.12
Bluetooth™ - WLAN coexistence in collocated scenario . . . . . . . . . . . . . 25
6.12.1
Algorithm 1: PTA (packet traffic arbitration) . . . . . . . . . . . . . . . . . . . . . . 26
6.12.2
Algorithm 2: WLAN master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.12.3
Algorithm 3: Bluetooth™ master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.12.4
Algorithm 4: Two-wire mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.12.5
Algorithm 5: Alternating wireless medium access (AWMA) . . . . . . . . . . 27
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1
UART interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2
Synchronous serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2.1
Feature description: Agilent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.2.2
Feature description: 32-bit SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2
7.3
I C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.4
USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.5
JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.6
RF interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.7
PCM voice interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
HCI UART transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.1
UART settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9
HCI USB transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10
Class1 power support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3/38
List of tables
STA2416
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
4/38
Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LVTTL DC input specification (3V<VDDIO<3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LVTTL DC output specification (3V<VDDIO<3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC input specification (1.55V<VDD<1.95V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC output specification (1.55V<VDD<1.95V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Typical power consumption of the STA2416
(VDD = VDD Flash = PLLVDD = 1.8V, VDDIO = 3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
WLAN HW signal assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
List of supported baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PCM interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
GPIOs alternate functionalities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STA2416
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin out (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
eSCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AFH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Algorithm 1: PTA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Algorithm 2: WLAN master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Algorithm 3: Bluetooth™ master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Agilent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
32-bit SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PCM (A-law, m-law) standard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Linear mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PCM interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
UART transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
LFBGA120 (10x10x1.4mm) mechanical data and package dimensions . . . . . . . . . . . . . . 36
5/38
Application features
1
STA2416
Application features
Typical applications in which the STA2416 can be used are:
2
●
cable replacement
●
portable computers, PDA
●
handheld data transfer devices
●
computer peripherals
●
other type of devices that require the wireless communication provided by Bluetooth™
●
SW host for STLC2500x ST single chip
●
audio application includes:
–
headset
–
headphone
–
wireless speakers
–
wireless transmitter
Description
The STA2416 from STMicroelectronics is a Bluetooth™ baseband controller with integrated
4-Mbit flash memory. Together with a Bluetooth™ Radio this product offers a compact and
complete solution for short-range wireless connectivity. It incorporates all the lower layer
functions of the Bluetooth™ protocol.
The microcontroller allows the support of all data packets of Bluetooth™ in addition to voice.
The embedded controller can be used to run the Bluetooth™ protocol and application layers
if required. The software is located in the integrated flash memory.
6/38
STA2416
Block diagram and pins description
3
Block diagram and pins description
3.1
Block diagram
Figure 1.
Block diagram
JTAG
5
PCM
VDD
2
INTERRUPT
CONTROLLER
100nF
USB
VDDIO
100nF
I2 C
VDDIO
100nF
RF BUS
ARM7
TDMI
13
RADIO
I/F
BLUETOOTH
CORE
D
M
A
LPOCLKOUT
RAM
4
APB
BRIDGE
SPI
TIMER
GPIO
START
DETECT
UART
UART
FIFO
UART
2
2
4
15
8
PCM
EXT._INT1/2
USB
I 2C
SPI
GPIO(0..9)(11...15)
UART2
(*)
22pF
LPOCLKP
BOOT
ROM
LPO
Y2
32kHz
22pF
2
SYSTEM
CONTROL
LPOCLKN
VDD
16
DATA(0..15)
ADDR(0..19)
VDDPLL
EMI
100nF
20
16
1
XIN
BOOT
2
CSN(1..2)
4Mbit
FLASH
NG
CSN(0)
1
5
16
RDN/NG ADDR DATA(0..15)
(0,2,17,18,19)
1
CSN(0)
VDD
100nF
NE
1
NRESET
SYS_CLK_REQ
DATA(0..15)
NW
1
UART1
ADDR(1..18)
18
WRN
RDN
2
1
NE
NRP
NWP
D05AU1623
(**)
(*) If a low-power clock is available, it can be connected to the LPOCLKP pin in stead of using a crystal
(**) For device testing only (should not be connected in the application.
7/38
Block diagram and pins description
3.2
STA2416
Pin description
Figure 2.
Pin out (top view)
18
17
nreset
nrp
16
15
14
uart1_ uart1_ i2c_
rxd
txd
dat
13
i2c_
clk
12
11
10
9
8
7
6
5
pcm_ pcm_ usb_ uart2_ uart2_ uart2_ uart2_
dn
rxd
txd
i1
o2 vddio
sync
a
4
3
2
1
vdd
vss
spi_
frm
spi_
clk
A
xin
spi_txd
B
pcm_ pcm- usb_ uart2_ uart2_ uart2_ uart2_
clk
b
dp
i2
o1
io1
io2 vssio rdn/ng
sys_cl
k_req
n.c.
tck
vssio
ne
csn1
tdo
tms
csn0
csn2
ntrst
tdi
addr0
vdd
btxen
vddio
n.c.
vss
brxen
ant_sw
nwp
addr2
bpktcl
bpaen
vpp
vdd
btxd
bdclk
vddf
vss
brclk
bmosi
vssf
addr17
brxd
bmiso
vddq
addr18
bsen
bnden
n.c.
addr19
gpio12
gpio14
n.c.
data0
data3
data1
data8 data7 data6 data5 data4
data2
int2
int1
vddio vssio
spi_rxd
C
D
E
F
G
H
J
K
L
M
N
P
Ipio_clk_out gpio15
R
gpio11
gpio13 vsspll vssio vddio gpio3 gpio1 boot
vss
vdd
T
gpio9
vdd
lpo_ lpo_
gpio8 gpio7 gpio6 vddpll gpio5 gpio4 gpio2 gpio0 clk_n clk_p data15 data14 data13 data12 data11 data10 data9
vss
U
V
D05AU1624
8/38
STA2416
3.3
Block diagram and pins description
Pin description and assignment
Table 1 shows the pin list of the STA2416. There are 91 functional pins of which 25 are used
for device testing only (should not be connected in the application) and 24 supply pins. The
column “PU/PD” shows the pads implementing an internal weak pull-up/down, to fix value if
the pin is left open. This cannot replace an external pull-up/down.
The pads are grouped according to two different power supply values, as shown in column
VDD:
●
V1 for 3.3 V typical 2.7 - 3.6 V range
●
V2 for 1.8 V typical 1.55 - 1.95 V range
Finally the column “DIR” describes the pin directions:
Table 1.
●
I for Inputs
●
O for Outputs
●
I/O for Input/Outputs
●
O/t for trim-state outputs
(
Pin list
Name
Pin #
Description
DIR
PU/PD
VDD
PAD
Clock and test pins
IN
B18
System clock
I
NEAREST
A18
Reset
I
UNRIPE
A17
Flash reset
I
V2
NWP
H3
Flash write protect
I
V2
CMOS 1.8V
V1
CMOS, 3.3V TTL
compatible, 2mA
tri-state
slew rate control
V1
SYS_CLK_REQ
C18
System clock request
I/O
LPO_CLK_P
V9
Low power oscillator + /slow clock
input
I
LPO_CLK_N
V10
Low power oscillator -
O
LPO_CLK_OUT
R18
32MHz clock out
O
-
INT1
C14
External interrupt used also as
external wakeup
I
(1)
CMOS, 3.3V TTL
compatible
Schmidt trigger
V2
INT2
C15
Second external interrupt
I
(1)
BOOT
T10
Select external boot from EMI or
internal from ROM
I
(1)
V1
V1
CMOS, 3.3V TTL
compatible
schmidt trigger
V2
CMOS 1.8V
9/38
Block diagram and pins description
Table 1.
STA2416
Pin list (continued)
Name
Pin #
Description
DIR
PU/PD
VDD
PAD
SPI interface
SPI_FRM
A2
Synchronous serial interface
frame sync
I/O
V1
CMOS, 3.3V TTL
compatible, 2mA tri-state
slew rate control
schmidt trigger
V1
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
V1
CMOS, 3.3V TTL
compatible
schmidt trigger
V1
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
V1
CMOS, 3.3V TTL
compatible
Schmidt trigger
SPI_CLK
A1
Synchronous serial interface clock
I/O
SPI_TXD
B1
Synchronous serial interface
transmit data
O/t
SPI_RXD
C1
Synchronous serial interface
receive data
I
UART1_TXD
A15
UART1 transmit data
O/t
UART1_RXD
A16
UART1 receive data
I
UART2_O1
C7
UART2 modem output
O
V1
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
UART2_O2
A6
UART2 modem output
O/t
V1
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
UART2_I1
A7
UART2 modem input
(1)
UART interface
(2)
I
(2)
V1
I
(2)
V1
UART2_I2
C8
UART2 modem input
UART2_IO1
C6
UART2 modem input/output
I/O
(2)
V1
UART2_IO2
C5
UART2 modem input/output
I/O
(2)
V1
UART2_TXD
A8
UART2 transmit data
O/t
UART2_RXD
A9
UART2 receive data
I
I2C_DAT
A14
I2C data pin
I2C_CLK
A13
I2C clock pin
CMOS, 3.3V TTL
compatible
CMOS, 3.3V TTL
compatible, 2mA
tri-state slew rate control
V1
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
(2)
V1
CMOS, 3.3V TTL
compatible
I/O
(3)
V1
I/O
(3)
V1
I2C interface
10/38
CMOS, 3.3V TTL
compatible, 2mA tri-state
slew rate control
STA2416
Table 1.
Block diagram and pins description
Pin list (continued)
Name
Pin #
Description
DIR
PU/PD
VDD
PAD
USB interface
USB_DN
A10
USB - pin (Needs a series resistor
of 27 Ω ±5%)
I/O
(1)
V1
USB_DP
C9
USB + pin (Needs a series
resistor of 27 Ω ±5%)
I/O
(1)
V1
GPIO0
V11
GPIO port 0
I/O
PU
GPIO1
T11
GPIO port 1
I/O
PU
GPIO2
V12
GPIO port 2
I/O
PU
GPIO interface
GPIO3
T12
GPIO port 3
I/O
PU
GPIO4
V13
GPO port 4
I/O
PU
GPIO5
V14
GPO port 5
I/O
PU
GPIO6
V16
GPO port 6
I/O
PU
GPIO7
V17
GPO port 7
I/O
PU
GPIO8
V18
GPO port 8
I/O
PU
GPIO9
U18
GPO port 9
I/O
PU
GPIO11
T18
GPO port 11
I/O
PU
GPIO12
P18
GPO port 12
I/O
PU
GPIO13
T16
GPO port 13
I/O
PU
GPIO14
P16
GPO port 14
I/O
PU
GPIO15
R16
GPO port 15
I/O
PU
V1
CMOS, 3.3V TTL
compatible, 4mA
tri-state
slew rate control
V1
CMOS, 3.3V TTL
compatible, 4mA
tri-state
slew rate control
schmidt trigger
V1
CMOS, 3.3V TTL
compatible, 4mA
trim-state
slew rate control
V1
CMOS, 3.3V TTL
compatible, 2mA
trim-state
slew rate control
11/38
Block diagram and pins description
Table 1.
STA2416
Pin list (continued)
Name
Pin #
Description
DIR
PU/PD
VDD
PAD
JTAG interface
ENTRUST
F18
JTAG pin
I
PD
V1
CMOS, 3.3V TTL
compatible
TKO
D18
JTAG pin
I
(1)
V1
CMOS, 3.3V TTL
compatible
Schmidt trigger
TAMS
E16
JTAG pin
I
PU
V1
TI
F16
JTAG pin
I
PU
CMOS, 3.3V TTL
compatible
DO
E18
JTAG pin (should be left open)
O/t
V1
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
PECAN
A11
PCM data
I/O
PD
BITMAP
C10
PCM data
I/O
PD
V1
PCM_SYNC
A12
PCM 8kHz sync
I/O
PD
CMOS, 3.3V TTL
compatible, 2mA
trim-state
slew rate control
V1
CMOS, 3.3V TTL
compatible, 2mA
tri-state
slew rate control
schmidt trigger
V1
CMOS, 3.3V TTL
compatible
schmidt trigger
V1
CMOS, 3.3V TTL
compatible
V1
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
V1
CMOS, 3.3V TTL
compatible, 2mA
slew rate control
V1
CMOS, 3.3V TTL
compatible, 8mA
slew rate control
PCM interface
PCM_CLK
C11
PCM clock
L18
Transmit clock
I/O
PD
I
(1)
Radio interface
BRCLK
BRXD
M18
Receive data
I
BMISO
M16
RF serial interface input data
I
BNDEN
N16
RF serial interface control
O
BMOSI
L16
RF serial interface output data
O
BDCLK
K16
RF serial interface clock
O
BTXD
K18
Transmit data
O
BSEN
N18
Synthesizer ON
O
BPAEN
J16
Open PLL
O
BRXEN
H18
Receive ON
O
BTXEN
G18
Transmit ON
O
BPKTCTL
J18
Packet ON
O
ANT_SW
H16
Antenna switch
O
12/38
(1)
STA2416
Table 1.
Block diagram and pins description
Pin list (continued)
Name
Pin #
Description
DIR
PU/PD
VDD
PAD
Power supply
VSSPLL
T15
PLL ground
VDDPLL
V15
1.8V supply for PLL
VDD
A4
1.8V digital supply
VDD
F1
1.8V digital supply
VDD
J1
1.8V digital supply
VDD
U1
1.8V digital supply
VDD
T8
1.8V digital supply
VDDF
K3
1.8V digital supply flash
VDDQ
M3
1.8V I/O’s supply flash
VPP
J3
12V fast program supply flash
VDDIO
C13
3.3V I/O’s supply
VDDIO
A5
3.3V I/O’s supply
VDDIO
T13
3.3V I/O’s supply
VDDIO
G16
3.3V I/O’s supply
VSS
A3
Digital ground
VSS
G1
Digital ground
VSS
K1
Digital ground
VSS
V1
Digital ground
VSS
T9
Digital ground
VSSF
L3
Digital ground flash
VSSIO
C12
I/O’s ground
VSSIO
C4
I/O’s ground
VSSIO
T14
I/O’s ground
VSSIO
D16
I/O’s ground
To be connected together on the PCB
NE
D3
Flash chip enable
I
CSN0
E3
External chip select bank 0
O
13/38
Block diagram and pins description
Table 1.
STA2416
Pin list (continued)
Name
Pin #
Description
DIR
PU/PD
VDD
PAD
Test only (Do NOT connect)
RDN/NG
C3
External read
O
CSN1
D1
External chip select bank 1
O
CSN2
E1
External chip select bank 2
O
ADDR0
F3
External address bit 0
O
ADDR2
H1
External address bit 2
O
ADDR17
L1
External address bit 17
O
ADDR18
M1
External address bit 18
O
ADDR19
N1
External address bit 19
O
DATA0
P1
External data bit 0
I/O
PD
DATA1
R1
External data bit 1
I/O
PD
DATA2
T1
External data bit 2
I/O
PD
DATA3
R3
External data bit 3
I/O
PD
DATA4
T3
External data bit 4
I/O
PD
DATA5
T4
External data bit 5
I/O
PD
DATA6
T5
External data bit 6
I/O
PD
DATA7
T6
External data bit 7
I/O
PD
DATA8
T7
External data bit 8
I/O
PD
DATA9
V2
External data bit 9
I/O
PD
DATA10
V3
External data bit 10
I/O
PD
DATA11
V4
External data bit 11
I/O
PD
DATA12
V5
External data bit 12
I/O
PD
DATA13
V6
External data bit 13
I/O
PD
DATA14
V7
External data bit 14
I/O
PD
DATA15
V8
External data bit 15
I/O
PD
C16,
G3,
N3,
P3
Not connected
Not connected
N.C.
1. Should be strapped to VSSIO if not used
2. Should be strapped to VDDIO if not used
3. Must have a 10 kOhm pull-up
14/38
V2
CMOS 1.8V
4mA
slew rate control
V2
CMOS 1.8V
4mA
slew rate control
STA2416
Quick reference data
4
Quick reference data
4.1
Absolute maximum ratings
Operation of the device beyond these conditions is not guaranteed.
Sustained exposure to these limits will adversely affect device reliability.
Table 2.
Absolute maximum ratings
Symbol
4.2
Conditions
Min
Max
Unit
VDD
Supply voltage baseband core
VSS – 0.5
2.5
V
VDDF
Supply voltage flash
VSS – 0.5
2.5
V
VPP
Fast Program Voltage
VSS – 0.5
13
V
4
V
VDDIO
Supply voltage baseband I/O
VDDQ
Supply voltage flash I/O
VSS – 0.5
2.5
V
VIN
Input voltage on any digital pin (excluding FLASH
input pins)
VSS – 0.5
VDDIO + 0.3
V
Tstg
Storage temperature
-55
+150
°C
Tlead
Lead temperature < 10s
+240
°C
Operating ranges
Operating ranges define the limits for functional operation and parametric characteristics of
the device. Functionality outside these limits is not implied.
Table 3.
Symbol
Operating ranges
Conditions
Min
Typ
Max
Unit
VDD
Supply voltage baseband core and EMI pads
1.55
1.8
1.95
V
VDDF
Supply voltage flash
1.55
1.8
1.95
V
VDDIO
Supply voltage digital I/O
2.7
3.3
3.6
V
VDDQ
Supply voltage flash I/O (VDDQ ≤VDDF)
1.55
1.8
1.95
V
Tamb
Operating ambient temperature
-40
+85
°C
15/38
Quick reference data
4.3
STA2416
I/O specifications
Depending on the interface, the I/O voltage is typical 1.8 V (interface to the flash memory) or
typical 3.3 V (all the other interfaces). These I/Os comply with the EIA/JEDEC standard
JESD8-B.
4.3.1
Specifications for 3.3 V I/Os
Table 4.
Symbol
LVTTL DC input specification (3V<VDDIO<3.6V)
Parameter
Conditions
Min
Typ
Max
Unit
0.8
V
Vil
Low level input
voltage
Vih
High level input
voltage
2
V
Vhyst
schmidt trigger
hysteresis
0.4
V
Table 5.
Symbol
LVTTL DC output specification (3V<VDDIO<3.6V)
Parameter
Conditions
Vol
Low level output
voltage
Iol = X mA
Voh
High level output
voltage
Ioh =-X mA
Min
Typ
Max
Unit
0.15
V
VDDIO0.15
V
Note:
X is the source/sink current under worst-case conditions according to the drive capability.
(See Table 1: Pin list on page 9 for the value of X).
4.3.2
Specifications for 1.8 V I/Os
Table 6.
Symbol
Low level input voltage
Vih
High level input voltage
Table 7.
Symbol
16/38
Parameter
Vil
Vhyst
Note:
DC input specification (1.55V<VDD<1.95V)
Conditions
Min
Typ
Max
Unit
0.35*VDD
V
0.65*VDD
schmidt trigger
hysteresis
0.2
V
0.3
0.5
V
DC output specification (1.55V<VDD<1.95V)
Parameter
Conditions
Vol
Low level output
voltage
Iol = X mA
Voh
High level output
voltage
Ioh =-X mA
Min
VDD-0.15
Typ
Max
Unit
0.15
V
V
X is the source/sink current under worst-case conditions according to the drive capability.
(See Table 1: Pin list on page 9 for the value of X).
STA2416
4.4
Quick reference data
Current consumption
Table 8.
Typical power consumption of the STA2416
(VDD = VDD Flash = PLLVDD = 1.8V, VDDIO = 3.3V)
Core
STA2416 state
IO
Unit
5.10
0.13
mA
0.94
0.94
0.13
mA
ACL connection (no transmission)
7.60
6.99
0.13
mA
ACL connection (data transmission)
7.90
7.20
0.13
mA
SCO connection (no codec connected)
8.70
7.90
0.14
mA
Inquiry and Page scan (low power mode
enabled)
127
n.a.
5
µA
Low Power mode (32 kHz crystal)
20
20
0
µA
Slave
Master
Standby (no low power mode)
5.10
Standby (low power mode enabled)
17/38
Functional description
5
Functional description
5.1
Baseband
●
5.1.1
STA2416
WLAN coexistence. See also Section 6.12: Bluetooth™ - WLAN coexistence in
collocated scenario.
Baseband 1.1 features
The baseband is based on Ericsson Technology Licensing Baseband Core (EBC) and it is
compliant with the Bluetooth™ specification 1.1.
5.1.2
●
Point to multipoint (up to 7 Slaves).
●
Asynchronous Connection Less (ACL) link support giving data rates up to 721 kbps.
●
Synchronous Connection Oriented (SCO) link with support for 2 voice channels over
the air interface.
●
Flexible voice format to host and over the air (CVSD, PCM 13/16 bits, A-law, µ-law).
●
HW support for packet types: DM1, 3, 5; DH1, 3, 5; HV1, 3; DV.
●
Scatternet capabilities (Master in one piconet and Slave in the other one; Slave in two
piconets). All scatternet v.1.1 errata supported.
●
Ciphering support up to 128 bits key.
●
Paging modes R0, R1, R2.
●
Channel Quality Driven Data Rate.
●
Full Bluetooth software stack available.
●
Low level link controller.
Baseband 1.2 features
The baseband part is also compliant with the Bluetooth specification 1.2.
18/38
●
Extended SCO (eSCO) links: supports EV3 and EV5 packets. See also Section 6.6:
V1.2 detailed functionality - extended SCO on page 22.
●
Adaptive Frequency Hopping (AFH): hopping kernel, channel assessment as Master
and as Slave. See also Section 6.7: V1.2 detailed functionality - adaptive frequency
hopping on page 23.
●
Faster Connection: Interlaced scan for Page and Inquiry scan, answer FHS at first
reception, RSSI used to limit range. See also Section 6.8: V1.2 detailed functionality faster connection on page 23.
●
QoS Flush. See also Section 6.9: V1.2 detailed functionality - quality of service on
page 24.
●
Synchronization: the local and the master BT clock are available via HCI commands for
synchronization of parallel applications on different slaves.
●
L2CAP Flow and Error control.
●
LMP Improvements.
●
LMP SCO handling.
●
Parameter Ranges update.
STA2416
5.2
Functional description
Integrated Flash memory
Features:
●
4-Mbit size
●
eight parameter blocks of 4 Kword (top configuration)
●
seven main blocks of 32 Kword
●
120 ns access time
See the datasheet for the standalone product M28R400CT for detailed information.
Figure 3.
Block addresses
M28R400CT
Top Boot Block Addresses
3FFFF
4 KWords
3F000
Total of 8
4 KWord Blocks
38FFF
4 KWords
38000
37FFF
32 KWords
30000
Total of 7
32 KWord Blocks
0FFFF
32 KWords
08000
07FFF
32 KWords
00000
5.2.1
Flash signal descriptions
Write protect (nwp)
Write protect is an input that gives an additional hardware protection for each block. When
Write Protect is ≤0.4V the Lock-Down is enabled and the protection status of the flash blocks
cannot be changed. When Write Protect is ≥ (VDDQ - 0.4V), the Lock-Down is disabled and
the flash memory blocks can be locked or unlocked.
Reset (nrp)
The Reset input provides a hardware reset of the memory. When Reset is ≤0.4V, the
memory is in reset mode: the outputs are high impedant and the current consumption is
minimized. After Reset all blocks are in Locked state. When Reset is ≥ (VDDQ - 0.4V), the
device is in normal operation. Exiting reset mode the device enters read array mode, but a
negative transition of Chip Enable or a change of the address is required to ensure valid
data outputs.
19/38
Functional description
STA2416
Vdd supply voltage (vddf)
Vdd provides the power supply to the internal core of the flash memory device. It is the main
power supply for all operations (Read, Program and Erase)
Vddq supply voltage (vddq)
Vddq provides the power supply to the I/O pins and enables all Outputs to be powered
independently from Vddf. Vddq can be tied to Vddf or can use separate supply.
Vpp program supply voltage (vpp)
Vpp is both a control input and a power supply pin. The two functions are selected by the
voltage range applied to the pin. The supply voltage Vddf and the program supply voltage
Vpp can be applied in any order.
If Vpp is kept in a low voltage range (0 V to 3.6 V) Vpp is seen as a control input. In this case
a voltage lower than 1 V gives protection agains program or block erase, while
1.65 V < Vpp < 3.6 V enables these functions. Vpp is only sampled at the beginning of a
program or block erase; a change in its value after the operation has started does not have
any effect and program or erase operations continue.
If Vpp is in the range 11.4 V to 12.6 V it acts as a power supply pin. In this condition Vpp
must be stable until the Program/Erase algorithm is completed.
Vssf Flash ground (vssf)
Vssf is the reference for all voltage measurements.
Address inputs (Addr0-Addr17), data input/output (Data0-Data15), chip
enable (csn0), output enable (rdn/ng), write enable (wrn)
These are connected to and controlled by the Bluetooth™ baseband controller.
20/38
STA2416
General specification
6
General specification
6.1
System clock
The STA2416 works with a single clock provided on the XIN pin. The value of this external
clock should be any integer value from 12 … 33 MHz ±20 ppm (overall).
6.1.1
Slow clock
The slow clock is used by the baseband as reference clock during the low power modes.
The slow clock requires an accuracy of ±250 ppm (overall).
Several options are foreseen in order to adjust the STA2416 behavior according to the
features of the radio used.
6.2
●
If the system clock (for example, 13 MHz) is not provided at all times (power
consumption saving) and no slow clock is provided by the system, a 32 kHz crystal
must be used by the STA2416 (default mode).
●
If the system clock (for example, 13 MHz) is not provided at all times (power
consumption saving) and the system provides a slow clock at 32 kHz or 3.2 kHz, this
signal is simply connected to the STA2416 (LPO_CLK_P).
●
If the system clock (for example, 13 MHz) is provided at all times, the STA2416
generates from the reference clock an internal 32 kHz clock. This mode is not an
optimized mode for power consumption.
Boot procedure
The boot code instructions are the first that ARM7TDMI executes after a HW reset. All the
internal device's registers are set to their default value.
There are two types of boot:
●
Flash boot
When boot pin is set to ‘1’ (connected to VDD), the STA2416 boots on its flash
●
UART download boot from ROM
When boot pin is set to ‘0’ (connected to GND), the STA2416 boots on its internal ROM
(needed to download the new firmware in the flash). When booting on the internal
ROM, the STA2416 will monitor the UART interface for approximately 1.4 second. If
there is no request for code downloading during this period, the ROM jumps to flash.
6.3
Clock detection
The STA2416 has an automatic slow clock frequency detection (32kHz, 3.2kHz or none).
21/38
General specification
6.4
STA2416
Master reset
When the device’s reset is held active (NRESET is low), UART1_TXD and UART2_TXD are
set to input state. When the NRESET returns high, the device starts to boot.
Note:
The device should be held in active reset for minimum 20 ms in order to guarantee a
complete reset of the device.
6.5
Interrupts/wake-up
All GPIOs can be used both as external interrupt source and as wake-up source. In addition
the chip can be woken-up by USB, UART1_RXD, UART2_RXD, INT1, INT2.
6.6
V1.2 detailed functionality - extended SCO
User perspective - extended SCO
This function gives improved voice quality since it enables the possibility to retransmit lost or
corrupted voice packets in both directions.
Technical perspective - extended SCO
eSCO incorporates CRC, negotiable data rate, negotiable retransmission window and
multi-slot packets. Retransmission of lost or corrupted packets during the retransmission
window guarantees on-time delivery.
Figure 4.
eSCO
SCO
SCO
SCO
SCO
ACL
eSCO retransmission window
22/38
ACL
SCO
SCO
t
STA2416
6.7
General specification
V1.2 detailed functionality - adaptive frequency hopping
User perspective - adaptive frequency hopping
In the Bluetooth™ specification 1.1 the Bluetooth devices hop in the 2.4 GHz band over
79-channels. Since WLAN 802.11 has become popular, there are specification
improvements in the 1.2-SIG spec for Bluetooth where the Bluetooth units can avoid the
jammed bands and thereby provide an improved co-existence with WLAN.
Technical perspective - adaptive frequency hopping
Figure 5.
AFH
f
AFH(79)
WLAN used frequency
t
f
AFH(19<N<79)
WLAN used frequency
t
First the Master and/or the Slaves identify the jammed channels. The Master decides on the
channel distribution and informs the involved slaves. The Master and the Slaves, at a
predefined instant, switch to the new channel distribution scheme.
No longer jammed channels are re-inserted into the channel distribution scheme. AFH uses
the same hop frequency for transmission as for reception
6.8
V1.2 detailed functionality - faster connection
User perspective - faster connection
This feature gives the User about 65% faster connection on average when enabled
compared to Bluetooth™ specification 1.1 connection procedure.
Technical perspective - faster connection
The faster Inquiry functionality is based on a removed/shortened random back off and also a
new Interlaced Inquiry scan scheme.
The faster Page functionality is based on Interlaced Page Scan.
23/38
General specification
6.9
STA2416
V1.2 detailed functionality - quality of service
User perspective - quality of service
Small changes to the BT1.1 spec regarding Quality of Service makes a large difference by
allowing all QoS parameters to be communicated over HCI to the link manager that enables
efficient BW management. Below is a short list of user perspectives.
6.10
●
Flush timeout: enables time-bounded traffic such as video streaming to become more
robust when the channel degrades. It sets the maximum delay of an L2CAP frame. It
does not enable multiple streams in one piconet, or heavy data transfer at the same
time.
●
Simple latency control: allows the host to set the poll interval. Provides enough
support for HID devices mixed with other traffic in the piconet.
Low power modes
To save power, two low power modes are supported. Depending on the Bluetooth™ and the
Host’s activity, the STA2416 autonomously decides to use Sleep Mode or Deep Sleep
Mode.
Table 9.
Low power modes
Low power mode
Description
Sleep Mode
The STA2416:
– accepts HCI commands from the Host
– supports page- and inquiry scans
– supports Bluetooth™ links that are in Sniff, Hold or Park
– can transfer data over Bluetooth™ links
– the system clock is still active in part of the design
Deep Sleep Mode(1)
The STA2416:
– does not accept HCI commands from the Host
– keeps track of page- and inquiry scan activities
– switches between sleep and active mode when it is time to scan
– supports Bluetooth™ links that are in Sniff, Hold or Park
– does not transfer data over Bluetooth™ links
– the system clock is not active in any part of the design
1. Deep Sleep mode is not compatible with a USB transport layer
6.10.1
Sniff or park
The STA2416 is in active mode with a Bluetooth™ connection, once the connection is
concluded the SNIFF or the PARK is programmed. Once one of these two states is entered
the STA2416 goes in Sleep Mode. After that, the Host may decide to place the STA2416 in
Deep Sleep Mode by putting the UART LINK in low power mode. The Deep Sleep Mode
allows smaller power consumption. When the STA2416 needs to send or receive a packet
(for example, at TSNIFF or at the beacon instant) it will require the clock and it will go in active
mode for the needed transmission/reception. Immediately afterwards it will go back to the
Deep Sleep Mode. If some HCI transmission is needed, the UART link will be reactivated,
using one of the two ways explained in 7.5, and the STA2416 will move from the Deep Sleep
Mode to the Sleep Mode.
24/38
STA2416
6.10.2
General specification
Inquiry/page scan
When only inquiry scan or page scan is enabled, the STA2416 will go in Sleep Mode or
Deep Sleep Mode outside the receiver activity. The selection between Sleep Mode and
Deep Sleep Mode depend on the UART activity like in SNIFF or PARK.
6.10.3
No connection
If the Host places the UART in low power and there is no activity, then the STA2416 can be
placed in Deep Sleep Mode.
6.10.4
Active link
When there is an active link (SCO or ACL), the STA2416 cannot go in Deep Sleep Mode
whatever the UART state is. But the STA2416 baseband is made such that whenever it is
possible, depending on the scheduled activity (number of link, type of link, amount of data
exchanged), it goes in Sleep Mode.
6.11
SW initiated low power mode
A wide set of wake up mechanisms are supported.
6.12
Bluetooth™ - WLAN coexistence in collocated scenario
The coexistence interface uses four GPIO pins, when enabled.
Bluetooth™ and WLAN 802.11 b/g technologies occupy the same 2.4 GHz ISM band.
STA2416 implements a set of mechanisms to avoid interference in a collocated scenario.
The STA2416 supports five different algorithms in order to provide efficient and flexible
simultaneous functionality between the two technologies in collocated scenarios.
●
Algorithm 1: PTA (Packet Traffic Arbitration) based coexistence algorithm defined in
accordance with the IEEE 802.15.2 recommended practice.
●
Algorithm 2: the WLAN is the master and it indicates to the STA2416 when not to
operate in case of simultaneous use of the air interface.
●
Algorithm 3: the STA2416 is the master and it indicates to the WLAN chip when not to
operate in case of simultaneous use of the air interface.
●
Algorithm 4: Two-wire mechanism.
●
Algorithm 5: Alternating Wireless Medium Access (AWMA), defined in accordance
with the WLAN 802.11 b/g technologies.
The algorithm is selected via HCI command. The default algorithm is algorithm 1.
25/38
General specification
6.12.1
STA2416
Algorithm 1: PTA (packet traffic arbitration)
Algorithm 1 is based on a bus connection between the STA2416 and the WLAN chip.
Figure 6.
Algorithm 1: PTA
STA2416
WLAN
D05AU1628
By using this coexistence interface it's possible to dynamically allocate bandwidth to the two
devices when simultaneous operations are required while the full bandwidth can be
allocated to one of them in case the other one does not require activity. The algorithm
involves a priority mechanism, which allows preserving the quality of certain types of link. A
typical application would be to guarantee optimal quality to the Bluetooth™ voice
communication while an intensive WLAN communication is ongoing.
Several algorithms have been implemented in order to provide a maximum of flexibility and
efficiency for the priority handling. Those algorithms can be activated via specific HCI
commands.
The combination of a time division multiplexing techniques to share the bandwidth in case of
simultaneous operations and of the priority mechanism avoid the interference due to packet
collision and it allows the maximization of the 2.4 GHz ISM bandwidth usage for both
devices while preserving the quality of some critical types of link.
6.12.2
Algorithm 2: WLAN master
In case the STA2416 has to cooperate, in a collocated scenario, with a WLAN chip not
supporting a PTA based algorithm, it's possible to put in place a simpler mechanism.
The interface is reduced to 1 line.
Figure 7.
Algorithm 2: WLAN master
RF_NOT_ALLOWED
STA2416
WLAN
D05AU1626
When the WLAN has to operate, it alerts HIGH the RF_NOT_ALLOWED signal and the
STA2416 will not operate while this signals stays HIGH.
This mechanism permits to avoid packet collision in order to make an efficient use of the
bandwidth but cannot provide guaranteed quality over the Bluetooth™ links.
26/38
STA2416
6.12.3
General specification
Algorithm 3: Bluetooth™ master
This algorithm represents the symmetrical case of Section 6.12.2: Algorithm 2: WLAN
master. Also in this case the interface is reduced to 1 line.
Figure 8.
Algorithm 3: Bluetooth™ master
RF_NOT_ALLOWED
STA2416
WLAN
D05AU1627
When the STA2416 has to operate it alerts HIGH the RF_NOT_ALLOWED signal and the
WLAN will not operate while this signals stays HIGH.
This mechanism permits to avoid packet collision in order to make an efficient use of the
bandwidth, it provides high quality for all Bluetooth™ links but cannot provide guaranteed
quality over the WLAN links.
6.12.4
Algorithm 4: Two-wire mechanism
Based on algorithm 2 and 3, the Host decides, on a case-by-case basis, whether WLAN or
Bluetooth™ is master.
6.12.5
Algorithm 5: Alternating wireless medium access (AWMA)
AWMA utilizes a portion of the WLAN beacon interval for Bluetooth™ operations. From a
timing perspective, the medium assignment alternates between usage following WLAN
procedures and usage following Bluetooth™ procedures.
The timing synchronization between the WLAN and the STA2416 is done by the HW signal
MEDIUM_FREE.
Table 10.
WLAN HW signal assignment
WLAN
Scenario 1:
PTA
Scenario 2:
WLAN master
Scenario 3:
BT master
Scenario 4:
2-wire
Scenario 5:
AWMA
WLAN 1
TX_ CONFIRM
BT_RF_NOT_
ALLOWED
Not used
BT_RF_NOT_
ALLOWED
MEDIUM_FREE
WLAN 2
TX_ REQUEST
Not used
WLAN 3
STATUS
Not used
Not used
Not used
Not used
WLAN 4
OPTIONAL_ SIGNAL
Not used
Not used
Not used
Not used
WLAN_RF_ NOT_ WLAN_RF_ NOT_
ALLOWED
ALLOWED
Not used
27/38
Interfaces
STA2416
7
Interfaces
7.1
UART interface
The chip contains two enhanced (128 byte transmit FIFO and 128 byte receive FIFO, sleep
mode, 127 Rx and 128 Tx interrupt thresholds) UARTs named UART1 and UART2
compatible with the standard M16550 UART.
For UART1, only Rx and Tx signals are available (used for debug purposes).
UART2 features:
●
standard HCI UART transport layer:
–
all HCI commands as described in the Bluetooth™ specification 1.1
–
ST specific HCI command (check STA2416 Software Interface document for more
information)
●
RXD, TXD, CTS, RTS on permanent external pins
●
128-byte FIFOs, for transmit and for receive
●
default configuration: 57.600 kbps
●
specific HCI command to change to the baud rates given in Table 11
Table 11.
List of supported baud rates
Baud rate
7.2
–
57.600 kbps (default)
4800
921.6k
38.4 k
2400
460.8 k
28.8 k
1800
230.4 k
19.2 k
1200
153.6 k
14.4 k
900
115.2 k
9600
600
76.8 k
7200
300
Synchronous serial interface
The synchronous serial interface (SSI) (or the synchronous peripheral interface (SPI)) is a
flexible module supporting full-duplex and half-duplex synchronous communications with
external devices in Master and Slave mode. It enables a microcontroller unit to
communicate with peripheral devices or allows inter-processor communications in a
multiple-master environment. This Interface is compatible with the Motorola SPI standard,
with the Texas Instruments Synchronous Serial frame format and with National
Semiconductor Microwire standard.
Special extensions are implemented to support the Agilent SPI interface for optical mouse
applications and the 32-bit data SPI for stereo codec applications.
28/38
STA2416
7.2.1
Interfaces
Feature description: Agilent mode
One application is a combination of a Bluetooth™ device with an Agilent optical mouse
sensor to build a Bluetooth™ Mouse. The Agilent chip has an SPI interface with one
bi-directional data port.
When SPI_IO from ADNS_2030 is driving, SPI_RXD should be active, while SPI_TXD is set
as a tri-state high impedance input.
For a read operation, the Bluetooth™ SPI_TXD is put in high impedance state after the
reception of the address.
Note that this feature works independently of the SPI mode, supporting other combinations.
In this case, the devices are connected as described in Figure 9.
Figure 9.
Agilent mode
STA2416
Agilent ADNS-2030
SPI_CLK
SPI_CLK
SPI_FRM
SPI_TXD
SPI_RXD
7.2.2
SPI_IO
Feature description: 32-bit SPI
One application is a Bluetooth™ stereo headset. In this application, the audio samples are
received from the emitter through the air using the Bluetooth™ baseband with ACL packets.
The samples are decoded by the embedded ARM CPU (the samples were encoded, for
compression, in SBC or MP3 format) and then sent to a stereo codec though the SPI
interface. The application is described in Figure 10.
Figure 10. 32-bit SPI
SPI_TXD
STA2416
Bluetooth
reception
SPI slave mode 32 bits
SPI_RXD
SPI_FRM
SPI_CLK
STw5094A CODEC
SPI master mode 32 bits
Stereo headset
32 SPI_CLK
16 SPI_CLK
To support this application, the data size is 32 bits. The 32-bit support is implemented for
both transmit and receive.
29/38
Interfaces
7.3
STA2416
I2C Interface
Used to access I2C peripherals.
The interface is a fast master I2C; it has full control of the interface at all times. I2C slave
functionality is not supported.
7.4
USB interface
The USB interface is compliant with the USB 2.0 full speed specification. Max throughput on
the USB interface is 12 Mbit/s.
Figure 11 gives an overview of the main components needed for supporting the USB
interface, as specified in the Bluetooth™ Core Specification. For clarity, the serial interface
(including the UART Transport Layer) is also shown.
Figure 11. USB Interface
HCI
UART TRANSPORT LAYER
USB DRIVER
SERIAL DRIVER
UART
DEVICE
REGISTERS
FIFOs
RTOS
IRQ
IRQ
STA2416 HW
D05AU1625
USB
DEVICE
REGISTERS
FIFOs
USB TRANSPORT LAYER
The USB device registers and FIFOs are memory mapped. The USB Driver will use these
registers to access the USB interface. The equivalent exists for the HCI communication over
UART.
For transmission to the host, the USB and Serial Drivers interface with the HW via a set of
registers and FIFOs, while in the other direction, the hardware may trigger the Drivers
through a set of interrupts (identified by the RTOS, and directed to the appropriate Driver
routines).
7.5
JTAG interface
The JTAG interface is compliant with the JTAG IEEE Std 1149.1. Its allows both the
boundary scan of the digital pins and the debug of the ARM7TDMI application when
connected with the standard ARM7 development tools.
30/38
STA2416
7.6
Interfaces
RF interface
The STA2416 radio interface is compatible to BlueRF (unidirectional RxMode2 for data and
unidirectional serial interface for control).
7.7
PCM voice interface
The voice interface is a direct PCM interface to connect to a standard CODEC (for example,
STw5093 or STw5094) including internal decimator and interpolator filters. The data can be
linear PCM (13 to 16-bit), µ-Law (8-bit) or A-Law (8-bit). By default the codec interface is
configured as master. The encoding on the air interface is programmable to be CVSD,
A-Law or µ-Law.
The PCM block is able to manage the PCM bus with up to three timeslots.
In master mode, PCM clock and data can operate at 2 MHz or at 2.048 MHz to allow
interfacing of standard codecs.
The four signals of the PCM interface are:
PCM_CLK:
PCM clock
PCM_SYNC:
PCM 8 KHz sync
PCM_A:
PCM data
PCM_B:
PCM data
Directions of PCM_A and PCM_B are software configurable.
Three additional PCM_SYNC signals can be provided via the GPIOs. See Chapter 10 on
page 35 for more details.
Figure 12. PCM (A-law, µ-law) standard mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PCM_CLK
PCM_SYNC
PCM_A
B
PCM_B
B
B
B
125µs
D02TL558
Figure 13. Linear mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PCM_CLK
PCM_SYNC
PCM_A
PCM_B
125µs
D02TL559
31/38
Interfaces
STA2416
Table 12.
PCM interface timing
Symbol
Description
Min
Typ
Max
Unit
PCM Interface
Fpcm_clk
Frequency of PCM_CLK (master)
Fpcm_sync Frequency of PCM_SYNC
kHz
8
kHz
tWCH
High period of PCM_CLK
200
ns
tWCL
Low period of PCM_CLK
200
ns
tWSH
High period of PCM_SYNC
200
ns
tSSC
Setup time, PCM_SYNC high to PCM_CLK low
100
ns
tSDC
Setup time, PCM_A/B input valid to PCM_CLK low
100
ns
tHCD
Hold time, PCM_CLK low to PCM_A/B input invalid
100
ns
tDCD
Delay time, PCM_CLK high to PCM_A/B output valid
150
Figure 14. PCM interface timing
tWCL
PCM_CLK
tWCH
tSSC
PCM_SYNC
tSDC
tWSH
PCM_A/B in
tHCD
MSB
MSB-1
MSB-2
MSB-3
MSB-4
tDCD
PCM_B/A out
MSB
MSB-1
MSB-2
MSB-3
MSB-4
D02TL557
32/38
2048
ns
STA2416
8
HCI UART transport layer
HCI UART transport layer
The UART Transport Layer has been specified by the Bluetooth™ SIG, and allows HCI level
communication between a host controller (STA2416) and a host (for example, PC), via a
serial line.
The objective of this HCI UART Transport Layer is to make it possible to use the Bluetooth™
HCI over a serial interface between two UARTs on the same PCB. The HCI UART Transport
Layer assumes that the UART communication is free from line errors.
8.1
UART settings
The HCI UART Transport Layer uses the following settings for RS232:
Baud rate:
Configurable (Default baud rate: 57.600 kbps)
Number of data bits:
8
Parity bit:
no parity
Stop bit:
1 stop bit
Flow control:
RTS/CTS
Flow-off response time: 3 ms
Flow control with RTS/CTS is used to prevent temporary UART buffer overrun. It should not
be used for flow control of HCI, since HCI has its own flow control mechanisms for HCI
commands, HCI events and HCI data.
If CTS is 1, then the Host/Host Controller is allowed to send.
If CTS is 0, then the Host/Host Controller is not allowed to send.
The flow-off response time defines the maximum time from setting RTS low until the byte
flow actually stops. The signals should be connected in a null-modem fashion; i.e. the local
TXD should be connected to the remote RXD and the local RTS should be connected to the
remote CTS and vice versa.
Figure 15. UART transport layer
BLUETHOOTH
HOST
BLUETHOOTH HCI
HCI UART TRANSPORT LAYER
BLUETHOOTH
HOST
CONTROLLER
D02TL556
33/38
HCI USB transport layer
9
STA2416
HCI USB transport layer
The USB Transport Layer has been specified by the Bluetooth™ SIG, and allows HCI level
communication between a host controller (STA2416) and a host (for example, PC), via a
USB interface. The USB Transport Layer is completely implemented in SW. It accepts HCI
messages from the HCI Layer, prepares it for transmission over a USB bus, and sends it to
the USB Driver. It reassembles the HCI messages from USB data received from the USB
Driver, and sends these messages to the HCI Layer. The Transport Layer does not interpret
the contents (payload) of the HCI messages; it only examines the header.
34/38
STA2416
10
Class1 power support
Class1 power support
The chip can control an external power amplifier (PA). Several signals are duplicated on
GPIOs for this purpose in order to avoid digital/analogue noise loops in the radio.
A software controlled register enables the alternate functions of GPIO [15:11] [9:6]to
generate the signals for driving an external PA in a Bluetooth™ class1 power application.
Every bit enables a dedicated signal on a GPIO pin, as described in Table 13.
Table 13.
GPIOs alternate functionalities
Involved GPIO
Description
GPIO0
No dedicated function
GPIO1
WLAN 1
GPIO2
WLAN 2
GPIO3
WLAN 3
GPIO4
WLAN 4
GPIO5
(Used for USB reset pull.)
GPIO6
Power Class 1 RX_ON
GPIO7
Power Class 1 NOT_RXON
GPIO8
Power Class 1 PA0 or PCM sync 1
GPIO9
Power Class 1 PA1 or PCM sync 2
GPIO11
Power Class 1 PA3
GPIO12
Power Class 1 PA4
GPIO13
Power Class 1 PA5
GPIO14
Power Class 1 PA6
GPIO15
Power Class 1 PA7
The signal BRXEN is the same as the RX_ON output pin. The signal NOT_BRXEN is the
inverted signal, in order to save components on the application board.
PA7 to PA0 are the power amplifier control lines. They are managed, on a connection basis,
by the baseband core. The Power Level programmed for a certain Bluetooth™ connection is
managed by the firmware, as specified in the Bluetooth™ SIG spec.
The WLAN signals, as described in Section 6.12: Bluetooth™ - WLAN coexistence in
collocated scenario on page 25, can be enabled on GIPIO pins
The WXTRA PCM sync signals, as described in Section 7.7: PCM voice interface on
page 31, can be flexibly configured on GPIO pins to connect multiple codecs.
35/38
Package information
11
STA2416
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 16. LFBGA120 (10x10x1.4mm) mechanical data and package dimensions
DIM.
A
A1
A2
b
D
D1
D2
E
E1
E2
eD
eE
FD
FE
mD
mE
n
SE
SD
aaa
bbb
ddd
eee
fff
MIN.
0.20
mm
TYP.
MAX.
1.40
MIN.
inch
TYP.
MAX.
0.055
0.008
1
0.039
0.30
0.35 0.010 0.012 0.014
10.00 10.10 0.390 0.394 0.398
8.50
0.335
6.50
0.256
9.90 10.00 10.10 0.390 0.394 0.398
8.50
0.335
6.50
0.256
0.50 basic
0.020 basic
0.50 basic
0.020 basic
0.75
0.029
0.75
0.029
18
18
120 balls
0.25 basic
0.0098 basic
0.25 basic
0.0098 basic
Tolerance
0.15
0.006
0.10
0.0039
0.08
0.0031
0.15
0.006
0.05
0.002
OUTLINE AND
MECHANICAL DATA
0.25
9.90
Body: 10 x 10 x 1.4mm
LFBGA120
Low Fine Ball Grid Array
7513355 A
36/38
STA2416
12
Revision history
Revision history
Table 14.
Document revision history
Date
Revision
20-Dec-2006
1
Changes
Initial release.
37/38
STA2416
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38/38