SiW3000 ULTIMATEBLUE™ RADIO PROCESSOR 0 Features Applications • • • • • Mobile phones. Notebook and desktop PCs. Cordless headsets. Personal digital assistants (PDAs). Computer accessories, peripherals, and wireless printers/ keyboards/mice). Sleep Control To Antenna 2.3 ~ 3.63 V • Single-chip IC with 2.4 GHz transceiver, baseband processor, and on-chip protocol stack for Bluetooth® wireless technology • Compliant with Bluetooth specification 1.2 features. • Low cost 0.18 µm CMOS process technology. • 1.8 V analog and digital core voltages; 1.62 V to 3.63 V external I/O interface voltage. • Typical -85 dBm receiver sensitivity, +2 dBm transmitter power for up to 100 meters nominal range. • On-chip VCO and PLL support multiple GSM/GPRS and CDMA cellular reference clock frequencies. • Hardware AGC dynamically adjusts receiver performance in changing environments. • Integrated 32-bit ARMTDMI® processor for extended features. • Full piconet connectivity with support for up to 7 active and 8 parked slaves. • Scatternet compatible with Microsoft® HID devices. • Supports three SCO voice channels. • Channel Quality Driven Data Rate (CQDDR) controls multi-slot packets to minimize packet overhead and maximize data throughput. • Option for Bluetooth + Wi-Fi coexistence. 2.4 GHz Direct Conversion Transceiver Voltage Reg MODEM Internal 32 kHz Clock Bluetooth Baseband with CVSD Power Management UART ARM7TDMI® Processor USB SRAM Data GPIO ROM HCI Firmware Audio CODEC Interface Fast Locking PLL Up to 2 Mbs USB Full Speed System I/O CODEC Master or Slave Crystal or Reference Clock Block Diagram Product Description The SiW3000 UltimateBlue™ Radio Processor is a recent innovation for Bluetooth® wireless technology. It combines the industry's best performing and most highly integrated radio design with an ARMTDMI® processor using CMOS technology. The SiW3000 uses direct conversion (zero-IF) architecture. This allows digital filtering for excellent interference rejection as compared to low IF solutions and also results in fewer spurious responses. The lower-layer protocol stack software is integrated into the on-chip ROM. Optional external Flash memory is also supported. The SiW3000 is compliant with Bluetooth specification 1.2 features. The device is available in multiple packages and bare die form with a guaranteed operating temperature range from -40°C to +85°C and an extended high temperature range to +105°C. Ordering Information SiW3000 UltimateBlue™ Radio Processor Optimum Technology Matching® Applied Si BJT GaAs HBT Si Bi-CMOS SiGe HBT GaInP/HBT GaN HEMT GaAs MESFET 9Si CMOS SiGe Bi-CMOS RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 60 0049 R01Drf SiW3000 Radio Processor DS September 30, 2004 1 of 24 SiW3000 Radio Features • Direct-conversion architecture with no external IF filter or VCO resonator components. • Single ended RF I/O reduces system bill of materials (BOM) costs by eliminating the need to use external balun and switch circuits. • On-chip VCO and PLL support multiple GSM, CDMA, GPRS standard reference clock frequencies. • Low out-of-band spurious emission transmitter prevents blocking of sensitive mobile phone RF circuits. • No tuning during production. • Internal temperature compensation circuit stabilizes performance across wide operating temperature. • Fast settling synthesizer reduces power consumption. • Up to 100 meter operating range in standard configuration without using an external PA. Baseband Features • ARM7TDMI processor core running at 16 MHz. • Digital GFSK modem for maximum performance and lower packet error rate. • On-chip CVSD conversion with hardware based gain adjustments to enhance audio quality. • Sleep control interface for low power operation modes. • Software execution from ROM or external FLASH memory. Standard Protocol Stack Features • Full piconet connectivity with support for up to 7 active and 8 parked slaves. • Able to establish up to 3 SCO connections. • Scatternet capable and compatible with Microsoft HID devices. • Standard Bluetooth test modes. • Low power connection states supported with hold, sniff, and park modes. Additional Protocol Stack Features • Channel Quality Driven Data Rate (CQDDR) optimizes data transfer rate in noisy or weak signal environments • Audio (SCO) routing over HCI interface for VOIP applications. • Support for Bluetooth + Wi-Fi coexistence technology. • Verified compatibility with multiple upper-layer stack vendors. • Extensive vendor specific HCI commands enables hardware specific controls. • Optional upper-layer stack and profiles can be licensed and integrated into the IC. Bluetooth 1.2 Features • Adaptive frequency hopping (AFH). • Faster connections. • LMP improvements. External System Interfaces Host HCI Transport (H:2 USB) The USB device interface provides a physical transport between the SiW3000 and the host for the transfer of Bluetooth control signals and data. This transport layer is fully compliant with Section H:2 of the Bluetooth specification with all end points supported. The SiW3000 USB interface encompasses three I/O signals: USB_DPLS, USB_DMNS, and USB_DPLS_PULLUP. If the USB transport is not used, the USB_DPLS and USB_DMNS pins should be grounded to reduce current consumption. 2 of 24 60 0049 R01Drf SiW3000 Radio Processor DS SiW3000 Host HCI Transport (H:4 UART) The high speed UART interface provides the physical transport between the SiW3000 and the application host for the transfer of Bluetooth control signals and data compliant to Section H:4 of the Bluetooth specification. The table below shows the supported baud rates. The default baud rate is 115,200, but can be configured depending on the application. SiW3000 Radio Processor HCI UART Parameters Required Host Setting Number of data bits Parity bit Stop bit Flow control Host flow-off response requirement from the SiW3000 SiW3000 IC flow-off response requirement from host 8 No parity 1 stop bit RTS/CTS 8 bytes 2 bytes Supported baud rates 9.6k, 19.2k, 38.4k, 57.6k, 115.2ka, 230.4k, 460.8k, 500k, 921.6k, 1M, 1.5M, 2M a.Default baud rate. Host HCI Transport (H:5 3-Wire UART) To reduce the number of signals and increase reliability of the HCI UART interface, a 3-wire UART using either the Bluetooth H:5 or BCSP protocol is supported. The selection between H:4, H:5, and BCSP is done automatically by the SiW3000, or can be set in NVM. SiW3000 Radio Processor HCI 3-Wire UART Parameters Number of data bits Parity bit Stop bit Error detection Sleep modes Required Host Setting 8 Even 1 stop bit Slip and checksum Shallow and deep Audio CODEC Interface The SiW3000 supports direct interface to an external audio CODEC or PCM host device. The interface is easily configured to support: • Standard 64-kHz PCM clock rate. • Up to 2-MHz clock rates with support for multi-slot handshakes and synchronization. • Either master or slave (Motorola SSI) mode. Configuration of the CODEC interface is done by the firmware during boot-up by reading non-volatile memory (NVM) parameters. The following are examples of supported CODEC modes: • Generic 64-kHz audio CODEC (e.g., OKI MSM-7702). • Motorola MC145481 or similar CODEC as master. • QUALCOMM MSM chip set audio port. • GSM/GPRS baseband IC audio ports. Programmable I/O (PIO) Up to twenty-nine (29) programmable IO (PIO) ports are available for customer use in the SiW3000. Three of these PIOs are dedicated and the remaining PIOs are shared with other functions. Availability of PIOs will depend on system configuration. The table below identifies the all twenty-nine PIOs and their usage. The PIO ports can be set to input or output. Reading, writing, and controlling the PIO pins by the host application software can be done via vendor specific HCI commands. 60 0049 R01Drf SiW3000 Radio Processor DS 3 of 24 SiW3000 PIO# Shared I/O Sampled at Reset PIO# Shared I/O Sampled at Reset 0 None Yes 15 PCM_OUT No 1 None Yes 16 PCM_IN No 2 None Yes 17 PCM_CLK No 3 D[8] No 18 PCM_SYNC No 4 D[4] No 19 EXT_WAKE No 5 D[5] No 20 HOST_WAKEUP No 6 D[6] No 21 UART_RXD No 7 D[7] No 22 UART_TXD No 8 PWR_REG_EN No 23 UART_CTS No 9 D[15] No 24 UART_RTS No 10 WE_N No 25 A[18] No 11 A[16] No 26 TX_RX_SWITCH No 12 A[17] No 27 D[9] No 13 A[11] No 28 D[10] No 14 USB_DPLS_PULLUP No External Memory Interface The Ultimate 3000 Radio Processor is a true single chip device and does not require additional memory for standard below HCI protocol functions. An external memory interface is available for adding optional memory. If external Flash memory will be used, the read access time of the device must be 100 ns or less. The external memory interface permits connection to Flash and SRAM devices. The interface has an 18-bit address bus and a 16-bit data bus for a total addressable memory of 512 KB. In certain embedded applications, both SRAM and Flash can be installed by using the high order address bit as an alternate chip select. Signal Description Address A[1] - A[18] 18-bit address bus Data D[0] - D[15] 16-bit data bus FCS_N Chip select OE_N Output enable WE_N Write enable External EEPROM Controller and Interface This interface is intended for use with ROM-based solutions. The EEPROM is not required for configurations with external flash. The EEPROM is the non-volatile memory (NVM) in the system and contains the system configuration parameters such as the Bluetooth device address, the CODEC type, as well as other parameters. These default parameters are set at the factory, and some parameters will change depending on the system configuration. Optionally, the non-volatile memory parameters can be downloaded from the host processor at boot up eliminating the need for EEPROM. Please consult the application support team for details. The EEPROMs should have a serial I2C interface with a minimum size of 2 Kbits and 16-byte page write buffer capabilities. Power Management The HOST_WAKEUP and EXT_WAKE signals are used for power management. HOST_WAKEUP is an output signal used to wake up the host. EXT_WAKE is an input signal used by the host to wake up the SiW3000 Radio Processor from sleep mode. For more information on the usage of HOST_WAKE and EXT_WAKE, please refer to RFMD application note 62 0031. 4 of 24 60 0049 R01Drf SiW3000 Radio Processor DS SiW3000 General System Requirements System Reference Clock The SiW3000 chip can use either an external crystal or a reference clock as the system clock input. The supported frequencies are: 9.6 MHz, 12 MHz, 12.8 MHz, 13 MHz, 14.4 MHz, 15.36 MHz, 16 MHz, 16.8 MHz, 19.2 MHz, 19.68 MHz, 19.8 MHz, 26 MHz, 32 MHz, 38.4 MHz, and 48 MHz. The default reference frequency can be selected by setting the proper system configuration parameter in the non-volatile memory (NVM). If the USB HCI transport will be used, the reference clock must be 32 MHz. The system reference crystal/clock must have accuracy of ±20 PPM or better to meet the specification of Bluetooth. To facilitate design and production, the SiW3000 processor incorporates internal crystal calibration circuits to allow factory calibration of initial crystal frequency accuracy. Low Power Clock For the Bluetooth low power clock, a 32.768-kHz crystal may be used to drive the SiW3000 oscillator circuit, or alternatively, a 32.768-kHz reference clock signal can be used instead of a crystal. If the lowest power consumption is not required during low-power modes such as sniff, hold, park, and idle modes, the 32.768-kHz crystal may be omitted in the design. If the 32.768-kHz clock source will be used, the clock source should be connected to the CLK32_IN pin and must meet the following requirements: • For AC-coupled via 100 pF or greater (peak-to-peak voltage): 400 mVP-P < CLK32_IN < VDD_C • For DC-coupled: CLK32_IN minimum peak voltage < VIL CLK32_IN maximum peak voltage > VIH Where VIL = 0.3 * VDD_C Where VIH = 0.7 * VDD_C For both cases, the signal is not to exceed: -0.3 V < CLK32_IN < VDD_C + 0.3 V Also, the CLK32_OUT pin must be coupled to VDD_P or GND through a 100 nF capacitor. Power Supply Description The SiW3000 Radio Processor operates at 1.8 V core voltage for internal analog and digital circuits. The chip has internal analog and digital voltage regulators simplifying power supply requirements to the chip. The internal voltage regulators can be supplied directly from a battery or from other system voltage sources. Optionally, the internal regulators can be by-passed if 1.8 V regulated source is available on the system. Function Internal Analog Regulator Internal Digital Regulator VBATT_ANA = 2.3 to 3.63 V VBATT_DIG = 2.3 to 3.63 V VCC_OUT = 1.8 V VDD_C = 1.8 V Function Analog Core Circuits Digital Core Circuits Circuit voltage supply pin VCC = 1.8 V VDD_C = 1.8 V Regulator input pin Regulator output pin Table 1. Internal Regulator Used Table 2. Internal Regulator Bypassed Note: Both regulators can be bypassed if external regulation is desired. When bypassing the analog regulator, the VBATT_ANA and VCC_OUT pins must be tied together and the external analog voltage (1.8 V) should be applied to the VBATT_ANA pin. When bypassing the digital regulator, the VBATT_DIG pin should be left unconnected and the external digital voltage (1.8 V) should be applied to VBB_OUT pin. The power for the I/Os is taken from a separate source (VDD_P). VDD_P can range from 1.62 to 3.63 Volts to maintain compatibility with a wide range of peripheral devices. Please check the pin list for the exact pins that are powered from the VDD_P source. Power for the USB circuits is taken from a separate source (VDD_USB). 60 0049 R01Drf SiW3000 Radio Processor DS 5 of 24 SiW3000 RF I/O Description The SiW3000 processor employs single-ended RF input and output pins for reduced external components. In typical Class-2 (0 dBm nominal) applications, simple LC network matching circuits will be required to combine the two ports into a single antenna port and provide impedance matching. Please refer to the RF impedance table and the application circuits for values and matching circuit examples. The SiW3000 can be used to design Class-1 (+20 dBm) products with the addition of power amplifier circuits. Control signals are available to facilitate the design of the external PA circuit. Reset The SiW3000 processor can be reset by asserting the RESET_N signal to the chip (active low). Upon applying power, the RESET_N must be asserted until voltage supply and internal voltage regulators have stabilized. A simple RC circuit can be used to provide the power-on reset signal to the SiW3000. On-Chip Memory The SiW3000 Radio Processor integrates both SRAM and ROM. The ROM is pre-programmed with Bluetooth protocol stack software (HCI software) and boot code that executes automatically upon reset. The boot code serves to control the boot sequence as well as to direct the execution to the appropriate memory for continued operation. Configuration Selection HCI Transport Interface Selection The HCI transport (USB or UART) is selected on power up by sampling PIO2. If UART is selected, the selection of the particular UART transport (H:4 or H:5) is performed automatically by the software. Value (PIO 2) Description 0 1 UART USB Reference Frequency Selection The SiW3000 radio processor is designed to operate with multiple reference frequencies. During boot up the processor samples PIO pins to determine the default reference frequency. If the USB transport is selected, the default reference frequency will always be 32 MHz. If the UART transport is selected, the reference frequency setting will be set according to the following table: PIO 1 USB_DPLS_PULLUP Reference Frequency Selection 1 Don't Care Reference frequency per NVM system configuration setting, or if NVM is not set, defaults to 32 MHz. 0 0 13 MHz 0 1 26 MHz Application Software Memory Selection The SiW3000 can support application (protocol stack) software execution from internal ROM and external FLASH memory. To run from internal ROM, D[9] and D[10] pins must be connected together as shown in the application circuit section of this document. To run from external FLASH memory the FLASH must be connected as shown in the application circuit diagram and contain valid application code. If an external memory does not have valid program data, the device enters a download mode in which a valid program may be loaded into the external memory through a sequence of commands over the HCI transport layer. 6 of 24 60 0049 R01Drf SiW3000 Radio Processor DS SiW3000 Pin Description The following table provides detailed listings of pin descriptions arranged by functional groupings. Name Pad Type Ball Description Radio (Power from VCC) RF_IN RF_OUT Analog Analog A2 A4 VTUNE Analog A6 CHG_PUMP Analog F1 XTAL_N Analog A7 XTAL_P/CLK Analog B7 IDAC Analog B1 VREFP_CAP VREFN_CAP Analog Analog C1 C2 RF signal input into the receiver. RF signal output from the transmitter. Pin for reference PLL loop filter, only used if reference frequency is not integer multiples of 4 MHz. Pin for RF loop filter. System clock crystal negative input. If a reference clock is used, this pin should be left unconnected. System clock crystal positive input or reference clock input. Power control to external power amplifier. This output provides a variable current source that can be used to control the external power amp. Leave unconnected if not used. Decoupling capacitor for internal A/D converter voltage reference. Decoupling capacitor for internal A/D converter voltage reference. Low Power Oscillator and Reset (Power from VDD_P) CLK32K_IN CLK32K_OUT RESET_N Analog Analog Analog K10 L11 C6 For crystal or external clock input (32.768 kHz). Drive for crystal. System level reset (active low). Power Control Interface (Power from VDD_P) PWR_REG_EN/PIO[8] CMOS bi-directional G1 TX_RX_SWITCH J9 CMOS output Enable for an external voltage regulator. Programmable active high or active low. Also used as PIO[8], which is the default mode until the appropriate configuration bit is set. Tie to ground if not used. Output signal used to indicate the current state of the radio. This could be used as a direction control for an external power amplifier.The polarity is programmable with the default set as: Low = Transmit mode High = Receive mode Table 3. SiW3000 Radio Processor Pin List 60 0049 R01Drf SiW3000 Radio Processor DS 7 of 24 SiW3000 Name Pad Type Ball Description Programmable I/O (Power from VDD_P) Programmable input/output. PIO[0] CMOS bi-directional K5 Needs to be low until internal reset goes high or tie to ground if not used. Programmable input/output. Sampled following reset for frequency selection: PIO[1] CMOS bi-directional B8 If UART transport is selected and PIO[1] = 0, frequency is selected by the state of USB_DPLS_PULLUP pin. If UART transport is selected and PIO[1] = 1, frequency is selected by NVM parameter. Default for proper UART operation will be configured as 32 MHz. If USB transport is selected, PIO[1] is ignored and the frequency will be configured as 32 MHz. Programmable input/output. PIO[2] CMOS bi-directional J10 Sampled following reset for transport selection: PIO[2] = 0, selects UART transport PIO[2] = 1, selects USB transport PCM data to the PCM CODEC. PCM data from the remote device. Normally an input. PCM synchronous data clock to the remote device. Normally an output. Input for Motorola SSI slave mode. PCM synchronization data strobe to the remote device. Normally an output. Input for Motorola SSI slave mode. PCM Interface (Power from VDD_P) PCM_IN PCM_OUT CMOS output CMOS input E10 F10 PCM_CLK CMOS bi-directional G10 PCM_SYNC CMOS bi-directional H10 UART Interface (Power from VDD_P) UART_RXD UART_TXD UART_CTS UART_RTS EXT_WAKE HOST_WAKEUP CMOS input CMOS output CMOS input CMOS output CMOS input CMOS output K7 K3 K6 G9 F3 G2 UART receive data. UART transmit data. UART flow control clear to send. UART flow control ready to send. Wake up signal from host. Wake up signal to host. K9 K8 USB differential pair positive signal. USB differential pair negative signal. Output signal for controlling the on/off of the pull-up of the USB_DPLS line. For UART transport, this pin is sampled following reset for frequency selection if PIO[1] = 0: USB_DPLS_ PULLUP = 0, selects 13 MHz USB_DPLS_ PULLUP = 1, selects 26 MHz USB Interface (Power from VDD_USB) USB_DPLS USB_DMNS Analog Analog USB_DPLS_ PULLUP CMOS bi-directional J8 Table 3. SiW3000 Radio Processor Pin List (Continued) 8 of 24 60 0049 R01Drf SiW3000 Radio Processor DS SiW3000 Name Pad Type Ball Description External Memory Interface (power from VDD_P) A[18] A[17]/EEPROM_SCL A[16]/EEPROM_SDA A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]/PIO[3] D[7]/PIO[7] D[6]/PIO[6] D[5]/PIO[5] D[4]/PIO[4] D[3] D[2] D[1] D[0] OE_N CMOS output L1 G3 H1 A8 H2 C9 H3 J1 K4 J7 L4 A11 L7 F9 E11 E9 D11 D9 B11 C10 C11 B10 G11 H11 H9 J2 J11 D10 L3 L2 J4 J3 K2 K1 A10 WE_N/EEPROM_WP CMOS output K11 FCS_N CMOS output B9 VBATT_ANA VBATT_DIG VCC_OUT Power Power Power VDD_P Power VDD_USB Power VDD_C Power VCC Power VSS_P GND VSS_C GND VSS_USB GND D3 L8 D1 F11 L5 L10 A9 L6 A1 B6 C4 C5 E1 E3 C7 J5 C8 J6 L9 CMOS output CMOS bi-directional with internal pull-down Address lines. Note: A[17] and A[16] can be used to support an optional external serial EEPROM when using the internal ROM in place of the external Flash memory. Data lines. Note: D[4] through D[8] can be used as programmable I/O when using the internal ROM in place of the external Flash memory. Note: Connect D[9] to D[10] to use internal ROM. Output enable for external memory (active low). Write enable for external memory (active low). Note: Can be used to support an optional external serial EEPROM when using the internal ROM in place of external Flash memory. Chip select for external memory (active low). Power and Ground Positive supply to internal analog voltage regulator. Positive supply to internal digital voltage regulator. Regulated output from internal analog voltage regulator. Positive supply for digital input/output ports including peripheral interface, external memory interface, and UART interface. Positive supply for USB Interface. Positive supply for digital circuitry or output of internal digital voltage. Positive supply for RF and analog circuitry. Ground connections for digital input/output ports including peripheral interface, external memory interface, and UART Interface. Ground connections for internal digital circuitry. Ground connections for USB Interface. Table 3. SiW3000 Radio Processor Pin List (Continued) 60 0049 R01Drf SiW3000 Radio Processor DS 9 of 24 SiW3000 Name GND Pad Type GND Ball A3 A5 B2 B3 B4 B5 C3 D2 E2 F2 Description Ground connections for RF and analog circuitry. Table 3. SiW3000 Radio Processor Pin List (Continued) 10 of 24 60 0049 R01Drf SiW3000 Radio Processor DS SiW3000 System Specifications Absolute Maximum Ratings Parameter Description Min Max VCC Analog circuit supply voltage -0.3 3.63 VDD_IO I/O supply voltage -0.3 3.63 VBATT_ANA Analog regulator supply voltage -0.3 3.63 VBATT_DIG Digital regulator supply voltage -0.3 3.63 TST Storage temperature -55 +125 RFMAX Maximum RF input level – +5 Absolute maximum ratings indicate limits beyond which the useful life of the device may be impaired or damage may occur. Unit V V V V °C dBm Recommended Operating Conditions Parameter TOP TEOP VBATT_ANA VBATT_DIG VCC VDD_C VDD_P VDD_USB Description Operating temperature (industrial grade) Extended operating temperature Unregulated supply voltage into internal analog regulator Unregulated supply voltage into internal digital regulator Regulated supply voltage directly into analog circuits Regulated supply voltage directly into digital circuits Digital interface I/O supply voltage Regulated supply voltage for USB Interface to meet USB specification requirements Min Max Unit -40 -40 2.3 2.3 1.71 1.62 1.62 +85 +105 3.63 3.63 1.89 2.16 3.63 °C °C V V V V V 3.1 3.63 V ESD Rating Symbol ESD Description Rating ESD protection - all pins 2000 V Note: This device is a high performance RF integrated circuit with an ESD rating of 2,000 volts (HBM conditions per Mil-Std-883, Method 3015). Handling and assembly of this device should only be done using appropriate ESD controlled processes. Electrical Characteristics DC Specification (TOP =+25 °C, VDD_P =3.0 V) Symbol VIL VIH Description Input low voltage Input high voltage VOL Output low voltage VOH Output high voltage IOH IOL IILI Output high current Output high current (ball J8) Output low current Output low current (ball J8) Input leakage current AC Characteristics (TOP = +25 °C, VDD_P =3.0 V, CLOAD =15 pF) Symbol Description tr tf Rise time Fall time 60 0049 R01Drf SiW3000 Radio Processor DS Min. Typ. Max. Unit GND-0.1 – 0.3 . VDD_P V – VDD_P V . 0.7 VDD_P GND . 0.8 VDD_P – – – – – . – 0.2 VDD_P V – VDD_P V 1 4 1 4 1 – – – – – mA mA mA mA µA Max. Unit 30 24 ns ns 11 of 24 SiW3000 Current Consumption (TOP = +25 °C, VBATT =3.0 V using internal regulators) Operating Mode Standby Parked slave, 1.28 sec. interval Page/Inquiry scan, 1.28 sec. interval ACL connection, sniff mode, 100 ms interval ACL data transfer 720 kbps, DH5 continuous packets SCO connection, HV1 packets SCO connection, HV3 packets Average Unit 25 160 1.5 1.2 60 60 32 µA µA mA mA mA mA mA Digital Regulator Specification (TOP = 25 °C) Parameter Description Min Typ Max Unit 1.62 1.85 2.16 V (I OUT = 0 mA, VBATT_DIG = 2.3 V to 3.63 V) – 8.0 – mV Load regulation (I OUT = 3 mA to 80 mA) – 9.0 – mV Dropout voltage (I OUT = 10 mA) – – 250 mV Output maximum current – – – 80 mA Quiescent current – – 10 – µA Ripple rejection f RIPPLE = 400 Hz – 40 – dB Min Typ Max Unit 2402 – 2480 MHz – 55 100 µs Min Typ Max Unit – – – – 769//1.1 26//2.4 142//1.8 45.7//0 – – – – Ω/pF Ω/pF Ω/pF Ω/pF Output voltage (I OUT = 10 mA) Line regulation Radio Specification Parameter VCO Operating Range PLL lock time Description Frequency – RF Impedances Parametera RF impedance Description TX on TX off RX on RX off a.The impedance values are for typical samples in 96-pin VFBGA package. 12 of 24 60 0049 R01Drf SiW3000 Radio Processor DS SiW3000 Receiver Specification (VBATT = 3.3 V, VCC =int. analog reg. output, nominal Bluetooth test conditions) Parameter Min Typ Max Unit Receiver sensitivity BER < 0.1% – -85 -80 dBm Maximum usable signal BER < 0.1% – 0 – dBm C/I co-channel (0.1% BER) Co-channel selectivity – 8 11 dB C/I 1 MHz (0.1% BER) Adjacent channel selectivity – -4 0 dB C/I 2 MHz (0.1% BER) 2nd adjacent channel selectivity – -38 -35 dB C/I ≥ 3 MHz (0.1% BER) 3rd adjacent channel selectivity – -43 -40 dB Out-of-band blocking Intermodulation Receiver spurious emission Note: Description 30 MHz - 2000 MHz -10 – – dBm 2000 MHz - 2399 MHz -27 – – dBm 2498 MHz - 3000 MHz -27 – – dBm 3000 MHz - 12.75 GHz -10 – – dBm Max interferer level to maintain 0.1% BER, interference signals at 3 and 6 MHz offset. -39 -36 – dBm 30 MHz to 1 GHz – – -57 dBm 1 GHz to 12.75 GHz – – -47 dBm Nominal and extreme Bluetooth test conditions as defined by the Bluetooth Test and Interoperability Working Group published RF Test Specification 1.1. Transmitter Specification (VBATT = 3.3 V, VCC = int. analog reg. output, nom. Bluetooth test conditions) Parameter Description Output RF transmit At maximum power output level power Min Typ Max Units -2 +2 +6 dBm Modulation index – 0.28 0.306 0.35 – Initial carrier frequency accuracy – -75 – +75 kHz One slot packet -25 – +25 kHz Two slot packet -40 – +40 kHz Five slot packet -40 – +40 kHz Max drift rate – – 400 Hz/µs Bluetooth specification – – 1000 kHz 2 MHz offset – -74 -55 dBm Carrier frequency drift 20 dB occupied bandwidth In-band spurious emission Out-of-band spurious emission >3 MHz offset – -74 -55 dBm 30 MHz to 1 GHz, operating mode – -70 -55 dBm 1 GHz to 12.75 GHz, operating modea – -70 -50 dBm 1.8 GHz to 1.9 GHz – – -62 dBm 5.15 GHz to 5.3 GHz – – -47 dBm a.Except transmit harmonics. 60 0049 R01Drf SiW3000 Radio Processor DS 13 of 24 SiW3000 System Requirements Analog Voltage Supply Requirements The SiW3000 processor is designed for use with integrated low noise analog voltage regulators and is recommended for all applications. If necessary, the internal analog regulator can be bypassed. In situations where bypassing the internal analog regulator is required, the supply voltage to the analog circuit must satisfy the following requirements to preserve the RF performance characteristics. Description Min Max Unit VCC Parameter Analog supply voltage to all VCC input pins 1.71 1.89 V Minimum load current External regulator current 80 – mA Minimum ripple rejection at 400Hz 40 – dB Output noise Integrated 10 Hz to 80 kHz noise – 22 mV RMS External Reference Requirements It is possible to provide a number of reference frequencies that are typical on most cellular phones directly into ball B7 (XTAL_P/CLK) of the device. The following reference frequencies (in MHz) can be used: 3.84, 9.6, 12, 12.8, 13, 14.4, 15.36, 16, 16.8, 19.2, 19.68, 19.8, 26, 32, 38.4, and 48 MHz. For other frequencies, please contact RFMD. Parameter Phase noise Description Min Max Units 100 Hz offset – -100 dBc/Hz 1 kHz offset – -120 dBc/Hz 10 kHz offset – -140 dBc/Hz AC amplitude 0.5 VCC VP-P 0.3 VCC V Drive level a DC level a.If DC-coupled, the external reference signal voltage must stay within this range at all times. Reference Crystal Requirements Many reference frequencies are supported by the device. If a crystal is used as the reference frequency source, the typical required parameters are listed below: Parameter Drive level ESR CO Description – a Effective serial resistance b Holder capacitance b Min Typ Max Unit – – 0.3 mW – – 150 W – 3 5 pF CL Load capacitance – 12 18 pF CM Motional capacitance – 6 – fF a.For 32-MHz crystal. b.The actual values for CO and CL are dependent on the crystal manufacturer and can be compensated for by an internal crystal calibration capability. 14 of 24 60 0049 R01Drf SiW3000 Radio Processor DS 2 OUT IN 1 L4 4.7nH L5 3.3nH L3 3.9nH R2, C16, and C17 are not required for 32MHz applications. For component values using other frequencies, refer to the reference design application note. RF_IN_OUT C11 2.7pF C7 8.2pF C12 2.7pF VCC C15 C14 C17 2.7nH L6 DNI C16 22pF R2 DNI 180pF C13 1.8pF L2 3.3nH L1 18nH C19 C18 DNI R1 47K 0.1uF 0.1uF C2 C1 B1 J9 A6 F1 A2 A4 Y1 XTL 32MHz 1 3 VREFN_CAP VREFP_CAP IDAC TX_RX_SWITCH VTUNE CHG_PUMP RF_IN RF_OUT U1 C8 18pF A7 XTAL_N B7 XTAL_P/CLK FL1 Shosin Filter HMD846H VCC C6 8.2pF VCC C1 1uF VBATT SiW3000 C2 1uF C3 0.1uF C10 1uF U2 2M or 4M FLASH RY/BY# RESET# BYTE# VCC CLK32K_IN C4 0.1uF L10 A3 B4 F6 G4 C21 0.1uF VDD_P RESET_N PCM_CLK PCM_SYNC PCM_IN PCM_OUT PIO[0] PIO[1] PIO[2] C6 G10 H10 E10 F10 K5 B8 J10 F3 G2 K7 K3 K6 G9 J8 K9 K8 G1 L11 K10 R3 100K EXT_WAKE HOST_WAKEUP UART_RXD UART_TXD UART_CTS UART_RTS USB_DPLS_PULLUP USB_DPLS USB_DMNS PWR_REG_EN/PIO[8] CLK32K_OUT VDD_P VDD_USB (EXTERNAL FLASH CONFIGURATION) C9 18pF C5 8.2pF VCC is the output from the internal voltage regulator. GND GND H1 H6 VSS_P VSS_P VSS_C VSS_C VSS_USB C7 J5 C8 J6 L9 A[18] A[17]/EEPROM_SCL A[16]/EEPROM_SDA A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] L1 G3 H1 A8 H2 C9 H3 J1 K4 J7 L4 A11 L7 F9 E11 E9 D11 D9 B2 E6 D6 C6 A6 B6 D5 C5 A5 B5 A2 C2 D2 B1 A1 C1 D1 E1 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 NC NC NC NC NC B3 C3 D3 C4 D4 D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]/PIO[3] D[7]/PIO[7] D[6]/PIO[6] D[5]/PIO[5] D[4]/PIO[4] D[3] D[2] D[1] D[0] B11 C10 C11 B10 G11 H11 H9 J2 J11 D10 L3 L2 J4 J3 K2 K1 G6 F5 G5 F4 G3 F3 G2 F2 E5 H5 E4 H4 H3 E3 H2 E2 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A4 F1 G1 GND GND GND GND GND GND GND GND GND GND A3 A5 B2 B3 B4 B5 C3 D2 E2 F2 D1 VCC_OUT C4 B6 A1 C5 E3 E1 VCC VCC VCC VCC VCC VCC L8 VBATT_DIG D3 VBATT_ANA L6 A9 VDD_C VDD_C F11 L5 VDD_P VDD_P K11 B9 WE_N/EEPROM_WP A10 FCS_N OE_N 60 0049 R01Drf SiW3000 Radio Processor DS WE CE OE VDD_USB Note: Filter is not required to meet BT and FCC specifications but may be added if better out-of-band performance is desired. C20 0.1uF SiW3000 Application Circuit for External Flash-based Products 15 of 24 HOST INTERFACE 2 OUT IN 1 L4 4.7nH C11 2.7pF L5 3.3nH L3 3.9nH C7 8.2pF R2, C16, and C17 are not required for 32MHz applications. For component values using other frequencies, refer to the reference design application note. RF_IN_OUT FL1 Shosin Filter HMD846H C12 2.7pF VCC C15 C14 C17 2.7nH L6 DNI C16 22pF R2 DNI 180pF C13 1.8pF L2 3.3nH L1 18nH C19 C18 DNI R1 47K 0.1uF 0.1uF VREFN_CAP VREFP_CAP IDAC TX_RX_SWITCH VTUNE CHG_PUMP RF_IN RF_OUT C21 0.1uF C2 C1 B1 J9 A6 F1 A2 A4 U1 C8 18pF B7 1 2 3 A0 A1 A2 U2 A3 A5 B2 B3 B4 B5 C3 D2 E2 F2 GND GND GND GND GND GND GND GND GND GND XTAL_P/CLK A7 XTAL_N Y1 XTL 32MHz 1 3 7 6 5 EEPROM WP SCL SDA C5 8.2pF C1 1uF SiW3000 C6 8.2pF VCC VBATT C2 1uF C10 1uF (INTERNAL ROM CONFIGURATION) C9 18pF VDD_P 8 VCC VCC is the output from the internal voltage regulator. GND 4 A[18] A[17]/EEPROM_SCL A[16]/EEPROM_SDA A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] R5 10K R4 10K VDD_P L1 G3 H1 A8 H2 C9 H3 J1 K4 J7 L4 A11 L7 F9 E11 E9 D11 D9 VSS_P VSS_P VSS_C VSS_C VSS_USB C7 J5 C8 J6 L9 VCC D1 VCC_OUT C4 B6 A1 C5 E3 E1 VCC VCC VCC VCC VCC VCC L8 VBATT_DIG D3 VBATT_ANA L6 A9 VDD_C VDD_C D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]/PIO[3] D[7]/PIO[7] D[6]/PIO[6] D[5]/PIO[5] D[4]/PIO[4] D[3] D[2] D[1] D[0] Connect D[9] to D[10] to select internal ROM mode. B11 C10 C11 B10 G11 H11 H9 J2 J11 D10 L3 L2 J4 J3 K2 K1 CLK32K_IN C4 0.1uF RESET_N PCM_CLK PCM_SYNC PCM_IN PCM_OUT PIO[0] PIO[1] PIO[2] EXT_WAKE HOST_WAKEUP UART_RXD UART_TXD UART_CTS UART_RTS USB_DPLS_PULLUP USB_DPLS USB_DMNS PWR_REG_EN/PIO[8] CLK32K_OUT VDD_USB L10 VDD_P C3 0.1uF F11 L5 VDD_P VDD_P K11 B9 WE_N/EEPROM_WP A10 FCS_N OE_N 16 of 24 VDD_USB Note: Filter is not required to meet BT and FCC specifications but may be added if better out-of-band performance is desired. C20 0.1uF C6 G10 H10 E10 F10 K5 B8 J10 F3 G2 K7 K3 K6 G9 J8 K9 K8 G1 L11 K10 R3 100K VDD_P SiW3000 Application Circuit for Internal ROM-based Products 60 0049 R01Drf SiW3000 Radio Processor DS HOST INTERFACE SiW3000 I/O Configuration (Top View) 1 A B C 2 3 E F G J L 7 8 9 10 11 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 RF_IN GND RF_OUT GND VTUNE XTAL_N A[15] VDD_C OE_N A[7] B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 IDAC GND GND GND GND VCC XTAL_P/CLK PIO[1] FCS_N D[12] D[15] C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 GND VCC VCC RESET_N VSS_P VSS_C A[13] D[14] D[13] D1 D2 VCC_OUT GND E1 E2 E3 VCC GND VCC F1 F2 F3 CHP_PUMP GND G1 D3 VBATT_ANA EXT_WAKE G2 HOST_ WAKEUP SiW3000 TOP VIEW G3 A[17]/ EEPROM_SCL D9 D10 D11 A[1] D[6]/PIO[6] A[2] E9 E10 E11 A[3] PCM_IN A[4] F9 F10 F11 A[5] PCM_OUT VDD_P G9 G10 UART_RTS PCM_CLK G11 D[11] H1 H2 H3 H9 H10 H11 A[16]/ EEPROM_SDA A[14] A[12] D[9] PCM_SYNC D[10] J1 J2 J3 J9 J10 J11 A[11] K 6 A1 PWR_REG_EN/ PIO[8] H 5 VCC VREFP_CAP VREFN_CAP D 4 D[8]/PIO[3] D[2] J4 D[3] J5 VSS_P K1 K2 K3 K4 K5 D[0] D[1] UART_TXD A[10] PIO[0] L2 L3 L1 A[18] D[4]/PIO[4] D[5]/PIO[5] J6 J7 J8 VSS_C A[9] USB_DPLS_ PULLUP K6 K7 K8 TX_RX_SWITCH PIO[2] K9 K10 UART_CTS UART_RXD USB_DMNS USB_DPLS CLK32K_IN L4 L5 L6 L7 L8 A[8] VDD_P VDD_C A[6] VBATT_DIG L9 L10 VSS_USB VDD_USB D[7]/PIO[7] K11 WE_N/ EEPROM_WP L11 CLK32K_OUT POWER DIGITAL GROUND RF GROUND 60 0049 R01Drf SiW3000 Radio Processor DS 17 of 24 SiW3000 Packaging and Product Marking Package Drawing 96-Pin, 6 mm x 6 mm, VFBGA Drawing and Dimensions Symbol A A1 A2 A3 b D E e D1 E1 18 of 24 Min 0.8 0.2 Max 1.0 0.3 0.22 REF 0.45 REF 0.25 0.35 6 BSC 6 BSC 0.5 BSC 5 BSC 5 BSC Notes: 1. Dimension b is measured at the maximum solder ball diameter, parallel to datum plane Z. 2. Datum Z is defined by the spherical crowns of the solder balls. 3. Parallelism measurement shall exclude any effect of mark on top surface of package. 4. All dimensions are in millimeters. 60 0049 R01Drf SiW3000 Radio Processor DS SiW3000 Package Drawing 96-Pin, 10 mm x 10 mm, LFBGA Drawing and Dimensions Symbol Min Max A A1 A2 A3 b D E e D1 E1 0.27 1.4 0.37 0.26 REF 0.8 REF 0.35 0.45 10 BSC 10 BSC 0.8 BSC 8 BSC 8 BSC Notes: 1. Dimension b is measured at the maximum solder ball diameter, parallel to datum plane Z. 2. Datum Z is defined by the spherical crowns of the solder balls. 3. Parallelism measurement shall exclude any effect of mark on top surface of package. 4. All dimensions are in millimeters. 5. Dimensions and tolerances: ASME Y14.5M. 6. Reference document: JEDEC-MO-210. 60 0049 R01Drf SiW3000 Radio Processor DS 19 of 24 SiW3000 Product Marking Pin 1 Corner SIW Trace Code 3000GIP1 LLLLL YYWW 4 Digit Date Code SiW3000AIP1 LLLLL YYWW ARM Note: Drawing not to scale. 10-by-10-mm LFBGA ARM 6-by-6-mm VFBGA Tape and Reel Specification 20 of 24 Carrier Tape: ADV ML0707-A Reel Type: Klik Reel (16 mm) 13" dia. QTY/Reel 2500 Peel Test: 20–80 grams Cover Tape: RS Standard (anti-static) Leader: 500 mm (minimum 400 mm) Trailer: 250 mm (minimum 160 mm) Peel Speed: 300 mm/minute 60 0049 R01Drf SiW3000 Radio Processor DS SiW3000 Tape Detail (6 mm x 6 mm VFBGA) DIRECTION OF FEED 0.25 See Note 1 0.30 ±0.05 4.0 See Note 6 1.50 (MIN) 2.0 1.50 +0.1 0.0 1.75 A R0.30 (TYP.) 7.5 See Note 6 16 ±0.3 Bo R0.25 B B A Ao Ko 12.0 Ao= 6.30 mm Bo= 6.30 mm Ko= 1.50 mm SECTION A-A SECTION B-B Note: 1. 2. 3. 4. 5. 6. 7. 8. Tolerances ±0.10 unless otherwise specified. 10 sprocket hole pitch cumulative tolerance ±0.2 Camber not to exceed 1mm in 100 mm. Material: Black Advantek Polystyrene. Ao and Bo measured on a plane 0.3 mm above the bottom of the pocket. Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. All dimensions in millimeters. 60 0049 R01Drf SiW3000 Radio Processor DS 21 of 24 SiW3000 Reel Dimensions: Klik Reel Tape Width A B(min) C D (min) N (min) W1 16 330 1.50 13.00+0.5 20.20 100 16.4+2.0 -0.00 Note: 22 of 24 W2 (max) W3 (min) W3 (max) 22.40 15.90 19.40 All dimensions in millimeters (mm) unless otherwise stated. 60 0049 R01Drf SiW3000 Radio Processor DS SiW3000 Ordering Information Part Number Operational Temperature Range1 SiW3000GIP1 Industrial SiW3000GIP1-T13 Industrial SiW3000GIG1 Industrial SiW3000GIG1-T13 Industrial SiW3000AIP1 Industrial SiW3000AIP1-T13 Industrial 1 Package 96-pin VFBGA 6-by-6-mm 96-pin VFBGA 6-by-6-mm 96-pin VFBGA 6-by-6-mm Green 96-pin VFBGA 6-by-6-mm Green 96-pin LFBGA 10-by-10-mm 96-pin LFBGA 10-by-10-mm Ordering Quantity 429 pcs. per tray 2500 on 13” reel 429 pcs. per tray 2500 on 13” reel 360 pcs. per tray 1500 on 13” reel Industrial temperature range: -40°C to +85°C 60 0049 R01Drf SiW3000 Radio Processor DS 23 of 24 SiW3000 RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. RF Micro Devices reserves the right to make changes to its products without notice and advises customers to verify that the information being used is current. The described products are not designed, manufactured or intended for use in equipment for medical, life support, aircraft control or navigation, or any other applications that require failsafe operation. RF Micro Devices does not assume responsibility for the use of the described products. RF MICRO DEVICES®, RFMD®, Providing Communication Solutions™, the diamond logo design, Silicon Wave, and the SiW product name prefix are trademarks of RFMD, LLC. BLUETOOTH® is a trademark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RF Micro Devices, Inc. Manufactured under license from ARM Limited. ARM, ARM7TDMI and the ARM logo are the registered trademarks of ARM Limited in the EU and other countries. All other product, service, and company names are trademarks, registered trademarks or service marks of their respective owners. 24 of 24 60 0049 R01Drf SiW3000 Radio Processor DS