STA333BW 2.1-channel high-efficiency digital audio system Preliminary Data Features ! Wide supply voltage range (4.5 to 20 V) ! 3 power output configurations – 2 channels of ternary PWM (stereo mode) (2 x 20 W @ 8 Ω, 18 V). – 3 channels - left, right using binary and LFE using ternary PWM (2.1 mode) (2 x 9 W + 1 x 20 W @ 2 x 4 Ω, 1 x 8 Ω, 18 V) – 2 channels of ternary PWM (2 x 20 W) + stereo line out ternary ! 2.1 channels of 24-bit DDX® ! 100 dB SNR and dynamic range ! Selectable 32 KHz to 192 KHz input sample rates ! I2C control with selectable device address ! Digital gain/attenuation +48 dB to -80 dB in 0.5 dB steps ! Soft volume update ! Individual channel and master gain/attenuation ! Dual independent limiters/compressors ! Dynamic range compression or anti-clipping modes ! AutomodesTM – 15 preset crossover filters – 2 preset anti-clipping modes – Preset nighttime listening mode ! Individual channel and master soft and hard mute ! Independent channel volume and DSP bypass ! Automatic zero-detect mute PowerSSO36 slug down ! Automatic invalid input detect mute ! 2-channel I2S input data interface ! Input and output channel mapping ! 4 x 28-bit user programmable biquads (EQ) per channel ! Bass/treble tone control ! DC blocking selectable high-pass filter ! Selectable de-emphasis ! Sub channel mix into left and right channels ! Advanced AM interference frequency switching and noise suppression modes ! Selectable high or low bandwidth noise shaping topologies ! Variable max power correction for lower fullpower THD ! Selectable clock input ratio ! 96 kHz internal processing sample rate, 24 to 28-bit precision ! Thermal overload and short-circuit protection embedded ! Video application supports 576 x fs input mode ! PSSO-36 slug down package, RoHS. Table 1. Device summary July 2007 Order codes Package Packing STA333BW PowerSSO36 slug down Tube STA333BW13TR PowerSSO36 slug down Tape and reel Rev 2 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/64 www.st.com 1 Contents STA333BW Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Connections and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 2.1 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5 Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6.1 Functional pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 Processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 I2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 5.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4 2/64 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.1 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.2 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.3 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.4 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 STA333BW 6 Contents 5.4.5 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4.6 Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 6.2 6.3 6.4 6.5 Configuration register A (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1.1 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1.2 Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1.3 Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1.4 Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1.5 Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Configuration register B (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2.1 Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2.2 Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2.3 Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2.4 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2.5 Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Configuration register C (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3.1 DDX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3.2 DDX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3.3 Over-current warning detect adjustment bypass . . . . . . . . . . . . . . . . . . 29 Configuration register D (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.4.1 High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.4.2 De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.4.3 DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.4.4 Post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.4.5 Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.4.6 Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . 30 6.4.7 Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.4.8 Miami ModeTM enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Configuration register E (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.5.1 Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.5.2 Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.5.3 Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.5.4 AM mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.5.5 PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.5.6 Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . 32 6.5.7 Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3/64 Contents STA333BW 6.5.8 6.6 6.7 6.8 6.9 6.10 Configuration register F (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.6.1 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.6.2 Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.6.3 Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . 38 6.6.4 LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.6.5 Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.6.6 IC power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.6.7 External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Volume control registers (0x06 to 0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.7.1 Mute/line output configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.7.2 Master volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.7.3 Channel 1 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.7.4 Channel 2 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.7.5 Channel 3 / line output volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Auto mode registers (0x0B and 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.8.1 AutoMode register 1 (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.8.2 AutoMode register 2 (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.8.3 AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.8.4 Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Channel configuration registers ( 0x0E to 0x10) . . . . . . . . . . . . . . . . . . . 43 6.9.1 Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.9.2 EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.9.3 Volume bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.9.4 Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.9.5 Limiter select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.9.6 Output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Tone control register (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.10.1 6.11 6.12 Tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Dynamics control registers (0x12 to 0x15) . . . . . . . . . . . . . . . . . . . . . . . . 46 6.11.1 Limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.11.2 Limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.11.3 Limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.11.4 Limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 User-defined coefficient control registers (0x16 to 0x26) . . . . . . . . . . . . . 50 6.12.1 4/64 Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 STA333BW Contents 6.12.2 Coefficient b1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.12.3 Coefficient b1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.12.4 Coefficient b1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.12.5 Coefficient b2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.12.6 Coefficient b2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.12.7 Coefficient b2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.12.8 Coefficient a1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.12.9 Coefficient a1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.12.10 Coefficient a1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.12.11 Coefficient a2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.12.12 Coefficient a2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.12.13 Coefficient a2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.12.14 Coefficient b0 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.12.15 Coefficient b0 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.12.16 Coefficient b0 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.12.17 Coefficient write/read control register . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.12.18 User-defined EQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.12.19 Pre-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.12.20 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.12.21 Over-current post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7 6.13 Variable max power correction registers (0x27 to 0x28) . . . . . . . . . . . . . 57 6.14 Variable distortion compensation registers (0x29 to 0x2A) . . . . . . . . . . . 57 6.15 Fault detect recovery constant registers (0x2B to 0x2C) . . . . . . . . . . . . . 58 6.16 Device status register (0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.1 Application scheme for power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.2 PLL filter schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.3 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5/64 List of tables STA333BW List of tables Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. 6/64 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical characteristics power section VCC= 18 V, f = 1 kHz, fsw = 384 kHz, Tamb = 25 °C, RL = 8 Ω unless otherwise specified13 Functional pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Input sampling rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 IR bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Support serial audio input formats for MSB-first (SAIFB = 0) . . . . . . . . . . . . . . . . . . . . . . . 25 Supported serial audio input formats for LSB-first (SAIFB = 1) . . . . . . . . . . . . . . . . . . . . . 26 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Output configuration engine selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Master volume offset as a function of MV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Channel volume as a function of CxV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 AutoMode gain compression/limiters selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 AutoMode AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Bass management crossover frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Channel limiter mapping as a function of CxLS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Channel output mapping as a function of CxOM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Tone control boost/cut as a function of BTC and TTC bits . . . . . . . . . . . . . . . . . . . . . . . . . 45 Limiter attack rate as a function of LxA bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Limiter release rate as a function of LxR bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Limiter attack threshold as a function of LxAT bits (AC-Mode). . . . . . . . . . . . . . . . . . . . . . 49 Limiter release threshold as a function of LxRT bits (AC-Mode). . . . . . . . . . . . . . . . . . . . . 49 Limiter attack threshold as a function of LxAT bits (DRC-Mode). . . . . . . . . . . . . . . . . . . . . 50 Limiter release threshold as a as a function of LxRT bits (DRC-Mode).. . . . . . . . . . . . . . . 50 RAM block for biquads, mixing, scaling and bass management. . . . . . . . . . . . . . . . . . . . . 56 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 STA333BW List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin connection PowerSSO-36 (Top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Test circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Test circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Processing data flow 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Processing data flow 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 OCFG = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 OCFG = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 OCFG = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 OCFG = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 STA333BW output mapping scheme.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.0 channels (OCFG=’00’) PWM slots.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.1 channels (OCFG=’01’) PWM slots.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.1 channels (OCFG=’10’) PWM slots.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Application scheme for power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 PLL application scheme.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Output configuration for stereo BTL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Double layer PCB Rth j-amb with 2 GND copper area and with 16 via holes . . . . . . . . . . . . 61 PSSO36 power derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 PowerSSO-36 (slug-up) mechanical data and package dimensions . . . . . . . . . . . . . . . . . 62 7/64 Overview 1 STA333BW Overview The STA333BW is an integrated circuit comprising digital audio processing, digital amplifier control, and DDX-power output stage to create a high-power single-chip DDX® solution with high-quality, high-efficiency and all digital amplification. The STA333BW is part of the Sound TerminalTM family that provides full digital audio streaming to the speaker, thereby offering cost effectiveness, low power dissipation and sound enrichment. The IC power section consists of four independent half-bridges. These can be configured via digital control to operate in different modes. 2.1 channels can be provided by two half-bridges and a single full-bridge, providing up to 2 x 9 W + 1 x 20 W of power output. Two channels can be provided by two full-bridges, providing up to 2 x 20 W of power. The IC can also be configured as a 2.1 channels with 2 x 20 W provided by the device and external power for DDX® power drive. Also provided in the STA333BW are a full assortment of digital processing features. This includes up to four programmable 28-bit biquads (EQ) per channel, and bass/treble tone control. Automodes™ enable a time-to-market advantage by substantially reducing the amount of software development needed for certain functions. This includes Auto Volume loudness, preset volume curves and preset EQ settings. New advanced AM radio interference reduction modes. The serial audio data input interface accepts all possible formats, including the popular I2S format. Three channels of DDX® processing are provided. This high-quality conversion from PCM audio to DDX patented tri-state PWM switching waveform provides over 100 dB SNR and dynamic range. Figure 1. Block diagram I2 C I2 S Protection current/thermal Channel 1A interface Volume control Power control Logic Channel 1B DDX Channel 2A Regulators Channel 2B PLL Bias Digital DSP 8/64 Power STA333BW Connections and pin description 2 Connections and pin description 2.1 Connection diagram Figure 2. Pin connection PowerSSO-36 (Top view) GND_SUB 1 36 VDD_DIG SA 2 35 GND_DIG TEST_MODE 3 34 SCL VSS 4 33 SDA VCC_REG 5 32 INT_LINE OUT2B 6 31 RESET GND2 7 30 SDI VCC2 8 29 LRCKI OUT2A 9 28 BICKI OUT1B 10 27 XTI VCC1 11 26 PLL_GND GND1 12 25 FILTER_PLL OUT1A 13 24 VDD_PLL GND_REG 14 23 PWRDN VDD 15 22 GND_DIG CONFIG 16 21 VDD_DIG OUT3B/DDX3B 17 20 TWARN/OUT4B OUT3A/DDX3A 18 19 EAPD/OUT4A D05AU1638 2.2 Pin description Table 2. Pin description Pin Type Name Description 1 GND GND_SUB Substrate ground 2 I SA I2C select address 3 I TEST_MODE 4 I/O VSS 5 I/O VCC_REG Internal Vcc reference 6 O OUT2B Output half bridge 2B 7 GND GND2 Power negative supply 8 Power VCC2 Power positive supply 9 O OUT2A Output half bridge 2A 10 O OUT1B Output half bridge 1B This pin must be connected to ground Internal reference at Vcc-3.3 V 9/64 Connections and pin description Table 2. 10/64 STA333BW Pin description (continued) Pin Type Name Description 11 Power VCC1 Power positive supply 12 GND GND1 Power negative supply 13 I/O OUT1A Output half bridge 1A 14 GND GND_REG 15 Power VDD 16 I CONFIG 17 O OUT3B/DDX3B PWM out CH3B, external bridge 18 O OUT3A/DDX3A PWM out CH3A, external bridge 19 O EAPD/OUT4A Power down for external bridge 20 I TWARN/OUT4B 21 Power VDD_DIG Digital supply voltage 22 GND GND_DIG Digital groun 23 I PWRDN Power down 24 Power VDD_PLL Positive supply for PLL 25 I FILTER_PLL Connection to PLL filter 26 GND GND_PLL Negative supply for PLL 27 I XTI PLL input clock 28 I BICKI I2S serial clock 29 I LRCKI I2S left/right clock 30 I SDI 31 I RESET 32 O INT_LINE 33 I/O SDA I2C serial data 34 I SCL I2C serial clock 35 GND GND_DIG Digital ground 36 Power VDD_DIG Digital supply voltage Internal ground reference Internal 3.3 V reference voltage Paralleled mode command Thermal warning from external bridge I2S serial data channels 1 and 2 Reset Fault interrupt: 0: fault detected in the power bridge, 1: normal operation) STA333BW 2.3 Connections and pin description Thermal data Table 3. Thermal data Parameter Rth j-case Min. Typ. Thermal resistance junction-case (thermal pad) Max. Unit 1.5 °C/W Tth-sdj Thermal shut-down junction temperature 150 °C Tth-w Thermal warning temperature 130 °C Tth-sdh Thermal shut-down hysteresis 20 °C Rth j-amb Thermal resistance junction-ambient (1) 1. See Section 8: Package thermal characteristics on page 61 for details. 11/64 Electrical specifications STA333BW 3 Electrical specifications 3.1 Absolute maximum ratings Stresses beyond those listed below in Table 4 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Section 3.2: Recommended operating conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In real applications, power supplies with nominal-rated voltages within the recommended operating conditions, may experience some rising beyond the maximum operating conditions for short times when no or very low current is being sunk (for example, amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum ratings are never exceeded. Table 4. Absolute maximum ratings Symbol Max Unit -0.3 23 V VDD_DIG Digital supply voltage -0.3 4 V VDD_PLL PLL supply voltage -0.3 4 V 0 150 °C -40 150 °C Max Unit 20 V Vcc 3.2 Parameter Power supply voltage (VCC1, VCC2) Top Operating junction temperature Tstg Storage temperature Typ Recommended operating conditions Table 5. Recommended operating condition Symbol Vcc Parameter Power supply voltage (VCC1, VCC2) Min Typ 4.5 VDD_DIG Digital supply voltage 2.7 3.3 3.6 V VDD_PLL PLL supply voltage 2.7 3.3 3.6 V 70 °C Tamb 12/64 Min Ambient temperature 0 STA333BW 3.3 Electrical specifications Electrical specifications - digital section Symbol Parameter Conditions Min Typ Max Unit Iil Low level input current , no pull-up resistor Vi=0 V -10 10 µA Iih High level input current, no pull-down resistor Vi = VDD_DIG = 3.6 V -10 10 µA Vil Low level input voltage 0.2 * VDD_DIG V Vih High level input voltage Vol Low level output voltage Iol = 2 mA Voh High level output voltage Ioh = 2 mA Ipu Pull-up current Rpu Equivalent pull-up resistance 0.8 * VDD_DIG V 0.4 * VDD_DIG 0.8 * VDD_DIG V V -25 66 125 50 µA kΩ 3.4 Electrical specifications - power section Table 6. Electrical characteristics power section VCC= 18 V, f = 1 kHz, fsw = 384 kHz, Tamb = 25 °C, RL = 8 Ω unless otherwise specified Symbol Parameter Conditions Min Typ THD = 1% 16 THD = 10% 20 Max Output power BTL W Po Output power SE Unit RL = 4 Ω THD = 1% 7 THD = 10% 9 W Power P-channel/N-channel MOSFET (total bridge) ld = 1.5 A gP Power P-channel RdsON matching ld = 1.5 A 95 % gN Power N-channel RdsON matching ld = 1.5 A 95 % Idss Power P-channel/N-channel leakage ldss VCC = 20 V ILDT Low-current dead time (static) Resistive load(1) IHDT High-current dead time (dynamic) Rise time RdsON tr tf Vcc Fall time Supply voltage operating voltage 180 250 mΩ 10 µA 8 15 ns Iload = 1.5 A(1) 15 30 ns Resistive load(1) 10 18 ns load(1) 10 18 ns 18 V Resistive 4.5 13/64 Electrical specifications Table 6. STA333BW Electrical characteristics power section (continued) VCC= 18 V, f = 1 kHz, fsw = 384 kHz, Tamb = 25 °C, RL = 8 Ω unless otherwise specified Symbol Parameter Conditions Min Supply current from Vcc in power PWRDN = 0 down IVCC Typ Max Unit 0.1 1 mA Supply current from Vcc in operation PCM input signal = -60 dBFS, Switching frequency = 384 kHz No LC filters 30 mA IVDD Supply current DDX processing (reference only) Internal clock = 49.152 MHz 80 mA Ilim Overcurrent limit (2) 2.2 3.0 Isc Short circuit protection Hi-Z output 2.7 3.6 UVL Under-voltage protection tmin Output minimum pulse width DR Dynamic range SNR Signal to noise ratio, ternary mode No load THD+N XTALK A A 3.5 4.3 V 30 60 ns 100 dB 100 dB 90 dB A-Weighted Signal to noise ratio binary mode PSSR 20 4.0 Power supply rejection ratio DDX stereo mode, <5 kHz VRIPPLE = 1 V RMS Audio input = dither only 80 dB Total harmonic distortion + noise DDX stereo mode, Po=1 W f = 1 kHz 0.2 % Crosstalk DDX stereo mode, <5 kHz One channel driven @ 1 W Other channel measured 80 dB Peak efficiency, DDX mode Po = 2 x 20 W, 8 Ω 90 Peak efficiency,binary modes Po = 2 x 9 W @ 4 Ω, 1 x 20 W @8Ω 87 η % 1. Refer to Figure 4: Test circuit 1. 2. Limit current if the register (OCRB par 6.1.3.3) overcurrent warning detect adjustment bypass is enabled. When disabled refer to the Isc. 14/64 STA333BW 3.5 Electrical specifications Power-on sequence Figure 3. Power-on sequence VCC VDD_DIG XTI Don’t care Reset TR I 2C TC Don’t care CMD0 CMD1 CMD2 PWDN Referring to Figure 3 above: TR = mimimum time between XTI master clock stable and reset removal: 1 ms, TC = minimum time between reset removal and I2C program sequence start: 1 ms. Note: Clock stable means: fmax - fmin < 1 MHz. Note: VCC > VDD_DIG must be guaranteed at all times. 3.6 Testing 3.6.1 Functional pin status Table 7. Functional pin status Pin name Number Logic value IC status PWRDN 23 0 Low-power mode PWRDN 23 1 Normal operation TWARN 20 0 Temperature warning from external power stage TWARN 20 1 Normal operation EAPD 19 0 Low-power operation for power stage. All internal regulators are switched off EAPD 19 1 Normal operation 15/64 Electrical specifications Figure 4. STA333BW Test circuit 1 OUTxY Vcc (3/4)Vcc Low-current dead time = MAX(DTr, DTf) (1/2)Vcc (1/4)Vcc +Vcc t DTr Duty cycle = 50% M58 OUTxY INxY DTf R8Ω M57 V67 vdc = Vcc/2 + gnd Figure 5. Test circuit 2 High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B DTout(A) M58 DTin(A) Q1 Q2 OUTA INA Iout=1.5A M57 Q3 DTout(B) Rload=4Ω L67 10µ C69 470nF L68 10µ C71 470nF C70 470nF DTin(B) OUTB INB Iout=1.5A Q4 Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure 16/64 M64 M63 D06AU1651 STA333BW 4 Processing data paths Processing data paths Here are some diagrams that represent the data processing paths inside STA333BW. The first 2x oversampling FIR filter allows 2fs audio processing. Then a selectable high-pass filter removes the DC level. Four biquad filters allow a full equalization system. A final crossover filter is present that can alternatively be used as a fifth biquad stage (see the IIC registers for this specific usage). A pre scaler and a final post scaler provide full control over the signal dynamics before and after the filtering stages, respectively. A mixer function is also available. Figure 6. Processing data flow 1 Sampling frequency=Fs Sampling frequency=2xFs x2 FIR over sampling PreScale Hi-Pass Filter Biquad #1 If HPB=0 Biquad #2 Biquad #3 Biquad #4 DeEmphasis User-Defined Filters Bass Treble L If C1TCB=0 BTC: Bass Boost/Cut TTC: Treble Boost/Cut If DEMP=0 From I2S input interface If DSPB=0 and C1EQBP=0 x2 FIR over sampling PreScale Hi-Pass Filter Biquad #1 If HPB=0 Biquad #2 Biquad #3 Biquad #4 User-Defined Filters DeEmphasis Bass Treble R If C2TCB=0 BTC: Bass Boost/Cut TTC: Treble Boost/Cut If DEMP=0 If DSPB=0 and C2EQBP=0 Figure 7. L Processing data flow 2 C1Mx1 + R Hi-Pass XO Filter Vol And Limiter Post scale Hi-Pass XO Filter Vol And Limiter Post scale Lo-Pass XO Filter Vol And Limiter Post scale C1Mx2 C2Mx1 + C2Mx2 C3Mx1 + C3Mx2 User-Defined Mix Coefficients Crossover Frequency determined by XO Setting User Defined If XO=0000 17/64 I2C bus specification 5 STA333BW I2C bus specification The STA333BW supports the I2C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. STA333BW is always a slave device in all of its communications. It supports up to 400 kb/sec rate (fast-mode bit rate). STA333BW I2C is a slave only interface. 5.1 Communication protocol 5.1.1 Data transition or change Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition. 5.1.2 Start condition START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer. 5.1.3 Stop condition STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between STA333BW and the bus master. 5.1.4 Data input During the data input the STA333BW samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low. 5.2 Device addressing To start communication between the master and the STA333BW, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8-bits (MSB first) corresponding to the device select address and read or write mode. The seven most significant bits are the device address identifiers, corresponding to the I2C bus definition. In the STA333BW the I2C interface has two device addresses depending on the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1. The eighth bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0 for write mode. After a START condition the STA333BW identifies on the bus the device address and if a match is found, it acknowledges the identification on SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address. 18/64 I2C bus specification STA333BW 5.3 Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA333BW acknowledges this and the writes for the byte of internal address. After receiving the internal byte address the STA333BW again responds with an acknowledgement. 5.3.1 Byte write In the byte write mode the master sends one data byte, this is acknowledged by the STA333BW. The master then terminates the transfer by generating a STOP condition. 5.3.2 Multi-byte write The multi-byte write modes can start from any internal address. The master generating a STOP condition terminates the transfer. 5.4 Read operation 5.4.1 Current address byte read Following the START condition the master sends a device select code with the RW bit set to 1. The STA333BW acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition. 5.4.2 Current address multi-byte read The multi-byte read modes can start from any internal address. Sequential data bytes are read from sequential addresses within the STA333BW. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer. 5.4.3 Random address byte read Following the START condition the master sends a device select code with the RW bit set to 0. The STA333BW acknowledges this and then the master writes the internal address byte. After receiving, the internal byte address the STA333BW again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA333BW acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition. 5.4.4 Random address multi-byte read The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA333BW. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer. 19/64 I2C bus specification STA333BW 5.4.5 Write mode sequence Figure 8. Write mode sequence ACK BYTE WRITE DEV-ADDR ACK DATA IN RW START STOP ACK DEV-ADDR MULTIBYTE WRITE ACK Read mode sequence Figure 9. Read mode sequence ACK DEV-ADDR DATA IN NO ACK DATA RW START STOP ACK DEV-ADDR ACK SUB-ADDR RW RW= ACK HIGH START SEQUENTIAL CURRENT READ DEV-ADDR ACK DEV-ADDR START RW ACK DATA NO ACK DATA STOP ACK DATA NO ACK DATA STOP START ACK SEQUENTIAL RANDOM READ DEV-ADDR START 20/64 ACK DATA IN STOP 5.4.6 RANDOM ADDRESS READ ACK SUB-ADDR RW START CURRENT ADDRESS READ ACK SUB-ADDR ACK SUB-ADDR RW ACK DEV-ADDR START ACK DATA RW ACK DATA NO ACK DATA STOP STA333BW Register description 6 Register description Table 8. Register summary Addr Name D7 D6 D5 D4 D3 D2 D1 D0 0x00 ConfA FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0 0x01 ConfB C2IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0 0x02 ConfC OCRB CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0 0x03 ConfD MME ZDE DRC BQL PSL DSPB DEMP HPB 0x04 ConfE SVE ZCE DCCV PWMS AME NSBW MPC MPCV 0x05 ConfF EAPD PWDN ECLE LDTE BCLE IDE OCFG1 OCFG0 0x06 Mute/LOC LOC1 LOC0 C3M C2M C1M MMute 0x07 Mvol MV7 MV6 MV5 MV4 MV3 MV2 MV1 MV0 0x08 C1Vol C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0 0x09 C2Vol C2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0 0x0A C3Vol C3V7 C3V6 C3V5 C3V4 C3V3 C3V2 C3V1 C3V0 0x0B Auto1 AMGC1 AMGC0 0x0C Auto2 0x0D Auto3 0x0E XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME C1Cfg C1OM1 C1OM0 C1LS1 C1LS0 C1BO C1VBP C1EQBP C1TCB 0x0F C2Cfg C2OM1 C2OM0 C2LS1 C2LS0 C2BO C2VBP C2EQBP C2TCB 0x10 C3Cfg C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3VBP 0x11 Tone TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0 0x12 L1ar L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0 0x13 L1atrt L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0 0x14 L2ar L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0 0x15 L2atrt L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0 0x16 Cfaddr CFA5 CFA4 CFA3 CFA2 CFA1 CFA0 0x17 B1cf1 C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16 0x18 B1cf2 C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8 0x19 B1cf3 C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0 0x1A B2cf1 C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16 0x1B B2cf2 C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8 0x1C B2cf3 C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0 0x1D A1cf1 C3B23 C3B22 C3B21 C3B20 C3B19 C3B18 C3B17 C3B16 0x1E A1cf2 C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8 0x1F A1cf3 C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0 21/64 Register description Table 8. STA333BW Register summary (continued) Addr Name D7 D6 D5 D4 D3 D2 D1 D0 0x20 A2cf1 C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16 0x21 A2cf2 C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8 0x22 A2cf3 C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0 0x23 B0cf1 C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16 0x24 B0cf2 C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8 0x25 B0cf3 C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 C5B0 0x26 Cfud RA R1 WA W1 0x27 MPCC1 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8 0x28 MPCC2 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0 0x29 DCC1 DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8 0x2A DCC2 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0 0x2B FDRC1 FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8 0x2C FDRC2 FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0 0x2D Status PLLUL FAULT UVFAULT OVFAULT OCFAULT OCWARN TFAULT TWARN 0x2E reserved RO1BACT R5BACT R4BACT R3BACT R2BACT R1BACT 0x2F reserved R01BEND R5BEND R4BEND R3BEND R2BEND R1BEND 0x30 reserved R5BBAD R4BBAD R3BBAD R2BBAD R1BBAD 6.1 6.1.1 Configuration register A (0x00) D7 D6 D5 D4 D3 D2 D1 D0 FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0 0 1 1 0 0 0 1 1 Master clock select Bit R/W RST Name 0 R/W 1 MCS0 1 R/W 1 MCS1 2 R/W 0 MCS2 Description Selects the ratio between the input I2S sample frequency and the input clock. The STA333BW supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. Therefore the internal clock is: 22/64 " 32.768 MHz for 32 kHz " 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz " 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz STA333BW Register description The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fs). The relationship between the input clock and the input sample rate is determined by both the MCSx and the IR (iInput rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally Table 9. Input sampling rates Input sample rate Fs (kHz) 6.1.2 IR[1:0] MCS[2:0] 101 100 011 010 001 000 32, 44.1, 48 00 576fs 128fs 256fs 384fs 512fs 768fs 88.2, 96 01 NA 64fs 128fs 192fs 256fs 384fs 176.4, 192 1X NA 32fs 64fs 96fs 128fs 192fs Interpolation ratio select Bit R/W RST Name 4:3 R/W 00 IR[1:0] Description Selects internal interpolation ratio based on input I2S sample frequency The STA333BW has variable interpolation (oversampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-through) or provides a 2 times downsample. The oversampling ratio of this interpolation is determined by the IR bits. Table 10. IR bit settings as a function of input sample rate Input sample rate Fs (kHz) IR[1:0] 1st stage interpolation ratio 32 00 2 times oversampling 44.1 00 2 times oversampling 48 00 2 times oversampling 88.2 01 Pass-through 96 01 Pass-through 176.4 10 2 times downsampling 192 10 2 times downsampling 23/64 Register description 6.1.3 STA333BW Thermal warning recovery bypass Bit R/W RST Name 5 R/W 1 TWRB Description 0: thermal warning recovery enabled 1: thermal warning recovery disabled If the thermal warning adjustment is enabled (TWAB=0), then the thermal warning recovery determines if the -3 dB output limit is removed when thermal warning is negative. If TWRB=0 and TWAB=0, then when a thermal warning disappears the -3 dB output limit is removed and the gain is added back to the system. If TWRB=1 and TWAB=0, then when a thermal warning disappears the -3 dB output limit remains until TWRB is changed to zero or the device is reset. 6.1.4 Thermal warning adjustment bypass Bit R/W RST Name 6 R/W 1 TWAB Description 0: thermal warning adjustment enabled 1: thermal warning adjustment disabled The on-chip STA333BW power output block provides feedback to the digital controller using inputs to the power control block. The TWARN input is used to indicate a thermal warning condition. When TWARN is asserted (set to 0) for a period of time greater than 400 ms, the power control block forces a -3 dB output limit (determined by TWOCL in Coeff RAM) to the modulation limit in an attempt to eliminate the thermal warning condition. Once the thermal warning output limit adjustment is applied, it remains in this state until reset, unless FDRB = 0. 6.1.5 Fault detect recovery bypass Bit R/W RST Name Description 7 R/W 0 FDRB 0: fault detect recovery enabled 1: fault detect recovery disabled The on-chip STA333BW power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either over-current or thermal). When FAULT is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the tri-state output (setting it to 0 which directs the power output block to begin recovery), holds it at 0 for period of time in the range of 0.1 ms to 1 second as defined by the fault-detect recovery constant register (FDRC registers 0x29, 0x2A), then toggles it back to 1. This sequence is repeated as log as the fault indication exists. This feature is enabled by default but can be bypassed by setting the FDRB control bit to 1. 24/64 STA333BW 6.2 6.2.1 6.2.2 Register description Configuration register B (0x01) D7 D6 D5 D4 D3 D2 D1 D0 C2IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0 1 0 0 0 0 0 0 0 Serial audio input interface format Bit R/W RST Name 0 R/W 0 SAI0 1 R/W 0 SAI1 2 R/W 0 SAI2 3 R/W 0 SAI3 Description Determines the interface format of the input serial digital audio interface. Serial data interface The STA333BW audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. STA333BW always acts a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 and 2 SDI12. The SAI register (configuration register B (0x01), bits D3 to D0) and the SAIFB register (configuration register B (0x01), bit D4) are used to specify the serial data format. The default serial data format is I2S, MSB-first. Available formats are shown in the tables and figure that follow. 6.2.3 Serial data first bit SAIFB Format 0 MSB-first 1 LSB-first Table 11. BICKI Support serial audio input formats for MSB-first (SAIFB = 0) SAI [3:0] SAIFB Interface format 0000 0 I2S 15-bit data 0001 0 Left/right-justified 16-bit data 32fs 25/64 Register description Table 11. BICKI STA333BW Support serial audio input formats for MSB-first (SAIFB = 0) (continued) SAI [3:0] SAIFB Interface format 0000 0 I2 0001 0 Left-justified 16 to 24-bit data 0010 0 Right-justified 24-bit data 0110 0 Right-justified 20-bit data 1010 0 Right-justified 18-bit data 1110 0 Right-justified 16-bit data 0000 0 I2S 16 to 24-bit data 0001 0 Left-justified 16 to 24-bit data 0010 0 Right-justified 24-bit data 0110 0 Right-justified 20-bit data 1010 0 Right-justified 18-bit data 1110 0 Right-justified 16-bit data S 16 to 23-bit data 48fs 64fs Table 12. BICKI Supported serial audio input formats for LSB-first (SAIFB = 1) SAI [3:0] SAIFB Interface Format 1100 1 I2S 1110 1 Left/right-justified 16-bit data 0100 1 I2S 23-bit data 0100 1 I2S 20-bit data 1000 1 I2S 18-bit data 1100 1 LSB first I2S 16-bit data 0001 1 Left-justified 24-bit data 0101 1 Left-justified 20-bit data 1001 1 Left-justified 18-bit data 1101 1 Left-justified 16-bit data 0010 1 Right-justified 24-bit data 0110 1 Right-justified 20-bit data 1010 1 Right-justified 18-bit data 1110 1 Right-justified 16-bit data 15-bit data 32fs 48fs 26/64 STA333BW Register description Table 12. Supported serial audio input formats for LSB-first (SAIFB = 1) (continued) BICKI SAI [3:0] SAIFB Interface Format 2 0000 1 I S 24-bit data 0100 1 I2S 20-bit data 1000 1 I2S 18-bit data 1100 1 LSB first I2S 16-bit data 0001 1 Left-justified 24-bit data 0101 1 Left-justified 20-bit data 1001 1 Left-justified 18-bit data 1101 1 Left-justified 16-bit data 0010 1 Right-justified 24-bit data 0110 1 Right-justified 20-bit data 1010 1 Right-justified 18-bit data 1110 1 Right-justified 16-bit data 64fs 6.2.4 6.2.5 Delay serial clock enable Bit R/W RST Name Description 5 R/W 0 DSCKE 0: no serial clock delay 1: serial clock delay by 1 core clock cycle to tolerate anomalies in some I2S master devices Channel input mapping Bit R/W RST Name Description 6 R/W 0 C1IM 0: processing channel 1 receives Left I2S Input 1: processing channel 1 receives Right I2S Input 7 R/W 1 C2IM 0: processing channel 2 receives Left I2S Input 1: processing channel 2 receives Right I2S Input Each channel received via I2S can be mapped to any internal processing channel via the Channel Input Mapping registers. This allows for flexibility in processing. The default settings of these registers map each I2S input channel to its corresponding processing channel. 27/64 Register description 6.3 STA333BW Configuration register C (0x02) D7 6.3.1 D6 D5 D4 D3 D2 D1 D0 OCRB CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0 1 0 1 0 1 1 1 DDX power output mode Bit R/W RST Name 0 R/W 1 OM0 1 R/W 1 OM1 Description Selects configuration of DDX output. The DDX power output mode selects how the DDX output timing is configured. Different power devices use different output modes. Table 13. Output modes OM[1,0] 6.3.2 Output stage / mode 00 Drop Compensation 01 Discrete Output Stage, Tapered Compensation 10 Full Power Mode 11 Variable Drop Compensation (CSZx bits) DDX compensating pulse size register Bit R/W RST Name 2 R/W 1 CSZ0 3 R/W 0 CSZ1 4 R/W 1 CSZ2 5 R/W 0 CSZ3 Table 6: Table 14. When OM[1,0] = 11, this register determines the size of the DDX compensating pulse from 0 clock ticks to 15 clock periods. Compensating pulse size CSZ[3:0] Compensating Pulse Size 0000 0 ns (0 tick) compensating pulse size 0001 20 ns (1 tick) clock period compensating pulse size … 1111 28/64 Description … 300 ns (15 tick) clock period compensating pulse size STA333BW 6.3.3 Register description Over-current warning detect adjustment bypass Bit R/W RST Name 7 R/W 1 OCRB Description 0: over-current warning adjustment enabled 1: over-current warning adjustment disabled The OCWARN input is used to indicate an over-current warning condition. When OCWARN is asserted (set to 0), the power control block forces an adjustment to the modulation limit (default is -3 dB) in an attempt to eliminate the over-current warning condition. Once the over-current warning volume adjustment is applied, it remains in this state until reset is applied. The level of adjustment can be changed via the TWOCL (thermal warning/over current limit) setting which is address 0x37 of the user defined coefficient RAM. 6.4 6.4.1 Configuration register D (0x03) D7 D6 D5 D4 D3 D2 D1 D0 MME ZDE DRC BQL PSL DSPB DEMP HPB 0 1 0 0 0 0 0 0 High-pass filter bypass Bit R/W RST Name Description 0 R/W 0 HPB Setting of one bypasses internal AC coupling digital high-pass filter The STA333BW features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through a DDX amplifier. DC signals can cause speaker damage. When HPB=0, this filter is enabled. 6.4.2 De-emphasis Bit R/W RST Name 1 R/W 0 DEMP Description 0: no de-emphasis 1: de-emphasis Setting the DEMP bit enables de-emphasis on all channels 6.4.3 DSP bypass Bit R/W RST Name 2 R/W 0 DSPB Description 0: normal operation 1: bypass of biquad and bass/treble functionality Setting the DSPB bit bypasses the EQ functionality of the STA333BW. 29/64 Register description 6.4.4 STA333BW Post-scale link Bit R/W RST Name 3 R/W 0 PSL Description 0: each channel uses individual post-scale value 1: each channel uses channel 1 post-scale value Post-scale functionality can be used for power-supply error correction. For multi-channel applications running off the same power-supply, the post-scale values can be linked to the value of channel 1 for ease of use and update the values faster. 6.4.5 Biquad coefficient link Bit R/W RST Name 4 R/W 0 BQL Description 0: each channel uses coefficient values 1: each channel uses channel 1 coefficient values For ease of use, all channels can use the biquad coefficients loaded into the Channel 1 Coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once. 6.4.6 Dynamic range compression/anti-clipping bit Bit R/W RST Name 5 R/W 0 DRC Description 0: limiters act in anti-clipping mode 1: limiters act in dynamic range compression mode Both limiters can be used in one of two ways, anti-clipping or dynamic range compression. When used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. In dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level. 6.4.7 Zero-detect mute enable Bit R/W RST Name Description 6 R/W 1 ZDE Setting of 1 enables the automatic zero-detect mute Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the data for each processing channel at the output of the crossover (bass management) filter. If any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled. 30/64 STA333BW 6.4.8 6.5 6.5.1 6.5.2 Register description Miami ModeTM enable Bit R/W RST Name 7 R/W 0 MME Description 0: sub mix into left/right disabled 1: sub mix into left/right enabled Configuration register E (0x04) D7 D6 D5 D4 D3 D2 D1 D0 SVE ZCE DCCV PWMS AME NSBW MPC MPCV 1 1 0 0 0 0 1 0 Max power correction variable Bit R/W RST Name 0 R/W 0 MPCV Description 0: use standard MPC coefficient 1: use MPCC bits for MPC coefficient Max power correction Bit R/W RST Name 1 R/W 1 MPC Description Setting of 1 enables Power Bridge correction for THD reduction near maximum power output. Setting the MPC bit turns on special processing that corrects the STA333BW power device at high power. This mode should lower the THD+N of a full DDX system at maximum power output and slightly below. If enabled, MPC is operational in all output modes except tapered (OM[1,0] = 01) and binary. When OCFG = 00, MPC will not effect channels 3 and 4, the line-out channels. 6.5.3 Noise-shaper bandwidth selection Bit R/W RST Name 2 R/W 0 NSBW Description 1: third order NS 0: fourth order NS 31/64 Register description 6.5.4 STA333BW AM mode enable Bit R/W RST Name 3 R/W 0 AME Description 0: normal DDX operation. 1: AM reduction mode DDX operation STA333BW features a DDX processing mode that minimizes the amount of noise generated in frequency range of AM radio. This mode is intended for use when DDX is operating in a device with an AM tuner active. The SNR of the DDX processing is reduced to ~83 dB in this mode, which is still greater than the SNR of AM radio. 6.5.5 6.5.6 6.5.7 PWM speed mode Bit R/W RST Name 4 R/W 0 PWMS Description 0: normal speed (384 kHz) all channels 1: odd speed (341.3 kHz) all channels Distortion compensation variable enable Bit R/W RST Name 5 R/W 0 DCCV Description 0: uses preset DC coefficient 1: uses DCC coefficient Zero-crossing volume enable Bit R/W RST Name 6 R/W 1 ZCE Description 1: volume adjustments only occur at digital zero-crossings 0: volume adjustments occur immediately The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks are audible. 6.5.8 32/64 Soft volume update enable Bit R/W RST Name 7 R/W 1 SVE Description 1: volume adjustments ramp according to SVR settings 0: volume adjustments occur immediately STA333BW 6.6 6.6.1 Register description Configuration register F (0x05) D7 D6 D5 D4 D3 D2 D1 D0 EAPD PWDN ECLE LDTE BCLE IDE OCFG1 OCFG0 0 1 0 1 1 1 0 0 Output configuration Bit R/W RST Name 0 R/W 0 OCFG0 1 R/W 0 OCFG1 Description Selects the output configuration Table 15. OCFG[1:0] Note: Output configuration engine selection Output configuration Config PIN 00 2-channel (full-bridge) power, 2 channel data-out: 1A/1B → 1A/1B 2A/2B → 2A/2B Line out1 → 3A/3B Line out2 → 4A/4B Line out configuration determined by LOC register 0 01 2(half-bridge).1(full-bridge) on-board power: 1A → 1A binary 0 ° 2A → 1B binary 90° 3A/3B → 2A/2B binary 45° 1A/B → 3A/B binary 0° 2A/B → 4A/B binary 90° 0 10 2-channel (full-bridge) power, 1 channel DDX: 1A/1B → 1A/1B 2A/2B → 2A/2B 3A/3B → 3A/3B EAPDEXT and TWARNEXT Active 0 11 1-channel mono-parallel: 3A → 1A/1B w/ C3BO 45° 3B → 2A/2B w/ C3BO 45° 1A/1B → 3A/3B 2A/2B → 4A/4B 1 To the left of the arrow is the processing channel. When using channel output mapping, any of the three processing channel outputs can be used for any of the three inputs. 33/64 Register description STA333BW Figure 10. OCFG = 00 (default value) OUT1A Half Bridge Channel 1 Half Bridge Half Bridge Channel 1 OUT1A OUT1B Half Bridge OUT2A Half Bridge Channel 2 OUT1B Channel 2 Half Bridge Half Bridge OUT2B OUT3A OUT3B LineOut 1 LPF OUT4A OUT4B Half Bridge OUT2A Channel 3 OUT2B LineOut 2 LPF Figure 12. OCFG = 10 Half Bridge Figure 11. OCFG = 01 Figure 13. OCFG = 11 OUT1A OUT1A Half Bridge Channel 1 Half Bridge Half Bridge OUT1B OUT1B Channel 3 Half Bridge Half Bridge OUT2A Half Bridge Channel 2 Half Bridge OUT2B OUT3A OUT3B OUT2A OUT2B OUT3A Power Device Channel 3 OUT3B Channel 1 EAPD OUT4A OUT4B Channel 2 STA333BW can be configured to support different output configurations. For each PWM output channel a "PWM slot" is defined. PWM slot is always 1 / (8 x Fs) seconds length. The PWM slot define the maximum extension for PWM rise and fall edge, that is, rising edge as far as the falling edge cannot range outside PWM slot boundaries. 34/64 STA333BW Register description Figure 14. STA333BW output mapping scheme. DDX 1A OUT1A OUT1A DDX 1B DDX 2A DDX™ m odulator O UT1B DDX 2B DDX 3A OUT2A OUT1B Power Bridge OUT2A DDX 3B DDX 4A O UT2B OUT2B DDX 4B REM AP OUT3A O UT3B OUT4A O UT4B For each configuration the PWM from the digital driver are mapped in different way to the power stage: 2.0 channels, two full bridges (OCFG="00"): " DDX1A ' OUT1A " DDX1B ' OUT1B " DDX2A ' OUT2A " DDX2B ' OUT2B " DDX3A ' OUT3A " DDX3B ' OUT3B " DDX4A ' OUT4A " DDX4B ' OUT4B " DDX1A/1B configured as ternary " DDX2A/2B configured as ternary " DDX3A/3B configured as lineout ternary " DDX4A/4B configured as lineout ternary On channel 3 line out (LOC bits = "00") the same datas as channel 1 processing are sent. On channel 4 line out (LOC bits = "00") the same datas as channel 2 processing are sent. In this configuration, no volume control or EQ have effect on channel 3 and 4. In this configuration the PWM slot phase is the following as shown in the next figures: 35/64 Register description STA333BW Figure 15. 2.0 channels (OCFG=’00’) PWM slots. OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B OUT4A OUT4B 2.1 channels, two half bridges + one full bridge (OCFG="01"): " DDX1A ' OUT1A " DDX2A ' OUT1B " DDX3A ' OUT2A " DDX3B ' OUT2B " DDX1A ' OUT3A " DDX1B ' OUT3B " DDX2A ' OUT4A " DDX2B ' OUT4B " DDX1A/1B configured as binary " DDX2A/2B configured as binary " DDX3A/3B configured as binary " DDX4A/4B is not used In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT3/OUT4 channels the channel 1 and channel 2 PWM are replicated. In this configuration the PWM slot phase is the following as shown in the next figures: 36/64 STA333BW Register description Figure 16. 2.1 channels (OCFG=’01’) PWM slots. OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B OUT4A OUT4B 2.1 channels, two fullbridge + one external full bridge (OCFG="10"): " DDX1A ' OUT1A " DDX1B ' OUT1B " DDX2A ' OUT2A " DDX2B ' OUT2B " DDX3A ' OUT3A " DDX3B ' OUT3B " EAPD " TWARN OUT4B " DDX1A/1B configured as ternary " DDX2A/2B configured as ternary " DDX3A/3B configured as ternary " DDX4A/4B is not used ' OUT4A In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT4 channel the external bridge control signals are muxed. In this configuration the PWM slot phase is the following as shown in the next figures: 37/64 Register description STA333BW Figure 17. 2.1 channels (OCFG=’10’) PWM slots. OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B 6.6.2 Invalid input detect mute enable Bit R/W RST Name 2 R/W 1 IDE Description Setting of 1 enables the automatic invalid input detect mute Setting the IDE bit enables this function, which looks at the input I2S data and will automatically mute if the signals are perceived as invalid. 6.6.3 Binary output mode clock loss detection Bit R/W RST Name 3 R/W 1 BCLE Description Binary output mode clock loss detection enable Detects loss of input MCLK in binary mode and will output 50% duty cycle. 6.6.4 LRCK double trigger protection Bit R/W RST Name 4 R/W 1 LDTE Description LRCLK double trigger protection enable Actively prevents double trigger of LRCLK. 6.6.5 Auto EAPD on clock loss Bit R/W RST Name 5 R/W 0 ECLE Description Auto EAPD on clock loss When active, issues a power device power down signal (EAPD) on clock loss detection. 38/64 STA333BW 6.6.6 Register description IC power down Bit R/W RST Name 7 R/W 1 PWDN Description 0: IC power down low-power condition 1: IC normal operation The PWDN register is used to place the IC in a low-power state. When PWDN is written as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted to power down the power-stage, then the master clock to all internal hardware expect the I2C block is gated. This places the IC in a very low power consumption state. 6.6.7 External amplifier power down Bit R/W RST Name 7 R/W 0 EAPD Description 0: external power stage power down active 1: normal operation The EAPD register directly disables/enables the internal power circuitry. When EAPD = 0, the internal power section is placed on a low-power state (disabled). This register also controls the DDX4B/EAPD output pin when OCFG = 10. 6.7 Volume control registers (0x06 to 0x0A) 6.7.1 Mute/line output configuration register D7 D6 LOC1 0 D5 D4 D3 D2 D1 D0 LOC0 C3M C2M C1M MMUTE 0 0 0 0 0 LOC[1:0] Line output configuration 00 Line output fixed, no volume, no EQ 01 Line output variable, CH3 volume effects line output, no EQ 10 Line output variable with EQ, CH3 volume effects line output Line output is only active when OCFG = 00. In this case LOC determines the line output configuration. The source of the line output is always the channel 1 and 2 inputs. 6.7.2 Master volume register D7 D6 D5 D4 D3 D2 D1 D0 MV7 MV6 MV5 MV4 MV3 MV2 MV1 MV0 1 1 1 1 1 1 1 1 39/64 Register description 6.7.3 6.7.4 6.7.5 STA333BW Channel 1 volume D7 D6 D5 D4 D3 D2 D1 D0 C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0 0 1 1 0 0 0 0 0 Channel 2 volume D7 D6 D5 D4 D3 D2 D1 D0 C2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0 0 1 1 0 0 0 0 0 Channel 3 / line output volume D7 D6 D5 D4 D3 D2 D1 D0 C3V7 C3V6 C3V5 C3V4 C3V3 C3V2 C3V1 C3V0 0 1 1 0 0 0 0 0 The Volume structure of the STA333BW consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to -80 dB. As an example if C3V = 0x00 or +48 dB and MV = 0x18 or –12 dB, then the total gain for channel 3 = +36 dB. The Master Mute when set to 1 mutes all channels at once, whereas the individual channel mutes (CxM) mutes only that channel. Both the Master Mute and the Channel Mutes provide a “soft mute” with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate(~96 kHz). A “hard mute” can be obtained by commanding a value of all 1’s (255) to any channel volume register or the master volume register. When volume offsets are provided via the master volume register any channel that whose total volume is less than –80 dB is muted. All changes in volume take place at zero-crossings when ZCE = 1 (configuration register F) on a per channel basis as this creates the smoothest possible volume transitions. When ZCE=0, volume updates occur immediately. Table 16. 40/64 Master volume offset as a function of MV[7:0] MV[7:0] Volume offset from channel value 00000000 (0x00) 0 dB 00000001 (0x01) -0.5 dB 00000010 (0x02) -1 dB … … 01001100 (0x4C) -38 dB STA333BW Register description Table 16. Master volume offset as a function of MV[7:0] (continued) MV[7:0] Volume offset from channel value … … 11111110 (0xFE) -127.5 dB 11111111 (0xFF) Hard master mute Table 17. Channel volume as a function of CxV[7:0] CxV[7:0] Volume 00000000 (0x00) +48 dB 00000001 (0x01) +47.5 dB 00000010 (0x02) +47 dB … … 01011111 (0x5F) +0.5 dB 01100000 (0x60) 0 dB 01100001 (0x61) -0.5 dB … … 11010111 (0xD7) -59.5 dB 11011000 (0xD8) -60 dB 11011001 (0xD9) -61 dB 11011010 (0xDA) -62 dB … … 11101100 (0xEC) -80 dB 11101101 (0xED) Hard channel mute … … 11111111 (0xFF) Hard channel mute 41/64 Register description STA333BW 6.8 Auto mode registers (0x0B and 0x0C) 6.8.1 AutoMode register 1 (0x0B) D7 D6 Table 18. D5 D4 D3 AMGC1 AMGC2 0 0 6.8.3 D0 Mode 00 User programmable GC 01 AC no clipping 2.1 10 AC limited clipping (10%) 2.1 11 DRC nighttime listening mode 2.1 AutoMode register 2 (0x0C) D7 D6 D5 D4 D3 D2 D1 D0 XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME 0 0 0 0 0 0 0 0 AM interference frequency switching Bit R/W RST Name Description 0 R/W 0 AMAME AutoMode AM Enable 0: switching frequency determined by PWMS setting 1: switching frequency determined by AMAM settings Table 19. 42/64 D1 AutoMode gain compression/limiters selection AMGC[1:0] 6.8.2 D2 AutoMode AM switching frequency selection AMAM[2:0] 48 kHz / 96 kHz input Fs 44.1 kHz / 88.2 kHz input Fs 000 0.535 MHz to 0.720 MHz 0.535 MHz to 0.670 MHz 001 0.721 MHz to 0.900 MHz 0.671 MHz to 0.800 MHz 010 0.901 MHz to 1.100 MHz 0.801 MHz to 1.000 MHz 011 1.101 MHz to 1.300 MHz 1.001 MHz to 1.180 MHz 100 1.301 MHz to 1.480 MHz 1.181 MHz to 1.340 MHz 101 1.481 MHz to 1.600 MHz 1.341 MHz to 1.500 MHz 110 1.601 MHz to 1.700 MHz 1.501 MHz to 1.700 MHz STA333BW 6.8.4 Register description Bass management crossover Bit R/W RST Name 4 R/W 0 XO0 5 R/W 0 XO1 6 R/W 0 XO2 7 R/W 0 XO3 Table 20. Description Selects the bass-management crossover frequency. A 1st-order high-pass filter (channels 1 and 2) or a 2nd-order low-pass filter (channel 3) at the selected frequency is performed. Bass management crossover frequency XO[3:0] 6.9 Crossover frequency 0000 User-Defined 0001 80 Hz 0010 100 Hz 0011 120 Hz 0100 140 Hz 0101 160 Hz 0110 180 Hz 0111 200 Hz 1000 220 Hz 1001 240 Hz 1010 260 Hz 1011 280 Hz 1100 300 Hz 1101 320 Hz 1110 340 Hz 1111 360 Hz Channel configuration registers ( 0x0E to 0x10) D7 D6 D5 D4 D3 D2 D1 D0 C1OM1 C1OM0 C1LS1 C1LS0 C1BO C1VPB C1EQBP C1TCB 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C2OM1 C2OM0 C2LS1 C2LS0 C2BO C2VPB C2EQBP C2TCB 0 1 0 0 0 0 0 0 43/64 Register description 6.9.1 STA333BW D7 D6 D5 D4 D3 D2 C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3VPB 1 0 0 0 0 0 D1 D0 Tone control bypass Tone control (bass/treble) can be bypassed on a per channel basis for channels 1 and 2. CxTCB: 0: perform tone control on channel X, normal operation 1: bypass tone control on channel X 6.9.2 EQ bypass EQ control can be bypassed on a per channel basis for channels 1 and 2. If EQ control is bypassed on a given channel the prescale and all filters (high-pass, biquads, de-emphasis, bass, treble in any combination) are bypassed for that channel. CxEQBP: 0: perform EQ on channel X, normal operation 1: bypass EQ on channel X 6.9.3 Volume bypass Each channel contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel. 6.9.4 Binary output enable registers Each individual channel output can be set to output a binary PWM stream. In this mode output A of a channel is considered the positive output and output B is negative inverse. CxBO: 0: DDX tri-state output, normal operation 1: binary output 6.9.5 Limiter select Limiter selection can be made on a per-channel basis according to the channel limiter select bits. . Table 21. Channel limiter mapping as a function of CxLS bits CxLS[1:0] 44/64 Channel limiter mapping 00 Channel has limiting disabled 01 Channel is mapped to limiter #1 10 Channel is mapped to limiter #2 STA333BW 6.9.6 Register description Output mapping Output mapping can be performed on a per channel basis according to the CxOM channel output mapping bits. Each input into the output configuration engine can receive data from any of the three processing channel outputs. . Table 22. Channel output mapping as a function of CxOM bits CxOM[1,0] Channel x output source from 00 Channel1 01 Channel 2 10 Channel 3 6.10 Tone control register (0x11) 6.10.1 Tone control D7 D6 D5 D4 D3 D2 D1 D0 TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0 0 1 1 1 0 1 1 1 Table 23. Tone control boost/cut as a function of BTC and TTC bits BTC[3:0]/TTC[3:0] Boost/Cut 0000 -12 dB 0001 -12 dB … … 0111 -4 dB 0110 -2 dB 0111 0 dB 1000 +2 dB 1001 +4 dB … … 1101 +12 dB 1110 +12 dB 1111 +12 dB 45/64 Register description STA333BW 6.11 Dynamics control registers (0x12 to 0x15) 6.11.1 Limiter 1 attack/release rate 6.11.2 6.11.3 6.11.4 D7 D6 D5 D4 D3 D2 D1 D0 L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0 0 1 1 0 1 0 1 0 Limiter 1 attack/release threshold D7 D6 D5 D4 D3 D2 D1 D0 L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0 0 1 1 0 1 0 0 1 Limiter 2 attack/release rate D7 D6 D5 D4 D3 D2 D1 D0 L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0 0 1 1 0 1 0 1 0 Limiter 2 attack/release threshold D7 D6 D5 D4 D3 D2 D1 D0 L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0 0 1 1 0 1 0 0 1 The STA333BW includes two independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode or to actively reduce the dynamic range for a better listening environment such as a night-time listening mode which is often needed for DVDs. The two modes are selected via the DRC bit in Configuration Register F, bit 0 address 0x05. Each channel can be mapped to either limiter or not mapped, meaning that channel will clip when 0dBFS is exceeded. Each limiter looks at the present value of each channel that is mapped to it, selects the maximum absolute value of all these channels, performs the limiting algorithm on that value, and then if needed adjusts the gain of the mapped channels in unison. The limiter attack thresholds are determined by the LxAT registers. It is recommended in anti-clipping mode to set this to 0dBFS, which corresponds to the maximum unclipped output power of a DDX amplifier. Since gain can be added digitally within STA333BW it is possible to exceed 0dBFS or any other LxAT setting, when this occurs, the limiter, when active, automatically starts reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. The gain reduction occurs on a peak-detect algorithm. 46/64 STA333BW Register description The release of limiter, when the gain is again increased, is dependent on a RMS-detect algorithm. The output of the volume/limiter block is passed through a RMS filter. The output of this filter is compared to the release threshold, determined by the Release Threshold register. When the RMS filter output falls below the release threshold, the gain is again increased at a rate dependent upon the Release Rate register. The gain can never be increased past it's set value and therefore the release only occurs if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as over-limiting can reduce the dynamic range to virtually zero and cause program material to sound “lifeless”. In AC mode, the attack and release thresholds are set relative to full-scale. In DRC mode, the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold. Figure 18. Basic limiter and volume flow diagram 47/64 Register description Table 24. 48/64 STA333BW Limiter attack rate as a function of LxA bits LxA[3:0] Attack Rate dB/ms 0000 3.1584 Fast Table 25. Limiter release rate as a function of LxR bits LxR[3:0] Release Rate dB/ms 0000 0.5116 0001 0.1370 0001 2.7072 0010 2.2560 0010 0.0744 0011 1.8048 0011 0.0499 0100 1.3536 0100 0.0360 0101 0.9024 0101 0.0299 0110 0.4512 0110 0.0264 0111 0.2256 0111 0.0208 1000 0.1504 1000 0.0198 1001 0.1123 1001 0.0172 1010 0.0902 1010 0.0147 1011 0.0752 1011 0.0137 1100 0.0645 1100 0.0134 1101 0.0564 1101 0.0117 1110 0.0501 1110 0.0110 1111 0.0451 1111 0.0104 Slow Fast Slow STA333BW Register description Anti-clipping mode Table 26. Limiter attack threshold as a function of LxAT bits (AC-Mode). Table 27. Limiter release threshold as a function of LxRT bits (AC-Mode). LxAT[3:0] AC(dB relative to FS) LxRT[3:0] AC(dB relative to FS) 0000 -12 0000 -∞ 0001 -10 0001 -29 dB 0010 -8 0010 -20 dB 0011 -6 0011 -16 dB 0100 -4 0100 -14 dB 0101 -2 0101 -12 dB 0110 0 0110 -10 dB 0111 +2 0111 -8 dB 1000 +3 1000 -7 dB 1001 +4 1001 -6 dB 1010 +5 1010 -5 dB 1011 +6 1011 -4 dB 1100 +7 1100 -3 dB 1101 +8 1101 -2 dB 1110 +9 1110 -1 dB 1111 +10 1111 -0 dB 49/64 Register description STA333BW Dynamic range compression mode Table 28. Limiter attack threshold as a function of LxAT bits (DRC-Mode). Table 29. Limiter release threshold as a as a function of LxRT bits (DRC-Mode). LxAT[3:0] DRC(dB relative to Volume) LxRT[3:0] DRC(db relative to Volume + LxAT) 0000 -31 0000 -∞ 0001 -29 0001 -38 dB 0010 -27 0010 -36 dB 0011 -25 0011 -33 dB 0100 -23 0100 -31 dB 0101 -21 0101 -30 dB 0110 -19 0110 -28 dB 0111 -17 0111 -26 dB 1000 -16 1000 -24 dB 1001 -15 1001 -22 dB 1010 -14 1010 -20 dB 1011 -13 1011 -18 dB 1100 -12 1100 -15 dB 1101 -10 1101 -12 dB 1110 -7 1110 -9 dB 1111 -4 1111 -6 dB 6.12 User-defined coefficient control registers (0x16 to 0x26) 6.12.1 Coefficient address register D7 6.12.2 50/64 D6 D5 D4 D3 D2 D1 D0 CFA5 CFA4 CFA3 CFA2 CFA1 CFA0 0 0 0 0 0 0 Coefficient b1 data register bits 23:16 D7 D6 D5 D4 D3 D2 D1 D0 C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16 0 0 0 0 0 0 0 0 STA333BW 6.12.3 6.12.4 6.12.5 6.12.6 6.12.7 6.12.8 Register description Coefficient b1 data register bits 15:8 D7 D6 D5 D4 D3 D2 D1 D0 C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8 0 0 0 0 0 0 0 0 Coefficient b1 data register bits 7:0 D7 D6 D5 D4 D3 D2 D1 D0 C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0 0 0 0 0 0 0 0 0 Coefficient b2 data register bits 23:16 D7 D6 D5 D4 D3 D2 D1 D0 C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16 0 0 0 0 0 0 0 0 Coefficient b2 data register bits 15:8 D7 D6 D5 D4 D3 D2 D1 D0 C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8 0 0 0 0 0 0 0 0 Coefficient b2 data register bits 7:0 D7 D6 D5 D4 D3 D2 D1 D0 C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0 0 0 0 0 0 0 0 0 Coefficient a1 data register bits 23:16 D7 D6 D5 D4 D3 D2 D1 D0 C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16 0 0 0 0 0 0 0 0 51/64 Register description 6.12.9 6.12.10 6.12.11 6.12.12 6.12.13 6.12.14 52/64 STA333BW Coefficient a1 data register bits 15:8 D7 D6 D5 D4 D3 D2 D1 D0 C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8 0 0 0 0 0 0 0 0 Coefficient a1 data register bits 7:0 D7 D6 D5 D4 D3 D2 D1 D0 C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0 0 0 0 0 0 0 0 0 Coefficient a2 data register bits 23:16 D7 D6 D5 D4 D3 D2 D1 D0 C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16 0 0 0 0 0 0 0 0 Coefficient a2 data register bits 15:8 D7 D6 D5 D4 D3 D2 D1 D0 C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8 0 0 0 0 0 0 0 0 Coefficient a2 data register bits 7:0 D7 D6 D5 D4 D3 D2 D1 D0 C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0 0 0 0 0 0 0 0 0 Coefficient b0 data register bits 23:16 D7 D6 D5 D4 D3 D2 D1 D0 C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16 0 0 0 0 0 0 0 0 STA333BW 6.12.15 6.12.16 6.12.17 Register description Coefficient b0 data register bits 15:8 D7 D6 D5 D4 D3 D2 D1 D0 C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8 0 0 0 0 0 0 0 0 Coefficient b0 data register bits 7:0 D7 D6 D5 D4 D3 D2 D1 D0 C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 C5B0 0 0 0 0 0 0 0 0 D3 D2 D1 D0 RA R1 WA W1 0 0 0 0 Coefficient write/read control register D7 D6 D5 D4 Coefficients for user-defined EQ, mixing, scaling, and bass management are handled internally in the STA333BW via RAM. Access to this RAM is available to the user via an I2C register interface. A collection of I2C registers are dedicated to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from RAM. Note: The read and write operation on RAM coefficients works only if LRCKI (pin 29) is switching. Reading a coefficient from RAM 1. Write 6-bits of address to I2C register 0x16. 2. Write 1 to R1 bit in I2C address 0x26. 3. Read top 8-bits of coefficient in I2C address 0x17. 4. Read middle 8-bits of coefficient in I2C address 0x18. 5. Read bottom 8-bits of coefficient in I2C address 0x19. Reading a set of coefficients from RAM 1. Write 6-bits of address to I2C register 0x16. 2. Write 1 to RA bit in I2C address 0x26. 3. Read top 8-bits of coefficient in I2C address 0x17. 4. Read middle 8-bits of coefficient in I2C address 0x18. 5. Read bottom 8-bits of coefficient in I2C address 0x19. 6. Read top 8-bits of coefficient b2 in I2C address 0x1A. 7. Read middle 8-bits of coefficient b2 in I2C address 0x1B. 8. Read bottom 8-bits of coefficient b2 in I2C address 0x1C. 53/64 Register description 9. STA333BW Read top 8-bits of coefficient a1 in I2C address 0x1D. 10. Read middle 8-bits of coefficient a1 in I2C address 0x1E. 11. Read bottom 8-bits of coefficient a1 in I2C address 0x1F. 12. Read top 8-bits of coefficient a2 in I2C address 0x20. 13. Read middle 8-bits of coefficient a2 in I2C address 0x21. 14. Read bottom 8-bits of coefficient a2 in I2C address 0x22. 15. Read top 8-bits of coefficient b0 in I2C address 0x23. 16. Read middle 8-bits of coefficient b0 in I2C address 0x24. 17. Read bottom 8-bits of coefficient b0 in I2C address 0x25. Writing a single coefficient to RAM 1. Write 6-bits of address to I2C register 0x16. 2. Write top 8-bits of coefficient in I2C address 0x17. 3. Write middle 8-bits of coefficient in I2C address 0x18. 4. Write bottom 8-bits of coefficient in I2C address 0x19. 5. Write 1 to W1 bit in I2C address 0x26. Writing a set of coefficients to RAM 1. Write 6-bits of starting address to I2C register 0x16. 2. Write top 8-bits of coefficient b1 in I2C address 0x17. 3. Write middle 8-bits of coefficient b1 in I2C address 0x18. 4. Write bottom 8-bits of coefficient b1 in I2C address 0x19. 5. Write top 8-bits of coefficient b2 in I2C address 0x1A. 6. Write middle 8-bits of coefficient b2 in I2C address 0x1B. 7. Write bottom 8-bits of coefficient b2 in I2C address 0x1C. 8. Write top 8-bits of coefficient a1 in I2C address 0x1D. 9. Write middle 8-bits of coefficient a1 in I2C address 0x1E. 10. Write bottom 8-bits of coefficient a1 in I2C address 0x1F. 11. Write top 8-bits of coefficient a2 in I2C address 0x20. 12. Write middle 8-bits of coefficient a2 in I2C address 0x21. 13. Write bottom 8-bits of coefficient a2 in I2C address 0x22. 14. Write top 8-bits of coefficient b0 in I2C address 0x23. 15. Write middle 8-bits of coefficient b0 in I2C address 0x24. 16. Write bottom 8-bits of coefficient b0 in I2C address 0x25. 17. Write 1 to WA bit in I2C address 0x26. The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. When using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the STA333BW generates the RAM addresses as offsets from this base value to write the complete set of coefficient data. 54/64 STA333BW 6.12.18 Register description User-defined EQ The STA333BW provides the ability to specify four EQ filters (biquads) per each of the two input channels. The biquads use the following equation: Y[n] = 2(b0/2)X[n] + 2(b1/2)X[n-1] + b2X[n-2] to 2(a1/2)Y[n-1] - a2Y[n-2] = b0X[n] + b1X[n-1] + b2X[n-2] - a1Y[n-1] - a2Y[n-2] where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF (0.9999998808). Coefficients stored in the User Defined Coefficient RAM are referenced in the following manner: CxHy0 = b1/2 CxHy1 = b2 CxHy2 = -a1/2 CxHy3 = -a2 CxHy4 = b0/2 where x represents the channel and the y the biquad number. For example C2H41 is the b2 coefficient in the fourth biquad for channel 2. Additionally, the STA333BW allows specification of a high-pass filter (processing channels 1 and 2) and a lo-pass filter (processing channel 3) to be used for bass-management crossover when the XO setting is 000 (user-defined). Both of these filters when defined by the user (rather than using the preset crossover filters) are second order filters that use the biquad equation noted above. They are loaded into the C12H0-4 and C3Hy0-4 areas of RAM noted in Table 30. By default, all user-defined filters are pass-through where all coefficients are set to 0, except the b0/2 coefficient which is set to 0x400000 (representing 0.5) 6.12.19 Pre-scale The STA333BW provides a multiplication for each input channel for the purpose of scaling the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiply is loaded into RAM using the same I2C registers as the biquad coefficients and the bass-management. All channels can use the channel 1 pre-scale factor by setting the Biquad link bit. By default, all pre-scale factors are set to 0x7FFFFF. 6.12.20 Post-scale The STA333BW provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel. This post-scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiply is loaded into RAM using the same I2C registers as the biquad coefficients and the bass-management. This post-scale factor can be used in conjunction with an ADC equipped micro-controller to perform power-supply error correction. All channels can use the channel 1 post-scale factor by setting the post-scale link bit. By default, all post-scale factors are set to 0x7FFFFF. When Line output is being utilized, channel 3 post-scale will affect both channels 3 and 4. 55/64 Register description 6.12.21 STA333BW Over-current post-scale The STA333BW provides a simple mechanism for reacting to over-current detection in the power-block. When the ocwarn input is asserted, the over-current post-scale value is used in place of the normal post-scale value to provide output attenuation on all channels. The default setting provides 3 dB of output attenuation when ocwarn is asserted. The amount of attenuation to be applied in this situation can be adjusted by modifying the Over-current Post-scale value. As with the normal post-scale, this scaling value is a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. By default, the over-current post-scale factor is set to 0x5A9DF7. Once the over-current attenuation is applied, it remains until the device is reset. Table 30. RAM block for biquads, mixing, scaling and bass management Index (Hex) Coefficient Default 0x00 C1H10(b1/2) 0x000000 0x01 C1H11(b2) 0x000000 C1H12(a1/2) 0x000000 0x03 C1H13(a2) 0x000000 0x04 C1H14(b0/2) 0x400000 0x02 Channel 1, Biquad 1 0x05 Channel 1, Biquad 2 C1H20 0x000000 … … … … 0x13 Channel 1, Biquad 4 C1H44 0x400000 C2H10 0x000000 C2H11 0x000000 0x14 Channel 2, Biquad 1 0x15 … … … … 0x27 Channel 2, Biquad 4 C2H44 0x400000 C12H0(b1/2) 0x000000 C12H1(b2) 0x000000 C12H2(a1/2) 0x000000 0x2B C12H3(a2) 0x000000 0x2C C12H4(b0/2) 0x400000 0x2D C3H0(b1/2) 0x000000 C3H1(b2) 0x000000 C3H2(a1/2) 0x000000 0x30 C3H3(a2) 0x000000 0x31 C3H4(b0/2) 0x400000 0x28 0x29 0x2A 0x2E 0x2F 56/64 Hi-Pass 2nd Order Filter for XO=000 Lo-Pass 2nd Order Filter for XO=000 0x32 Channel 1, Pre-Scale C1PreS 0x7FFFFF 0x33 Channel 2, Pre-Scale C2PreS 0x7FFFFF 0x34 Channel 1, Post-Scale C1PstS 0x7FFFFF 0x35 Channel 2, Post-Scale C2PstS 0x7FFFFF STA333BW Register description Table 30. RAM block for biquads, mixing, scaling and bass management Index (Hex) 6.13 Coefficient Default 0x36 Channel 3, Post-Scale C3PstS 0x7FFFFF 0x37 TWARN/OC– Limit TWOCL 0x5A9DF7 0x38 Channel 1, Mix 1 C1MX1 0x7FFFFF 0x39 Channel 1, Mix 2 C1MX2 0x000000 0x3A Channel 2, Mix 1 C2MX1 0x000000 0x3B Channel 2, Mix 2 C2MX2 0x7FFFFF 0x3C Channel 3, Mix 1 C3MX1 0x400000 0x3D Channel 3, Mix 2 C3MX2 0x400000 0x3E UNUSED 0x3F UNUSED Variable max power correction registers (0x27 to 0x28) MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1. 6.14 D7 D6 D5 D4 D3 D2 D1 D0 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8 0 0 0 1 1 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0 1 1 0 0 0 0 0 0 Variable distortion compensation registers (0x29 to 0x2A) DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient is used in place of the default coefficient when DCCV = 1. D7 D6 D5 D4 D3 D2 D1 D0 DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8 1 1 1 1 0 0 1 1 57/64 Register description 6.15 STA333BW D7 D6 D5 D4 D3 D2 D1 D0 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0 0 0 1 1 0 0 1 1 Fault detect recovery constant registers (0x2B to 0x2C) FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the TRISTATE output is immediately asserted low and held low for the time period specified by this constant. A constant value of 0x0001 in this register is ~.083 ms. The default value of 0x000C specifies ~.1 mS. 6.16 D7 D6 D5 D4 D3 D2 D1 D0 FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0 0 0 0 0 1 1 0 0 Device status register (0x2D) D7 D6 D5 D4 D3 D2 D1 D0 PLLUL FAULT UVFAULT OVFAULT OCFAULT OCWARN TFAULT TWARN This read-only register provides fault and thermal-warning status information from the power control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault or warning detected on power bridge. The PLLUL=’1’ means that the PLL is not locked. 58/64 " PLLUL: 0 = PLL locked, 1= PLL not locked. " FAULT: 0 = fault detected on power bridge, 1 = normal operation " UVFAULT: 0 = VCC1, VCC2 internally detected < under-voltage threshold. " OVFAULT: 0 = VCC1, VCC2 internally detected > over-voltage threshold. " OCFAULT: 0 = over-current fault detected " OCWARN: 0 = over-current warning. " TFAULT: 0 = thermal fault, junction temperature over-limit detection. " TWARN: 0 = thermal warning, junction temperature is close to the fault condition. STA333BW Application 7 Application 7.1 Application scheme for power supplies Here in the next figure the typical application scheme for STA333BW concerning the power supplies. A particular care has to be devoted to the layout of the PCB. In particular the 3.3 Ω resistors on the digital supplies (VDD_DIG) have to be put as close as possible to the device. This is to avoid any unwanted oscillation on the digital portion of the device due to the PCB track inductance. The same rule must also be applied to all the decoulpling capacitors in order to limit any kind of voltage spikes on all the supplies. Figure 19. Application scheme for power supplies 3R3 1 2 + 3 1000uF 35V 4 100nF 1uF 35V OUT2B 5 6 7 8 100nF OUT2A 9 100nF VCC OUT1B 10 11 12 1uF 35V OUT1A 13 14 100nF 15 16 7.2 DDX3B 17 DDX3A 18 GND_SUB VDD_DIG SA GND_DIG TEST_MODE SCL VSS SDA VCC_REG OUT2B INT_LINE RESET GND2 SDI VCC2 LRCKI OUT2A BICKI OUT1B VCC1 GND1 OUT1A GND_REG XTI PLL_GND FILTER_PLL VDD_PLL PWRDN VDD GND_DIG CONFIG VDD_DIG DDX3B TWARN/4A DDX3A EAPD/4B 3V3 36 100nF 35 34 SCL 33 SDA INTL 32 3V3 GND_DIG 10K 31 RESET 30 DATA 29 LRCKI 28 BICKI 27 XTI GND_DIG BEAD 26 25 PLL_FILT 100nF PLL_GND BEAD 24 23 GND_DIG 3V3 PWDN 22 21 RESET 1nF 3R3 100nF GND_DIG 3V3 20 TW 19 EAPD PLL filter schematic It is recommended to use the below scheme and values for the PLL loop filter to achieve the best performances from the device in general application. Please be noted that the ground of this filter scheme has to be conncted to the ground of the PLL without any resistive path. Concerning the component values, please take into acount that the greater is the filter bandwidth, the less is the lock time but the higher is the PLL output jitter. 59/64 Application STA333BW Figure 20. PLL application scheme. FILTER_PLL 2K2 680pF 100pF 4.7nF BEAD GND_DIG 7.3 PLL_GND Typical output configuration Here after the typical output configuration used for BTL stereo mode. Please refer to the application note for all the other possible output configuration recommended schematics. Figure 21. Output configuration for stereo BTL mode 22uH OUT1A 100nF 6.2 22 6.2 330pF 100nF 470nF LEFT 470nF RIGHT 100nF 100nF OUT1B 22uH 22uH OUT2A 100nF 6.2 22 6.2 330pF 100nF OUT2B 22uH 60/64 100nF 100nF STA333BW 8 Package thermal characteristics Package thermal characteristics Using a double-layer PCB the thermal resistance junction to ambient with 2 copper ground area of 3x3 cm and with 16 via holes (see Figure 22) is 24 °C/W in natural air convection. The dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level. The estimated maximum dissipated power for the STA333BW is: 2 x 20 W into 8 Ω, 18 V Pd max ~ 4 W 2 x 10 W + 1 x 20 W into 4 Ω, 8 Ω, 18 V Pd max < 5 W Figure 22. Double layer PCB Rth j-amb with 2 GND copper area and with 16 via holes Figure 23 shows the power derating curve for the PSSO36 package with PCB copper areas of 2 x 2 cm and 3 x 3 cm. Figure 23. PSSO36 power derating curve Pd (W) 8 7 Copper Area 3x3 cm and via holes 6 5 STA333BW PSSO36 4 3 Copper Area 2x2 cm and via holes 2 1 0 0 20 40 60 80 100 120 140 160 Tamb ( °C) 61/64 Package information 9 STA333BW Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 24. PowerSSO-36 (slug-up) mechanical data and package dimensions DIM. MIN. 2.15 2.15 0 0.18 0.23 10.10 A A2 a1 b c D (1) mm TYP. 7.4 E (1) e e3 F G G1 H h k L M N O Q S T U X Y MAX. 2.47 2.40 0.075 0.36 0.32 10.50 MIN. 0.084 0.084 0 0.007 0.009 0.398 7.6 0.291 0.5 8.5 2.3 inch TYP. MAX. 0.097 0.094 0.003 0.014 0.012 0.413 OUTLINE AND MECHANICAL DATA 0.299 0.019 0.335 0.090 0.10 0.06 10.50 0.40 10.10 0.004 0.002 0.413 0.016 0.398 5˚ 5˚ 0.55 0.90 0.022 4.3 0.035 0.169 10˚ 10˚ 1.2 0.8 2.9 3.65 1.0 0.047 0.031 0.114 0.144 0.039 4.1 6.5 4.7 7.3 0.161 0.256 PowerSSO-36 (slug-down) 0.185 0.287 A A2 (1) "D” and “E" do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0.15 mm per side(0.006”) hx45û Gauge plane 0.25 c G LEAD COPLANARITY A D M a1 stand-off Y k e T L H E X O F S Q U BOTTOM VIEW B 0.1 M A B b e3 7587131 A 62/64 STA333BW 10 Revision history Revision history Table 31. Document revision history Date Revision 11-Apr-2006 1 Initial release. 2 Added: Electrical specifications, digital section Power on sequence Processing data path Application Improved: Pin description Absolute maximum ratings Recommended operative conditions Output configuration Device status register 26-Jul-2007 Changes 63/64 STA333BW Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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