STMICROELECTRONICS STA335BWS

STA335BWS
2.1-channel high-efficiency digital audio system
Features
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Wide supply voltage range
– 4.5 V to 21.5 V operating
– 24 V absolute maximum rating
Three power-output configurations
– 2-channel ternary PWM (stereo mode)
(2 x 20 W into 8 Ω at 18 V)
– 3-channel (left, right using binary and LFE)
ternary PWM (2.1 mode) (2 x 9 W +
1 x 20 W into 2 x 4 Ω, 1 x 8 Ω at 18 V)
– 2-channel ternary PWM (2 x 20 W) +
stereo lineout ternary
2.1 channels of 24-bit DDX®
100 dB SNR and dynamic range
Selectable 32 kHz to 192 kHz input sample
rates
I2C control with selectable device address
Digital gain/attenuation +48 dB to -80 dB in
0.5 dB steps
Software volume update
Individual channel and master gain/attenuation
Dual independent limiters/compressors
Dynamic range compression or anti-clipping
modes
Automodes
– 15 preset cross-over filters
– 5 preset anti-clipping modes
– Preset night-time listening mode
Individual channel and master software and
hardware mute
Independent channel volume and DSP bypass
Automatic zero-detect mute
Automatic invalid input detect mute
Figure 1.
PowerSSO-36
Exposed pad down
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2-channel I2S input data interface
Input and output channel mapping
4 x 28-bit user programmable biquads (EQ) per
channel
Up to 3 different EQ coefficients settings can
be stored and selected using I2C interface
Bass/treble tone control
DC-blocking selectable high-pass filter
Selectable de-emphasis
Sub channel mix into left and right channels
Advanced AM interference frequency
switching and noise-suppression modes
Selectable high or low-bandwidth
noise-shaping topologies
Variable max power correction for lower
full-power THD
Selectable clock input ratio
96 kHz internal processing sample rate,
24 to 28-bit precision
Thermal overload and short-circuit protection
embedded
Video application: 576 x fs input mode
supported
PowerSSO-36 exposed pad down package
Device summary
Order code
Package
Packaging
STA335BWS
PowerSSO-36 exposed pad down
Tube
STA335BWS13TR
PowerSSO-36 exposed pad down
Tape and reel
January 2008
Rev 1
1/68
www.st.com
1
Contents
STA335BWS
Contents
1
2
3
Description and block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Connection diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . 11
2.1
Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2
Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3
Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4
Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5
Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6
Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6.1
Functional pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5
I2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1
5.1.1
Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.2
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.3
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.4
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3
Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.4
2/68
Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3.1
Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3.2
Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.4.1
Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.4.2
Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STA335BWS
6
Contents
5.4.3
Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.4.4
Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.4.5
Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.4.6
Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1
6.2
6.3
6.4
6.5
Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.1
Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.2
Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1.3
Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1.4
Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.5
Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2.1
Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2.2
Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2.3
Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2.4
Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2.5
Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3.1
DDX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3.2
DDX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3.3
Over-current warning detect adjustment bypass . . . . . . . . . . . . . . . . . . 31
Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4.1
High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4.2
De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.4.3
DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.4.4
Post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.4.5
Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.4.6
Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . 33
6.4.7
Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.4.8
Miami ModeTM enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.5.1
Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.5.2
Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.5.3
Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.5.4
AM mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.5.5
PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3/68
Contents
STA335BWS
6.6
6.7
6.8
6.9
6.10
6.5.6
Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . 34
6.5.7
Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.5.8
Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.6.1
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.6.2
Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.6.3
Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . 41
6.6.4
LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.6.5
Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.6.6
IC power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.6.7
External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Volume control registers (addr 0x06 to 0x0A) . . . . . . . . . . . . . . . . . . . . . 42
6.7.1
Mute/line output configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.7.2
Master volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.7.3
Channel 1 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.7.4
Channel 2 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.7.5
Channel 3 and line-output volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Auto mode registers (addr 0x0B and 0x0C) . . . . . . . . . . . . . . . . . . . . . . . 44
6.8.1
Automode register 1 (address 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.8.2
AutoMode register 2 (address 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.8.3
AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.8.4
Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Channel configuration registers (addr 0x0E to 0x10) . . . . . . . . . . . . . . . . 46
6.9.1
Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.9.2
EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.9.3
Volume bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.9.4
Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.9.5
Limiter select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.9.6
Output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.10.1
6.11
4/68
Tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Dynamics control registers (addr 0x12 to 0x15) . . . . . . . . . . . . . . . . . . . . 48
6.11.1
Limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.11.2
Limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.11.3
Limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.11.4
Limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STA335BWS
6.12
Contents
User-defined coefficient control registers (addr 0x16 to 0x26) . . . . . . . . . 52
6.12.1
Coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.12.2
Coefficient b1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.12.3
Coefficient b1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.12.4
Coefficient b1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.12.5
Coefficient b2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.12.6
Coefficient b2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.12.7
Coefficient b2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.12.8
Coefficient a1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.12.9
Coefficient a1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.12.10 Coefficient a1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.12.11 Coefficient a2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.12.12 Coefficient a2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.12.13 Coefficient a2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.12.14 Coefficient b0 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.12.15 Coefficient b0 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.12.16 Coefficient b0 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.12.17 Coefficient write/read control register . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.12.18 User-defined EQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.12.19 Pre-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.12.20 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.12.21 Over-current post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7
6.13
Variable max power correction registers (addr 0x27 to 0x28) . . . . . . . . . 59
6.14
Variable distortion compensation registers (addr 0x29 to 0x2A) . . . . . . . 59
6.15
Fault detect recovery constant registers (addr 0x2B to 0x2C) . . . . . . . . . 60
6.16
Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.17
EQ coefficients and DRC configuration register (addr 0x31) . . . . . . . . . . 61
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.1
Application schematic and power supplies . . . . . . . . . . . . . . . . . . . . . . . . 62
7.2
PLL filter schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.3
Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5/68
Contents
STA335BWS
10
Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 66
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6/68
STA335BWS
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Input sampling rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
IR bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Support serial audio input formats for MSB-first (SAIFB = 0) . . . . . . . . . . . . . . . . . . . . . . . 28
Supported serial audio input formats for LSB-first (SAIFB = 1) . . . . . . . . . . . . . . . . . . . . . 29
Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Output configuration engine selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Master volume offset as a function of MV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Channel volume as a function of CxV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
AutoMode gain compression/limiters selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
AutoMode AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Bass management crossover frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Channel limiter mapping as a function of CxLS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Channel output mapping as a function of CxOM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Tone control boost/cut as a function of BTC and TTC bits . . . . . . . . . . . . . . . . . . . . . . . . . 48
Limiter attack rate as a function of LxA bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Limiter release rate as a function of LxR bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Limiter attack threshold as a function of LxAT bits (AC-mode). . . . . . . . . . . . . . . . . . . . . . 51
Limiter release threshold as a function of LxRT bits (AC-mode) . . . . . . . . . . . . . . . . . . . . 51
Limiter attack threshold as a function of LxAT bits (DRC-Mode) . . . . . . . . . . . . . . . . . . . . 52
Limiter release threshold as a as a function of LxRT bits (DRC-Mode) . . . . . . . . . . . . . . . 52
RAM block for biquads, mixing, scaling and bass management. . . . . . . . . . . . . . . . . . . . . 58
SEL bitfield description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
AMGC bitfield description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
AMGC bitfield description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7/68
List of figures
STA335BWS
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
8/68
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin connection PowerSSO-36 (Top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Test circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Test circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STA335BWS processing data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
OCFG = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
OCFG = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
OCFG = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STA335BWS output mapping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.0 channels (OCFG = 00) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.1 channels (OCFG = 01) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.1 channels (OCFG = 10) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PLL application scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Output configuration for stereo BTL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Triple-layer PCB with copper ground area and 16 via holes . . . . . . . . . . . . . . . . . . . . . . . 64
PowerSSO-36 power derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PowerSSO-36 (slug-up) mechanical data and package dimensions . . . . . . . . . . . . . . . . . 65
STA335BWS
1
Description and block diagram
1.1
Description
Description and block diagram
The STA335BWS is an integrated solution of digital audio processing, digital amplifier
control, and DDX® power-output stage, thereby creating a high-power single-chip DDX®
solution comprising of high-quality, high-efficiency, all digital amplification.
The STA335BWS is part of the Sound Terminal™ family that provides full digital audio
streaming to the speaker offering cost effectiveness, low energy dissipation and sound
enrichment.
The STA335BWS power section consists of four independent half-bridges. These can be
configured via digital control to operate in different modes. 2.1 channels can be provided by
two half-bridges and a single full-bridge, providing up to 2 x 9 W + 1 x 20 W of power output.
Two channels can be provided by two full-bridges, providing up to 2 x 20 W of power. The IC
can also be configured as a 2.1 channels with 2 x 20 W provided by the device and external
power for DDX® power drive.
Also provided in the STA335BWS are a full assortment of digital processing features. This
includes up to four programmable 28-bit biquads (EQ) per channel, and bass/treble tone
control. AutoModes enable a time-to-market advantage by substantially reducing the
amount of software development needed for certain functions. This includes auto volume
loudness, preset volume curves and preset EQ settings. New advanced AM
radio-interference reduction modes. The serial audio data input interface accepts all
possible formats, including the popular I2S format. Three channels of DDX® processing are
provided. This high-quality conversion from PCM audio to DDX patented tri-state PWM
switching waveform provides over 100 dB SNR and dynamic range.
9/68
Description and block diagram
1.2
Block diagram
Figure 2.
Block diagram
I2C
I2S
interface
Volume
control
STA335BWS
Protection
current/thermal
Channel
1A
Power
control
Logic
Channel
1B
DDX
Channel
2A
Regulators
Channel
2B
PLL
Bias
Digital DSP
10/68
Power
STA335BWS
Connection diagram and pin description
2
Connection diagram and pin description
2.1
Connection diagram
Figure 3.
Pin connection PowerSSO-36 (Top view)
GND_SUB
1
36
VDD_DIG
SA
2
35
GND_DIG
TEST_MODE
3
34
SCL
VSS
4
33
SDA
VCC_REG
5
32
INT_LINE
OUT2B
6
31
RESET
GND2
7
30
SDI
VCC2
8
29
LRCKI
OUT2A
9
28
BICKI
OUT1B
10
27
XTI
VCC1
11
26
PLL_GND
GND1
12
25
FILTER_PLL
OUT1A
13
24
VDD_PLL
GND_REG
14
23
PWRDN
VDD
15
22
GND_DIG
CONFIG
16
21
VDD_DIG
OUT3B/DDX3B
17
20
TWARN/OUT4B
OUT3A/DDX3A
18
19
EAPD/OUT4A
D05AU1638
2.2
Pin description
Table 1.
Pin description
Pin
Type
Name
Description
1
GND
GND_SUB
Substrate ground
2
I
SA
I2C select address
3
I
TEST_MODE
4
I/O
VSS
5
I/O
Vcc_REG
Internal Vcc reference
6
O
OUT2B
Output half bridge 2B
7
GND
GND2
Power negative supply
8
Power
VCC2
Power positive supply
This pin must be connected to ground
Internal reference at Vcc - 3.3 V
11/68
Connection diagram and pin description
Table 1.
12/68
STA335BWS
Pin description (continued)
Pin
Type
Name
Description
9
O
OUT2A
Output half bridge 2A
10
O
OUT1B
Output half bridge 1B
11
Power
VCC1
Power positive supply
12
GND
GND1
Power negative supply
13
I/O
OUT1A
Output half bridge 1A
14
GND
GND_REG
15
Power
VDD
16
I
CONFIG
17
O
OUT3B/DDX3B
PWM out CH3B - external bridge
18
O
OUT3A/DDX3A
PWM out CH3A - external bridge
19
O
EAPD/OUT4A
20
I
TWARN/OUT4B
21
Power
VDD_DIG
Digital supply voltage
22
GND
GND_DIG
Digital ground
23
I
PWRDN
24
Power
VDD_PLL
Positive supply for PLL
25
I
FILTER_PLL
Connection to PLL filter
26
GND
GND_PLL
Negative supply for PLL
27
I
XTI
PLL input clock
28
I
BICKI
I2S serial clock
29
I
LRCKI
I2S left/right clock
30
I
SDI
31
I
RESET
32
O
INT_LINE
Fault interrupt
33
I/O
SDA
I2C serial data
34
I
SCL
I2C serial clock
35
GND
GND_DIG
Digital ground
36
Power
VDD_DIG
Digital supply voltage
Internal ground reference
Internal 3.3 V reference voltage
Paralleled mode command
Power down for external bridge
Thermal warning from external bridge
Power down
I2S serial data channels 1 and 2
Reset
STA335BWS
2.3
Connection diagram and pin description
Thermal data
Table 2.
Thermal data
Parameter
Min
Typ
Max
Unit
Rth j-case
Thermal resistance junction-case (thermal
pad)
Tth-sdj
Thermal shut-down junction temperature
150
°C
Tth-w
Thermal warning temperature
130
°C
Tth-sdh
Thermal shut-down hysteresis
20
°C
Rth j-amb
Thermal resistance junction-ambient
1.5
°C/W
(1)
1. See Section 8: Package thermal characteristics on page 64 for details.
13/68
Electrical specifications
STA335BWS
3
Electrical specifications
3.1
Absolute maximum ratings
Table 3.
Absolute maximum ratings
Symbol
Vcc
Note:
3.2
1
Parameter
Power supply voltage (VCCxA, VCCxB)
Typ
Max
Unit
-0.3
23
V
VDD_DIG Digital supply voltage
-0.3
4
V
VDD_PLL PLL supply voltage
-0.3
4
Top
Operating junction temperature
0
150
°C
Tstg
Storage temperature
-40
150
°C
Stresses beyond those listed under “Absolute maximum ratings” make cause permanent
damage to the device. These are stress ratings only, and functional operation of the device
at these or any other conditions beyond those indicated under “Recommended operating
condition” are not implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability. In the real application, power supply with nominal value
rated inside recommended operating conditions, may experience some rising beyond the
maximum operating condition for short time when no or very low current is sinked (amplifier
in mute state). In this case the reliability of the device is guaranteed, provided that the
absolute maximum rating is not exceeded.
Recommended operating condition
Table 4.
Recommended operating condition
Symbol
14/68
Min
Parameter
Min
Vcc
Power supply voltage (VCCxA, VCCxB)
4.5
VDD_DIG
Digital supply voltage
2.7
VDD_PLL
PLL supply voltage
2.7
Tamb
Ambient temperature
-20
Typ
Max
Unit
21.5
V
3.3
3.6
V
3.3
3.6
V
70
°C
STA335BWS
Electrical specifications
3.3
Electrical specifications - digital section
Table 5.
Electrical specifications - digital section
Symbol
Parameter
Conditions
Iil
Low level input current without pull device Vi = 0 V
Iih
High level input current without pull device
Vil
Low level input voltage
Vih
High level input voltage
Vol
Low level output voltage
Iol = 2 mA
Voh
High level output voltage
Ioh = 2 mA
Ipu
Pull current
Rpu
Equivalent pull resistance
3.4
Min
Typ
Max
Unit
-10
10
µA
Vi = VDD_DIG =
-10
3.6 V
10
µA
0.2*VDD_DIG
V
0.8*VDD_DIG
V
0.4*VDD_DIG
V
0.8*VDD_DIG
-25
V
66
125
µA
50
KΩ
Electrical specifications - power section
The specifications given in this section are with the operating conditions VCC = 18 V, f =
1 kHz, fsw = 384 kHz, Tamb = 25° C, RL = 8 Ω, unless otherwise specified.
Table 6.
Symbol
Electrical specifications - power section
Parameter
Output power BTL
Conditions
Min
Typ
THD = 1%
16
THD = 10%
20
THD = 1%
4
THD = 10%
5
Max
VCC = 18 V
Unit
W
Po
Output power SE
VCC = 18V
W
RdsON
Power Pchannel/Nchannel
MOSFET (total bridge)
ld = 1.5 A
gP
Power Pchannel RdsON
matching
ld = 1.5 A
95
%
gN
Power Nchannel RdsON
matching
ld = 1.5 A
95
%
Idss
Power Pchannel/Nchannel
leakage ldss
VCC = 20 V
gP
Power Pchannel RdsON
Matching
ld = 1.5 A
95
%
gN
Power Nchannel RdsON
Matching
ld = 1.5 A
95
%
Idss
Power Pchannel/Nchannel
leakage
VCC = 20 V
ILDT
Low current dead time (static)
Resistive load(1)
180
250
10
8
mΩ
µA
10
µA
15
ns
15/68
Electrical specifications
Table 6.
STA335BWS
Electrical specifications - power section (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IHDT
High current dead time
(dynamic)
Iload = 1.5 A (1)
15
30
ns
tr
Rise time
Resistive load (1)
10
18
ns
tf
Fall time
Resistive load (1)
10
18
ns
Vcc
Supply voltage operating
voltage
21.5
V
Ivcc
4.5
Supply current from Vcc in
power down
PWRDN = 0
0.1
1
mA
Supply current from Vcc in
operation
PCM Input signal = -60 dBFS
Switching frequency = 384 kHz
No LC filters
52
60
mA
55
70
mA
4.0
A
Ivdd
Supply current DDX processing
Internal clock = 49.152 MHz
(reference only)
Ilim
Overcurrent limit
Isc
Short circuit protection
UVL
Under voltage protection
tmin
Output minimum pulse width
DR
Dynamic range
100
dB
Signal to noise ratio, ternary
mode
100
dB
90
dB
SNR
(2)
2.2
3.0
Hi-Z output
2.7
3.6
No load
20
A
3.5
4.3
V
30
60
ns
A-Weighted
Signal to noise ratio binary
mode
PSSR
Power supply rejection ratio
DDX stereo mode, <5 kHz
VRIPPLE = 1 V RMS
Audio input = dither only
80
dB
THD+N
Total harmonic distortion +
noise
DDX stereo mode, Po = 1 W
f = 1 kHz
0.2
%
XTALK
Crosstalk
DDX stereo mode, <5 kHz
One channel driven @ 1 W
Other channel measured
80
dB
Peak efficiency, DDX mode
Po = 2 x 20 W into 8 Ω
90
Peak efficiency, binary modes
Po = 2 x 9 W into 4 Ω,
1 x 20 W into 8 Ω
87
η
%
1. Refer to Figure 4: Test circuit 1.
2. Limit current if the register (OCRB par 6.1.3.3) overcurrent warning detect adjustment bypass is enabled. When disabled
refer to Isc.
16/68
STA335BWS
3.5
Electrical specifications
Power-on sequence
Table 7.
Power-on sequence
VCC
Don’t care
VDD_Dig
XTI
Don’t care
Reset
TR
I2C
TC
Don’t care
CMD0
CMD1
CMD2
PWDN
Where:
TR = minimum time between XTI master clock stable and Reset removal: 1 ms
TC = minimum time between Reset removal and I2C program, sequence start: 1msec
Note:
Clock stable means: fmax - fmin < 1 MHz
Note:
No specific VCC and VDD_Dig turn−on sequence is required
3.6
Testing
3.6.1
Functional pin status
Table 8.
Functional pin status
Pin name
Pin #
Logic value
IC status
PWRDN
23
0
Low absorption
PWRDN
23
1
Normal operation
TWARN
20
0
From external power stage is indicated a temperature
warning
TWARN
20
1
Normal operation
EAPD
19
0
Low absorption for power stage
All internal regulators are switched off
EAPD
19
1
Normal operation
17/68
Electrical specifications
Figure 4.
STA335BWS
Test circuit 1
OUTxY
Vcc
(3/4)Vcc
Low current dead time = MAX(DTr, DTf)
(1/2)Vcc
(1/4)Vcc
+Vcc
t
DTr
Duty cycle = 50%
DTf
M58
OUTxY
INxY
R8Ω
M57
V67
vdc = Vcc/2
+
gnd
Figure 5.
Test circuit 2
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+VCC
Duty cycle=A
Duty cycle=B
DTout(A)
M58
DTin(A)
Q1
Q2
OUTA
INA
Iout=1.5A
M57
Q3
DTout(B)
Rload=4Ω
L67 10µ
C69
470nF
L68 10µ
C71 470nF
C70
470nF
DTin(B)
OUTB
INB
Iout=1.5A
Q4
Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure
18/68
M64
M63
D06AU1651
STA335BWS
4
Processing data paths
Processing data paths
Here after some pictures that represent the data processing paths inside STA335BWS. A
first 2x oversampling FIR filter allows a 2*fs audio processing. Then a selectable high pass
filter removes the DC level. 4 biquads filter allow a full equalization system. A final crossover
filter is present. This filter can eventually be used as a fifth biquad stage, see the I2C
registers settings for this specific usage. A prescaler and a final post scaler allow a full
control over the signal dynamic respectively before and after the filtering stages. A mixer
function is also available.
Figure 6.
STA335BWS processing data flow
Sampling
frequency=Fs
Sampling
frequency=2xFs
x2
FIR
over
sampling
PreScale
Hi-Pass
Filter
Biquad
#1
If HPB=0
Biquad
#2
Biquad
#3
Biquad
#4
DeEmphasis
User-Defined Filters
Bass
Treble
L
If C1TCB=0
BTC: Bass Boost/Cut
TTC: Treble Boost/Cut
If DEMP=0
From
I2S input
interface
If DSPB=0 and C1EQBP=0
x2
FIR
over
sampling
PreScale
Hi-Pass
Filter
If HPB=0
Biquad
#1
Biquad
#2
Biquad
#3
DeEmphasis
Biquad
#4
User-Defined Filters
Bass
Treble
R
If C2TCB=0
BTC: Bass Boost/Cut
TTC: Treble Boost/Cut
If DEMP=0
If DSPB=0 and C2EQBP=0
L
C1Mx1
+
R
C1Mx2
Channel ½
Hi-Pass XO
Biquad #5
Filter
-------------Hi-pass XO
filter
Vol
And
Limiter
Post scale
Vol
And
Limiter
Post scale
Vol
And
Limiter
Post scale
C2Mx1
+
C2Mx2
Channel ½
Hi-Pass
XO
Biquad
Filter#5
-------------Hi-pass XO
filter
C3Mx1
+
C3Mx2
User-Defined Mix Coefficients
Channel 3
Lo-Pass XO
Biquad
Filter
-------------Low-pass XO
filter
Crossover Frequency determined by XO Setting
User Defined If XO=0000
19/68
I2C bus specification
5
STA335BWS
I2C bus specification
The STA335BWS supports the I2C protocol via the input ports SCL and SDA_IN (master to
slave) and the output port SDA_OUT (slave to master). This protocol defines any device that
sends data on to the bus as a transmitter and any device that reads the data as a receiver.
The device that controls the data transfer is known as the master and the other as the slave.
The master always starts the transfer and provides the serial clock for synchronization.
STA335BWS is always a slave device in all of its communications. It supports up to 400 kb/s
(fast-mode bit rate). STA335BWS I2C is a slave only interface.
5.1
Communication protocol
5.1.1
Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition
while the clock is high is used to identify a START or STOP condition.
5.1.2
Start condition
START is identified by a high to low transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A START condition must precede any command for
data transfer.
5.1.3
Stop condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal
SCL is stable in the high state. A STOP condition terminates communication between
STA335BWS and the bus master.
5.1.4
Data input
During the data input the STA335BWS samples the SDA signal on the rising edge of clock
SCL. For correct device operation the SDA signal must be stable during the rising edge of
the clock and the data can change only when the SCL line is low.
5.2
Device addressing
To start communication between the master and the STA335BWS, the master must initiate
with a start condition. Following this, the master sends onto the SDA line 8-bits (MSB first)
corresponding to the device select address and read or write mode.
The seven most significant bits are the device address identifiers, corresponding to the I2C
bus definition. In the STA335BWS the I2C interface has two device addresses depending on
the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1.
The eighth bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode
and 0 for write mode. After a START condition the STA335BWS identifies on the bus the
device address and if a match is found, it acknowledges the identification on SDA bus during
the 9th bit time. The byte following the device identification byte is the internal space
address.
20/68
STA335BWS
5.3
I2C bus specification
Write operation
Following the START condition the master sends a device select code with the RW bit set
to 0. The STA335BWS acknowledges this and the writes for the byte of internal address.
After receiving the internal byte address the STA335BWS again responds with an
acknowledgement.
5.3.1
Byte write
In the byte write mode the master sends one data byte, this is acknowledged by the
STA335BWS. The master then terminates the transfer by generating a STOP condition.
5.3.2
Multi-byte write
The multi-byte write modes can start from any internal address. The master generating a
STOP condition terminates the transfer.
5.4
Read operation
5.4.1
Current address byte read
Following the START condition the master sends a device select code with the RW bit set
to 1. The STA335BWS acknowledges this and then responds by sending one byte of data.
The master then terminates the transfer by generating a STOP condition.
5.4.2
Current address multi-byte read
The multi-byte read modes can start from any internal address. Sequential data bytes are
read from sequential addresses within the STA335BWS. The master acknowledges each
data byte read and then generates a STOP condition terminating the transfer.
5.4.3
Random address byte read
Following the START condition the master sends a device select code with the RW bit set
to 0. The STA335BWS acknowledges this and then the master writes the internal address
byte. After receiving, the internal byte address the STA335BWS again responds with an
acknowledgement. The master then initiates another START condition and sends the device
select code with the RW bit set to 1. The STA335BWS acknowledges this and then
responds by sending one byte of data. The master then terminates the transfer by
generating a STOP condition.
5.4.4
Random address multi-byte read
The multi-byte read modes could start from any internal address. Sequential data bytes are
read from sequential addresses within the STA335BWS. The master acknowledges each
data byte read and then generates a STOP condition terminating the transfer.
21/68
I2C bus specification
STA335BWS
5.4.5
Write mode sequence
Figure 7.
Write mode sequence
ACK
BYTE
WRITE
DEV-ADDR
ACK
DATA IN
RW
START
STOP
ACK
DEV-ADDR
MULTIBYTE
WRITE
ACK
Read mode sequence
Figure 8.
Read mode sequence
ACK
DEV-ADDR
DATA IN
NO ACK
DATA
RW
START
STOP
ACK
DEV-ADDR
ACK
SUB-ADDR
RW
RW= ACK
HIGH
START
SEQUENTIAL
CURRENT
READ
DEV-ADDR
ACK
DEV-ADDR
START
RW
ACK
DATA
NO ACK
DATA
STOP
ACK
DATA
NO ACK
DATA
STOP
START
ACK
SEQUENTIAL
RANDOM
READ
DEV-ADDR
START
22/68
ACK
DATA IN
STOP
5.4.6
RANDOM
ADDRESS
READ
ACK
SUB-ADDR
RW
START
CURRENT
ADDRESS
READ
ACK
SUB-ADDR
ACK
SUB-ADDR
RW
ACK
DEV-ADDR
START
ACK
DATA
RW
ACK
DATA
NO ACK
DATA
STOP
STA335BWS
Register description
6
Register description
Table 9.
Register summary
Addr
Name
D7
D6
D5
D4
D3
D2
D1
D0
0x00
ConfA
FDRB
TWAB
TWRB
IR1
IR0
MCS2
MCS1
MCS0
0x01
ConfB
C2IM
C1IM
DSCKE
SAIFB
SAI3
SAI2
SAI1
SAI0
0x02
ConfC
OCRB
CSZ3
CSZ2
CSZ1
CSZ0
OM1
OM0
0x03
ConfD
MME
ZDE
DRC
BQL
PSL
DSPB
DEMP
HPB
0x04
ConfE
SVE
ZCE
DCCV
PWMS
AME
NSBW
MPC
MPCV
0x05
ConfF
EAPD
PWDN
ECLE
LDTE
BCLE
IDE
OCFG1
OCFG0
0x06
Mute/LOC
LOC1
LOC0
C3M
C2M
C1M
MMute
0x07
Mvol
MV7
MV6
MV5
MV4
MV3
MV2
MV1
MV0
0x08
C1Vol
C1V7
C1V6
C1V5
C1V4
C1V3
C1V2
C1V1
C1V0
0x09
C2Vol
C2V7
C2V6
C2V5
C2V4
C2V3
C2V2
C2V1
C2V0
0x0A
C3Vol
C3V7
C3V6
C3V5
C3V4
C3V3
C3V2
C3V1
C3V0
0x0B
Auto1
AMGC1
AMGC0
0x0C
Auto2
0x0D
Auto3
0x0E
XO3
XO2
XO1
XO0
AMAM2
AMAM1
AMAM0
AMAME
C1Cfg
C1OM1
C1OM0
C1LS1
C1LS0
C1BO
C1VBP
C1EQBP
C1TCB
0x0F
C2Cfg
C2OM1
C2OM0
C2LS1
C2LS0
C2BO
C2VBP
C2EQBP
C2TCB
0x10
C3Cfg
C3OM1
C3OM0
C3LS1
C3LS0
C3BO
C3VBP
0x11
Tone
TTC3
TTC2
TTC1
TTC0
BTC3
BTC2
BTC1
BTC0
0x12
L1ar
L1A3
L1A2
L1A1
L1A0
L1R3
L1R2
L1R1
L1R0
0x13
L1atrt
L1AT3
L1AT2
L1AT1
L1AT0
L1RT3
L1RT2
L1RT1
L1RT0
0x14
L2ar
L2A3
L2A2
L2A1
L2A0
L2R3
L2R2
L2R1
L2R0
0x15
L2atrt
L2AT3
L2AT2
L2AT1
L2AT0
L2RT3
L2RT2
L2RT1
L2RT0
0x16
Cfaddr
CFA5
CFA4
CFA3
CFA2
CFA1
CFA0
0x17
B1cf1
C1B23
C1B22
C1B21
C1B20
C1B19
C1B18
C1B17
C1B16
0x18
B1cf2
C1B15
C1B14
C1B13
C1B12
C1B11
C1B10
C1B9
C1B8
0x19
B1cf3
C1B7
C1B6
C1B5
C1B4
C1B3
C1B2
C1B1
C1B0
0x1A
B2cf1
C2B23
C2B22
C2B21
C2B20
C2B19
C2B18
C2B17
C2B16
0x1B
B2cf2
C2B15
C2B14
C2B13
C2B12
C2B11
C2B10
C2B9
C2B8
0x1C
B2cf3
C2B7
C2B6
C2B5
C2B4
C2B3
C2B2
C2B1
C2B0
0x1D
A1cf1
C3B23
C3B22
C3B21
C3B20
C3B19
C3B18
C3B17
C3B16
0x1E
A1cf2
C3B15
C3B14
C3B13
C3B12
C3B11
C3B10
C3B9
C3B8
0x1F
A1cf3
C3B7
C3B6
C3B5
C3B4
C3B3
C3B2
C3B1
C3B0
23/68
Register description
Table 9.
STA335BWS
Register summary (continued)
Addr
Name
D7
D6
D5
D4
D3
D2
D1
D0
0x20
A2cf1
C4B23
C4B22
C4B21
C4B20
C4B19
C4B18
C4B17
C4B16
0x21
A2cf2
C4B15
C4B14
C4B13
C4B12
C4B11
C4B10
C4B9
C4B8
0x22
A2cf3
C4B7
C4B6
C4B5
C4B4
C4B3
C4B2
C4B1
C4B0
0x23
B0cf1
C5B23
C5B22
C5B21
C5B20
C5B19
C5B18
C5B17
C5B16
0x24
B0cf2
C5B15
C5B14
C5B13
C5B12
C5B11
C5B10
C5B9
C5B8
0x25
B0cf3
C5B7
C5B6
C5B5
C5B4
C5B3
C5B2
C5B1
C5B0
0x26
Cfud
RA
R1
WA
W1
0x27
MPCC1
MPCC15 MPCC14
MPCC13
MPCC12
MPCC11
MPCC10
MPCC9
MPCC8
0x28
MPCC2
MPCC7
MPCC6
MPCC5
MPCC4
MPCC3
MPCC2
MPCC1
MPCC0
0x29
DCC1
DCC15
DCC14
DCC13
DCC12
DCC11
DCC10
DCC9
DCC8
0x2A
DCC2
DCC7
DCC6
DCC5
DCC4
DCC3
DCC2
DCC1
DCC0
0x2B
FDRC1
FDRC15
FDRC14
FDRC13
FDRC12
FDRC11
FDRC10
FDRC9
FDRC8
0x2C
FDRC2
FDRC7
FDRC6
FDRC5
FDRC4
FDRC3
FDRC2
FDRC1
FDRC0
0x2D
Status
PLLUL
FAULT
UVFAULT
OVFAULT
OCFAULT OCWARN
TFAULT
TWARN
0x2E
reserved
RO1BACT
R5BACT
R4BACT
R3BACT
R2BACT
R1BACT
0x2F
reserved
R01BEND
R5BEND
R4BEND
R3BEND
R2BEND R1BEND
0x30
reserved
R5BBAD
R4BBAD
R3BBAD
R2BBAD R1BBAD
0x31
EQCFG
AMGC3
AMGC2
reserved
24/68
XOB
SEL1
SEL0
STA335BWS
6.1
6.1.1
Register description
Configuration register A (addr 0x00)
D7
D6
D5
D4
D3
D2
D1
D0
FDRB
TWAB
TWRB
IR1
IR0
MCS2
MCS1
MCS0
0
1
1
0
0
0
1
1
Master clock select
Bit
R/W
RST
Name
0
R/W
1
MCS0
1
R/W
1
MCS1
2
R/W
0
MCS2
Description
Selects the ratio between the input I2S sample
frequency and the input clock.
The STA335BWS supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. Therefore the internal clock is:
"
32.768 MHz for 32 kHz
"
45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
"
49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample
frequency (fs).
The relationship between the input clock and the input sample rate is determined by both
the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor
generating the internal clock and the IR bit determines the oversampling ratio used
internally
Table 10.
Input sampling rates
Input sample rate
fs (kHz)
IR
MCS[2:0)
101
100
011
010
001
000
32, 44.1, 48
00
576fs
128fs
256fs
384fs
512fs
768fs
88.2, 96
01
NA
64fs
128fs
192fs
256fs
384fs
176.4, 192
1X
NA
32fs
64fs
96fs
128fs
192fs
25/68
Register description
6.1.2
STA335BWS
Interpolation ratio select
Bit
R/W
RST
Name
Description
4:3
R/W
00
IR[1:0)
Selects internal interpolation ratio based on input I2S
sample frequency
The STA335BWS has variable interpolation (oversampling) settings such that internal
processing and DDX output rates remain consistent. The first processing block interpolates
by either 2 times or 1 time (pass-through) or provides a 2 times downsample. The
oversampling ratio of this interpolation is determined by the IR bits.
Table 11.
6.1.3
IR bit settings as a function of input sample rate
Input sample rate Fs (kHz)
IR
1st stage interpolation ratio
32
00
2 times oversampling
44.1
00
2 times oversampling
48
00
2 times oversampling
88.2
01
Pass-through
96
01
Pass-through
176.4
10
2 times downsampling
192
10
2 times downsampling
Thermal warning recovery bypass
Bit
R/W
RST
Name
5
R/W
1
TWRB
Description
0: Thermal warning recovery enabled
1: Thermal warning recovery disabled
If the thermal warning adjustment is enabled (TWAB = 0), then the thermal warning
recovery determines if the -3 dB output limit is removed when thermal warning is negative.
If TWRB = 0 and TWAB = 0, then when a thermal warning disappears the -3 dB output limit
is removed and the gain is added back to the system. If TWRB = 1 and TWAB = 0, then
when a thermal warning disappears the -3 dB output limit remains until TWRB is changed to
zero or the device is reset.
26/68
STA335BWS
6.1.4
Register description
Thermal warning adjustment bypass
Bit
R/W
RST
Name
6
R/W
1
TWAB
Description
0: Thermal warning adjustment enabled
1: Thermal warning adjustment disabled
The on-chip STA335BWS power output block provides feedback to the digital controller
using inputs to the power control block. The TWARN input is used to indicate a thermal
warning condition. When TWARN is asserted (set to 0) for a period of time greater than
400 ms, the power control block forces a -3 dB output limit (determined by TWOCL in the
coefficient RAM) to the modulation limit in an attempt to eliminate the thermal warning
condition. Once the thermal warning output limit adjustment is applied, it remains in this
state until reset, unless FDRB = 0.
6.1.5
Fault detect recovery bypass
Bit
R/W
RST
Name
Description
7
R/W
0
FDRB
0: fault detect recovery enabled
1: fault detect recovery disabled
The on-chip STA335BWS power output block provides feedback to the digital controller
using inputs to the power control block. The FAULT input is used to indicate a fault condition
(either over-current or thermal). When FAULT is asserted (set to 0), the power control block
attempts a recovery from the fault by asserting the tri-state output (setting it to 0 which
directs the power output block to begin recovery), holds it at 0 for period of time in the range
of 0.1 ms to 1 s as defined by the fault-detect recovery constant register (FDRC registers
0x29, 0x2A), then toggles it back to 1. This sequence is repeated as log as the fault
indication exists. This feature is enabled by default but can be bypassed by setting the
FDRB control bit to 1.
6.2
6.2.1
Configuration register B (addr 0x01)
D7
D6
D5
D4
D3
D2
D1
D0
C2IM
C1IM
DSCKE
SAIFB
SAI3
SAI2
SAI1
SAI0
1
0
0
0
0
0
0
0
Serial audio input interface format
Bit
R/W
RST
Name
0
R/W
0
SAI0
1
R/W
0
SAI1
2
R/W
0
SAI2
3
R/W
0
SAI3
Description
Determines the interface format of the input serial
digital audio interface.
27/68
Register description
6.2.2
STA335BWS
Serial data interface
The STA335BWS audio serial input was designed to interface with standard digital audio
components and to accept a number of serial data formats. STA335BWS always acts a
slave when receiving audio input from standard digital audio components. Serial data for two
channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial
data 1 and 2 SDI12.
The SAI register (configuration register B (0x01), bits D3 to D0) and the SAIFB register
(configuration register B (0x01), bit D4) are used to specify the serial data format. The
default serial data format is I2S, MSB-first. Available formats are shown in the tables and
figure that follow.
6.2.3
Serial data first bit
SAIFB
Table 12.
Format
0
MSB-first
1
LSB-first
Support serial audio input formats for MSB-first (SAIFB = 0)
BICKI
SAI [3:0]
SAIFB
Interface format
0000
0
I2S
0001
0
Left/right-justified 16-bit data
0000
0
I2S 16 to 23-bit data
0001
0
Left-justified 16 to 24-bit data
0010
0
Right-justified 24-bit data
0110
0
Right-justified 20-bit data
1010
0
Right-justified 18-bit data
1110
0
Right-justified 16-bit data
0000
0
I2S 16 to 24-bit data
0001
0
Left-justified 16 to 24-bit data
0010
0
Right-justified 24-bit data
0110
0
Right-justified 20-bit data
1010
0
Right-justified 18-bit data
1110
0
Right-justified 16-bit data
15-bit data
32fs
48fs
64fs
28/68
STA335BWS
Register description
Table 13.
Supported serial audio input formats for LSB-first (SAIFB = 1)
BICKI
SAI [3:0]
SAIFB
Interface Format
1100
1
I2S 15-bit data
1110
1
Left/right-justified 16-bit data
0100
1
I2S 23-bit data
0100
1
I2S 20-bit data
1000
1
I2S 18-bit data
1100
1
LSB first I2S 16-bit data
0001
1
Left-justified 24-bit data
0101
1
Left-justified 20-bit data
1001
1
Left-justified 18-bit data
1101
1
Left-justified 16-bit data
0010
1
Right-justified 24-bit data
0110
1
Right-justified 20-bit data
1010
1
Right-justified 18-bit data
1110
1
Right-justified 16-bit data
0000
1
I2S 24-bit data
0100
1
I2S 20-bit data
1000
1
I2S 18-bit data
1100
1
LSB first I2S 16-bit data
0001
1
Left-justified 24-bit data
0101
1
Left-justified 20-bit data
1001
1
Left-justified 18-bit data
1101
1
Left-justified 16-bit data
0010
1
Right-justified 24-bit data
0110
1
Right-justified 20-bit data
1010
1
Right-justified 18-bit data
1110
1
Right-justified 16-bit data
32fs
48fs
64fs
6.2.4
Delay serial clock enable
Bit
R/W
RST
Name
Description
5
R/W
0
DSCKE
0: No serial clock delay
1: Serial clock delay by 1 core clock cycle to tolerate
anomalies in some I2S master devices
29/68
Register description
6.2.5
STA335BWS
Channel input mapping
Bit
R/W
RST
Name
Description
6
R/W
0
C1IM
0: Processing channel 1 receives Left I2S Input
1: Processing channel 1 receives Right I2S Input
7
R/W
1
C2IM
0: Processing channel 2 receives Left I2S Input
1: Processing channel 2 receives Right I2S Input
Each channel received via I2S can be mapped to any internal processing channel via the
Channel Input Mapping registers. This allows for flexibility in processing. The default
settings of these registers map each I2S input channel to its corresponding processing
channel.
6.3
Configuration register C (addr 0x02)
D7
D6
D5
D4
D3
D2
D1
D0
OCRB
Reserved
CSZ3
CSZ2
CSZ1
CSZ0
OM1
OM0
0
1
0
1
1
1
1
6.3.1
DDX power output mode
Bit
R/W
RST
Name
0
R/W
1
OM0
1
R/W
1
OM1
Description
Selects configuration of DDX output.
The DDX power output mode selects how the DDX output timing is configured.
Different power devices use different output modes.
Table 14.
Output modes
OM[1,0]
30/68
Output stage mode
00
Drop compensation
01
Discrete output stage - tapered compensation
10
Full power mode
11
Variable drop compensation (CSZx bits)
STA335BWS
6.3.2
Register description
DDX compensating pulse size register
Bit
R/W
RST
Name
2
R/W
1
CSZ0
3
R/W
0
CSZ1
4
R/W
1
CSZ2
5
R/W
0
CSZ3
Table 6:
Table 15.
Description
When OM[1,0] = 11, this register determines the
size of the DDX compensating pulse from 0 clock
ticks to 15 clock periods.
Compensating pulse size
CSZ[3:0]
Compensating Pulse Size
0000
0 ns (0 tick) compensating pulse size
0001
20 ns (1 tick) clock period compensating pulse size
…
…
1111
6.3.3
300 ns (15 ticks) clock period compensating pulse size
Over-current warning detect adjustment bypass
Bit
R/W
RST
Name
7
R/W
1
OCRB
Description
0: Over-Current warning Adjustment enabled
1: Over-Current warning Adjustment disabled
The OCWARN input is used to indicate an over-current warning condition. When OCWARN
is asserted (set to 0), the power control block forces an adjustment to the modulation limit
(default is -3 dB) in an attempt to eliminate the over-current warning condition. Once the
over-current warning volume adjustment is applied, it remains in this state until reset is
applied. The level of adjustment can be changed via the TWOCL (thermal warning/over
current limit) setting which is address 0x37 of the user defined coefficient RAM.
6.4
6.4.1
Configuration register D (addr 0x03)
D7
D6
D5
D4
D3
D2
D1
D0
MME
ZDE
DRC
BQL
PSL
DSPB
DEMP
HPB
0
1
0
0
0
0
0
0
High-pass filter bypass
Bit
R/W
RST
Name
Description
0
R/W
0
HPB
Setting of one bypasses internal AC coupling digital
high-pass filter
The STA335BWS features an internal digital high-pass filter for the purpose of AC coupling.
The purpose of this filter is to prevent DC signals from passing through a DDX amplifier. DC
signals can cause speaker damage. When HPB = 0, this filter is enabled.
31/68
Register description
6.4.2
STA335BWS
De-emphasis
Bit
R/W
RST
Name
1
R/W
0
DEMP
Description
0: No de-emphasis
1: De-emphasis
Setting the DEMP bit enables de-emphasis on all channels
6.4.3
DSP bypass
Bit
R/W
RST
Name
2
R/W
0
DSPB
Description
0: Normal operation
1: Bypass of biquad and bass/treble functionality
Setting the DSPB bit bypasses the EQ functionality of the STA335BWS.
6.4.4
Post-scale link
Bit
R/W
RST
Name
3
R/W
0
PSL
Description
0: Each channel uses individual post-scale value
1: Each channel uses channel 1 post-scale value
Post-scale functionality can be used for power-supply error correction. For multi-channel
applications running off the same power-supply, the post-scale values can be linked to the
value of channel 1 for ease of use and update the values faster.
6.4.5
Biquad coefficient link
Bit
R/W
RST
Name
4
R/W
0
BQL
Description
0: Each channel uses coefficient values
1: Each channel uses channel 1 coefficient values
For ease of use, all channels can use the biquad coefficients loaded into the Channel 1
Coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to
be performed once.
32/68
STA335BWS
6.4.6
Register description
Dynamic range compression/anti-clipping bit
Bit
R/W
RST
Name
5
R/W
0
DRC
Description
0: Limiters act in anti-clipping mode
1: Limiters act in dynamic range compression mode
Both limiters can be used in one of two ways, anti-clipping or dynamic range compression.
When used in anti-clipping mode the limiter threshold values are constant and dependent on
the limiter settings. In dynamic range compression mode the limiter threshold values vary
with the volume settings allowing a nighttime listening mode that provides a reduction in the
dynamic range regardless of the volume level.
6.4.7
Zero-detect mute enable
Bit
R/W
RST
Name
Description
6
R/W
1
ZDE
Setting of 1 enables the automatic zero-detect mute
Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at
the data for each processing channel at the output of the crossover (bass management)
filter. If any channel receives 2048 consecutive zero value samples (regardless of fs) then
that individual channel is muted if this function is enabled.
6.4.8
6.5
6.5.1
Miami ModeTM enable
Bit
R/W
RST
Name
7
R/W
0
MME
Description
0: Sub Mix into Left/Right Disabled
1: Sub Mix into Left/Right Enabled
Configuration register E (addr 0x04)
D7
D6
D5
D4
D3
D2
D1
D0
SVE
ZCE
DCCV
PWMS
AME
NSBW
MPC
MPCV
1
1
0
0
0
0
1
0
Max power correction variable
Bit
R/W
RST
Name
0
R/W
0
MPCV
Description
0: Use standard MPC coefficient
1: Use MPCC bits for MPC coefficient
33/68
Register description
6.5.2
STA335BWS
Max power correction
Bit
R/W
RST
Name
1
R/W
1
MPC
Description
Setting of 1 enables Power Bridge correction for
THD reduction near maximum power output.
Setting the MPC bit turns on special processing that corrects the STA335BWS power device
at high power. This mode should lower the THD+N of a full DDX system at maximum power
output and slightly below. If enabled, MPC is operational in all output modes except tapered
(OM[1,0] = 01) and binary. When OCFG = 00, MPC will not effect channels 3 and 4, the
line-out channels.
6.5.3
6.5.4
Noise-shaper bandwidth selection
Bit
R/W
RST
Name
2
R/W
0
NSBW
Description
1: Third order NS
0: Fourth order NS
AM mode enable
Bit
R/W
RST
Name
3
R/W
0
AME
Description
0: Normal DDX operation.
1: AM reduction mode DDX operation
STA335BWS features a DDX processing mode that minimizes the amount of noise
generated in frequency range of AM radio. This mode is intended for use when DDX is
operating in a device with an AM tuner active. The SNR of the DDX processing is reduced to
~83 dB in this mode, which is still greater than the SNR of AM radio.
6.5.5
6.5.6
34/68
PWM speed mode
Bit
R/W
RST
Name
4
R/W
0
PWMS
Description
0: Normal speed (384 kHz) all channels
1: Odd speed (341.3 kHz) all channels
Distortion compensation variable enable
Bit
R/W
RST
Name
5
R/W
0
DCCV
Description
0: Uses preset DC coefficient
1: Uses DCC coefficient
STA335BWS
6.5.7
Register description
Zero-crossing volume enable
Bit
R/W
RST
Name
6
R/W
1
ZCE
Description
1: Volume adjustments only occur at digital
zero-crossings
0: Volume adjustments occur immediately
The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital
zero-crossings no clicks are audible.
6.5.8
6.6
6.6.1
Soft volume update enable
Bit
R/W
RST
Name
7
R/W
1
SVE
Description
1: Volume adjustments ramp according to SVR settings
0: Volume adjustments occur immediately
Configuration register F (addr 0x05)
D7
D6
D5
D4
D3
D2
D1
D0
EAPD
PWDN
ECLE
LDTE
BCLE
IDE
OCFG1
OCFG0
0
1
0
1
1
1
0
0
Output configuration
Bit
R/W
RST
Name
0
R/W
0
OCFG0
1
R/W
0
OCFG1
Description
Selects the output configuration
Table 16.
OCFG[1:0]
Output configuration engine selection
Output configuration
Config pin
00
2 channel (full-bridge) power, 2 channel data-out:
1A/1B → 1A/1B
2A/2B → 2A/2B
LineOut1 → 3A/3B
LineOut2 → 4A/4B
Line Out Configuration determined by LOC register
0
01
2 (half-bridge), 1 (full-bridge) on-board power:
1A → 1A, Binary 0 °
2A → 1B, Binary 90°
3A/3B → 2A/2B, Binary 45°
1A/B → 3A/B, Binary 0°
2A/B → 4A/B, Binary 90°
0
35/68
Register description
STA335BWS
Table 16.
Output configuration engine selection (continued)
OCFG[1:0]
Output configuration
Config pin
10
2 channel (full-bridge) power, 1 channel DDX:
1A/1B → 1A/1B
2A/2B → 2A/2B
3A/3B → 3A/3B
EAPDEXT and TWARNEXT Active
0
11
1 channel mono-parallel:
3A → 1A/1B, w/ C3BO 45°
3B → 2A/2B, w/ C3BO 45°
1A/1B → 3A/3B
2A/2B → 4A/4B
1
Note:
To the left of the arrow is the processing channel. When using channel output mapping, any
of the three processing channel outputs can be used for any of the three inputs.
Figure 9.
OCFG = 00 (default value)
Half
Bridge
OUT1A
Channel 1
Half
Bridge
Half
Bridge
Half
Bridge
Half
Bridge
Channel 1
OUT1A
OUT1B
Half
Bridge
OUT2A
Channel 2
OUT1B
Channel 2
Half
Bridge
OUT2B
OUT3A
OUT3B
LineOut 1
LPF
OUT4A
OUT4B
36/68
Figure 10. OCFG = 01
LineOut 2
LPF
Half
Bridge
OUT2A
Channel 3
OUT2B
STA335BWS
Register description
Figure 11. OCFG = 10
Half
Bridge
OCFG = 11
OUT1A
OUT1A
Half
Bridge
Channel 1
Half
Bridge
Half
Bridge
OUT1B
OUT1B
Channel 3
Half
Bridge
Half
Bridge
OUT2A
Half
Bridge
Channel 2
Half
Bridge
OUT2B
OUT3A
OUT3B
OUT2A
OUT2B
OUT3A
Power
Device
OUT3B
Channel 3
Channel 1
EAPD
OUT4A
OUT4B
Channel 2
STA335BWS can be configured to support different output configurations. For each PWM
output channel a PWM slot is defined. The PWM slot always has a time duration of 1/(8 * Fs)
seconds. The PWM slot defines the maximum extension for PWM rising and falling edges,
that is, rising edge as far as the falling edge cannot range outside PWM slot boundaries.
Figure 12. STA335BWS output mapping scheme
DDX 1A
OUT1A
OUT1A
DDX 1B
DDX 2A
DDX™
m odulator
OUT1B
DDX 2B
DDX 3A
OUT2A
OUT1B
Power
Bridge
OUT2A
DDX 3B
DDX 4A
OUT2B
OUT2B
DDX 4B
REM AP
OUT3A
OUT3B
OUT4A
OUT4B
37/68
Register description
STA335BWS
For each configuration the PWM from the digital driver are mapped in different way to the
power stage:
2.0 channels, two full bridges (OCFG = 00):
"
DDX1A ' OUT1A
"
DDX1B ' OUT1B
"
DDX2A ' OUT2A
"
DDX2B ' OUT2B
"
DDX3A ' OUT3A
"
DDX3B ' OUT3B
"
DDX4A ' OUT4A
"
DDX4B ' OUT4B
"
DDX1A/1B configured as ternary
"
DDX2A/2B configured as ternary
"
DDX3A/3B configured as line-out ternary
"
DDX4A/4B configured as line-out ternary
On channel 3 line out (LOC bits = 00) the same data as channel 1 processing are sent. On
channel 4 line out (LOC bits = 00) the same data as channel 2 processing are sent. In this
configuration, no volume control or EQ have effect on channel 3 and 4.
In this configuration the PWM slot phase is the following as shown in the next figures.
Figure 13. 2.0 channels (OCFG = 00) PWM slots
OUT1A
OUT1B
OUT2A
OUT2B
OUT3A
OUT3B
OUT4A
OUT4B
38/68
STA335BWS
Register description
2.1 channels, two half bridges + one full bridge (OCFG = 01):
"
DDX1A ' OUT1A
"
DDX2A ' OUT1B
"
DDX3A ' OUT2A
"
DDX3B ' OUT2B
"
DDX1A ' OUT3A
"
DDX1B ' OUT3B
"
DDX2A ' OUT4A
"
DDX2B ' OUT4B
"
DDX1A/1B configured as binary
"
DDX2A/2B configured as binary
"
DDX3A/3B configured as binary
"
DDX4A/4B is not used
In this configuration, channel 3 has full control (for example, on volume and EQ). On
OUT3/OUT4 channels the channel 1 and channel 2 PWM are replicated.
In this configuration the PWM slot phase is the following as shown in the next figures:
Figure 14. 2.1 channels (OCFG = 01) PWM slots
OUT1A
OUT1B
OUT2A
OUT2B
OUT3A
OUT3B
OUT4A
OUT4B
39/68
Register description
STA335BWS
2.1 channels, two fullbridge + one external full bridge (OCFG = 10):
"
DDX1A ' OUT1A
"
DDX1B ' OUT1B
"
DDX2A ' OUT2A
"
DDX2B ' OUT2B
"
DDX3A ' OUT3A
"
DDX3B ' OUT3B
"
EAPD ' OUT4A
"
TWARN OUT4B
"
DDX1A/1B configured as ternary
"
DDX2A/2B configured as ternary
"
DDX3A/3B configured as ternary
"
DDX4A/4B is not used
In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT4 channel the
external bridge control signals are muxed.
In this configuration the PWM slot phase is the following as shown in the next figures:
Figure 15. 2.1 channels (OCFG = 10) PWM slots
OUT1A
OUT1B
OUT2A
OUT2B
OUT3A
OUT3B
6.6.2
Invalid input detect mute enable
Bit
R/W
RST
Name
2
R/W
1
IDE
Description
Setting of 1 enables the automatic invalid input
detect mute
Setting the IDE bit enables this function, which looks at the input I2S data and will
automatically mute if the signals are perceived as invalid.
40/68
STA335BWS
6.6.3
Register description
Binary output mode clock loss detection
Bit
R/W
RST
Name
3
R/W
1
BCLE
Description
Binary output mode clock loss detection enable
Detects loss of input MCLK in binary mode and will output 50% duty cycle.
6.6.4
LRCK double trigger protection
Bit
R/W
RST
Name
4
R/W
1
LDTE
Description
LRCLK double trigger protection enable
Actively prevents double trigger of LRCLK.
6.6.5
Auto EAPD on clock loss
Bit
R/W
RST
Name
5
R/W
0
ECLE
Description
Auto EAPD on clock loss
When active, issues a power device power down signal (EAPD) on clock loss detection.
6.6.6
IC power down
Bit
R/W
RST
Name
7
R/W
1
PWDN
Description
0: IC power down low-power condition
1: IC normal operation
The PWDN register is used to place the IC in a low-power state. When PWDN is written
as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted
to power down the power-stage, then the master clock to all internal hardware expect the
I2C block is gated. This places the IC in a very low power consumption state.
6.6.7
External amplifier power down
Bit
R/W
RST
Name
7
R/W
0
EAPD
Description
0: External power stage power down active
1: Normal operation
The EAPD register directly disables/enables the internal power circuitry.
When EAPD = 0, the internal power section is placed on a low-power state (disabled). This
register also controls the DDX4B/EAPD output pin when OCFG = 10.
41/68
Register description
STA335BWS
6.7
Volume control registers (addr 0x06 to 0x0A)
6.7.1
Mute/line output configuration register
D7
D6
LOC1
LOC0
0
0
D5
D4
Reserved
LOC[1:0]
D3
D2
D1
D0
C3M
C2M
C1M
MMUTE
0
0
0
0
Line output configuration
00
Line output fixed - no volume, no EQ
01
Line output variable - CH3 volume effects line output, no EQ
10
Line output variable with EQ - CH3 volume effects line output
Line output is only active when OCFG = 00. In this case LOC determines the line output
configuration. The source of the line output is always the channel 1 and 2 inputs.
6.7.2
6.7.3
6.7.4
42/68
Master volume register
D7
D6
D5
D4
D3
D2
D1
D0
MV7
MV6
MV5
MV4
MV3
MV2
MV1
MV0
1
1
1
1
1
1
1
1
Channel 1 volume
D7
D6
D5
D4
D3
D2
D1
D0
C1V7
C1V6
C1V5
C1V4
C1V3
C1V2
C1V1
C1V0
0
1
1
0
0
0
0
0
Channel 2 volume
D7
D6
D5
D4
D3
D2
D1
D0
C2V7
C2V6
C2V5
C2V4
C2V3
C2V2
C2V1
C2V0
0
1
1
0
0
0
0
0
STA335BWS
6.7.5
Register description
Channel 3 and line-output volume
D7
D6
D5
D4
D3
D2
D1
D0
C3V7
C3V6
C3V5
C3V4
C3V3
C3V2
C3V1
C3V0
0
1
1
0
0
0
0
0
The Volume structure of the STA335BWS consists of individual volume registers for each
channel and a master volume register that provides an offset to each channels volume
setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB
to -80 dB.
As an example if C3V = 0x00 or +48 dB and MV = 0x18 or -12 dB, then the total gain for
channel 3 = +36 dB.
The Master Mute when set to 1 mutes all channels at once, whereas the individual channel
mutes (CxM) mutes only that channel. Both the master mute and the channel mutes provide
a “soft” mute with the volume ramping down to mute in 4096 samples from the maximum
volume setting at the internal processing rate (~96 kHz).
A “hard mute” can be obtained by commanding a value of all 1’s (255) to any channel
volume register or the master volume register. When volume offsets are provided via the
master volume register any channel that whose total volume is less than -80 dB is muted.
All changes in volume take place at zero-crossings when ZCE = 1 (configuration register F)
on a per channel basis as this creates the smoothest possible volume transitions. When
ZCE = 0, volume updates occur immediately.
Table 17.
Master volume offset as a function of MV[7:0]
MV[7:0]
Volume offset from channel value
00000000 (0x00)
0 dB
00000001 (0x01)
-0.5 dB
00000010 (0x02)
-1 dB
…
…
01001100 (0x4C)
-38 dB
…
…
11111110 (0xFE)
-127.5 dB
11111111 (0xFF)
Hard master mute
Table 18.
Channel volume as a function of CxV[7:0]
CxV[7:0]
Volume
00000000 (0x00)
+48 dB
00000001 (0x01)
+47.5 dB
00000010 (0x02)
+47 dB
…
…
01011111 (0x5F)
+0.5 dB
01100000 (0x60)
0 dB
01100001 (0x61)
-0.5 dB
43/68
Register description
Table 18.
STA335BWS
Channel volume as a function of CxV[7:0] (continued)
CxV[7:0]
Volume
…
…
11010111 (0xD7)
-59.5 dB
11011000 (0xD8)
-60 dB
11011001 (0xD9)
-61 dB
11011010 (0xDA)
-62 dB
…
…
11101100 (0xEC)
-80 dB
11101101 (0xED)
Hard channel mute
…
…
11111111 (0xFF)
Hard channel mute
6.8
Auto mode registers (addr 0x0B and 0x0C)
6.8.1
Automode register 1 (address 0x0B)
AMGC[1:0], in conjunction with AMGC[3:2] defined in register 0x31, defines anti-clipping
and DRC presets. Using AMGC[3:0] bits, attack and release thresholds and rates are
automatically configured to properly fit application specific configuration.
D7
D6
Reserved
Table 19.
D5
D4
AMGC1
AMGC2
0
0
D3
44/68
D1
D0
Reserved
AutoMode gain compression/limiters selection
AMGC[1:0]
6.8.2
D2
Mode
00
User programmable GC
01
AC no clipping 2.1
10
AC limited clipping (10%) 2.1
11
DRC nighttime listening mode 2.1
AutoMode register 2 (address 0x0C)
D7
D6
D5
D4
D3
D2
D1
D0
XO3
XO2
XO1
XO0
AMAM2
AMAM1
AMAM0
AMAME
0
0
0
0
0
0
0
0
STA335BWS
6.8.3
Register description
AM interference frequency switching
Bit
R/W
RST
Name
Description
0
R/W
0
AMAME
AutoMode AM Enable
0: Switching frequency determined by PWMS setting
1: Switching frequency determined by AMAM settings
Table 20.
6.8.4
AutoMode AM switching frequency selection
AMAM[2:0]
48 kHz/96 kHz Input Fs
44.1 kHz/88.2 kHz Input Fs
000
0.535 MHz - 0.720 MHz
0.535 MHz - 0.670 MHz
001
0.721 MHz - 0.900 MHz
0.671 MHz - 0.800 MHz
010
0.901 MHz - 1.100 MHz
0.801 MHz - 1.000 MHz
011
1.101 MHz - 1.300 MHz
1.001 MHz - 1.180 MHz
100
1.301 MHz - 1.480 MHz
1.181 MHz - 1.340 MHz
101
1.481 MHz - 1.600 MHz
1.341 MHz - 1.500 MHz
110
1.601 MHz - 1.700 MHz
1.501 MHz - 1.700 MHz
Bass management crossover
Bit
R/W
RST
Name
4
R/W
0
XO0
5
R/W
0
XO1
6
R/W
0
XO2
7
R/W
0
XO3
Table 21.
Description
Selects the bass-management crossover frequency.
A 1st-order hi-pass filter (channels 1 and 2) or a
2nd-order lo-pass filter (channel 3) at the selected
frequency is performed.
Bass management crossover frequency
XO[3:0]
Crossover frequency
0000
User-Defined
0001
80 Hz
0010
100 Hz
0011
120 Hz
0100
140 Hz
0101
160 Hz
0110
180 Hz
0111
200 Hz
1000
220 Hz
1001
240 Hz
1010
260 Hz
1011
280 Hz
45/68
Register description
Table 21.
STA335BWS
Bass management crossover frequency (continued)
XO[3:0]
6.9
6.9.1
Crossover frequency
1100
300 Hz
1101
320 Hz
1110
340 Hz
1111
360 Hz
Channel configuration registers (addr 0x0E to 0x10)
D7
D6
D5
D4
D3
D2
D1
D0
C1OM1
C1OM0
C1LS1
C1LS0
C1BO
C1VPB
C1EQBP
C1TCB
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
C2OM1
C2OM0
C2LS1
C2LS0
C2BO
C2VPB
C2EQBP
C2TCB
0
1
0
0
0
0
0
0
D1
D7
D6
D5
D4
D3
D2
C3OM1
C3OM0
C3LS1
C3LS0
C3BO
C3VPB
1
0
0
0
0
0
D0
Reserved
Tone control bypass
Tone control (bass/treble) can be bypassed on a per channel basis for channels 1 and 2.
CxTCB:
0: Perform tone control on channel X (normal operation)
1: Bypass tone control on channel X
6.9.2
EQ bypass
EQ control can be bypassed on a per channel basis for channels 1 and 2. If EQ control is
bypassed on a given channel the prescale and all filters (high-pass, biquads, de-emphasis,
bass, treble in any combination) are bypassed for that channel.
CxEQBP:
0: Perform EQ on channel X - normal operation
1: Bypass EQ on channel X
46/68
STA335BWS
6.9.3
Register description
Volume bypass
Each channel contains an individual channel volume bypass. If a particular channel has
volume bypassed via the CxVBP = 1 register then only the channel volume setting for that
particular channel affects the volume setting, the master volume setting will not affect that
channel.
6.9.4
Binary output enable registers
Each individual channel output can be set to output a binary PWM stream. In this mode
output A of a channel is considered the positive output and output B is negative inverse.
CxBO:
0: DDX tri-state output - normal operation
1: Binary output
6.9.5
Limiter select
Limiter selection can be made on a per-channel basis according to the channel limiter select
bits.
.
Table 22.
Channel limiter mapping as a function of CxLS bits
CxLS[1,0]
6.9.6
Channel limiter mapping
00
Channel has limiting disabled
01
Channel is mapped to limiter #1
10
Channel is mapped to limiter #2
Output mapping
Output mapping can be performed on a per channel basis according to the CxOM channel
output mapping bits. Each input into the output configuration engine can receive data from
any of the three processing channel outputs.
.
Table 23.
Channel output mapping as a function of CxOM bits
CxOM[1,0]
Channel x output source from
00
Channel1
01
Channel 2
10
Channel 3
47/68
Register description
STA335BWS
6.10
Tone control register (addr 0x11)
6.10.1
Tone control
D7
D6
D5
D4
D3
D2
D1
D0
TTC3
TTC2
TTC1
TTC0
BTC3
BTC2
BTC1
BTC0
0
1
1
1
0
1
1
1
Table 24.
Tone control boost/cut as a function of BTC and TTC bits
BTC[3:0]/TTC[3:0]
Boost/Cut
0000
-12 dB
0001
-12 dB
…
…
0111
-4 dB
0110
-2 dB
0111
0 dB
1000
+2 dB
1001
+4 dB
…
…
1101
+12 dB
1110
+12 dB
1111
+12 dB
6.11
Dynamics control registers (addr 0x12 to 0x15)
6.11.1
Limiter 1 attack/release rate
6.11.2
6.11.3
48/68
D7
D6
D5
D4
D3
D2
D1
D0
L1A3
L1A2
L1A1
L1A0
L1R3
L1R2
L1R1
L1R0
0
1
1
0
1
0
1
0
Limiter 1 attack/release threshold
D7
D6
D5
D4
D3
D2
D1
D0
L1AT3
L1AT2
L1AT1
L1AT0
L1RT3
L1RT2
L1RT1
L1RT0
0
1
1
0
1
0
0
1
Limiter 2 attack/release rate
D7
D6
D5
D4
D3
D2
D1
D0
L2A3
L2A2
L2A1
L2A0
L2R3
L2R2
L2R1
L2R0
0
1
1
0
1
0
1
0
STA335BWS
6.11.4
Register description
Limiter 2 attack/release threshold
D7
D6
D5
D4
D3
D2
D1
D0
L2AT3
L2AT2
L2AT1
L2AT0
L2RT3
L2RT2
L2RT1
L2RT0
0
1
1
0
1
0
0
1
The STA335BWS includes two independent limiter blocks. The purpose of the limiters is to
automatically reduce the dynamic range of a recording to prevent the outputs from clipping
in anti-clipping mode or to actively reduce the dynamic range for a better listening
environment such as a night-time listening mode which is often needed for DVDs. The two
modes are selected via the DRC bit in Configuration Register F, bit 0 address 0x05. Each
channel can be mapped to either limiter or not mapped, meaning that channel will clip when
0dBFS is exceeded. Each limiter looks at the present value of each channel that is mapped
to it, selects the maximum absolute value of all these channels, performs the limiting
algorithm on that value, and then if needed adjusts the gain of the mapped channels in
unison.
The limiter attack thresholds are determined by the LxAT registers. It is recommended in
anti-clipping mode to set this to 0dBFS, which corresponds to the maximum unclipped
output power of a DDX amplifier. Since gain can be added digitally within STA335BWS it is
possible to exceed 0dBFS or any other LxAT setting, when this occurs, the limiter, when
active, automatically starts reducing the gain. The rate at which the gain is reduced when
the attack threshold is exceeded is dependent upon the attack rate register setting for that
limiter. The gain reduction occurs on a peak-detect algorithm.
The release of limiter, when the gain is again increased, is dependent on a RMS-detect
algorithm. The output of the volume/limiter block is passed through a RMS filter. The output
of this filter is compared to the release threshold, determined by the Release Threshold
register. When the RMS filter output falls below the release threshold, the gain is again
increased at a rate dependent upon the Release Rate register. The gain can never be
increased past it's set value and therefore the release only occurs if the limiter has already
reduced the gain. The release threshold value can be used to set what is effectively a
minimum dynamic range, this is helpful as over-limiting can reduce the dynamic range to
virtually zero and cause program material to sound “lifeless”.
In AC mode, the attack and release thresholds are set relative to full-scale. In DRC mode,
the attack threshold is set relative to the maximum volume setting of the channels mapped
to that limiter and the release threshold is set relative to the maximum volume setting plus
the attack threshold.
49/68
Register description
STA335BWS
Figure 16. Basic limiter and volume flow diagram
Table 25.
50/68
Limiter attack rate as a
function of LxA bits
LxA[3:0]
Attack rate dB/ms
0000
3.1584
Fast
Table 26.
Limiter release rate as a
function of LxR bits
LxR[3:0]
Release rate dB/ms
0000
0.5116
0001
0.1370
0001
2.7072
0010
2.2560
0010
0.0744
0011
1.8048
0011
0.0499
0100
1.3536
0100
0.0360
0101
0.9024
0101
0.0299
0110
0.4512
0110
0.0264
0111
0.2256
0111
0.0208
1000
0.1504
1000
0.0198
1001
0.1123
1001
0.0172
1010
0.0902
1010
0.0147
1011
0.0752
1011
0.0137
1100
0.0645
1100
0.0134
1101
0.0564
1101
0.0117
1110
0.0501
1110
0.0110
1111
0.0451
1111
0.0104
Slow
Fast
Slow
STA335BWS
Register description
Anti-clipping mode
Table 27.
Limiter attack threshold
as a function of LxAT bits
(AC-mode)
Table 28.
Limiter release threshold
as a function of LxRT
bits (AC-mode)
LxAT[3:0]
AC
(dB relative to FS)
LxRT[3:0]
AC
(dB relative to FS)
0000
-12
0000
-∞
0001
-10
0001
-29 dB
0010
-8
0010
-20 dB
0011
-6
0011
-16 dB
0100
-4
0100
-14 dB
0101
-2
0101
-12 dB
0110
0
0110
-10 dB
0111
+2
0111
-8 dB
1000
+3
1000
-7 dB
1001
+4
1001
-6 dB
1010
+5
1010
-5 dB
1011
+6
1011
-4 dB
1100
+7
1100
-3 dB
1101
+8
1101
-2 dB
1110
+9
1110
-1 dB
1111
+10
1111
-0 dB
51/68
Register description
STA335BWS
Dynamic range compression mode
Table 29.
Limiter attack threshold
as a function of LxAT bits
(DRC-Mode)
Table 30.
Limiter release threshold
as a as a function of
LxRT bits (DRC-Mode)
LxAT[3:0]
DRC
(dB relative to Volume)
LxRT[3:0]
DRC
(db relative to Volume + LxAT)
0000
-31
0000
-∞
0001
-29
0001
-38 dB
0010
-27
0010
-36 dB
0011
-25
0011
-33 dB
0100
-23
0100
-31 dB
0101
-21
0101
-30 dB
0110
-19
0110
-28 dB
0111
-17
0111
-26 dB
1000
-16
1000
-24 dB
1001
-15
1001
-22 dB
1010
-14
1010
-20 dB
1011
-13
1011
-18 dB
1100
-12
1100
-15 dB
1101
-10
1101
-12 dB
1110
-7
1110
-9 dB
1111
-4
1111
-6 dB
6.12
User-defined coefficient control registers (addr 0x16 to 0x26)
6.12.1
Coefficient address register
D7
D6
Reserved
6.12.2
52/68
D5
D4
D3
D2
D1
D0
CFA5
CFA4
CFA3
CFA2
CFA1
CFA0
0
0
0
0
0
0
Coefficient b1 data register bits 23:16
D7
D6
D5
D4
D3
D2
D1
D0
C1B23
C1B22
C1B21
C1B20
C1B19
C1B18
C1B17
C1B16
0
0
0
0
0
0
0
0
STA335BWS
6.12.3
6.12.4
6.12.5
6.12.6
6.12.7
6.12.8
6.12.9
Register description
Coefficient b1 data register bits 15:8
D7
D6
D5
D4
D3
D2
D1
D0
C1B15
C1B14
C1B13
C1B12
C1B11
C1B10
C1B9
C1B8
0
0
0
0
0
0
0
0
Coefficient b1 data register bits 7:0
D7
D6
D5
D4
D3
D2
D1
D0
C1B7
C1B6
C1B5
C1B4
C1B3
C1B2
C1B1
C1B0
0
0
0
0
0
0
0
0
Coefficient b2 data register bits 23:16
D7
D6
D5
D4
D3
D2
D1
D0
C2B23
C2B22
C2B21
C2B20
C2B19
C2B18
C2B17
C2B16
0
0
0
0
0
0
0
0
Coefficient b2 data register bits 15:8
D7
D6
D5
D4
D3
D2
D1
D0
C2B15
C2B14
C2B13
C2B12
C2B11
C2B10
C2B9
C2B8
0
0
0
0
0
0
0
0
Coefficient b2 data register bits 7:0
D7
D6
D5
D4
D3
D2
D1
D0
C2B7
C2B6
C2B5
C2B4
C2B3
C2B2
C2B1
C2B0
0
0
0
0
0
0
0
0
Coefficient a1 data register bits 23:16
D7
D6
D5
D4
D3
D2
D1
D0
C1B23
C1B22
C1B21
C1B20
C1B19
C1B18
C1B17
C1B16
0
0
0
0
0
0
0
0
Coefficient a1 data register bits 15:8
D7
D6
D5
D4
D3
D2
D1
D0
C3B15
C3B14
C3B13
C3B12
C3B11
C3B10
C3B9
C3B8
0
0
0
0
0
0
0
0
53/68
Register description
6.12.10
6.12.11
6.12.12
6.12.13
6.12.14
6.12.15
6.12.16
54/68
STA335BWS
Coefficient a1 data register bits 7:0
D7
D6
D5
D4
D3
D2
D1
D0
C3B7
C3B6
C3B5
C3B4
C3B3
C3B2
C3B1
C3B0
0
0
0
0
0
0
0
0
Coefficient a2 data register bits 23:16
D7
D6
D5
D4
D3
D2
D1
D0
C4B23
C4B22
C4B21
C4B20
C4B19
C4B18
C4B17
C4B16
0
0
0
0
0
0
0
0
Coefficient a2 data register bits 15:8
D7
D6
D5
D4
D3
D2
D1
D0
C4B15
C4B14
C4B13
C4B12
C4B11
C4B10
C4B9
C4B8
0
0
0
0
0
0
0
0
Coefficient a2 data register bits 7:0
D7
D6
D5
D4
D3
D2
D1
D0
C4B7
C4B6
C4B5
C4B4
C4B3
C4B2
C4B1
C4B0
0
0
0
0
0
0
0
0
Coefficient b0 data register bits 23:16
D7
D6
D5
D4
D3
D2
D1
D0
C5B23
C5B22
C5B21
C5B20
C5B19
C5B18
C5B17
C5B16
0
0
0
0
0
0
0
0
Coefficient b0 data register bits 15:8
D7
D6
D5
D4
D3
D2
D1
D0
C5B15
C5B14
C5B13
C5B12
C5B11
C5B10
C5B9
C5B8
0
0
0
0
0
0
0
0
Coefficient b0 data register bits 7:0
D7
D6
D5
D4
D3
D2
D1
D0
C5B7
C5B6
C5B5
C5B4
C5B3
C5B2
C5B1
C5B0
0
0
0
0
0
0
0
0
STA335BWS
6.12.17
Register description
Coefficient write/read control register
D7
D6
D5
D4
Reserved
D3
D2
D1
D0
RA
R1
WA
W1
0
0
0
0
Coefficients for user-defined EQ, Mixing, Scaling, and Bass Management are handled
internally in the STA335BWS via RAM. Access to this RAM is available to the user via an
I2C register interface. A collection of I2C registers are dedicated to this function. One
contains a coefficient base address, five sets of three store the values of the 24-bit
coefficients to be written or that were read, and one contains bits used to control the
write/read of the coefficient(s) to/from RAM.
Three different RAM banks are embedded in STA335BWS. The 3 banks are managed in
paging mode using EQCFG register bits. They can be used to store different EQ settings.
For speaker frequency compensation, a sampling frequency independent EQ must be
implemented. Computing 3 different coefficients set for 32 kHz, 44.1kHz, 48 kHz and
downloading them in the 3 RAM banks, it is possible to select the suitable RAM block
depending from the incoming frequency with a simple I2C write operation on register 0x31.
For example, in case of different input sources (different sampling rates), the 3 different set
of coefficients can be downloaded once at the start up, and during the normal play it is
possible to switch among the 3 RAM blocks allowing a faster operation, without any
additional download from the microcontroller.
To write the coefficients in a particular RAM bank, this bank must be selected first writing bit
0 and bit 1 in register 0x31. Then the below write procedure can be used.
Note that as soon as a RAM bank is selected, the EQ settings will be automatically switched
to the coefficients stored in the active RAM block.
Note:
The read and write operation on RAM coefficients works only if LRCKI (pin 29) is switching.
Reading a coefficient from RAM
1.
Select the RAM block with register 0x31 bit1, bit0.
2.
Write 6-bits of address to I2C register 0x16.
3.
Write 1 to R1 bit in I2C address 0x26.
4.
Read top 8-bits of coefficient in I2C address 0x17.
5.
Read middle 8-bits of coefficient in I2C address 0x18.
6.
Read bottom 8-bits of coefficient in I2C address 0x19.
Reading a set of coefficients from RAM
1.
Select the RAM block with register 0x31 bit1, bit0.
2.
Write 6-bits of address to I2C register 0x16.
3.
Write 1 to RA bit in I2C address 0x26.
4.
Read top 8-bits of coefficient in I2C address 0x17.
5.
Read middle 8-bits of coefficient in I2C address 0x18.
6.
Read bottom 8-bits of coefficient in I2C address 0x19.
7.
Read top 8-bits of coefficient b2 in I2C address 0x1A.
8.
Read middle 8-bits of coefficient b2 in I2C address 0x1B.
55/68
Register description
9.
STA335BWS
Read bottom 8-bits of coefficient b2 in I2C address 0x1C.
10. Read top 8-bits of coefficient a1 in I2C address 0x1D.
11. Read middle 8-bits of coefficient a1 in I2C address 0x1E.
12. Read bottom 8-bits of coefficient a1 in I2C address 0x1F.
13. Read top 8-bits of coefficient a2 in I2C address 0x20.
14. Read middle 8-bits of coefficient a2 in I2C address 0x21.
15. Read bottom 8-bits of coefficient a2 in I2C address 0x22.
16. Read top 8-bits of coefficient b0 in I2C address 0x23.
17. Read middle 8-bits of coefficient b0 in I2C address 0x24.
18. Read bottom 8-bits of coefficient b0 in I2C address 0x25.
Writing a single coefficient to RAM
1.
Select the RAM block with register 0x31 bit1, bit0.
2.
Write 6-bits of address to I2C register 0x16.
3.
Write top 8-bits of coefficient in I2C address 0x17.
4.
Write middle 8-bits of coefficient in I2C address 0x18.
5.
Write bottom 8-bits of coefficient in I2C address 0x19.
6.
Write 1 to W1 bit in I2C address 0x26.
Writing a set of coefficients to RAM
1.
Select the RAM block with register 0x31 bit1, bit0.
2.
Write 6-bits of starting address to I2C register 0x16.
3.
Write top 8-bits of coefficient b1 in I2C address 0x17.
4.
Write middle 8-bits of coefficient b1 in I2C address 0x18.
5.
Write bottom 8-bits of coefficient b1 in I2C address 0x19.
6.
Write top 8-bits of coefficient b2 in I2C address 0x1A.
7.
Write middle 8-bits of coefficient b2 in I2C address 0x1B.
8.
Write bottom 8-bits of coefficient b2 in I2C address 0x1C.
9.
Write top 8-bits of coefficient a1 in I2C address 0x1D.
10. Write middle 8-bits of coefficient a1 in I2C address 0x1E.
11. Write bottom 8-bits of coefficient a1 in I2C address 0x1F.
12. Write top 8-bits of coefficient a2 in I2C address 0x20.
13. Write middle 8-bits of coefficient a2 in I2C address 0x21.
14. Write bottom 8-bits of coefficient a2 in I2C address 0x22.
15. Write top 8-bits of coefficient b0 in I2C address 0x23.
16. Write middle 8-bits of coefficient b0 in I2C address 0x24.
17. Write bottom 8-bits of coefficient b0 in I2C address 0x25.
18. Write 1 to WA bit in I2C address 0x26.
The mechanism for writing a set of coefficients to RAM provides a method of updating the
five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible
unpleasant acoustic side-effects. When using this technique, the 6-bit address specifies the
address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the
56/68
STA335BWS
Register description
STA335BWS generates the RAM addresses as offsets from this base value to write the
complete set of coefficient data.
6.12.18
User-defined EQ
The STA335BWS provides the ability to specify four EQ filters (biquads) per each of the two
input channels. The biquads use the following equation:
Y[n] = 2(b0/2)X[n] + 2(b1/2)X[n-1] + b2X[n-2] - 2(a1/2)Y[n-1] - a2Y[n-2]
= b0X[n] + b1X[n-1] + b2X[n-2] - a1Y[n-1] - a2Y[n-2]
where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed
fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF
(0.9999998808).
Coefficients stored in the user-defined coefficient RAM are referenced as follows:
CxHy0 = b1/2
CxHy1 = b2
CxHy2 = -a1/2
CxHy3 = -a2
CxHy4 = b0/2
where x represents the channel and the y the biquad number. For example C2H41 is the
b2 coefficient in the fourth biquad for channel 2.
Additionally, the STA335BWS allows specification of a high-pass filter (processing channels
1 and 2) and a lo-pass filter (processing channel 3) to be used for bass-management
crossover when the XO setting is 000 (user-defined). Both of these filters when defined by
the user (rather than using the preset crossover filters) are second order filters that use the
biquad equation noted above. They are loaded into the C12H0-4 and C3Hy0-4 areas of
RAM noted in Table 31.
By default, all user-defined filters are pass-through where all coefficients are set to 0, except
the b0/2 coefficient which is set to 0x400000 (representing 0.5)
6.12.19
Pre-scale
The STA335BWS provides a multiplication for each input channel for the purpose of scaling
the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed
fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor
for this multiply is loaded into RAM using the same I2C registers as the biquad coefficients
and the bass-management. All channels can use the channel 1 pre-scale factor by setting
the Biquad link bit. By default, all pre-scale factors are set to 0x7FFFFF.
6.12.20
Post-scale
The STA335BWS provides one additional multiplication after the last interpolation stage and
the distortion compensation on each channel. This post-scaling is accomplished by using a
24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The
scale factor for this multiply is loaded into RAM using the same I2C registers as the biquad
coefficients and the bass-management. This post-scale factor can be used in conjunction
with an ADC equipped micro-controller to perform power-supply error correction. All
channels can use the channel 1 post-scale factor by setting the post-scale link bit. By
default, all post-scale factors are set to 0x7FFFFF. When line output is being used,
channel 3 post-scale affects both channels 3 and 4.
57/68
Register description
6.12.21
STA335BWS
Over-current post-scale
The STA335BWS provides a simple mechanism for reacting to over-current detection in the
power-block. When the OCWARN input is asserted, the over-current post-scale value is
used in place of the normal post-scale value to provide output attenuation on all channels.
The default setting provides 3 dB of output attenuation when OCWARN is asserted.
The amount of attenuation to be applied in this situation can be adjusted by modifying the
over-current post-scale value. As with the normal post-scale, this scaling value is a 24-bit
signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. By default,
the over-current post-scale factor is set to 0x5A9DF7. Once the over-current attenuation is
applied, it remains until the device is reset.
Table 31.
RAM block for biquads, mixing, scaling and bass management
Index (Decimal) Index (Hex)
Coefficient
Default
0
0x00
C1H10(b1/2)
0x000000
1
0x01
C1H11(b2)
0x000000
2
0x02
C1H12(a1/2)
0x000000
3
0x03
C1H13(a2)
0x000000
4
0x04
C1H14(b0/2)
0x400000
5
0x05
Channel 1, Biquad 2
C1H20
0x000000
…
…
…
…
…
19
0x13
Channel 1, Biquad 4
C1H44
0x400000
20
0x14
C2H10
0x000000
C2H11
0x000000
Channel 1, Biquad 1
Channel 2, Biquad 1
58/68
21
0x15
…
…
…
…
…
39
0x27
Channel 2, Biquad 4
C2H44
0x400000
40
0x28
C12H0(b1/2)
0x000000
41
0x29
C12H1(b2)
0x000000
42
0x2A
C12H2(a1/2)
0x000000
43
0x2B
C12H3(a2)
0x000000
44
0x2C
C12H4(b0/2)
0x400000
45
0x2D
C3H0(b1/2)
0x000000
46
0x2E
C3H1(b2)
0x000000
47
0x2F
C3H2(a1/2)
0x000000
48
0x30
C3H3(a2)
0x000000
49
0x31
C3H4(b0/2)
0x400000
50
0x32
Channel 1, Pre-Scale
C1PreS
0x7FFFFF
51
0x33
Channel 2, Pre-Scale
C2PreS
0x7FFFFF
52
0x34
Channel 1, Post-Scale
C1PstS
0x7FFFFF
53
0x35
Channel 2, Post-Scale
C2PstS
0x7FFFFF
Channel 1/2 - Biquad 5
for XO = 000
Hi-pass 2nd Order filter
for XO≠000
Channel 3 - Biquad
for XO = 000
Low-pass 2nd Order filter
for XO≠000
STA335BWS
Register description
Table 31.
RAM block for biquads, mixing, scaling and bass management
Index (Decimal) Index (Hex)
6.13
Coefficient
Default
54
0x36
Channel 3, Post-scale
C3PstS
0x7FFFFF
55
0x37
TWARN/OC - Limit
TWOCL
0x5A9DF7
56
0x38
Channel 1, Mix 1
C1MX1
0x7FFFFF
57
0x39
Channel 1, Mix 2
C1MX2
0x000000
58
0x3A
Channel 2, Mix 1
C2MX1
0x000000
59
0x3B
Channel 2, Mix 2
C2MX2
0x7FFFFF
60
0x3C
Channel 3, Mix 1
C3MX1
0x400000
61
0x3D
Channel 3, Mix 2
C3MX2
0x400000
62
0x3E
Unused
63
0x3F
Unused
Variable max power correction registers (addr 0x27 to 0x28)
MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is
used in place of the default coefficient when MPCV = 1.
6.14
D7
D6
D5
D4
D3
D2
D1
D0
MPCC15
MPCC14
MPCC13
MPCC12
MPCC11
MPCC10
MPCC9
MPCC8
0
0
0
1
1
0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
MPCC7
MPCC6
MPCC5
MPCC4
MPCC3
MPCC2
MPCC1
MPCC0
1
1
0
0
0
0
0
0
Variable distortion compensation registers (addr 0x29 to
0x2A)
DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient
is used in place of the default coefficient when DCCV = 1.
D7
D6
D5
D4
D3
D2
D1
D0
DCC15
DCC14
DCC13
DCC12
DCC11
DCC10
DCC9
DCC8
1
1
1
1
0
0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
DCC7
DCC6
DCC5
DCC4
DCC3
DCC2
DCC1
DCC0
0
0
1
1
0
0
1
1
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Register description
6.15
STA335BWS
Fault detect recovery constant registers (addr 0x2B to 0x2C)
FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the
TRISTATE output is immediately asserted low and held low for the time period specified by
this constant. A constant value of 0x0001 in this register is ~0.083 ms. The default value of
0x000C specifies ~0.1 ms.
6.16
D7
D6
D5
D4
D3
D2
D1
D0
FDRC15
FDRC14
FDRC13
FDRC12
FDRC11
FDRC10
FDRC9
FDRC8
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
FDRC7
FDRC6
FDRC5
FDRC4
FDRC3
FDRC2
FDRC1
FDRC0
0
0
0
0
1
1
0
0
Device status register (addr 0x2D)
D7
D6
D5
D4
D3
D2
D1
D0
PLLUL
FAULT
UVFAULT
OVFAULT
OCFAULT
OCWARN
TFAULT
TWARN
This read-only register provides fault and thermal-warning status information from the power
control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault
or warning detected on power bridge. The PLLUL = 1 means that the PLL is not locked.
60/68
"
PLLUL: 0 = PLL locked, 1 = PLL not locked.
"
FAULT: 0 = fault detected on power bridge, 1 = normal operation
"
UVFAULT: 0 = VCCxX internally detected < undervoltage threshold.
"
OVFAULT: 0 = VCCxX internally detected > overvoltage threshold.
"
OCFAULT: 0 = overcurrent fault detected
"
OCWARN: 0 = overcurrent warning.
"
TFAULT: 0 = thermal fault. Junction temperature over limit detection.
"
TWARN: 0 = thermal warning. The junction temperature is close to the fault condition.
STA335BWS
6.17
Register description
EQ coefficients and DRC configuration register (addr 0x31)
D7
D6
XOB
D5
Reserved
0
0
Table 32.
D4
D3
D2
D1
D0
AMGC[3]
AMGC[2]
reserved
SEL1
SEL0
0
0
0
0
0
0
SEL bitfield description
SEL[1,0]
Table 33.
EQ RAM bank selected
00/11
Bank 0 activated
01
Bank 1 activated
10
Bank 2 activated
AMGC bitfield description
AMGC[3,2]
Anti-clipping and DRC preset selected
00
DRC/Anti-clipping (default)
01
DRC/Anti-clipping
10/11
Reserved, do not use
AC0, AC1, AC2 settings are designed for loudspeaker protection function, limiting at the
minimum any audio artefact introduced by typical anti-clipping/DRC algorithms. More
detailed information can be retrieved in the “Configurable output power rate using
STA335BW” and “STA335BWS vs STA335BW” application notes.
Table 34.
AMGC bitfield description
AMGC[1:0]
Mode
00
AC0, stereo anti-clipping 0dB limiter
01
AC1, stereo anti-clipping +1.25dB limiter
10
AC2, stereo anti-clipping +2dB limiter
11
reserved do not use
Bit XOB can be used to bypass the crossover filters. Logic 1 means that the function is not
active. In this case, high pass crossover filter works as a pass through on the data path
(b0 = 1, all the other coefficients at logic 0) while the low pass filter is configured to have
zero signal on channel 3 data processing (all the coefficients are at logic 0).
61/68
Application
STA335BWS
7
Application
7.1
Application schematic and power supplies
Figure 17 shows a circuit diagram of a typical application for STA335BWS. Particular care
has to be given to the layout of the PCB, especially the power supplies. The 3.3 Ω resistors
on the digital supplies (VDD_DIG) have to be placed as close as possible to the device. This
helps to prevent unwanted oscillation on the digital portion of the device due to inductive
tracks of the PCB. This same rule is also be applied to all the decoupling capacitors in order
to limit any kind of spikes on all the supplies.
Figure 17. Application schematic
3R3
1
2
+
3
1000uF 35V
4
100nF
1uF 35V
OUT2B
5
6
7
8
100nF
OUT2A
9
100nF
VCC
OUT1B
10
11
12
1uF 35V
OUT1A
13
14
100nF
15
16
7.2
DDX3B
17
DDX3A
18
GND_SUB
SA
VDD_DIG
GND_DIG
TEST_MODE
SCL
VSS
SDA
VCC_REG
OUT2B
INT_LINE
RESET
GND2
SDI
VCC2
LRCKI
OUT2A
BICKI
OUT1B
VCC1
GND1
OUT1A
GND_REG
VDD
XTI
PLL_GND
FILTER_PLL
VDD_PLL
PWRDN
GND_DIG
CONFIG
VDD_DIG
DDX3B
TWARN/4A
DDX3A
EAPD/4B
3V3
36
100nF
35
34
SCL
33
SDA
INTL
32
3V3
GND_DIG
10K
31
RESET
30
DATA
29
LRCKI
28
BICKI
27
XTI
1nF
GND_DIG
BEAD
26
25
PLL_FILT
100nF
PLL_GND
BEAD
24
23
GND_DIG
3V3
PWDN
22
21
RESET
3R3
100nF
GND_DIG
3V3
20
TW
19
EAPD
PLL filter schematic
It is recommended to use the below scheme and values for the PLL loop filter to achieve the
best performances from the device in general application. Please be noted that the ground
of this filter scheme has to be connected to the ground of the PLL without any resistive path.
Concerning the component values, please take into account that the greater is the filter
bandwidth, the less is the lock time but the higher is the PLL output jitter.
62/68
STA335BWS
Application
Figure 18. PLL application scheme
FILTER_PLL
2K2
680pF
4.7nF
100pF
BEAD
GND_DIG
7.3
PLL_GND
Typical output configuration
Here after the typical output configuration used for BTL stereo mode. Please refer to the
application note for all the other possible output configuration recommended schematics.
Figure 19. Output configuration for stereo BTL mode
22uH
OUT1A
100nF
6.2
22
6.2
330pF
100nF
470nF
LEFT
470nF
RIGHT
100nF
100nF
OUT1B
22uH
22uH
OUT2A
100nF
6.2
22
6.2
330pF
100nF
100nF
100nF
OUT2B
22uH
63/68
Package thermal characteristics
8
STA335BWS
Package thermal characteristics
Using a triple-layer PCB the thermal resistance (junction to ambient) with a center copper
ground area of 3 x 3 cm2 and with 16 via holes (see Figure 20) is 24° C/W in natural air
convection.
The dissipated power within the device depends primarily on the supply voltage, load
impedance and output modulation level.
The max estimated dissipated power for the STA335BWS is:
2 x 20 W @ 8 Ω, 18 V
Pd max ~ 4 W
2 x 10 W + 1 x 20 W @ 4 Ω, 8 Ω, 18 V
Pd max < 5 W
Figure 20. Triple-layer PCB with copper ground area and 16 via holes
Figure 21 shows the power derating curves for the PowerSSO-36 package on a board with
two different sizes of copper layers.
Figure 21. PowerSSO-36 power derating curve
Pd (W)
8
7
Copper Area 3x3 cm
and via holes
6
5
STA335BWS
STA335BW
PowerSSO-36
PSSO36
4
3
Copper Area 2x2 cm
and via holes
2
1
0
0
20
40
60
80
100
Tamb ( °C)
64/68
120
140
160
STA335BWS
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 22. PowerSSO-36 (slug-up) mechanical data and package dimensions
DIM.
MIN.
2.15
2.15
0
0.18
0.23
10.10
A
A2
a1
b
c
D (1)
mm
TYP.
7.4
E (1)
e
e3
F
G
G1
H
h
k
L
M
N
O
Q
S
T
U
X
Y
MAX.
2.47
2.40
0.075
0.36
0.32
10.50
MIN.
0.084
0.084
0
0.007
0.009
0.398
7.6
0.291
0.5
8.5
2.3
inch
TYP.
MAX.
0.097
0.094
0.003
0.014
0.012
0.413
OUTLINE AND
MECHANICAL DATA
0.299
0.019
0.335
0.090
0.10
0.06
10.50
0.40
10.10
0.004
0.002
0.413
0.016
0.398
5˚
5˚
0.55
0.90
0.022
4.3
0.035
0.169
10˚
10˚
1.2
0.8
2.9
3.65
1.0
0.047
0.031
0.114
0.144
0.039
4.1
6.5
4.7
7.3
0.161
0.256
PowerSSO-36
(slug-down)
0.185
0.287
A
A2
(1) "D” and “E" do not include mold flash or protrusions Mold flash
or protrusions shall not exceed 0.15 mm per side(0.006”)
hx45û
Gauge plane 0.25
c
G
LEAD COPLANARITY
A
D
M
a1
stand-off
Y
k
e
T
L
H
E
X
O
S
Q
F
9
Package information
U
BOTTOM VIEW
B
0.1 M A B
b
e3
7587131 A
65/68
Trademarks and other acknowledgements
10
Trademarks and other acknowledgements
DDX is a registered trademark of Apogee Technology Inc.
Sound Terminal is a trademark of STMicroelectronics.
ECOPACK is a registered trademark of STMicroelectronics.
66/68
STA335BWS
STA335BWS
11
Revision history
Revision history
Table 35.
Document revision history
Date
Revision
18-Jan-2008
1
Changes
Initial release.
67/68
STA335BWS
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