STA330 2.0 digital audio processor with FFX digital modulator and analog and digital inputs Features ! Up to 96 dB dynamic range ! Sample rates from 8 kHz to 192 kHz ! FFX (digital modulation) class-D driver ! Digital supply voltage from 1.5 V to 3.6 V ! Analog supply voltage from 1.5 V to 3.6 V ! 18-bit audio processing and class-D FFX digital modulator ! 100-dB SNR analog to digital converter ! Digital volume control: – +36 dB to -105 dB in 0.5 dB steps – Software volume update VFQFPN52 ! Individual channel and master gain/attenuation ! Automatic invalid-input detect mute Table 1. ! 2-channel serial input/output data interface ! Digitally controlled pop-free operation Device summary Order code Package Packaging STA330 VFQFPN52 Tube STA33013TR VFQFPN52 Tape and reel December 2007 Rev 1 1/55 www.st.com 1 Contents STA330 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Connection diagrams and pin descriptions . . . . . . . . . . . . . . . . . . . . . . 5 3 2.1 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Maximum and recommended operating conditions . . . . . . . . . . . . . . . . . . 8 3.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Lock time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 ADC performance values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Digital processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 7 5.1 Signal processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 I2C interface disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 Volume control and gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 Configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Analog-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1 8 7.1.1 Digital anti-aliasing filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1.2 High-pass filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1.3 Programmable gain amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.2 Application scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.3 Configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Serial digital audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.1 2/55 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STA330 Contents 8.2 Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.3 Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.4 Serial formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.5 9 DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.4.2 I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.4.3 PCM/IF (non-delayed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.4.4 PCM/IF (delayed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SAI pass-through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.1 Data transition and change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.5 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.6 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.7 10 8.4.1 9.6.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.6.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.7.1 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.7.2 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.7.3 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.7.4 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.2 General registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 53 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3/55 Introduction 1 STA330 Introduction The STA330 is a digital stereo audio processor with analog and digital input. It includes an audio DSP and FFX, a ST proprietary high-efficiency class-D driver. In conjunction with a power device, the STA330 provides high-quality digital amplification. The STA330 contains an on-chip volume/gain control. The PWM amplifier achieves greater than 90% efficiency for longer battery life for portable systems. The STA330 I2CDIS pin disables the audio DSP functions to provide a direct conversion of the input signal into output power (the I2C interface is disabled). This conversion is done without the microcontroller. The STA330 is designed for low-power operation with extremely low-current consumption in standby mode. It is available in the package VFQFPN52, a very thin (1.2 mm thick) package that can be used for small portable applications. VCC1 VCC2 GND1 GND2 VCC33 GND33 VDDIO GNDIO TM RST_N STBY MUTE POWERFAULT/ EAPD BICLKI BICLKO/PWM1A LRCLKI LRCLKO/PWM1B SDATAI SDATAO/PWM2A GND Block diagram VDD Figure 1. Serial digital audio interface MUX driver ADC Divider FILT VDDPLL GNDPLL CLKOUT/ PWM2B PLL XTI XTO AVCC AGND OSC 4/55 OUT2B Control interface I2CDIS INR MCLK33 SELCLK33 VLO driver PWM out I/F PGA SCL VCM OUT2A PWM SDA ADC MUX MUX INL OUT1B FFX modulator Digital volume VBIAS VHI OUT1A PWM STA330 Connection diagrams and pin descriptions 2 Connection diagrams and pin descriptions 2.1 Connection diagram Figure 2. Pin out (package underside view) 27 39 26 40 VFQFPN52 Exposed pad down Exposed pad, EP 14 13 52 1 5/55 Connection diagrams and pin descriptions 2.2 Pin description Table 2. Pin list Pin # 6/55 STA330 Name Type Description 1 STBY Digital input Standby (active high) 2 INL Analog input ADC left channel line input or microphone input 3 INR Analog input/output ADC right channel line input 4 VBIAS Analog input/output ADC microphone bias voltage 5 AVDD Supply ADC analog supply 6 VHI Analog input ADC high reference voltage 7 VLO Analog input ADC low reference voltage 8 AGND Ground ADC analog ground 9 VCM Analog input/output ADC Common mode voltage 10 RST_N Digital input Reset (active low) 11 CLKOUT Digital output Buffered clock output 12 GND1 Ground Digital ground 13 VDD1 Supply Digital supply 14 MUTE Digital input Mute (active high) 15 VCC1A Supply Channel 1 PWM A power supply 16 OUT1A PWM output Channel 1 PWM A output 17 GND1A Ground Channel 1 PWM A power ground 18 GND1B Ground Channel 1 PWM B power ground 19 OUT1B PWM output Channel 1 PWM B output 20 VCC1B Supply Channel 1 PWM B power supply 21 VCC2B Supply Channel 2 PWM B power supply 22 OUT2B PWM output Channel 2 PWM B output 23 GND2B Ground Channel 2 PWM B power ground 24 GND2A Ground Channel 2 PWM A power ground 25 OUT2A PWM output Channel 2 PWM A output 26 VCC2A Supply Channel 2 PWM A power supply 27 GND33 Ground Pre-driver ground 28 GNDIO1 Ground I/O ring ground 29 VDDIO1 Supply I/O ring supply 30 VCC33 Supply Pre-driver supply STA330 Connection diagrams and pin descriptions Table 2. Pin list (continued) Pin # Name Type Description 31 POWERFAULT/ EAPD Digital output Power fault signal (active high) / External audio power-down signal 32 TM Digital input Test mode (active high) 33 I2CDIS Digital input I2C disable pin (active high) 34 SCL Digital input I2C serial clock 35 SDA Digital input/output I2C serial data 36 SELCLK33 Digital input Master clock input selector: SELCLK33 = 1 -> MCLK33 selected SELCLK33 = 0 -> XTI selected 37 MCLK33 Digital input Master clock input 3.3-V capable XTI: crystal input or master clock input 3.3-V capable 38 XTI Digital input Crystal input or master clock input 39 XTO Digital output Crystal output 40 FILT Analog input/output PLL loop filter terminal 41 GNDPLL Ground PLL analog ground 42 VDDPLL Supply PLL analog supply 43 GND2 Ground Digital ground 44 VDD2 Supply Digital supply 45 SDATAI Digital input Input serial audio interface data 46 SDATAO Digital output Output serial audio interface data 47 LRCLKI Digital input/output Input serial audio interface L/R-clock 48 LRCLKO Digital input/output Output serial audio interface L/R-clock (volume UP when I2CDIS=1) 49 GNDIO2 Ground I/O ring ground 50 VDDIO2 Supply I/O ring supply 51 BICLKI Digital input/output Input serial audio interface bit-clock 52 BICLKO Digital input/output Output serial audio interface bit-clock (volume DOWN when I2CDIS=1) EP Ground Exposed pad ground 7/55 Electrical specifications STA330 3 Electrical specifications 3.1 Maximum and recommended operating conditions Table 3 gives the maximum ratings and Table 4 the recommended operating conditions. Table 3. Absolute maximum ratings Symbol Note: Min Max Unit VDD/VDD1/VDD2 Digital supply voltage -0.5 +4.0 V AVDD ADC supply voltage -0.5 +4.0 V VDDPLL PLL analog supply voltage -0.5 +4.0 V VCC1A/1B/2A/2B Power stage supply voltage -0.5 +4.0 V VCC33 Pre-driver supply -0.5 +4.0 V VDDIO Digital I/O supply -0.5 +4.0 V VDI Voltage range digital in -0.5 VDDIO +0.3 V VAI Voltage range analog in -0.5 AVDD +0.3 Vo Voltage on output pins -0.5 VDDIO +0.3 V TSTG Storage temperature -40 150 oC TAMB Ambient operating temperature -20 85 oC V All grounds must be within 0.3 V of each other. Table 4. Recommended operating conditions Symbol 8/55 Description Parameter Min Typ Max Unit VDD/VDD1/VDD2 Digital supply voltage 1.55 1.8 3.6 V AVDD ADC supply voltage 1.8 3.3 3.6 V VDDPLL PLL analog supply voltage 1.55 1.8 3.6 V VCC1A/1B/2A/2B Power stage supply voltage 1.8 3.3 3.6 V VCC33 Pre-driver supply voltage 1.8 3.3 3.6 V GND1, GND2, GND33 Channel 1 and 2 power ground, pre-driver ground TAMB Ambient operating temperature 0 0 25 V 70 o C STA330 3.2 Electrical specifications Electrical characteristics Table 5 lists the device electrical characteristics under the conditions nominal supply voltage (see Table 4), LRCLKI frequency (fS) = 48 kHz, input frequency = 1 kHz, and Rload = 32 Ω, unless otherwise specified. Table 5. Electrical characteristics Symbol Parameter Test conditions Min Typ Max Unit IstbyL Logic power supply current at standby 1.3 µA IddL Logic power supply current at operating 15 mA Tds Low current dead time (static) 1 ns Tdd High current dead time (dynamic) 2.5 ns Tr Rise time 3 ns Tf Fall time 3 ns DNR Dynamic range A-weighted Speaker mode 96 dB SNR Signal-to-noise ratio (A-weighted) Speaker mode 92 dB 0 dBFS input, 8 Ω speaker 0.1 % -6 dBFS input, 8 Ω speaker 0.05 % 0 dBFS input, 32 Ω headphone 0.1 % -6 dBFS input, 32 Ω headphone 0.05 % THDN Total harmonic distortion 9/55 Electrical specifications 3.3 STA330 Lock time Table 6 gives the typical lock time of the PLL using the suggested loop filter on page 18, a 1.8-V supply and 30o C junction temperature. Table 6. PLL lock time Parameter Lock time 3.4 200 µs ADC performance values Table 7. Programmable gain performance Parameter 10/55 Value Min Typ Max Unit Dynamic range, 1 kHz, 3.3-V supply dB Dynamic range, 1 kHz, 1.8-V supply dB Dynamic range, 1 kHz, 3.3-V supply A-weighted 92 dB Dynamic range, 1 kHz, 1.8-V supply A-weighted 84 dB SNDR 1 kHz, 3.3 V supply dB SNDR 1 kHz, 1.8 V supply dB SNDR 1 kHz, 3.3 V supply A-weighted 92 dB SNDR 1 kHz, 1.8 V supply A-weighted 84 dB THD 1 kHz, -1 dB input, 1.8-V supply 75 dB THD 1 kHz, -1 dB input, 3.3-V supply 85 dB Deviation from linear phase ° Pass band kHz Pass band ripple dB Stop band kHz Stop band attenuation dB Group delay, 8 kHz ms Group delay, 48 kHz ms Cross talk, 1.8 V dB Cross talk, 3.3 V dB STA330 4 Applications Applications Figure 3 to Figure 6 below show the circuit diagrams of a typical application with the STA510F. Figure 3. STA330 codec block PWM output selection Figure 4. STA510F power stage block IC401 IC - STA510F Binary, Ternary 11/55 Applications STA330 Figure 5. Connector and power supply block Figure 6. Direct control and settings block Table 8. Components for setting up application Component 12/55 µController µLess Comments R413 No Yes EAPD (µLess mode) R28 Yes No POWERFAULT -> EAPD (µP mode) R12 Yes Yes STA510F: PWM1B R21 No No R11 Yes Yes R18 No No R17 Yes Yes STA510F: PWM1A STA510F: PWM2B STA330 Applications Table 8. Components for setting up application (continued) Component µController µLess Comments R25 No No R16 Yes Yes R22 No No J7 2-3 1-2 Volume up (µLess mode) J6 2-3 1-2 Volume down (µLess mode) J5 2-3 2-3 3.3-V supply J4 2-3 (L) 1-2 (H) I2CDIS STA510F: PWM2A 13/55 Digital processing 5 STA330 Digital processing The STA330 processor block is a digital block providing two channels of audio processing and channel-mapping capability. 5.1 Signal processing flow I2S or stereo ADC data can be selected. The I2S frequency range is from 8 kHz to 192 kHz. ADC sampling frequency can be selected from 8 kHz to 48 kHz. 5.2 I2C interface disabled When pin I2CDIS = 1, the SDA, SCL, LRCLKO and BICLKO pins can be pulled high or low to change certain parameters of operation. " SDA = 0: FFX input comes from ADC SDA = 1: FFX input comes from digital audio interface " SCL = 0: binary output mode (binary soft start/stop enabled) SCL = 1: phase shift output mode " LRCLKO = 0: no volume change LRCLKO = 1: volume up " BICLKO = 0: no volume change BICLKO = 1: volume down At power-up, the master volume is set to -60 dB. When holding pin LRCLKO = 1 and pin BICLKO = 1 simultaneously, the master volume is set to 0 dB. A high pulse on pin LRCLKO causes a master volume change of +0.5 dB and a high pulse on pin BICLKO causes a master volume change of -0.5 dB. 14/55 STA330 5.3 Digital processing Volume control and gain The volume control structure of the STA330 consists of individual volume registers for each channel and a master volume register that provides an offset to each channel’s volume setting. The individual channel volumes are adjustable in 0.5 dB steps from +36 dB to -91.5 dB. As an example, if register LVOL = 0x00 or +36 dB and register MVOL = 0x18 or -12 dB, then the total gain for the left channel is +24 dB. When the mute bit is set to 1, all channels are muted. The volume control provides a soft mute with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (approximately 48 kHz). Table 9. Master volume offset as a function of register MVOL MVOL[7:0] Volume offset from channel value 0x00 0 dB 0x01 -0.5 dB 0x02 -1dB … … 0x78 -60 dB … … 0xFE -105 dB 0xFF Hard master mute Table 10. Channel volume as a function of registers LVOL and RVOL LVOL/RVOL[7:0] Volume 0x00 +36 dB 0x01 +35.5 dB 0x02 +35 dB … … 0x47 +0.5 dB 0x48 0 dB 0x49 -0.5 dB … … … … 0xFF -91.5 dB 15/55 PLL 6 STA330 PLL Figure 7 shows the main components of the PLL. Figure 7. PLL block diagram INFIN CLKIN Input frequency divider FBCLK LOCKP Lock detect IDF FILT INFIN Buffer INFOUT REFOUT Phase / frequency divider (PFD) LF Charge pump and loop filter VCONT FBCLK VCO FVCO Loop frequency divider STRB STRB_ BYPASS FRAC_CTRL DITHER_DISABLE FRAC_INPUT 16/55 Fractional controller NDIV Output frequency divider PHI STA330 6.1 PLL Functional description Phase/frequency detector The phase/frequency detector (PFD) compares the phase difference between the corresponding rising edges of INFIN and FBCLK, (clock output from the loop frequency divider) by generating voltage pulses with widths proportional to the input phase error. Charge pump and loop filter This block converts the voltage pulses from the phase/frequency detector to current pulses which charge the loop filter and generate the control voltage for the voltage-controlled oscillator. The loop filter is placed external to the PLL on pin FILT. Voltage controlled oscillator The voltage controlled oscillator (VCO) is the oscillator inside the PLL. It produces a frequency output (FVCO) proportional to the input control voltage. Input frequency divider This frequency divider divides the PLL input clock CLKIN by a factor called the input division factor (IDF) to generate the PFD input frequency INFIN. Loop frequency divider This frequency divider is present within the PLL for dividing FVCO by a factor called the loop division factor (LDF). The output of this block is the FBCLK. Output frequency divider The PLL output PHI is generated by dividing the FVCO by the output division factor (ODF). The divider that divides the FVCO to generate the clock to the core is called the output frequency divider. In the STA330, the ODF is fixed to be divisible by 2 and cannot be configured. Lock-detect circuit The output of this block (the LOCKP signal) is asserted high when the PLL enters the state of COARSE LOCK in which the output frequency is within ±10% (approximately) of the desired frequency. The LOCKP signal is refreshed every 32 cycles of the INFIN. The generated value is based on the result of comparing the number of FBCLK cycles in a window of 14 INFIN cycles. The different cases generated after comparison are as follows. " If LOCKP is already at 0, then in the next refresh cycle LOCKP goes to 1 if the number of FBCLK cycles in the 14-cycle INFIN window is 13, 14, or 15. Otherwise LOCKP stays at 0. " If LOCKP is already at 1, then in the next refresh cycle LOCKP goes to 0 if the number of FBCLK cycles in the 25-cycle INFIN window is less than 11 or higher than 17, otherwise LOCKP stays at 1. " If LOCKP is already at 1 and CLKIN is lost (no longer present on the input pin), LOCKP stays at 1. In this case, the PLL is unlocked. 17/55 PLL STA330 PLL filter Figure 8 shows the PLL filter scheme. Recommended values are R1 = 12.5 kΩ, C1 = 250 pF, and C2 = 82 pF. Figure 8. PLL filter scheme Vc R1 C2 C1 Ground Table 6 on page 10 gives a typical lock time value for the PLL. 6.2 Configuration examples The STA330 PLL can be configured in two ways: " default startup configuration " direct PLL programming The default startup configuration reads the device defaults. With this configuration, it is not necessary to program the PLL dividers directly as some presets are used. In this mode, the oversampling ratio between pins XTI (or MCLK33) and LRCLKI is fixed to 256. The direct PLL programming bypasses the automatic presets allowing direct programming of the PLL dividers. The output PLL frequency can be determined as following: Output division factor: ODF = 2 Relation between input and output clock frequency: FINFIN = FXTI / IDF If register bit PLLCFG0.FRAC_CTRL = 1 FVCO = FINFIN * (LDF + FRACT / 216 + 1 / 217) FPHI = FVCO / ODF When register bit PLLCFG0.DITHER_DISABLE[1] = 1, the 1 / 217 factor is not in the multiplication. It is recommended to keep register bit PLLCFG0.DITHER_DISABLE[1] = 0, otherwise there can be spurious signals in the output clock spectrum. 18/55 STA330 PLL If register bit PLLCFG0.FRAC_CTRL = 0, then: FVCO = FINFIN * LDF FPHI = FVCO / ODF In the above equations: FRACT = Decimal equivalent of register bit PLLCFG1.FRAC_INPUT[15:0] IDF = Input division factor (refer to previous formulas) LDF = Loop division factor (refer to previous formulas) ODF = Output division factor = 2 FINFIN = INFIN frequency FXTI = XTI frequency FVCO = VCO frequency FPHI = Frequency of the PLL output clock When selecting the value of IDF, LDF and FRACT make sure the following limits are maintained: 2.048 MHz < FXTI < 49.152 MHz 2.048 MHz < FINFIN < 16.384 MHz 65.536 MHz < FVCO < 98.304 MHz There are also some additional constraints on IDF and LDF. IDF should be greater than 0, LDF should be greater than 5 if FRAC_CTRL = 0 and greater than 8 if FRAC_CTRL = 1. When automatic settings are not used, the PLL must be configured to generate an internal frequency of N * fS, where fS is the LRCLKI pin frequency. Values of N are given in Table 11. Table 11. Oversampling table fS (kHz) N FPHI (MHz) 8 4096 32.768 11.025 4096 45.1584 12 4096 49.152 16 2048 32.768 22.05 2048 45.1584 24 2048 49.152 32 1024 32.768 44.1 1024 45.1584 48 1024 49.152 64 512 32.768 88.2 512 45.1584 96 512 49.152 128 256 32.768 176.4 256 45.1584 192 256 49.152 19/55 PLL STA330 In the following examples floor means rounded towards zero and round means rounded to nearest integer. Example 1 FXTI = 13 MHz fS = 44.1 kHz IDF should be equal to 3 otherwise LDF become less than 8 (FRAC_CTRL must be 1): LDF = floor(45.1584 / (13 / IDF)) = 10 FRACT = round([(45.1584 / (13 / IDF)) - floor(45.1584 / (13 / IDF))] * 216) = 27602 Using the above configuration, the system clock is 45.15841675 MHz, the approximate static error is 16 Hz (that is, 0.5 ppm). Example 2 FXTI = 19.2 MHz fS = 48 kHz IDF should be equal to 4 otherwise LDF become less than 8 (FRAC_CTRL must be 1): LDF = floor(49.152 / (19.2 / IDF)) = 10 FRACT = round([(49.152 / (19.2 / IDF)) - floor(49.152 / (19.2 / IDF))] * 216) = 15728 Using the above configuration, the system clock is 49.151953125 MHz, the approximate static error is 47 Hz (that is, 1 ppm). 20/55 STA330 Analog-digital converter (ADC) 7 Analog-digital converter (ADC) 7.1 Functional description The STA330 analog input is provided through a low-power, low-voltage, stereo, audio-ADC front end designed for audio applications. It includes a programmable gain amplifier, antialiasing filter, a low-noise microphone biasing circuit, a third-order, MASH2-1, delta-sigma modulator, a digital decimating filter and a first-order DC-removal filter. This device is fabricated using a 0.18 µm CMOS process, where high-speed precision analog circuits are combined with high-density logic circuits. The ADC works in a microphone-input (mic-in) mode and in a line-input mode. If the line-input mode is selected, the ADC is configured in stereo and all conversion channels are active. If the microphone-input mode is selected, the ADC is configured in mono. The mono channel is routed through the left conversion path, and the right conversion path is kept in power-down mode to minimize power consumption. A programmable gain amplifier (PGA) is available in mic-in mode, giving the possibility to amplify the signal from 0 to +42 dB in steps of 6 dB. 7.1.1 Digital anti-aliasing filter characteristics The digital filter characteristics are shown in Table 12. Table 12. Digital filter characteristics Parameter Typical Pass band 0.4535 * fS Pass band ripple: Fs mode Fs_by_2 mode Fs_by_4 mode 0.08 dB at 44.1 kHz 0.08 dB at 22.05 kHz 0.08 dB at 11.025 kHz Stop band attenuation: Fs mode Fs_by_2 mode Fs_by_4 mode 45 dB at 44.1 kHz 45 dB at 22.05 kHz 45 dB at 11.025 kHz Group delay: Fs mode Fs_by_2 mode Fs_by_4 mode 0.4 ms at 32 kHz 0.7 ms at 16 kHz 1.4 ms at 8 kHz 21/55 Analog-digital converter (ADC) 7.1.2 STA330 High-pass filter characteristics Table 13. High-pass filter characteristics Parameter 7.1.3 Typical Frequency response: -3 dB -0.08 dB 7 Hz 50 Hz Phase deviation at 20 Hz 19.35° Pass-band ripple 0.08 dB Programmable gain amplifier The programmable gain amplifier (PGA) is available in mic-in mode only. It is possible to amplify the input signal from 0 to 42 db in steps of 6 db. The setting is done through bits PGA of register ADCCFG on page 47. See Table 7 on page 10 for performance values. 7.2 Application scheme Figure 9 shows the filter circuit. Figure 9. Block diagram C9 AC coupled INL DC coupled C0 AC coupled INR DC coupled 3-V, 3-A supply AVDD VSSA C5 AGND R1 VHI VSSA C5 = 1 µF C6, C7 = 10 µF (low ESR and ESL capacitors are recommended) The VSSA plane must be a different plane to the other ground planes C6 VLO VCM The 3-V, 3-A supply must be low-noise and separate from the other supplies C7 VBIAS C8 22/55 R1 = 500 Ω C8 = 10 µF C9, C0 = 1 µF (low ESR) STA330 7.3 Analog-digital converter (ADC) Configuration examples The ADC sampling frequency can be selected from three values: " normal (from 32 kHz to 48 kHz) " low (from 16 kHz to 24 kHz) " very-low (from 8 kHz to 12 kHz). The setting is done through bits ADC_FS_RANGE in register MISC on page 48. For all other settings, register ADCCFG on page 47 is used. 23/55 Serial digital audio interface (SAI) STA330 8 Serial digital audio interface (SAI) 8.1 Specifications The serial-to-parallel interface and the parallel-to-serial interface can have different sampling rates. The following terms are used in this section: 8.2 " BICLK active edge: Pins SDATAI, SDATAO, LRCLKI, LRCLKO always change synchronously with BITCLK active edges. The active edge can be configured to a rising or falling edge via register programming. " BICLK strobe edge: Pins SDATAI, SDATAO, LRCLKI, LRCLKO should be stable near BICLK strobe edges, the slave device is able to use strobe edges to latch serial data internally. Master mode In this mode pins BICLKI/BICLKO and pins LRCLKI/LRCLKO are configured as outputs. Figure 10. Master mode BICLKI/ BICLKO tDL LRCLKI/ LRCLKO tDDA SDATAO SDATAI tDST Table 14. 24/55 tDHT Master mode Symbol Parameter Min tDL LRCLKI/LRCLKO propagation delay from BICLK active edge tDDA Typ Max Unit 0 10 ns SDATAI propagation delay from BICLKI/O active edge 0 15 ns tDST Sdatao setup time to BICLKI/O strobing edge 10 ns tDHT Sdatao hold time from BICLKI/O strobing edge 10 ns STA330 8.3 Serial digital audio interface (SAI) Slave mode In this mode, pins BICLKI/O and pins LRCLKI/O are configured as inputs. Figure 11. Slave mode tBCH tBCL BICLKI/ BICLKO tBCY LRCLKI/ LRCLKO tDS tLRH tLRSU SDATAO tDH SDATAI tDD Table 15. Slave mode Symbol Parameter Min Typ Max Unit tBCY BICLK cycle time 50 ns tBCH BICLK pulse width high 20 ns tBCL BICLK pulse width low 20 ns tLRSU LRCLKI/LRCLKO setup time to BICLK strobing edge 10 ns tLRH LRCLKI/LRCLKO hold time to BICLK strobing edge 10 ns tDS SDATAO setup time to BICLK strobing edge 10 ns tDH SDATAO hold time to BICLK strobing edge 10 ns tDD SDATAI propagation delay from BICLK active edge 0 10 ns 25/55 Serial digital audio interface (SAI) 8.4 STA330 Serial formats Different audio formats are supported in both master and slave modes. Clock and data configurations can be customized to match most of the serial audio protocols available on the market. Data length can be customized for 8-, 16-, 24- and 32-bit. Figure 12. Right justified LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI/ SDATAO n-1 n 1 2 3 n-1 n 1 2 3 Figure 13. Left justified LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI/ SDATAO 26/55 1 2 3 n-1 n 1 2 3 n-1 n STA330 8.4.1 Serial digital audio interface (SAI) DSP Figure 14. DSP LRCLKI/ LRCLKO BICLKI/ BICLKO Left SDATAI/ SDATAO 8.4.2 1 2 3 Right n-1 n 1 2 3 n-1 n I2S Figure 15. I2S LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI/ SDATAO 1 2 3 n-1 n 1 2 3 n-1 n 27/55 Serial digital audio interface (SAI) 8.4.3 STA330 PCM/IF (non-delayed mode) " MSB first " 16-bit data Figure 16. PCM/IF (non-delayed mode) Any width LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI/ SDATAO 8.4.4 1 2 3 n-1 n PCM/IF (delayed mode) " MSB first " 16-bit data Figure 17. PCM/IF (delayed mode) LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI/ SDATAO 28/55 1 2 3 n-1 n STA330 8.5 Serial digital audio interface (SAI) SAI pass-through A configuration is available which allows the SAI input signal to be passed straight to the digital output. The STA330 is able to translate the incoming serial audio interface signal from SAI-in to a different output format on SAI-out. So the SAI pass-through enables devices to be cascaded, even devices with slightly different protocols. The pass-through is set by programming register PWMINT1 on page 49 with the value 0x00 and register PWMINT2 with the value 0x01. SAI-in protocol is set up with registers S2PCFG0 on page 39 and S2PCFG1 and SAI-out protocol with P2SCFG0 on page 41 and P2SCFG1. Input and output data sampling frequencies must be the same. 29/55 I2C interface 9 STA330 I2C interface This section describes the communication protocol of the I2C interface. 9.1 Data transition and change Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a start or stop condition. 9.2 Start condition A start condition is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A start condition must precede any command for data transfer. 9.3 Stop condition A stop condition is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A stop condition terminates communication between the STA330 and the master bus. 9.4 Data input During data input, the STA330 samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low. 9.5 Device addressing To start communication between the master and the STA330, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode. The 7 most significant bits are the device address identifiers, corresponding to the I2C bus definition. In the STA330, the I2C interface has the device address 0x34. The 8th bit (LSB) identifies read or write operation (R/W), this bit is set to 1 in read mode and 0 in write mode. After a start condition, the STA330 identifies on the bus the device address and if a match is found, it acknowledges the identification on SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address. 30/55 I2C interface STA330 9.6 Write operation Following the start condition the master sends a device select code with the R/W bit set to 0. The STA330 acknowledges this and the writes to the byte of the internal address. After receiving the internal byte address, the STA330 responds with an acknowledgement. 9.6.1 Byte write In the byte-write mode the master sends one data byte. This is acknowledged by the STA330. The master then terminates the transfer by generating a stop condition. 9.6.2 Multi-byte write The multi-byte write modes can start from any internal address. The master generates a stop condition which terminates the transfer. 9.7 Read operation 9.7.1 Current address byte read Following the start condition the master sends a device select code with the R/W bit set to 1. The STA330 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a stop condition. 9.7.2 Current address multi-byte read The multi-byte read modes can start from any internal address. Sequential data bytes are read from sequential addresses within the STA330. The master acknowledges each data byte read and then generates a stop condition terminating the transfer. 9.7.3 Random address byte read Following the start condition the master sends a device select code with the R/W bit set to 0. The STA330 acknowledges this and then the master writes the internal address byte. After receiving the internal byte address, the STA330 again responds with an acknowledgement. The master then initiates another start condition and sends the device select code with the R/W bit set to 1. The STA330 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a stop condition. 31/55 I2C interface 9.7.4 STA330 Random address multi-byte read The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA330. The master acknowledges each data byte read and then generates a stop condition terminating the transfer. Figure 18. I2C write operations ACK ACK Byte Write Start Dev address R/W Sub address Start Dev address R/W Data in Stop ACK ACK Multibyte Write ACK ACK Sub address ACK Data in Data in Stop Figure 19. I2C read operations ACK Current address read Start Dev address R/W No ACK Data ACK Random address read Start Dev address R/W ACK Sub address ACK Sequential current read Start Dev address R/W=High Dev address R/W ACK Start Dev address ACK No ACK Data ACK Dev address R/W Data ACK Data 32/55 Stop ACK ACK Start Stop No ACK Data ACK Sub address R/W Data Data ACK Sequential random read Start Stop No ACK Data Stop STA330 Registers 10 Registers 10.1 Summary Table 16. Register summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 0x00 FFXCFG0 MUTE POW_STBY SOFT_ VOL_ON BIN_SOFT START 0x01 FFXCFG1 L1_R2 MUTE_ON_ INVALID 0x02 MVOL SET_VOL_MASTER[7:0] 0x03 LVOL SET_VOL_LEFT[7:0] 0x04 RVOL SET_VOL_RIGHT[7:0] 0x05 TTF0 TIM_TS_FAULT[15:8] 0x06 TTF1 TIM_TS_FAULT[7:0] 0x07 TTP0 TIM_TS_POWUP[15:8] 0x08 TTP1 TIM_TS_POWUP[7:0] 0x0A S2PCFG0 BICLK_ STRB 0x0B S2PCFG1 PDATA_LENGTH[1:0] 0x0C P2SCFG0 BICLK_ STRB 0x0D P2SCFG1 PDATA_LENGTH[1:0] 0x14 PLLCFG0 0x15 PLLCFG1 FRAC_INPUT[15:8] 0x16 PLLCFG2 FRAC_INPUT[7:0] 0x17 PLLCFG3 0x18 PLLPFE 0x19 PLLST 0x1E ADCCFG 0x1F CKOCFG CLKOUT_ DIS 0x20 MISC OSC_DIS 0x21 PADST0 Reserved 0x22 PADST1 Reserved 0x23 FFXST 0x28 BISTRUN Reserved 0x29 BISTST0 Reserved PLL_DIRECT _PROG LRCLK_ LEFT PWM_MODE[1:0] SHARE_ BILR LRCLK_ LEFT SDATAO_ ACT MSB_FIRST PLL_ BYP_ UNL BICLK2PLL Bit 0 MASTER_ MODE DATA_FORMAT[2:0] MAP_L[1:0] MSB_FIRST MAP_R[1:0] MASTER_ MODE DATA_FORMAT[2:0] MAP_L[1:0] DITHER_DISABLE[1:0] STRB _BYPASS Bit 1 PWM_SHIFT[1:0] BICLK_OS[1:0] FRAC_ CTRL Bit 2 TIM_SOFT_VOL[3:0] BICLK_OS[1:0] STRB PLL_ UNLOCK Bit 3 MAP_R[1:0] IDF[3:0] NDIV[5:0] PLL_ PWDN PFE1A PFE1B PFE2A PFE2B INSEL STBY BYPASS_ CALIB CLKENBL RESET_ FAULT PLL_ PLL_ PWD_STATE BYP_STATE PGA[2:0] CLKOUT_SEL[1:0] P2P_FS_RANGE[2:0] ADC_FS_RANGE[1:0] INVALID_ INP_FBK P2P_ IN_ ADC CORE_ CLKENBL MUTE_ INT_FBK BINSS_FBK 33/55 Registers STA330 Table 16. Register summary (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0x2A BISTST1 Reserved 0x2B BISTST2 Reserved 0x2D PWMINT1 PWM_INT[15:8] 0x2E PWMINT2 PWM_INT[7:0] 0x32 POWST 10.2 POWER DOWN POW_ TRISTATE POW_ FAULT1A POW_ FAULT1B Bit 2 POW_ FAULT2A Bit 1 POW_ FAULT2B General registers FFXCFG0 Bit 7 MUTE FFX configuration register 0 Bit 6 POW_STBY Address: 0x00 Type: R/W Buffer: No Reset: 0x75 Bit 5 Bit 4 SOFT_VOL_ON BIN_ SOFTSTART Bit 3 Bit 2 Bit 1 TIM_SOFT_VOL[3:0] Description: 7 MUTE: 0: default 1: FFX output is zero 6 POW_STBY: 0: FFX bridge is in power-up mode 1: FFX bridge is in standby mode (default) 5 SOFT_VOL_ON: 0: smooth transition not active 1: smooth transition when changing volume control (default) 4 BIN_SOFTSTART: Reserved (default is 1) 3:0 TIM_SOFT_VOL: volume control time step for any 0.5 dB volume change Time is 2TIM_SOFT_VOL * 20.83 µs Default is 666.66 µs 34/55 Bit 0 Bit 0 STA330 Registers FFXCFG1 Configuration register 1 Bit 7 Bit 6 L1_R2 MUTE_ON_ INVALID Address: 0x01 Type: R/W Buffer: No Reset: 0xF8 Bit 5 Bit 4 PWM_MODE[1:0] Bit 3 Bit 2 Bit 1 Bit 0 PWM_SHIFT[1:0] Description: 7 L1_R2: channel mapping: 0: right channel is mapped to output channel 1 and left channel is mapped to output channel 2 1: left channel is mapped to output channel 1 and right channel is mapped to output channel 2 (default) 6 MUTE_ON_ INVALID: mutes PWM outputs if invalid digital data is received: 0: outputs are not muted 1: outputs are muted (default) 5:4 PWM_MODE[1:0]: 00: binary (output B is opposite of output A) 01: binary headphones (output B is 50% duty cycle) 10: ternary 11: phase shift (default) 3:2 PWM_SHIFT[1:0]: 10: default PWM period-shift between channels 1 and 2 Value is N * 90° Default is 180° 1:0 Reserved (default is 0) MVOL Bit 7 Master volume control Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SET_VOL_MASTER[7:0] Address: 0x02 Type: R/W Buffer: No Reset: 0x00 Description: 7:0 SET_VOL_MASTER[7:0]: master volume control: From 0 dB to -127.5 dB in 0.5 dB steps 35/55 Registers STA330 LVOL Bit 7 Left channel volume control Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 1 Bit 0 SET_VOL_LEFT[7:0] Address: 0x03 Type: R/W Buffer: No Reset: 0x48 Description: 7:0 SET_VOL_LEFT[7:0]: left channel volume control: Left channel volume control (from +36 dB to -91.5 dB in 0.5 dB steps) Default value (0x48) corresponds to 0 dB RVOL Bit 7 Right channel volume control Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 SET_VOL_RIGHT[7:0] Address: 0x04 Type: R/W Buffer: No Reset: 0x48 Description: 7:0 SET_VOL_RIGHT[7:0]: right channel volume control: Right channel volume control (from +36 dB to -91.5 dB in 0.5 dB steps) Default value (0x48) corresponds to 0 dB 36/55 STA330 Registers TTF0 Bit 7 Tri-state time-after-fault register 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 1 Bit 0 TIM_TS_FAULT[15:8] Address: 0x05 Type: R/W Buffer: No Reset: 0x00 Description: 7:0 MSBs of TIM_TS_FAULT[15:0]: See TTF1 on page 37. TTF1 Bit 7 Tri-state time-after-fault register 1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TIM_TS_FAULT(7:0) Address: 0x06 Type: R/W Buffer: No Reset: 0x02 Description: 7:0 LSBs of TIM_TS_FAULT[15:0]: time in which power is held in tri-state mode after a fault signal: Time is TIM_TS_FAULT * 83.33 µs. Default value (0x0002) corresponds to 166.66 µs tri-state time after fault 37/55 Registers STA330 TTP0 Bit 7 Tri-state time-after-power-up register 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TIM_TS_POWUP[15:8] Address: 0x07 Type: R/W Buffer: No Reset: 0x00 Description: 7:0 MSBs of TIM_TS_POWUP[15:0]: See register TTP1. TTP1 Bit 7 Tri-state time-after-power-up register 1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 TIM_TS_POWUP[7:0] Address: 0x08 Type: R/W Buffer: No Reset: 0x02 Description: 7:0 LSBs of TIM_TS_POWUP[15:0]: time in which power is held in tri-state mode after a power-up signal: Time is TIM_TS_POWUP * 83.33 µs Default value(0x0002) corresponds to 166.66 µs tri-state time after power-up 38/55 Bit 0 STA330 Registers S2PCFG0 Serial-to-parallel audio interface config register 0 Bit 7 Bit 6 Bit 5 Bit 4 BICLK_STRB LRCLK_LEFT SHARE_BILR MSB_FIRST Address: 0x0A Type: R/W Buffer: No Reset: 0xD2 Bit 3 Bit 2 Bit 1 DATA_FORMAT[2:0] Bit 0 MASTER_ MODE Description: 7 BICLK_STRB: 0: bit clock strobe edge is falling edge, bit clock active edge is rising edge 1: bit clock strobe edge is rising edge, bit clock active edge is falling edge (default) 6 LRCLK_LEFT: 0: left/right clock is low for left channel, high for right channel 1: left/right clock is high for left channel, low for right channel (default) 5 SHARE_BILR: 0: default 1: left/right clock and bit clock are shared between serial-parallel interface and parallel-toserial interface, BICLKI and LRCLKI are used 4 MSB_FIRST: 0: LSB first 1: MSB first (default) 3:1 DATA_FORMAT[2:0]: serial interface protocol format: 000: left Justified 001: I2S (default) 010: right justified 100: PCM no delay 101: PCM delay 111: DSP 0 MASTER_MODE: 0: default 1: serial interface is in master mode 39/55 Registers STA330 S2PCFG1 Bit 7 Serial-to-parallel audio interface config register 1 Bit 6 PDATA_LENGTH[1:0] Address: 0x0B Type: R/W Buffer: No Reset: 0x91 Bit 5 Bit 4 BICLK_OS[1:0] Bit 3 Bit 2 MAP_L[1:0] Description: 7:6 PDATA_LENGTH[1:0]: serial-to-parallel interface data length: 10: 24 bits (default) Length is (N+1) * 8 bit 5:4 BICLK_OS[1:0]: bit clock oversampling: 01:64 * fs (default) Value is (N+1) * 32 * fs (where fs = sampling frequency) 3:2 MAP_L[1:0]: left data-mapping slot: 00: slot0 (default) Value is nth slot 1:0 MAP_R[1:0]: right data-mapping slot: 01: slot1 (default) Value is nth slot 40/55 Bit 1 Bit 0 MAP_R[1:0] STA330 Registers P2SCFG0 Bit 7 BICLK_ STRB Parallel-to-serial audio interface configuration register 0 Bit 6 LRCLK_LEFT Address: 0x0C Type: R/W Buffer: No Reset: 0xD3 Bit 5 SDATAO_ACT Bit 4 MSB_FIRST Bit 3 Bit 2 Bit 1 DATA_FORMAT[2:0] Bit 0 MASTER_ MODE Description: 7 BICLK_STRB: defines the bit clock edges: 0: strobe is falling edge, active edge is rising 1: strobe is rising edge, active edge is falling (default) 6 LRCLK_LEFT: defines the channel for the LR clock: 0: clock is low for left channel, high for right channel 1: clock is high for left channel, low for right channel (default) 5 SDATAO_ ACT: sets the behavior of pin SDATAO: 0: output is tri-stated when no data is sent (default) 1: output is never in tri-state (it is 0 when no data is sent) 4 MSB_FIRST: data alignment in the protocol for SDATAI and SDATAO: 0: LSB is the first bit 1: MSB is the first bit (default) 3:1 DATA_FORMAT[2:0]: serial interface protocol format: 000: left justified 001: I2S (default) 010: right justified 100: PCM no delay 101: PCM delay 110: Reserved 111: DSP 0 MASTER_ MODE: selects serial interface master/slave mode: 0: slave 1: master (default) 41/55 Registers STA330 P2SCFG1 Bit 7 Parallel-to-serial audio interface config register 1 Bit 6 PDATA_LENGTH[1:0] Address: 0x0D Type: R/W Buffer: No Reset: 0x91 Bit 5 Bit 4 Bit 3 BICLK_OS[1:0] Bit 2 MAP_L[1:0] Description: 7:6 PDATA_LENGTH[1:0]: serial-to-parallel interface data length: 10: 24 bits (default) Length is (PDATA_LENGTH + 1) * 8 bit 5:4 BICLK_OS[1:0]: bit clock oversampling: 01: 64 * fs (default) Value is (BICLK_OS+1) * 32 * fs 3:2 MAP_L[1:0]: left data-mapping slot: 00: slot0 (default) Value is nth slot 1:0 MAP_R[1:0]: right channel data-mapping slot: 01: slot1 (default) Value is nth slot 42/55 Bit 1 Bit 0 MAP_R[1:0] STA330 Registers PLLCFG0 PLL configuration register 0 Bit 7 Bit 6 PLL_DIRECT_ PROG FRAC_CTRL Address: 0x14 Type: R/W Buffer: No Reset: 0x00 Bit 5 Bit 4 Bit 3 Bit 2 DITHER_DISABLE[1:0] Bit 1 Bit 0 Bit 1 Bit 0 IDF[3:0] Description: 7 PLL_DIRECT_PROG: PLL programming: 0: default 1: PLL is programmed according to the PLLCFG register settings 6 FRAC_CTRL: 0: default 1: PLL fractional-frequency synthesis is enabled 5:4 DITHER_DISABLE[1:0]: 00: default MSB = 1: disables rectangular PDF dither input to SDM LSB = 1: disables triangular PDF dither input to SDM 3:0 IDF[3:0]: PLL input division factor: 0000: IDF = 1 (default) 0010: IDF = 2 1111: IDF = 15 PLLCFG1 Bit 7 0001: IDF = 1 … PLL configuration register 1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 FRAC_INPUT[15:8] Address: 0x15 Type: R/W Buffer: No Reset: 0x00 Description: 7:0 FRAC_INPUT[15:8]: 16 bits are used to set the fractional part of PLL multiplication factor 43/55 Registers STA330 PLLCFG2 Bit 7 PLL configuration register 2 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FRAC_INPUT[7:0] Address: 0x16 Type: R/W Buffer: No Reset: 0x00 Description: 7:0 FRAC_INPUT[7:0]: 16 bits are used to set the fractional part of PLL multiplication factor PLLCFG3 PLL configuration register 3 Bit 7 Bit 6 STRB STRB_BYPASS Address: 0x17 Type: R/W Buffer: No Reset: 0x00 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 NDIV[5:0] Description: 7 STRB: asynchronous strobe input to the fractional controller: 0: default 6 STRB_BYPASS: standby bypass: 0: STRB signal is not bypassed (default) 1: STRB signal is bypassed 5:0 NDIV[5:0]: PLL multiplication factor (integral part) named as loop division factor: 00 00XX: LDF = NA 00 0100: LDF = NA 00 0101: LDF = 5 ... 11 0111: LDF = 55 11 1XXX: LDF = NA 44/55 Bit 0 STA330 Registers PLLPFE PLL/POP-free configuration register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLL_BYP_UNL BICLK2PLL PLL_PWDN PFE1A PFE1B PFE2A PFE2B RESET_FAULT Address: 0x18 Type: R/W Buffer: No Reset: 0x00 Description: 7 PLL_BYP_UNL: PLL bypass: 0: PLL is not bypassed (default) 1: PLL is bypassed when not locked 6 BICLK2PLL: 0: default 1: BICLKI is input to PLL 5 PLL_PWDN: 0: default 1: PLL is put in power-down mode 4 PFE1A: 0: default 1: pop-free resistances are connected to output 1A 3 PFE1B: 0: default 1: pop-free resistances are connected to output 1B 2 PFE2A: 0: default 1: pop-free resistances are connected to output 2A 1 PFE2B: 0: default 1: pop-free resistances are connected to output 2B 0 RESET_FAULT: 0: default 1: fault signal in the I2C register POWST is reset 45/55 Registers STA330 PLLST PLL status register (RO) Bit 7 Bit 6 Bit 5 PLL_UNLOCK PLL_ PWD_ STATE PLL_ BYP_ STATE Address: 0x19 Type: RO Buffer: No Reset: Undefined Bit 4 Bit 3 Bit 2 Bit 1 Description: 7 PLL_UNLOCK: PLL unlock state: 0: PLL is not in unlock state 1: PLL is in unlock state 6 PLL_PWD_ STATE: PLL power-down state: 0: PLL is not in power-down state 1: PLL is in power-down state 5 PLL_BYP_STATE: PLL bypass state: 0: PLL is not in bypass state 1: PLL is in bypass state 4:0 Reserved 46/55 Bit 0 STA330 Registers ADCCFG Bit 7 ADC configuration register Bit 6 Bit 5 PGA[2:0] Address: 0x1E Type: RO Buffer: No Reset: Undefined Bit 4 Bit 3 Bit 2 Bit 1 INSEL STBY BYPASS_CALIB CLKENBL Bit 0 Description: 7:5 PGA[2:0]: gain selection bits for the ADC programmable gain amplifier: 000: default Values are from 0 to 42 dB in 6 dB steps 4 INSEL: 0: line input selected (default) 1: microphone input selected (INL is the input) 3 STBY: ADC standby mode: 0: ADC in power-up mode (default) 1: ADC in standby mode 2 BYPASS_CALIB: 0: ADC DC-removal block not bypassed (default) 1: ADC DC-removal block bypassed 1 CLKENBL: Clock enable: 0: system clock not enabled 1: system clock available at ADC input (default) 0 Reserved CKOCFG Bit 7 CLKOUT_DIS Clock-out configuration register Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CLKOUT_SEL[1:0] Address: 0x1F Type: R/W Buffer: No Reset: Undefined Description: 7 CLKOUT_DIS: CLKOUT PAD disabled 0: default 1: disabled 6:5 CLKOUT_SEL[1:0]: 00: default The CLKOUT output frequency is the PLL output frequency divided by 2CLKOUT_SEL. 4:0 Reserved 47/55 Registers STA330 MISC Bit 7 Miscellaneous configuration register Bit 6 OSC_DIS Bit 5 P2P_FS_RANGE[2:0] Address: 0x20 Type: R/W Buffer: No Reset: 0x21 Bit 4 Bit 3 Bit 2 ADC_FS_RANGE[1:0] Bit 1 Bit 0 P2P_IN_ADC CORE_ CLKENBL Description: 7 OSC_DIS: enable/disable crystal oscillator: 0: default 1: disabled 6:4 P2P_FS_RANGE[2:0]: FFX audio frequency range: 000: very low (fs = 8 to 12 kHz) 001: low (fs = 16 to 24 kHz) 010: normal (fs = 32 to 48 kHz) (default) 011: high (fs = 64 to 96 kHz) 1X: very high (fs = 128 to 192 kHz) 3:2 ADC_FS_RANGE[2:0]: ADC audio frequency range: 00: normal (fs = 32 to 48 kHz) (default) 01: low (fs = 16 to 24 kHz) 1X: very low (fs = 8 to 12 kHz) 1 P2P_IN_ADC: FFX input: 0: FFX input is from serial-to-parallel audio interface (default) 1: FFX input is from ADC 0 CORE_CLKENBL: availability of system clock: 0: FFX system clock disabled 1: FFX system clock enabled (default) 48/55 STA330 Registers FFXST Bit 7 FFX status register Bit 6 Address: 0x23 Type: RO Buffer: No Reset: Undefined Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 INVALID_ INP_ FBK MUTE_INT_FBK Bit 0 Description: 7:3 Reserved 2 INVALID_INP_FBK: invalid input status: 1: invalid input sent to FFX 1 MUTE_INT_FBK: FFX mute status 1: FFX is in mute state 0 Reserved PWMINT1 Bit 7 PWM driver configuration register 1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWM_INT1[7:0] Address: 0x2D Type: R/W Buffer: No Reset: 0x00 Description: 7:0 PWM_INT1[7:0]: see Section 8.5: SAI pass-through on page 29 PWMINT2 Bit 7 PWM driver configuration register 2 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWM_INT2[7:0] Address: 0x2E Type: R/W Buffer: No Reset: 0x00 Description: 7:0 PWM_INT2[7:0]: see Section 8.5: SAI pass-through on page 29 49/55 Registers STA330 POWST Power bridge status register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 POW_ POWERDOWN POW_ TRISTATE POW_FAULT1A POW_FAULT1B POW_FAULT2A POW_FAULT2B Address: 0x32 Type: RO Buffer: No Reset: Undefined Description: 7 POW_POWERDOWN: power-down bridge: 0: not in power-down state 6 POW_TRISTATE: 1: power bridge is in tri-state 5 POW_FAULT1A: 1: power bridge 1A is in fault state 4 POW_FAULT1B: 1: power bridge 1B is in fault state 3 POW_FAULT2A: 1: power bridge 2A is in fault state 2 POW_FAULT2B: 1: power bridge 2B is in fault state 1:0 Reserved 50/55 1: power-down state Bit 1 Bit 0 STA330 11 Package information Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These package have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Table 17 gives the package dimensions for the parameters shown in Figure 20: VFQFPN52 outline below. Figure 20. VFQFPN52 outline 51/55 Package information STA330 Table 17. VFQFPN52 dimensions Dimensions in mm Dimensions in inches Reference Min Typical Max Min Typical Max 0.800 0.900 1.000 0.031 0.035 0.039 A1 0.020 0.050 0.001 0.002 A2 0.650 1.000 0.026 0.039 A3 0.250 A b 0.180 0.230 0.300 0.007 0.009 0.012 D 7.875 8.000 8.125 0.310 0.315 0.320 D2 2.750 5.700 6.250 0.108 0.224 0.246 E 7.875 8.000 8.125 0.310 0.315 0.320 E2 2.750 5.700 6.250 0.108 0.224 0.246 e 0.450 0.500 0.550 0.018 0.020 0.022 L 0.350 0.550 0.750 0.014 0.022 0.030 ddd 52/55 0.010 0.080 0.003 STA330 12 Trademarks and other acknowledgements Trademarks and other acknowledgements FFX is a STMicroelectronics proprietary digital modulation technology. ECOPACK is a registered trademark of STMicroelectronics. 53/55 Revision history 13 STA330 Revision history Table 18. Date 12-Dec-2007 54/55 Document revision history Revision 1 Changes Initial release STA330 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 55/55