STA015
MPEG 2.5 LAYER III AUDIO DECODER
WITH ADPCM CAPABILITY
SINGLE CHIP MPEG2 LAYER 3 DECODER
SUPPORTING:
– All features specified for Layer III in ISO/IEC
11172-3 (MPEG 1 Audio)
TQFP44
SO28
– All features specified for Layer III in ISO/IEC
13818-3.2 (MPEG 2 Audio)
– Lower sampling frequencies syntax extension, (not specified by ISO) called MPEG 2.5
DECODES LAYER III STEREO CHANNELS,
DUAL CHANNEL, SINGLE CHANNEL (MONO)
SUPPORTING ALL THE MPEG 1 & 2
SAMPLING FREQUENCIES AND THE
EXTENSION TO MPEG 2.5:
48, 44.1, 32, 24, 22.05, 16, 12, 11. 025, 8 KHz
ACCEPTS MPEG 2.5 LAYER III
ELEMENTARY COMPRESSED BITSTREAM
WITH DATA RATE FROM 8 Kbit/s UP TO 320
Kbit/s
ADPCM CODEC CAPABILITIES:
– sample frequency from 8 kHz to 32 kHz
– sample size from 8 bits to 32 bits
– encoding algorithm: DVI,
ITU-G726 pack (G723-24, G721,G723-40)
– Tone control and fast-forward capability
EASY PROGRAMMABLE GPSO INTERFACE
FOR ENCODED DATA UP TO 5Mbit/s
(TQFP44 & LFBGA 64)
DIGITAL VOLUME CONTROL
DIGITAL BASS & TREBLE CONTROL
BYPASS MODE FOR EXTERNAL AUDIO
SOURCE
SERIAL BITSTREAM INPUT INTERFACE
EASY PROGRAMMABLE ADC INPUT
INTERFACE
ANCILLARY DATA EXTRACTION VIA I2C
INTERFACE.
SERIAL PCM OUTPUT INTERFACE (I2S AND
OTHER FORMATS)
PLL FOR INTERNAL CLOCK AND FOR
OUTPUT PCM CLOCK GENERATION
CRC CHECK AND SYNCHRONISATION
ERROR DETECTION WITH SOFTWARE
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April 2010
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LFBGA64
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ORDERING NUMBER: STA015$ (SO28)
STA015T$ (TQFP44)
STA015B$ (LFBGA 8x8)
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INDICATORS
I2C CONTROL BUS
LOW POWER 2.4V CMOS TECHNOLOGY
WIDE RANGE OF EXTERNAL CRYSTALS
FREQUENCIES SUPPORTED
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APPLICATIONS
PC SOUND CARDS
MULTIMEDIA PLAYERS
VOICE RECORDERS
DESCRIPTION
The STA015 is a fully integrated high flexibility
MPEG Layer III Audio Decoder, capable of decoding Layer III compressed elementary streams, as
specified in MPEG 1 and MPEG 2 ISO standards.
The device decodes also elementary streams
compressed by using low sampling rates, as specified by MPEG 2.5. STA015 receives the input
data through a Serial input Interface. The decoded
signal is a stereo, mono, or dual channel digital
output that can be sent directly to a D/A converter,
by the PCM Output Interface.
This interface is software programmable to adapt
the STA015 digital output to the most common
DACs architectures used on the market. The functional STA015 chip partitioning is described in
Fig.1a and Fig.1b.
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STA015
Figure 1.
1a. Block Diagram for TQFP44 and LFBGA64 package.
SDA
SCL
31
35
32
TQFP44
STROBE
20
18
I2C CONTROL
SDI
SCKR
BIT_EN
DATA-REQ
SCK_ADC
LRCK_ADC
SDI_ADC
16
14
34
36
38
GPIO
INTERFACE
SERIAL
INPUT
INTERFACE
39
41
43
27
BUFFER
256 x 8
VOLUME
& TONE
CONTROL
MPEG L III
ADPCM
CORE
PARSER
PCM
OUTPUT
INTERFACE
40
26
24
42
OUTPUT
BUFFER
15
13
XTI
XTO
TESTEN
28
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SO28
28
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GPSO_SCKR
SCK_ADC
LRCK_ADC
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SDI_ADC
bs
(s)
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27
25
BUFFER
256 x 8
2/56
GPSO_DATA
SCL
4
I2C CONTROL
DSP BASED
9
MPEG L III
ADPCM
CORE
PARSER
VOLUME
& TONE
CONTROL
OUTPUT
BUFFER
PCM
OUTPUT
INTERFACE
10
11
12
ADC
INPUT
INTERFACE
SYSTEM & AUDIO CLOCKS
26
RESET
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33
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SDA
SERIAL
INPUT
INTERFACE
GPSO_SCKR
D99AU1116B
FILT
3
5
OCLK
GPSO_REQ
12
22
1b. BLOCK DIAGRAM for SO28 package
BIT_EN
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4
RESET
7
LRCKT
3
25
6
SCKT
2
ADC
INPUT
INTERFACE
GPSO
INTERFACE
SDI
SDO
44
SYSTEM & AUDIO CLOCKS
SCKR
IODATA
[7:0]
37
DSP BASED
21
20
XTI
XTO
24
TESTEN
19
FILT
D99AU1117B
SDO
SCKT
LRCKT
OCLK
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STA015
Figure 2. Pin Connection
VDD_1
1
28
GPSO_SCKR
VSS_1
2
27
LRCK_ADC
SDA
3
26
RESET
SCL
4
25
SDI_ADC
SDI
5
24
TESTEN
SCKR
6
23
VDD_4
BIT_EN
7
22
VSS_4
SRC_INT/SCK_ADC
8
21
XTI
SDO
9
20
XTO
SCKT
10
19
FILT
LRCKT
11
18
PVSS
OCLK
12
17
PVDD
VSS_2
13
16
VDD_3
VDD_2
14
15
VSS_3
8
6
5
4
B
C
IODATA[7]
SDO
IODATA[6]
SRC_INT/SCK_ADC
IODATA[5]
BIT_EN
IODATA[4]
SCKR
GPIO/STROBE
SDI
42
41
40
39
38
37
36
35
34
33
GPSO_DATA
LRCKT
2
32
SCL
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OCLK
3
31
SDA
GPSO_REQ
4
30
VSS_1
VSS_2
5
29
VDD_1
VDD_2
6
VSS_3
7
VDD_3
8
N.C.
9
2
1
G
H
17
18
19
20
21
22
IODATA[0]
VDD_4
TESTEN
XTI
16
VSS_4
15
IODATA[1]
14
N.C.
13
(s)
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3
12
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IODATA[2]
11
IODATA[3]
PVSS
XTO
10
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so
FILT
PVDD
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43
1
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44
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N.C.
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A
D
7
SCKT
D99AU1061A
A1 = SDI
B2 = SCKR
D4 = BIT_EN
D1 = SRC_INT
E2 = SDO
F2 = SCKT
H1 = LRCKT
H3 = OCLK
F3 = VSS_2
E4 = VDD_2
G4 = VSS_3
G5 = VDD_3
F5 = PVDD
G6 = PVSS
28
GPSO_SCKR
27
OUT_CLK/DATA_REC
26
LRCK_ADC
25
RESET
24
SDI_ADC
23
N.C.
D99AU1062
G7 = FILT
G8 = XTO
F7 = XTI
E7 = VSS_4
C8 = VDD_4
D7 = TESTEN
A7 = SDI_ADC
B6 = RESET
A5 = LRCK_ADC
C5 = OUT_CLK/DATA_REQ
B5 = VDD_1
B4 = VSS_1
A4 = SDA
B3 = SCL
C2 = GPIO_STROBE
C3 = IODATA [4]
E3 = IODATA [5]
D2 = IODATA [6]
F1 = IODATA [7]
G3 = GPSO_REQ
F8 = IODATA [3]
F6 = IODATA [2]
E6 = IODATA [1]
C7 = IODATA [0]
C6 = GPSO_SCKR
A2 = GPSO_DATA
D00AU1149
LFBGA64
3/56
STA015
1.0 OVERVIEW
1.1 MP3 decoder engine
The MP3 decoder engine is able to decode any Layer III compliant bitstream: MPEG1, MPEG2 and
MPEG2.5 streams are supported. Besides audio data decoding the MP3 engine also performs ANCILLARY data extraction: these data can be retrieved via I2C bus by the application microcontroller in order
to implement specific functions.
Decoded audio data goes through a software volume control and a two-band equalizer blocks before feeding the output I2S interface. This results in no need for an external audio processor.
MP3 bitstream is sent to the decoder using a simple serial input interface (see pins SDI, SCKR, BIT_EN
and DATA_REQ), supporting input rate up to 20 Mbit/s. Received data are stored in a 256 bytes long input
buffer which provides a feedback line (see DATA_REQ pin) to the bitstream source (tipically an MCU).
1.2 ADPCM encoder/decoder engine
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This device also embeds a multistandard ADPCM encoder/decoder supporting different sample rates
(from 8 KHz up to 32 KHz) and different sample sizes (from 8 bit to 32 bits).
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During encoding process two different interfaces can be used to feed data: the serial input interface (same
interface used also to feed MP3 bitstream) or the ADC input interface, which provides a seamless connection with an external A/D converter. The currently used interface is selected via I2C bus.
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Also to retrieve encoded data two different interfaces are available: the I2C bus or the faster GPSO output
interface. GPSO interface is able to output data with a bitrate up to 5 Mbit/s and its control pins
(GPSO_SCKR, GPSO_DATA and GPSO_REQ) can be configured in order to easily fit the target application.
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1.3 BYPASS functional mode
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In order to allow using the device to post-process auxiliary audio sources a special BYPASS mode is available. When the device is configured in BYPASS mode the embedded DSP will process digital audio data
coming through the ADC input interface and will output the resulting data to the external DAC.
Available processings include volume and a tone ontrols.
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THERMAL DATA
Symbol
Rth j-amb
Parameter
Thermal resistance Junction to Ambient
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Value
Unit
85
°C/W
ABSOLUTE MAXIMUM RATINGS
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Symbol
VDD
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Unit
-0.3 to 4
V
Voltage on Input pins
-0.3 to VDD +0.3
V
VO
Voltage on output pins
-0.3 to VDD +0.3
V
Storage Temperature
-40 to +150
°C
Operative ambient temp
-20 to +85
°C
oper
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Power Supply
Value
Vi
Tstg
T
Parameter
STA015
PIN DESCRIPTION
SO28
1
2
3
TQFP44
29
30
31
LFBGA64
B5
B4
A4
Pin Name
VDD_1
VSS_1
SDA
Type
4
32
B3
SCL
I
5
6
7
34
36
38
A1
B2
D4
SDI
SCKR
BIT_EN
I
I
I
8
40
D1
I
9
42
E2
SRC_INT/
SCK_ADC
SDO
O
10
11
12
44
2
3
F2
H1
H3
SCKT
LRCKT
OCLK
O
O
I/O
13
14
15
16
17
18
19
5
6
7
8
10
11
12
F3
E4
G4
G5
F5
G6
G7
VSS_2
VDD_2
VSS_3
VDD_3
PVDD
PVSS
FILT
O
20
21
13
15
G8
F7
XTO
XTI
O
I
Ground
Supply Voltage
Ground
Supply Voltage
PLL Power
PLL Ground
PLL Filter Ext. Capacitor
Conn.
Crystal Output
Crystal Input (Clock Input)
22
23
24
19
21
22
E7
C8
D7
VSS_4
VDD_4
TESTEN
I
Ground
Supply Voltage
Test Enable
25
26
24
25
A7
B6
SDI_ADC
RESET
I
I
ADC Data Input
System Reset
27
28
26
27
LRCK_ADC
IN_CLK/
DATA_REQ
IODATA[0]
IODATA[1]
IODATA[2]
IODATA[3]
IODATA[4]
IODATA[5]
IODATA[6]
IODATA[7]
GPIO_STROBE
GPSO_REQ
GPSO_SCKR
GPSO_DATA
I
O
ADC left/Right Clock
Buffered Output Clock/
Data Request Signal
GPIO Data Line
GPIO Data Line
GPIO Data Line
GPIO Data Line
GPIO Data Line
GPIO Data Line
GPIO Data Line
GPIO Data Line
GPIO Strobe Signal
GPSO Request Signal
GPSO Serial Clock
GPSO Serial Data
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Note:
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20
18
16
14
37
39
41
43
35
4
28
33
ct
A5
C5
C7
E6
F6
F8
C3
E3
D2
F1
C2
G3
C6
A2
(s)
I/O
Function
Supply Voltage
Ground
i2C Serial Data +
Acknowledge
CMOS Input Pad Buffer
CMOS 4mA Output Drive
I2C Serial Clock
Receiver Serial Data
Receiver Serial Clock
Bit Enable
CMOS Input Pad Buffer
Interrupt Line/ADC Serial
Clock
Transmitter Serial Data (PCM
Data)
Transmitter Serial Clock
Transmitter Left/Right Clock
Oversampling Clock for DAC
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I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
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PAD Description
CMOS Input Pad Buffer
CMOS Input Pad Buffer
CMOS Input Pad Buffer
with pull up
CMOS Input Pad Buffer
CMOS 4mA Output Drive
CMOS 4mA Output Drive
CMOS 4mA Output Drive
CMOS Input Pad Buffer
CMOS 4mA Output Drive
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CMOS 4mA Output Drive
Specific Level Input Pad
(see paragraph 2.1)
CMOS Input Pad Buffer
with pull up
CMOS Input Pad Buffer
CMOS Input Pad Buffer
with pull up
CMOS Output Pad Buffer
CMOS 4mA Output Drive
CMOS 4mA Schmitt
Trigger
Bidir Pad Buffer
CMOS Output Pad Buffer
CMOS Input Pad Buffer
CMOS Output Pad Buffer
In functional mode TESTEN must be connected to VDD,
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STA015
ELECTRICAL CHARACTERISTICS: VDD = 3.3V ±0.3V; Tamb = 0 to 70°C; Rg = 50Ω unless otherwise
specified
DC OPERATING CONDITIONS
Symbol
VDD
Tj
Parameter
Value
Power Supply Voltage
2.4 to 3.6V
Operating Junction Temperature
-20 to 125°C
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Note
IIL
Low Level Input Current
Without pull-up device
Vi = 0V
-10
10
µA
1
IIH
High Level Input Current
Without pull-up device
Vi = VDD
-10
10
µA
1
Vesd
Electrostatic Protection
Leakage < 1µA
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2000
V
2
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Notes: 1. The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic
stress on the pin.
2. Human Body Model.
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
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Test Condition
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
Vol
Low Level Output Voltage
Voh
High Level Output Voltage
Min.
Typ.
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Max.
Unit
0.2*VDD
V
0.8*VDD
b
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-
Iol = Xma
Note
V
0.4V
0.85*VDD
V
1, 2
V
1, 2
Notes: 1. Takes into account 200mV voltage drop in both supply lines.
2. X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
Symbol
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Parameter
Ipu
Pull-up current
Rpu
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Test Condition
Min.
Typ.
Max.
Unit
Note
Vi = 0V; pin numbers 7, 24
and 26;
-25
-66
-125
µA
1
Equivalent Pull-up Resistance
50
kΩ
Notes: 1. Min. condition: VDD = 2.7V, 125°C Min process
Max. condition: VDD = 3.6V, -20°C Max.
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POWER DISSIPATION
Symbol
bs
PD
O
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Parameter
Power Dissipation
@ VDD = 2.4V
Test Condition
Min.
Typ
Max
Unit
Sampling_freq ≤24 kHz
76
mW
Sampling_freq ≤32 kHz
79
mW
Sampling_freq ≤48 kHz
85
mW
Note
STA015
Figure 3. Test Circuit
OUT_CLK/DATA_REQ
VDD
OCLK
12
SDI
5
SCR_INT
8
15
LRCK_ADC
27
23
XTI
21
100nF
XTO
20
22
VSS
SDI_ADC
25
100nF
VDD
BIT_EN
7
16
VSS
SCKR
6
13
VDD
4.7µF
LRCKT
11
14
VSS
PVDD
SCKT
10
2
100nF
VDD
SDO
9
100nF
VDD
SCL
4
1
VSS
SDA
3
28
10K
19
17
1K
TESTEN
RESET
470pF
VSS
PVDD
PVSS
PVSS
D00AU1143
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Test Load
VDD
Output
SDA
OUTPUT
VREF
CL
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Other Outputs
4.7nF
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PVSS
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Figure 4. Test Load Circuit
IOL
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24
26
18
100nF
4.7µF
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IOL
1mA
100µA
CL
VREF
100pF
3.6V
100pF
1.5V
IOH
100µA
D98AU967
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2.0 FUNCTIONAL DESCRIPTION
2.1 Clock Signal
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The STA015 input clock is derivated from an external source or from a industry standard crystal oscillator,
generating input frequencies of 10, 14.31818 or 14.7456 MHz.
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Other frequencies may be supported upon request to STMicroelectronics. Each frequency is supported
by downloading a specific configuration file, provided by STM XTI is an input Pad with specific levels.
Symbol
Parameter
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
Test Condition
Min.
VDD-0.8
Typ.
Max.
Unit
VDD-1.8
V
V
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STA015
CMOS compatibility
The XTI pad low and high levels are CMOS compatible; XTI pad noise margin is better than typical CMOS
pads.
TTL compatibility
The XTI pad low level is compatible with TTL while the high level is not compatible (for example if VDD =
3V TTL min high level = 2.0V while XTI min high level = 2.2V)
2.2 PLL & Clock Generator System
When STA015 receives the input clock, as described in Section 2.1, and a valid layer III input bit stream,
the internal PLL locks, providing to the DSP Core the master clock (DCLK), and to the Audio Output Interface the nominal frequencies of the incoming compressed bit stream. The STA015 PLL block diagram is
described in Figure 5.
The audio sample rates are obtained dividing the oversampling clock (OCLK) by software programmable
factors. The operation is done by STA015 embedded software and it is transparent to the user.
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The STA015 PLL can drive directly most of the ommercial DACs families, providing an over sampling
clock, OCLK, obtained dividing the VCO frequency with a software programmable dividers.
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Figure 5. PLL and Clocks Generation System
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2.3 STA015 Operational Modes
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The device can be configured in 4 different operational modes. To select one specific mode a dedicated
CHIP_MODE registers is available. For proper operation the following steps must be issued to switch between different modes:
– issue a software reset (SOFT_RESET register)
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– select the desired mode (CHIP_MODE register)
– run the device (RUN register)
Hereby is a short description of each available mode
ADPCM Encoder
This mode can be used to encode the incoming bitstream with 4 different compression algorithms.
Moreover different sample frequencies and word size are supported. For a detailed escription of this
features refer to the related registers.
ADPCM Decoder
This mode can be used when an ADPCM compressed bitstream must be decoded. The input interface
handling and control flow is the same as in the MP3 Mode.
BYPASS mode
Using this mode it’s possible to use the embedded post-processing controls (volume and tone controls)
to process an incoming uncompressed stereo audio stream. In this configuration ADC input is the only
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STA015
supported interface. This could be useful, for instance, to process audio data coming from an external
tuner or some other auxiliary source.
MP3 mode
In MP3 Mode (default mode) STA015 decodes the incoming bitstream, acting as a master of the data
communication from the source to itself. This control is done by a specific buffer management,
controlled by STA015 embedded oftware.
The data coming from the serial interface are stored in the input buffer, a 256 bytes long FIFO.
The feedback line DATA_REQ actually is the result of the h/w comparison between the writing address
of the FIFO and the constant value 252. This means that if the buffer is filled up with more than 252
bytes the DATA_REQ line goes low, requesting MCU to stop transmission: the maximum time to stop
transmitting is given by the time required to transmit 4 bytes (this time, in turn, depends on the bitstream
speed used to send MP3 data).
The input interface can receive data with a speed up to 20Mbit/s. The speed at which the FIFO is
emptied is equal to the MP3 nominal bitrate. Provided the FIFO is filled up with 252 bytes the time
required to empty it (in worst condition, which is 320kbit/s mpeg stream) is about 6ms. So if no more
data is received in this time the buffer will be emptied and this will badly affect the output audio.
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In this mode the fractional part of the PLL is disabled and the audio clocks are generated at nominal rates.
Fig. 6 describes the default DATA_REQ signal behaviour. Programming STA015 it is possible to invert the
polarity of the DATA_REQ line (register REQ_POL).
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In order to allow proper operation of the device in broadcast applications a special BRAODCAST MP3 decoding mode is available. When configured in BROADCAST mode the device will operate as a slave decoder and no more feedback will be generated to the data source.
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The output PCM clock will be automatically adjusted by the embedded DSP in order to follow the incoming
bitstream rate and to avoid input buffer underrun/overrun. A special configuration file must be used to enable this operational mode: the file must be downloaded via I2C link after device power-on. Please contact
your local ST branch to have more information about.
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Figure 6. DATA_REQ control line
SOURCE STOPS TRANSMITTING DATA
DATA_REQ
(s)
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SOURCE STOPS TRANSMITTING DATA
SOURCE SEND DATA TO STA015
D00AU1144
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2.4 STA015 Decoding States
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There are three different decoder states: Idle, Init, and Decode. Commands to change the decoding
states are described in the STA015 I2C registers description.
Idle Mode
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IIn this mode (entered after a S/W or H/W reset) the decoder is waiting for the RUN command. This mode
should be used to initialize the configuration registers of the device. The DAC connected to STA015 can
be initialized during this mode (set MUTE to 1).
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MUTE to 1).
PLAY
MUTE
Clock State
PCM Output
X
0
Not Running
0
X
1
Running
0
9/56
STA015
Init Mode
"PLAY" and "MUTE" changes are ignored in this mode. The internal state of the decoder will be updated
only when the decoder changes from the state "init" to the state "decode". The "init" phase ends when the
first decoded samples are at the output stage of the device.
Decode Mode
This mode is completely described by the following table:
PLAY
MUTE
Clock State
PCM Output
Decoding
0
0
Not Running
0
No
0
1
Running
0
No
1
0
Running
Decoded Samples
Yes
1
1
Running
0
Yes
Figure 7. MPEG Decoder Interface
c
u
d
µP
XTI
FILT
XTO
IIC
SCL
DATA_REQ
PLL
SDA
IIC
SDI
SCKR
DATA
SOURCE
MPEG
DECODER
SCKT
BIT_EN
o
s
b
O
RX
)
s
(
ct
Figure 8. Serial Input Interface Clocks
SDI
r
P
e
SCKR
t
e
l
o
O
bs
DAC
TX
DATA
OCLK
IGNORED
u
d
o
SCKR
BIT_EN
DATA VALID
o
r
P
LRCKT
SERIAL AUDIO INTERFACE
D98AU912
e
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SDO
)
s
t(
SCLK_POL=0
SCLK_POL=4
D98AU968A
DATA IGNORED
3.0 INTERFACE DESCRIPTION
3.1 Serial Input Interface
STA015 receives the input data (MSB first) through the Serial Input Interface (Fig.7). It is a serial communication interface connected to the SDI (Serial Data Input) and SCKR (Receiver Serial Clock).
The interface can be configured to receive data sampled on both rising and falling edge of the SCKR clock.
The BIT_EN pin, when set to low, forces the bitstream input interface to ignore the incoming data. For
10/56
STA015
proper operation BIT_EN line should be toggled only when SCKR is stable low (for both SCLK_POL configuration). The possible configurations are described in Fig. 8.
3.2 GPSO Output Interface
In order to retrieve ADPCM encoded data a General Purpose Serial Output interface is available (in
TQFP44 and LFBGA64 packages only). The maximum frequency for GPSO_SCKR clock is the DSP system clock frequency divided by 3 (i.e. 8.192 MHz @ 24.58MHz). The interface is based on a simple and
configurable 3-lines protocol, as described by figure 10.
3.3 PCM Output Interface
The decoded audio data are output in serial PCM format. The interface consists of the following signals:
SDO
PCM Serial Data Output
SCKT
PCM Serial Clock Output
LRCLK
Left/Right Channel Selection Clock
)
s
t(
The output samples precision is selectable from 16 to 24 bits/word, by setting the output precision with
PCMCONF (16, 18, 20 and 24 bits mode) register. Data can be output either with the most significant bit
first (MS) or least significant bit first LS), selected by writing into a flag of the PCMCONF register.
c
u
d
Figure 9 gives a description of the several STA015 PCM Output Formats. The sample rates set decoded
by STA015 is described in Table 1.
o
r
P
To enable the GPSO interface bit GEN of GPSO_ENABLE register must be set. Using the GPSO_CONF
register the protocol can be configured in order to provide outcoming data on rising/ falling edge of
GPSO_SCKR input clock; the GPSO_REQ request signal polarity (usually connected to an MCU interrupt
line) can be configured as well.
Figure 9. PCM Output Formats
)
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o
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-
u
d
o
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e
t
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l
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Table 1. MPEG Sampling Rates (KHz)
MPEG 1
MPEG 2
MPEG 2.5
48
24
12
44.1
22.05
11.025
32
16
8
11/56
STA015
3.4 ADC Inteface
Beside the serial input interface based on SDI and SCKR lines a 3 wire flexible and user configurable input
interface is also available, suitable to interface with most A/D converters. To configure this interface 4 specific I2C registers are available (ADC_ENABLE, ADC_CONF, ADC_WLEN and ADC_WPOS). Refer to
registers description for more details.
3.5 General Purpose I/O Interface
A new general purpose I/O interface has been added to this device (TQFP44 and LFBGA64 only). Actually
only the strobe line is used in ADPCM encoding mode to provide an interrupt; other pins are reserved for
future use. The related configuration register is GPIO_CONF. See the following summary for related pin
usage:
Name
Description
Dir
I/ODATA [0]
..................
I/ODATA [7]
GPIO data line
I/O
.....
I/O
GPIO_STROBE
GPIO strobe line
I/O
c
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d
4.0 ADPCM ENCODING: OVERVIEW
)
s
t(
According to the previously described interfaces there are 4 ways to manage ADPCM data stream while
encoding. Input interface can be either the serial receiver block (SDI + SCKR + DATA_REQ lines) or the
ADC specific interface.
o
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P
Output interfaces can be either the I2C bus (with or without interrupt line) or the GPSO high-speed serial
interface (GPSO_REQ + GPSO_ DATA + GPSO_SCKR lines). This result in the following 4 methods to
handle encoding flow:
e
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so
INPUT (data to encode)
Output (encoded data)
Available on package
ADC I/F (SDI_ADC + LRCK_ADC + SCK_ADC)
GPSO I/F (GPSO_REQ + GPSO_DATA +
GPSO_SCKR)
TQFP44/LFBGA64
ADC I/F (SDI_ADC + LRCK_ADC + SCK_ADC)
I2C + Interrupt (SCL + SDA +DATA_REQ)
SO28/TQFP44
LFBGA64
(s)
SERIAL I/F (SCKR + SDI + DATA_REQ)
ct
SERIAL I/F (SCKR + SDI + DATA_REQ) (*)
u
d
o
(*) STA013 Compatible mode
r
P
e
Figure 10.
t
e
l
o
s
b
O
b
O
-
GPSO I/F (GPSO_REQ + GPSO_DATA +
GPSO_SCKR)
I2C (polling) (SCL + SDA)
GPSO_SCKR
STA015
GPSO_DATA
GPSO_REQ
MCU
GPSO_SCKR
GPSO_REQ
GPSO_DATA
D00AU1145
12/56
TQFP44/LFBGA64
SO28/TQFP44
LFBGA64
STA015
Figure 11.
LRCK_ADC
SDI_ADC
SCK_ADC
GPSO_REQ
MUX
ADC I/F
GPSO
GPSO_DATA
GPSO_SCKR
ENCOD
ENGINE
SDI
SCKR
DATA_REQ
SERIAL
RECEIVER
SDA
I2C
SCL
DATA_REQ
D99AU1064
The following 4 figures (fig. 12, 13, 14, 15) show the available connection diagrams as far as ADPCM encoding function. As shown in the figures some configuration is not available in SO28 package.
Figure 12. Input from BITSTREAM, Output from I2C
SDI
SCKR
MCU
SCKT
SO28
TQFP44
LFBGA64
DATA_REQ
BIT_EN
SDO
DAC
OCLK
I2C
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le
D99AU1121A
STA013 compatible mode
Figure 13. Input from ADC, Output from
I2C
I2C
(t s)
DATA_REQ
c
u
d
MCU
o
r
P
e
t
e
l
o
bs
+IRQ
LRCKT
SCKT
STA015
I2C
STA015
LRCK_ADC
SCK_ADC
ADC
SDI_ADC
DAC
OCLK
LRCKT
DATA_REQ
MASTER
o
r
P
o
s
b
O
SO28
TQFP44
LFBGA64
SLAVE
O
)
s
t(
SDO
SDI_ADC
ADC
MCU
c
u
d
LRCKT
SO28
TQFP44
LFBGA64
SCKT
DAC
SDO
OCLK
D99AU1123A
13/56
STA015
Figure 14. Input from BITSTREAM, Output from GPSO
GPSO_DATA
GPSO_SCKR
GPSO_REQ
SDI
LRCKT
SCKR
MCU
DATA_REQ
BIT_EN
I2C
SCKT
STA015
SDO
TQFP44
LFBGA64
OCLK
DAC
D99AU1122A
Figure 15. Input from ADC, Output from GPSO
c
u
d
GPSO_DATA
MCU
GPSO_SCKR
LRCKT
GPSO_REQ
SCKT
STA015
SCK_ADC
ADC
SDI_ADC
SDO
TQFP44
LFBGA64
e
t
le
OCLK
so
MASTER
5.0 I2C BUS SPECIFICATION
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P
DAC
LRCK_ADC
)
s
t(
D99AU1124A
b
O
-
The STA015 supports the I2C protocol. This protocol defines any device that sends data on to the bus as
a transmitter and any device that reads the data as a receiver. The device that controls the data transfer
is known as the master and the others as the slave. The master always starts the transfer and provides
the serial clock for synchronisation. The STA015 is always a slave device in all its communications.
)
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(
ct
5.1 COMMUNICATION PROTOCOL
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3.1.0 - Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock
is high are used to identify START or STOP condition.
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5.1.1 Start condition
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START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is
stable in the high state. A START condition must precede any command for data transfer.
s
b
O
5.1.2 Stop condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable
in the high state. A STOP condition terminates communications between STA015 and the bus master.
5.1.3 Acknowledge bit
An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either master or
slave, releases the SDA bus after sending 8 bit of data. During the 9th clock pulse the receiver pulls the
SDA bus low to acknowledge the receipt of 8 bits of data.
14/56
STA015
5.1.4 Data input
During the data input the STA015 samples the SDA signal on the rising edge of the clock SCL. For correct
device operation the SDA signal has to be stable during the rising edge of the clock and the data can
change only when the SCL line is low.
5.2 DEVICE ADDRESSING
To start communication between the master and the STA015, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode. The 7 most significant bits are the device address identifier,
corresponding to the I2C bus definition. For the STA015 these are fixed as 1000011.
The 8th bit (LSB) is the read or write operation RW, this bit is set to 1 in read mode and 0 for write mode.
After a START condition the STA015 identifies on the bus the device address and, if a match is found, it
acknowledges the identification on SDA bus during the 9th bit time. The following byte after the device
identification byte is the internal space address.
5.3 WRITE OPERATION (see fig. 16)
c
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)
s
t(
Following a START condition the master sends a device select code with the RW bit set to 0. The STA015
acknowledges this and waits for the byte of internal address.
After receiving the internal bytes address the STA015 again responds with an acknowledge.
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5.3.1 Byte write
In the byte write mode the master sends one data byte, this is acknowledged by STA015. The master then
terminates the transfer by generating a STOP condition.
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5.3.2 Multibyte write
The multibyte write mode can start from any internal address. The transfer is terminated by the master
generating a STOP condition.
Figure 16. Write Mode Sequence
ACK
ACK
DEV-ADDR
BYTE
WRITE
START
SUB-ADDR
MULTIBYTE
WRITE
(s)
RW
ct
ACK
DEV-ADDR
START
du
o
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b
O
-
ACK
DATA IN
ACK
STOP
ACK
ACK
SUB-ADDR
DATA IN
DATA IN
RW
o
r
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STOP
D98AU825B
Figure 17. Read Mode Sequence
CURRENT
ADDRESS
READ
s
b
O
t
e
l
o
ACK
DEV-ADDR
START
RANDOM
ADDRESS
READ
NO ACK
DATA
RW
STOP
ACK
ACK
DEV-ADDR
RW
START
START
RW= ACK
HIGH
SEQUENTIAL
CURRENT
READ
DEV-ADDR
ACK
STOP
RW
ACK
DATA
NO ACK
DATA
DEV-ADDR
SUB-ADDR
ACK
NO ACK
DATA
DATA
STOP
START
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV-ADDR
START
RW
ACK
START
RW
ACK
ACK
DATA
DEV-ADDR
SUB-ADDR
DATA
NO ACK
DATA
D98AU826A
STOP
15/56
STA015
5.4 READ OPERATION (see Fig. 17)
5.4.1 Current byte address read
The STA015 has an internal byte address counter. Each time a byte is written or read, this counter is incremented. For the current byte address read mode, following a START condition the master sends the
device address with the RW bit set to 1.
The STA015 acknowledges this and outputs the byte addressed by the internal byte address counter. The
master does not acknowledge the received byte, but terminates the transfer with a STOP condition.
5.4.2 Sequential address read
This mode can be initiated with either a current address read or a random address read. However in this
case the master does acknowledge the data byte output and the STA015 continues to output the next byte
in sequence. To terminate the streams of bytes the master does not acknowledge the last received byte,
but terminates the transfer with a STOP condition. The output data stream is from consecutive byte addresses, with the internal byte address counter automatically incremented after one byte output.
6.0 I2C REGISTERS
c
u
d
The following table gives a description of the MPEG Source Decoder (STA015) register list.
The first column (HEX_COD) is the hexadecimal code for the sub-address.
The second column (DEC_COD) is the decimal code.
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The third column (DESCRIPTION) is the description of the information contained in the register.
The fourth column (RESET) inidicate the reset value if any. When no reset value is specifyed, the default
is "undefined".
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le
The fifth column (R/W) is the flag to distinguish register "read only" and "read and write", and the useful
size of the register itself. Each register is 8 bit wide. The master shall operate reading or writing on 8 bits
only.
I2C REGISTERS
HEX_COD
DEC_COD
$00
0
VERSION
$01
1
IDENT
$05
5
PLLCTL [7:0]
ct
R/W
R (8)
0xAC
R (8)
0xA1
R/W (8)
R/W (8)
6
PLLCTL [20:16] (MF[4:0]=M)
0x0C
7
PLLCTL [15:12] (IDF[3:0]=N)
0x00
R/W (8)
12
REQ_POL
0x01
R/W (8)
13
SCLK_POL
0x04
R/W (8)
15
ERROR_CODE
0x00
R (8)
16
SOFT_RESET
0x00
W (8)
R/W(8)
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$0F
$10
$13
19
PLAY
0x01
$14
20
MUTE
0x00
R/W(8)
$16
22
CMD_INTERRUPT
0x00
R/W(8)
R/W(8)
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$18
24
$40 - $51
64 - 81
$40
16/56
(s)
RESET
$07
$0D
O
DESCRIPTION
$06
$0C
bs
o
s
b
O
-
DATA_REQ_ENABLE
0x00
ADPCM_DATA_1 to ADPCM_DATA_18
0x00
R (8)
64
SYNCSTATUS
0x00
R (8)
$41
65
ANCCOUNT_L
0x00
R (8)
$42
66
ANCCOUNT_H
0x00
R (8)
$43
67
HEAD_H[23:16]
0x00
R(8)
$44
68
HEAD_M[15:8]
0x00
R(8)
STA015
I2C REGISTERS
$45
69
HEAD_L[7:0]
0x00
R(8)
$46
70
DLA
0x00
R/W (8)
$47
71
DLB
0xFF
R/W (8)
$48
72
DRA
0x00
R/W (8)
$49
73
DRB
0xFF
R/W (8)
$4D
77
CHIP_MODE
0x00
R/W (2)
R/W (1)
$4E
78
CRCR
0x00
$50
80
MFSDF_441
0x00
R/W (8)
$51
81
PLLFRAC_441_L
0x00
R/W (8)
$52
82
ADPCM_DATA_READY
0x00
R/W (1)
$52
82
PLLFRAC_441_H
0x00
R/W (8)
$53
83
ADPCM_SAMPLE_FREQ
0x00
R/W (4)
$54
84
PCM DIVIDER
0x03
R/W (8)
$55
85
PCMCONF
0x21
R/W (8)
86
PCMCROSS
0x00
$61
97
MFSDF (X)
0x07
$63
99
DAC_CLK_MODE
0x00
$64
100
PLLFRAC_L
0x46
$65
101
PLLFRAC_H
0x5B
$67
103
FRAME_CNT_L
$68
104
FRAME_CNT_M
$69
105
FRAME_CNT_H
$6A
106
AVERAGE_BITRATE
$71
113
SOFTVERSION
$72
114
RUN
0x00
R/W (8)
$77
119
TREBLE_FREQUENCY_LOW
0x00
R/W (8)
$78
120
TREBLE_FREQUENCY_HIGH
0x00
R/W (8)
$79
121
BASS_FREQUENCY_LOW
0x00
R/W (8)
$7A
122
BASS_FREQUENCY_HIGH
0x00
R/W (8)
$7B
123
TREBLE_ENHANCE
0x00
R/W (8)
$7C
124
BASS_ENHANCE
0x00
R/W (8)
R/W (8)
)
s
(
ct
125
126 - 181
$B6
R/W (8)
R/W (8)
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let
0x00
o
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b
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-
du
$7D
$7E - B5
R/W (8)
R/W (8)
R/W (8)
R (8)
0x00
R (8)
0x00
R (8)
0x00
R (8)
R (8)
TONE_ATTEN
0x00
ANC_DATA_1 to ANC_DATA_56
0x00
R (8)
182
ISR
0x00
R/W (1)
$B8
184
ADPCM_CONFIG
0x00
R/W (2)
$B9
185
GPSO_ENABLE
0x00
R/W (1)
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)
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$BA
186
GPSO_CONF
0x00
R/W (2)
$BB
187
ADC_ENABLE
0x00
R/W (1)
R/W (5)
$BC
188
ADC_CONF
0x00
$BD
189
ADPCM_FRAME_SIZE
0x00
R/W (8)
$BE
190
ADPCM_INT_CFG
0x00
R/W (8)
$BF
191
GPIO_CONF
0x00
R/W (2)
$C0
192
ADC_ WLEN
0x0F
R/W (5)
$C1
193
ADC_ WPOS
0x00
R/W (5)
$C2
194
ADPCM_SKIP_FRAME
0x00
R/W (8)
Notes: 1. The HEX_COD is the hexadecimal adress that the microcontroller has to generate to access the information.
2. RESERVED: register used for production test only, or for future use.
17/56
STA015
6.1 STA015 REGISTERS DESCRIPTION
The STA015 device includes 128 I2C registers. In this document, only the user-oriented registers are described. The undocumented registers are reserved. These registers must never be accessed (in Read or
in Write mode). The Read-Only registers must never be written.
The following table describes the meaning of the abbreviations used in the I2C registers description:
Symbol
Comment
NA
Not Applicable
UND
Undefined
NC
No Charge
RO
Read Only
WO
Write Only
R/W
Read and Write
R/WS
Read, Write in specific mode
VERSION
c
u
d
Address: 0x00 (00)
Type: RO
MSB
b7
b6
b5
b4
b3
V8
V7
V6
V5
V4
b2
e
t
le
V3
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LSB
b1
b0
V2
V1
The VERSION register is read-only and it is used to identify the IC on the application board.
IDENT
Address: 0x01
Type: RO
Software Reset: 0xAC
)
s
(
ct
Hardware Reset: 0xAC
MSB
u
d
o
o
s
b
O
-
LSB
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
1
1
0
0
r
P
e
IDENT is a read-only register and is used to identify the IC on an application board. IDENT always has the
value "0xAC"
t
e
l
o
PLLCTL
Address: 0x05
O
bs
Type: R/W
Software Reset: 0x21
Hardware Reset: 0x21
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
XTO_BUF
XTODIS
OCLKEN
SYS2OCLK
PPLDIS
XTI2DSPCLK
XTI2OCLK
UPD_FRAC
18/56
STA015
UPD_FRAC: when is set to 1, update FRAC in the switching circuit. It is set to 1 after autoboot.
XTI2OCLK: when is set to 1, use the XTI as input of the divider X instead of VCO output. It is set to 0 on
HW reset.
XTI2DSPCLK: when is to 1, set use the XTI as input of the divider S instead of VCO output. It is set to 0
on HW reset.
PLLDIS: when set to 1, the VCO output is disabled. It is set to 0 on HW reset.
SYS2OCLK: when is set to 1, the OCLK frequency is equal to the system frequency. It is useful for testing.
It is set to 0 on HW reset.
OCLKEN: when is set to 1, the OCLK pad is enable as output pad. It is set to 1 on HW reset.
XTODIS: when is set to 1, the XTO pad is disable. It is set to 0 on HW reset.
XTO_BUF: when this bit is set, the pin nr. 28 (OUT_CLOCK/DATA_REQ) is enabled. It is set to 0 after
autoboot.
PLLCTL (M)
Address: 0x06 (06)
c
u
d
Type: R/W
Software Reset: 0x0C
Hardware Reset: 0x0C
PLLCTL (N)
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le
Address: 0x07 (07)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
)
s
t(
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r
P
o
s
b
O
-
The M and N registers are used to configure the STA015 PLL by DSP embedded software.
M and N registers are R/W type but they are completely controlled, on STA015, by DSP software.
)
s
(
ct
REQ_POL
Address: 0x0C (12)
Type: R/W
u
d
o
Software Reset: 0x01
Hardware Reset: 0x00
r
P
e
The REQ_POL registers is used to program the polarity of the DATA_REQ line.
MSB
s
b
O
t
e
l
o
LSB
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
1
Default polarity (the source sends data when the DATA_REQ line is high)
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
1
0
1
Inverted polarity (the source sends data when the ATA_REQ line is low)
19/56
STA015
SCKL_POL
Address: 0x0D (13)
Type: R/W
Software Reset: 0x04
Hardware Reset: 0x04
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
0
0
0
(1)
1
0
0
(2)
X = don’t care
SCKL_POL is used to select the working polarity of the Input Serial Clock (SCKR).
)
s
t(
(1) If SCKL_POL is set to 0x00, the data (SDI) are sent with the falling edge of SCKR and sampled on the
rising edge.
c
u
d
(2) If SCKL_POL is set to 0x04, the data (SDI) are sent with the rising edge of SCKR and sampled on the
falling edge.
ERROR_CODE
Address: 0x0F (15)
e
t
le
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
MSB
o
s
b
O
-
b7
b6
b5
b4
X
X
EC5
EC4
)
s
(
ct
X = don’t care
o
r
P
LSB
b3
b2
b1
b0
EC3
EC2
EC1
EC0
ERROR_CODE register contains the last error occourred if any. The codes can be as follows:
CODE
o
r
P
e
t
e
l
o
s
b
O
20/56
du
Description
0x00
No error since the last SW or HW Reset
0x01
CRC Failure
0x02
DATA not available
0x04
Ancillary data not read
0x10
Audio synch word not found
0x2X
MPEG Header error
0x3X
MPEG Decoding errors
STA015
SOFT_RESET
Address: 0x10 (16)
Type: WO
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
X
X
X
X
X
X
X
b0
0
1
X = don’t care; 0 = normal operation; 1 = reset
)
s
t(
When this register is written, a soft reset occours. The STA015 core command register and the interrupt
register are cleared. The decoder goes in to idle mode.
c
u
d
PLAY
Address: 0x13 (19)
Type: R/W
Software Reset: 0x01
e
t
le
Hardware Reset: 0x01
MSB
b7
b6
b5
b4
X
X
X
X
X = don’t care; 0 = normal operation; 1 = play
)
s
(
ct
so
b3
b
O
X
o
r
P
LSB
b2
b1
b0
X
X
0
1
The PLAY command is handled according to the state of the decoder, as described in section 2.5. PLAY
only becomes active when the decoder is in DECODE mode.
u
d
o
MUTE
Address: 0x14
r
P
e
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
t
e
l
o
MSB
s
b
O
LSB
b7
b6
b5
b4
b3
b2
b1
X
X
X
X
X
X
X
b0
0
1
X = don’t care; 0 = normal operation; 1 = mute The MUTE command is handled according to the state of
the decoder, as described in section 2.5. MUTE sets the clock running.
21/56
STA015
CMD_INTERRUPT
Address: 0x16 (22)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
X
X
X
X
X
X
X
b0
0
1
X = don’t care;
0 = normal operation;
1 = write into I2C/Ancillary Data
)
s
t(
The INTERRUPT is used to give STA015 the command to write into the I2C/Ancillary Data Buffer (Registers: 0x7E ... 0xB5). Every time the Master has to extract the new buffer content it writes into this register,
setting it to a non-zero value.
c
u
d
DATA_REQ_ENABLE
Address: 0x18 (24)
Type: R/W
e
t
le
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
b6
b5
b4
b3
X
X
X
X
X
X
X
X
X
X
)
s
(
ct
o
s
b
O
-
o
r
P
LSB
b2
b1
b0
Description
0
X
X
buffered output clock
1
X
X
request signal
The DATA_REQ_ENABLE register is used to configure Pin n. 28 working as buffered output clock or data
request signal, used for multimedia mode.
The buffered Output Clock has the same frequency than the input clock (XTI)
SYNCSTATUS
u
d
o
r
P
e
Address: 0x40 (64)
Type: RO
t
e
l
o
Software Reset: 0x00
Hardware Reset: 0x00
s
b
O
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
SS1
SS0
0
0
Research of sync word
0
1
Wait for Confirmation
1
0
Synchronised
22/56
Description
STA015
ADPCM_DATA BUFFER
Address: 0x40 - 0x51 (64 - 81)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
LSB
b6
b5
b4
b3
b2
b1
b0
ENCODED DATA N to N+18
ANCCOUNT_L
Address: 0x41 (65)
Type: RO
Software Reset: 0x00
b1
c
u
d
AC1
AC0
Hardware Reset: 0x00
MSB
b7
b6
b5
b4
b3
b2
AC7
AC6
AC5
AC4
AC3
AC2
ANCCOUNT_H
Address: 0x42 (66)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
)
s
(
ct
ANCCOUNT_H
MSB
e
t
le
o
r
P
LSB
b0
o
s
b
O
-
LSB
b7
b6
b5
b4
b3
b2
b1
b0
AC15
AC14
AC13
AC12
AC11
AC10
AC9
AC8
u
d
o
)
s
t(
r
P
e
ANCCOUNT registers are logically concatenated and indicate the number of Ancillary Data bits available
at every correctly decoded MPEG frame.
t
e
l
o
HEAD_H[23:16]
MSB
O
bs
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
H20
H19
H18
H17
H16
x = don’t care
23/56
STA015
HEAD_M[15:8]
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
H15
H14
H13
H12
H11
H10
H9
H8
b7
b6
b5
b4
b3
b2
b1
b0
H7
H6
H5
H4
H3
H2
H1
H0
HEAD_L[7:0]
MSB
LSB
Address: 0x43, 0x44, 0x45 (67, 68, 69)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
c
u
d
Head[1:0] emphasis
Head[2] original/copy
Head[3] copyrightHead
[5:4] mode extension
Head[7:6] mode
e
t
le
Head[8] private bit
Head[9] padding bit
Head[11:10] sampling frequency index
Head[15:12] bitrate index
Head[16] protection bit
Head[18:17] layer
Head[19] ID
)
s
(
ct
Head[20] ID_ex
)
s
t(
o
r
P
o
s
b
O
-
The HEAD registers can be viewed as logically concatenated to store the MPEG Layer III Header content.
The set of three registers is updated every time the synchronisation to the new MPEG frame is achieved
The meaning of the flags are shown in the following tables:
u
d
o
MPEG IDs
r
P
e
IDex
0
s
b
O
t
e
l
o
ID
0
MPEG 2.5
0
1
reserved
1
0
MPEG 2
1
1
MPEG 1
Layer
in Layer III these two flags must be set always to "01".
Protection_bit
It equals "1" if no redundancy has been added and "0" if redundancy has been added.
24/56
STA015
Bitrate_index
indicates the bitrate (Kbit/sec) depending on the MPEG ID.
bitrate index
ID = 1
ID = 0
’0000’
free
free
’0001’
32
8
’0010’
40
16
’0011’
48
24
’0100’
56
32
’0101’
64
40
’0110’
80
48
’0111’
96
56
’1000’
112
64
’1001’
128
80
’1010’
160
96
’1011’
192
112
’1100’
224
128
’1101’
256
144
’1110’
320
160
’1111’
forbidden
o
r
P
forbidden
e
t
le
Sampling Frequency
c
u
d
)
s
t(
indicates the sampling frequency of the encoded audio signal (KHz) depending on the MPEG ID
so
MPEG2.5
16
8
reserved
reserved
Sampling Frequency
MPEG1
MPEG2
’00’
44.1
22.05
’01’
48
’10’
32
’11’
reserved
)
s
(
ct
Padding bit
b
O
-
24
11.03
12
if this bit equals ’1’, the frame contains an additional slot to adjust the mean bitrate to the sampling frequency, otherwise this bit is set to ’0’.
u
d
o
Private bit
r
P
e
Bit for private use. This bit will not be used in the future by ISO/IEC.
t
e
l
o
Mode
O
bs
Indicates the mode according to the following table. The joint stereo mode is intensity_stereo and/or
ms_stereo.
mode
mode specified
’00’
stereo
’01’
joint stereo (intensity_stereo and/or ms_stereo)
’10’
dual_channel
’11’
single_channel (mono)
25/56
STA015
Mode extension
These bits are used in joint stereo mode. They indicates which type of joint stereo coding method is applied. The frequency ranges, over which the intensity_stereo and ms_stereo modes are applied, are implicit in the algorithm.
Copyright
If this bit is equal to ’0’, there is no copyright on the bitstream, ’1’ means copyright protected.
Original/Copy
This bit equals ’0’ if the bitstream is a copy, ’1’ if it is original.
Emphasis
Indicates the type of de-emphasis that shall be used.
emphasis
emphasis specified
’00’
none
’01’
50/15 microseconds
’10’
reserved
’11’
CCITT J, 17
c
u
d
DLA
e
t
le
Address: 0x46 (70)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
o
s
b
O
-
)
s
t(
o
r
P
LSB
b7
b6
b5
b4
b3
DLA7
DLA6
0
0
0
0
DLA5
DLA4
DLA3
0
0
0
0
0
0
:
:
0
1
r
P
e
:
1
b1
b0
Description
DLA2
DLA1
DLA0
OUTPUT ATTENUATION
0
0
0
0
NO ATTENUATION
0
0
0
1
-1dB
0
0
0
1
0
-2dB
:
:
:
:
:
:
0
0
0
0
0
-96dB
)
s
(
ct
u
d
o
0
b2
DLA register is used to attenuate the level of audio output at the Left Channel using the butterfly shown in
Fig. 18. When the register is set to 255 (0xFF), the maximum attenuation is achieved.
t
e
l
o
A decimal unit correspond to an attenuation step of 1 dB.
Figure 18. Volume Control and Output Setup
bs
DSP Left Channel
DLA
X
+
Output Left Channel
DLB
O
X
DRB
X
DRA
DSP Right Channel
26/56
X
+
Output Right Channel
D97AU667
STA015
DLB
Address: 0x47 (71)
Type: R/W
Software Reset: 0xFF
Hardware Reset: 0xFF
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
Description
DLB7
DLB6
DLB5
DLB4
DLB3
DLB2
DLB1
DLB0
OUTPUT ATTENUATION
0
0
0
0
0
0
0
0
NO ATTENUATION
0
0
0
0
0
0
0
1
-1dB
0
0
0
0
0
0
1
0
-2dB
:
:
:
:
:
:
:
:
:
0
1
1
0
0
0
0
0
-96dB
c
u
d
)
s
t(
DLB register is used to re-direct the Left Channel on the Right, or to mix both the Channels. Default value
is 0x00, corresponding at the maximum attenuation in the re-direction channel.
e
t
le
DRA
Address: 0x48 (72)
Type: R/W
Software Reset: 0X00
Hardware Reset: 0X00
MSB
LSB
b7
b6
b5
DRA7
DRA6
0
0
0
0
:
0
t
e
l
o
)
s
(
ct
b4
b3
b2
b1
b0
Description
DRA5
DRA4
DRA3
DRA2
DRA1
DRA0
OUTPUT ATTENUATION
0
0
0
0
0
0
NO ATTENUATION
0
0
0
0
1
-1dB
0
0
0
0
1
0
-2dB
:
:
:
:
:
:
:
:
1
1
0
0
0
0
0
-96dB
o
r
P
e
0
o
s
b
O
-
o
r
P
0
du
0
DRA register is used to attenuate the level of audio output at the Right Channel using the butterfly shown
in Fig. 11. When the register is set to255 (0xFF), the maximum attenuation is achieved.
bs
A decimal unit correspond to an attenuation stepof 1 dB.
O
27/56
STA015
DRB
Address: 0x49 (73)
Type: R/W
Software Reset: 0xFF
Hardware Reset: 0xFF
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
Description
DRB7
DRB6
DRB5
DRB4
DRB3
DRB2
DRB1
DRB0
OUTPUT ATTENUATION
0
0
0
0
0
0
0
0
NO ATTENUATION
0
0
0
0
0
0
0
1
-1dB
0
0
0
0
0
0
1
0
-2dB
:
:
:
:
:
:
:
:
:
0
1
1
0
0
0
0
0
-96dB
c
u
d
)
s
t(
DRB register is used to re-direct the Right Channel on the Left, or to mix both the Channels. Default value
is 0x00, corresponding at the maximum attenuation in the re-direction channel.
CHIP_MODE
Address: 0x4D (77)
e
t
le
Type: R/W
Hardware Reset: 0x00
o
r
P
Using this register it’s possible to select which operation will be performed by the DSP.
Possible values are:
0x00 - MP3 decoding
0x01 - Reserved
0x02 - ADPCM Encoder
)
s
(
ct
0x03 - ADPCM Decoder
0x04 - BYPASS mode
o
s
b
O
-
The DSP will check for the value of this register right after the RUN command has been issued (refer to
RUN register). After that no more checks will be performed: therefore a SOFT_RESET must be generated
in order to change the device mode.
u
d
o
r
P
e
CRCR
Address: 0x4E (78)
t
e
l
o
Type: R/W
Software Reset: 0x00
s
b
O
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
X
CRCEN
The CRC register is used to enable/disable the CRC check. If CRC_EN bit is cleared, the CRC value encoded in the bitstream is checked against the hardware one. If a discrepance occurs, the current frame is
skipped and the decoder is muted. The ERROR_CODE register is affected with the value 0x01.
28/56
STA015
If CRC_EN bit is set, the result of the CRC check is ignored, but the ERROR_CODE register is nevertheless affected with the value 0x01 if a discrepance has occurred.
MFSDF_441
Address: 0x50 (80)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
M4
M3
M2
M1
M0
This register contains the value for the PLL X driver for the 44.1KHz reference frequency.
The VCO output frequency, when decoding 44.1KHz bitstream, is divided by (MFSDF_441 +1)
c
u
d
PLLFRAC_441_L
Address: 0x51 (81)
Type: R/W
Software Reset: 0x00
e
t
le
Hardware Reset: 0x00
MSB
b7
b6
b5
b4
b3
PF7
PF6
PF5
PF4
PF3
ADPCM_DATA_READY
)
s
(
ct
Address: 0x52 (82)
Type: R/W
Software Reset: 0x00
u
d
o
Hardware Reset: 0x00
MSB
r
P
e
so
b
O
-
)
s
t(
o
r
P
LSB
b2
b1
b0
PF2
PF1
PF0
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
X
ADR
t
e
l
o
ADR: Adpcm Data Ready
This bit signal ADPCM encoded data are ready to be retrieved.
s
b
O
PLLFRAC_441_H
Address: 0x52 (82)
Type: R/W
Software Reset: 0x00
29/56
STA015
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
PF15
PF14
PF13
PF12
PF11
PF10
PF19
PF8
The registers are considered logically concatenated and contain the fractional values for the PLL, for
44.1KHz reference frequency.
(see also PLLFRAC_L and PLLFRAC_H registers)
ADPCM_SAMPLE_FREQ
Address: 0x53 (83)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
c
u
d
MSB
LSB
b7
b6
b5
X
X
X
b4
b3
b2
ADPCM_SF
e
t
le
ADPCM_SF: Adpcm Sample Frequency
0x02
8KHz
0x0A
32KHz
PCMDIVIDER
)
s
(
ct
Address: 0x54 (84)
Type: RW
Software Reset: 0x01
u
d
o
Hardware Reset: 0x01
MSB
r
P
e
b0
o
r
P
o
s
b
O
16KHz
0x0E
b1
LSB
b7
b6
b5
b4
b3
b2
b1
b0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
t
e
l
o
)
s
t(
PCMDIVIDER is used to set the frequency ratio between the OCLK (Oversampling Clock for DACs), and
the SCKT (Serial Audio Transmitter Clock).
The relation is the following:
s
b
O
OCLK_freq SCKT_freq = --------------------------------------------2 ( 1 + PCM_DIV )
The Oversampling Factor (O_FAC) is related to OCLK and SCKT by the following expression:
1) OCLK_freq = O_FAC * LRCKT_ Freq (DAC relation)
2) OCLK_ Freq = 2 * (1+PCM_DIV) * 32* LRCKT_Freq (when 16 bit PCM mode is used)
3) OCLK_ Freq = 2 * (1+PCM_DIV) * 64* LRCKT_Freq (when 32 bit PCM mode is used)
30/56
STA015
4) PCM_DIV = (O_FAC/64) - 1 in 16 bit mode
5) PCM_DIV = (O_FAC/128) - 1 in 32 bit mode
Example for setting:
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
0
0
0
0
0
1
1
1
16 bit mode
512 x Fs
0
0
0
0
0
1
0
1
16 bit mode
384 x Fs
0
0
0
0
0
0
1
1
16 bit mode
256 x Fs
0
0
0
0
0
0
1
1
32 bit mode
512 x Fs
0
0
0
0
0
0
1
0
32 bit mode
384 x Fs
0
0
0
0
0
0
0
1
32 bit mode
256 x Fs
for 16 bit PCM Mode
for 32 bit PCM Mode
O_FAC = 512 ; PCM_DIV = 7
O_FAC = 512 ; PCM_DIV = 3
O_FAC = 256 ; PCM_DIV = 3
O_FAC = 256 ; PCM_DIV = 1
O_FAC = 384 ; PCM_DIV = 5
O_FAC = 384 ; PCM_DIV = 2
Address: 0x55 (85)
Type: R/W
Software Reset: 0x21
Hardware Reset: 0x21
MSB
b6
b5
b4
b3
X
ORD
DIF
INV
FOR
X
1
X
0
X
X
t
e
l
o
X
O
0
o
r
P
e
X
X
o
s
b
O
-
)
s
t(
o
r
P
LSB
b7
X
c
u
d
e
t
le
PCMCONF
bs
Description
1
ct
(s)
du
b2
SCL
b1
b0
PREC (1)
PREC (1)
Description
PCM order the LS bit is transmitted First
PCM order the MS bit is transmitted First
The word is right aligned
The word is left aligned
0
LRCKT Polarity compliant to I2S format
1
LRCKT Polarity inverted
0
I2S format
1
Different formats
X
1
Data are sent on the rising edge of SCKT
X
0
Data are sent on the falling edge of SCKT
X
0
0
16 bit mode (16 slots transmitted)
X
0
1
18 bit mode (32 slots transmitted)
X
1
0
20 bit mode (32 slots transmitted)
X
1
1
24 bit mode (32slots transmitted)
31/56
STA015
PCMCONF is used to set the PCM Output Interface configuration:
ORD: PCM order. If this bit is set to’1’, the LS Bit is transmitted first, otherwise MS Bit is transmiited first.
DIF: PCM_DIFF. It is used to select the position of the valid data into the transmitted word. This setting is
significant only in 18/20/24 bit/word mode.If it is set to ’0’ the word is right-padded, otherwise it is left-padded.
INV (fig.13): It is used to select the LRCKT clock polarity. If it is set to ’1’ the polarity is compliant to I2S
format (low -> left , high -> right), otherwise the LRCKT is inverted.
The default value is ’0’. (if I2S have to be selected, must be set to ’1’ in the TA013 configuration phase).
Figure 19. LRCKT Polarity Selection
LEFT
LRCKT
LEFT
INV_LRCLK=1
RIGHT
RIGHT
LEFT
LRCKT
LEFT
c
u
d
INV_LRCLK=0
D00AU1192
FOR: FORMAT is used to select the PCM Output Interface format.
After hw and sw reset the value is set to 0 corresponding to I2S format.
e
t
le
)
s
t(
o
r
P
SCL (fig.14): used to select the Transmitter Serial Clock polarity. If set to ’1’ the data are sent on the falling
edge and sampled on the rising. This last option is the most commonly used by the commercial DACs.
The default configuration for this flag is ’0’.
Figure 20. SCKT Polarity Selection
)
s
(
ct
o
s
b
O
-
u
d
o
PREC [1:0]: PCM PRECISION
r
P
e
It is used to select the PCM samples precision, as follows:
’00’: 16 bit mode (16 slots transmitted)
’01’: 18 bit mode (32 slots transmitted)
t
e
l
o
’10’: 20 bit mode (32 slots transmitted)
’11’: 24 bit mode (32 slots transmitted)
s
b
O
The PCM samples precision in STA015 can be 16 or 18-20-24 bits.
When STA015 operates in 16 (18-20-24) bits mode, the number of bits transmitted during a LRCLT period
is 32 (64).
32/56
STA015
PCMCROSS
Address: 0x56 (86)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
Description
X
X
X
X
X
X
0
0
Left channel is mapped on the left output.
Right channel is mapped on the Right output
X
X
X
X
X
X
0
1
Left channel is duplicated on both Output channels.
X
X
X
X
X
X
1
0
Right channel is duplicated on both Output channels
X
X
X
X
X
X
1
1
Right and Left channels are toggled
c
u
d
The default configuration for this register is ’0x00’.
MFSDF (X)
Address: 0x61 (97)
Type: R/W
e
t
le
Software Reset: 0x07
Hardware Reset: 0x07
so
MSB
b7
b6
b5
b4
X
X
X
M4
b
O
b3
M3
)
s
t(
o
r
P
LSB
b2
b1
b0
M2
M1
M0
The register contains the values for PLL X divider (see Fig. 7).
)
s
(
ct
The value is changed by the internal STA015 Core, to set the clocks frequencies, according to the incoming bitstream. This value can be even set by the user to select the PCM interface configuration.
The VCO output frequency is divided by (X+1). This register is a reference for 32KHz and 48KHz input
bitstream.
u
d
o
DAC_CLK_MODE (99)
r
P
e
Address: 0x63
Type: RW
t
e
l
o
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
X
MODE
Software Reset: 0x00
Hardware Reset: 0x00
s
b
O
MSB
LSB
This register is used to select the operating mode for OCLK clock signal. If it is set to “1”, the OCLK frequency is fixed, and it is mantained to the value fixed by the user even if the sampling frequency of the
incoming bitstream changes. It the MODE flag is set to f0f, the OCLK frequency changes, and can be set
to (512, 384, 256) * Fs. The default configuration for this mode is 256 * Fs. When this mode is selected,
33/56
STA015
the default OCLK frequency is 12.288 MHz.
PLLFRAC_L ([7:0])
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
PLLFRAC_H ([15:8])
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
PF15
PF14
PF13
PF12
PF11
PF10
PF9
PF8
c
u
d
Address: 0x64 - 0x65 (100 - 101)
Type: R/W
Software Reset: 0x46 | 0x5B
Hardware Reset: 0xNA | 0x5B
o
r
P
)
s
t(
The registers are considered logically concatenated and contain the fractional values for the PLL, used to
select the internal configuration. After Reset, the values are NA, and the operational setting are done when
the MPEG synchronisation is achieved.
e
t
le
The following formula describes the relationships among all the STA015 fractional PLL parameters:
o
s
b
O
-
1
MCLK_Freq
OCLK_Freq = ------------- ⋅ ------------------------------------ ⋅ M + 1 + FRAC
----------------X+1
N+1
65536
where:
FRAC=256 x FRAC_H + FRAC_L (decimal)
These registers are a reference for 48 / 24 / 12 / 32 / 16 / 8KHz audio.
)
s
(
ct
FRAME_CNT_L
u
d
o
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
FC7
FC6
FC5
FC4
FC3
FC2
FC1
FC0
b7
b6
b5
b4
b3
b2
b1
b0
FC15
FC14
FC13
FC12
FC11
FC10
FC9
FC8
b7
b6
b5
b4
b3
b2
b1
b0
FC23
FC22
FC21
FC20
FC19
FC18
FC17
FC16
r
P
e
FRAME_CNT_M
t
e
l
o
MSB
s
b
O
LSB
FRAME_CNT_H
MSB
34/56
LSB
STA015
Address: 0x67, 0x68, 0x69 (103 - 104 - 105)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
The three registers are considered logically concatenated and compose the Global Frame Counter as described in the table.
It is updated at every decoded MPEG Frame. The registers are reset on both hardware and software reset.
AVERAGE_BITRATE
Address: 0x6A (106)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
AB7
AB6
AB5
AB4
AB3
AB2
AB1
o
r
P
c
u
d
b0
)
s
t(
AB0
AVERAGE_BITRATE is a read-only register and it contains the average bitrate of the incoming bitstream
divided by two.
e
t
le
The value is rounded with an accuracy of 1 Kbit/sec.
SOFTVERSION
Address: 0x71 (113)
Type: RO
MSB
o
s
b
O
-
b7
b6
b5
b4
SV7
SV6
SV5
SV4
)
s
(
ct
LSB
b3
b2
b1
b0
SV3
SV2
SV1
SV0
After the STA015 boot, this register contains the version code of the embedded software.
u
d
o
RUN
r
P
e
Address: 0x72 (114)
Type: RW
Software Reset: 0x00
t
e
l
o
Hardware Reset: 0x00
MSB
O
bs
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
X
RUN
Setting this register to 1, STA015 leaves the idle state, starting the decoding process.
The Microcontroller is allowed to set the RUN flag, once all the control registers have been initialized.
35/56
STA015
TREBLE_FREQUENCY_LOW
Address: 0x77 (119)
Type: RW
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
TF7
TF6
TF5
TF4
TF3
TF2
TF1
TF0
TREBLE_FREQUENCY_HIGH
Address: 0x78
Type: RW
Software Reset: 0x00
c
u
d
Hardware Reset: 0x00
MSB
)
s
t(
LSB
b7
b6
b5
b4
b3
TF15
TF14
TF13
TF12
TF11
b2
ro
b1
P
e
let
TF10
TF9
b0
TF8
The registers TREBLE_FREQUENCY-HIGH and TREBLE_FREQUENCY-LOW, logically concatenated
as a 16 bit wide register, are used to select the frequency, in Hz, where the selected frequency is +12dB
respect to the stop band. By setting these registers, the following rule must be kept:
Treble_Freq < Fs/2
BASS_FREQUENCY_LOW
Address: 0x79 (121)
Software Reset: 0x00
)
s
(
ct
Hardware Reset: 0x00
MSB
u
d
o
o
s
b
O
-
LSB
b7
b6
b5
b4
b3
b2
b1
b0
BF7
BF6
BF5
BF4
BF3
BF2
BF1
BF0
r
P
e
BASS_FREQUENCY_HIGH
Address: 0x7A (122)
t
e
l
o
Software Reset: 0x00
Hardware Reset: 0x00
O
bs
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
BF15
BF14
BF13
BF12
BF11
BF10
BF9
BF8
The registers BASS_FREQUENCY_HIGH and BASS_FREQUENCY_LOW, logically concatenated as a
16 bit wide register, are used to select the frequency, in Hz, where the selected frequency is -12dB respect
to the pass-band. By setting the BASS_FREQUENCY registers, the following rules must be kept:
36/56
STA015
Bass_Freq <= Treble_Freq
Bass_Freq > 0
(suggested range: 20 Hz < Bass_Freq < 750 Hz)
Example:
Bass = 200Hz
Treble = 3kHz
TFS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
1
0
1
1
1
0
1
1
1
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
BFS
c
u
d
TREBLE_ENHANCE
Address: 0x7B (123)
Software Reset: 0x00
Hardware Reset: 0x00
e
t
le
MSB
b7
b6
b5
b4
b3
TE7
TE6
TE5
TE4
TE3
o
s
b
O
-
Signed number (2 complement)
o
r
P
)
s
t(
LSB
b2
b1
b0
TE2
TE1
TE0
This register is used to select the enhancement or attenuation STA015 has to perform on Treble Frequency range at the digital signal.
A decrement (increment) of a decimal unit corresponds to a step of attenuation (enhancement) of 1.5dB.
)
s
(
ct
The allowed Attenuation/Enhancement range is [-18dB, +18dB].
MSB
b7
0
0
0
0
s
b
O
1
1
1
1
b5
0
0
0
0
b4
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
1
r
P
e
t
e
l
o
0
0
1
u
d
o
b6
0
0
0
0
b3
1
1
1
1
b2
1
0
0
0
b1
0
1
1
0
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
LSB
b0
0
1
0
1
:
:
1
0
1
:
:
1
0
0
0
ENHANCE/ATTENUATION
1.5dB step
+18
+16.5
+15
+13.5
+1
0
-1
+13.5
-15
-16.5
-18
37/56
STA015
BASS_ENHANCE
Address: 0x7C (1240
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
BE7
BE6
BE5
BE4
BE3
BE2
BE1
BE0
Signed number (2 complement)
This register is used to select the enhancement or attenuation STA015 has to perform on Bass Frequency
range at the digital signal. A decrement (increment) of a decimal unit corresponds to a step of attenuation
(enhancement) of 1.5dB.
The allowed Attenuation/Enhancement range is [-18dB, +18dB].
MSB
LSB
ENHANCE/ATTENUATION
1.5dB step
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
1
1
0
0
+18
0
0
0
0
1
0
1
1
+16.5
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
1
+13.5
e
t
le
:
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
)
s
(
ct
u
d
o
1
1
1
1
so
1
b
O
1
0
o
r
P
+15
:
0
c
u
d
)
s
t(
1
+1
0
-1
:
:
0
1
1
1
0
1
1
0
+13.5
-15
0
1
0
0
-16.5
0
1
0
0
-18
r
P
e
TONE_ATTEN
t
e
l
o
Address: 0x7D (125)
Type: RW
Software Reset: 0x00
O
bs
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
TA7
TA6
TA5
TA4
TA3
TA2
TA1
TA0
In the digital output audio, the full signal is achieved with 0 dB of attenuation. For this reason, before applying Bass & Treble Control, the user has to set the TONE_ATTEN register to the maximum value of en-
38/56
STA015
hancement is going to perform.
For example, in case of a 0 dB signal (max. level) only attenuation would be possible. If enhancement is
desired, the signal has to be attenuated accordingly before in order to reserve a margin in dB.
An increment of a decimal unit corresponds to a Tone Attenuation step of 1.5dB.
MSB
LSB
ATTENUATION
b7
b6
b5
b4
b3
b2
b1
b0
1.5dB step
0
0
0
0
0
0
0
0
0dB
0
0
0
0
0
0
0
1
-1.5dB
0
0
0
0
1
0
1
0
3dB
0
0
0
0
0
0
1
1
4.5dB
:
:
0
0
0
0
1
0
1
0
-15
0
0
0
0
1
0
1
1
-16.5
0
0
0
0
1
1
0
0
e
t
le
Address: 0x7E - 0xB5 (126 - 181)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
o
r
P
-18
ANCILLARY DATA BUFFER
c
u
d
)
s
t(
o
s
b
O
-
The STA015 contains 56 consecutive 8-bit registers corresponding to the maximum number of ancillary
data that may be contained in MPEG frame.
The ANCCOUNT_L and ANCOUNT_H registers contain the number of ancillary data bits available within
the current MPEG frame.
)
s
(
ct
To perform ancillary data reading a status register (0xB6 - INTERRUPT_STATUS_REGISTER) is available: bit 0 of this register should be polled by the microcontroller in order to understand when new data
are available.
u
d
o
r
P
e
s
b
O
t
e
l
o
0x7E
ANC_DATA_1
.......
.......
.......
.......
.......
.......
0xB5
ANC_DATA_56
0xB6
ISR
ISR
Address: 0xB6 (182)
Type: R/W
Software Reset: 0x00
39/56
STA015
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
X
0
1
X = don’t care;
0 = no ancillary data
1 = Ancillary Data Available
The ISR is used by the microcontroller to understand when a new ancillary data block is available.
After all ancillary data has been retrieved this bit must be cleared.
ADPCM_CONFIG
c
u
d
Address: 0xB8 (184)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
b6
b5
b4
b3
X
X
X
X
AA1
e
t
le
o
s
b
O
-
b2
AA0
o
r
P
)
s
t(
LSB
b1
b0
ASM_EN
AFM_EN
This register controls ADPCM engine and how data must be compressed.
AFM_EN
ADPCM Frame Mode Enable
0 = no frames (raw format)
)
s
(
ct
1 = select the framed output format for ADPCM encoded data
ASM_EN:
ADPCM Stereo Mode Enable
0 = Disable stereo mode
u
d
o
1 = Enable stereo mode
AA0,AA1:
ADPCM Algorithm selection The ADPCM encoding/decoding algorithm can be selected
according to the following table:
r
P
e
t
e
l
o
O
bs
AA1
AA0
0
0
DVI algorithm
0
1
G723-24 algorithm (24kbp/s)
1
0
G721 algorithm (32kbp/s)
1
1
G723-40 algorithm (40kbp/s)
The above bitrates refers to an 8 KHz 16 bits mono input stream.
Please note that 32KHz stereo mode is only available (both in encoding and decoding) with DVI algorithm
40/56
STA015
GPSO_ENABLE
Address: 0xB9 (185)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
X
GEN
This register enable/disable the GPSO interface.
Setting the GEN bit will enable the serial interface for ADPCM data retrieving. Reset GEN bit to disable
GPSO interface.
GPSO_CONF
c
u
d
Address: 0xBA (186)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
e
t
le
MSB
b7
b6
b5
b4
b3
X
X
X
X
X
so
o
r
P
)
s
t(
LSB
b2
b1
b0
X
GRP
GSP
b
O
-
GSP: GPSO clock polarity sing this bit the GPSO_SCKR polarity can be controlled. Clearing GSP bit data
on GPSO_DATA line will be provided on the rising edge of GPSO_SCKR (sampling on falling
edge). Setting GSP bit data are provided on falling edge of GPSO_SCKR (sampling on rising edge)
)
s
(
ct
GRP: GPSO Request Polarity This bit is used to determine the polarity of GPSO_REQ signal. If GRP bit
is cleared data are valid on GPSO_REQ signal high. If this bit is set data are valid on GPSO_REQ
signal low
u
d
o
ADC_ENABLE
Address: 0xBB (187)
r
P
e
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
t
e
l
o
MSB
s
b
O
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
X
ADCEN
This register controls if the ADPCM data to be encoded comes from A/D interface or from MP3 bitstream
input interface.
If ADCEN bit is set data to be encoded comes from ADC interface, otherwise data comes from MP3
stream interface
41/56
STA015
ADC_CONF
Address: 0xBC (188)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
ALRCS
ALRCP
ASCP
ADC
AIIS
Using this register the ADC input interface can be configured as follow:
AIIS: ADC I2S mode
0 = sample word must be aligned with LRCK (no I2S mode)
1 = sample word not aligned with LRCK (I2S compliant mode)
c
u
d
ADC: ADC Data Config.
0 = sample word is LSB first
1 = sample word is MSB first
ASCP: ADC Serial Clock Polarity
0 = Data is sampled on rising edge
1 = Data is sampled an falling edge
e
t
le
ALRCP: ADC Left/Right Clock Polarity
o
r
P
o
s
b
O
-
ALRCS: ADC Left/Right Clock Start value. This two
bits permit to determine Left/Right clock
usage according to the following table:
ALRCP
ALRCS
0
0
o
r
P
e
1
0
1
t
e
l
o
bs
O
0
1
)
s
(
ct
du
1
LEFT/RIGHT COUPLE
(Data1, Data2)
(Data3, Data4)
(0, 1)
(2, 3)
(0, 1)
(2, 3)
(1, 2)
(3, 4)
LRCK
DATA
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
D99AU1065
42/56
)
s
t(
STA015
ADPCM_FRAME_SIZE
Address: 0xBD (189)
Type: R/W
Software Reset: 0x13
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
AFS7
AFS6
AFS5
AFS4
AFS3
AFS2
AFS1
AFS0
The ADPCM frame size may be adjusted to match a trade-off between the bitrate overhead and the frame
length. The frame size (in bytes) is calculated as follow:
FRAME size = (ADPCM_FRAME_SIZE * 90) +108
The frame starts with a 12 bytes header:
– 6 bytes for DVI algorithm
c
u
d
– 96 bytes for G726 pack algorithms
ADPCM_INT_CFG
Address: 0xBE (190)
Type: R/W
e
t
le
Software Reset: 0x0B
Hardware Reset: 0x00
so
MSB
b7
b6
b5
b4
INTL6
INTL5
INTL4
INTL3
b3
b
O
-
INTL2
)
s
t(
o
r
P
LSB
b2
b1
b0
INTL1
INTL0
X
Using this register the ADPCM interrupt capability can be properly configured. INTL0 - INTL6 Interrupt
Length he interrupt length can be programmed, using this bits, from 0 up to 128 system clock cycles
)
s
(
ct
GPIO_CONF
Address: 0xBF (191)
u
d
o
Type: R/W
Software Reset: 0x00
r
P
e
Hardware Reset: 0x00
MSB
s
b
O
t
e
l
o
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
GOSP
GISP
This register controls how data are strobed on the GPIO interface.
GISP: GPIO Strobe Polarity in INPUT mode
0 = data strobed an falling edge
1 = data strobed on rising edge
GOSP: GPIO Strobe Polarity in OUTPUT mode
0 = non inverted
1 = inverted
43/56
STA015
ADC_WLEN
Address: 0xC0 (192)
Type: R/W
Software Reset: 0x0F
Hardware Reset: 0x0F
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
AWL4
AWL3
AWL2
AWL1
AWL0
To select ADC word length AWL4 through AWL0 bits can be used.
This 5 bit value must contain the size of the significant data bits minus one.
ADC_WPOS
Address: 0xC1 (193)
c
u
d
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
b6
b5
b4
b3
X
X
X
AWP4
AWP3
o
s
b
O
-
e
t
le
b2
AWP2
o
r
P
)
s
t(
LSB
b1
b0
AWP1
AWP0
These bits specify the position of the sample word referred to the LRCK slot boundary.
Bit AWP0 thru AWP4 must be programmed with the number of bits to ignore after the sample word.
ADPCM_SKIP_FRAME
)
s
(
ct
Address: 0xC2 (194)
Type: R/W
Software Reset:0x00
u
d
o
Hardware Reset: 0x00
MSB
r
P
e
LSB
b7
b6
b5
b4
b3
b2
b1
b0
ASF7
ASF6
ASF5
ASF4
ASF3
ASF2
ASF1
ASF0
t
e
l
o
This register is useful when decoding ADPCM frame-based streams in order to skip the specified number
of frames.
bs
The content of the register will automatically be decremented on each new frame and the skip process will
continue until the content reaches zero.
O
44/56
STA015
6.2 I/O CELL DESCRIPTION (pinout relative to TQFP44 package)
1) CMOS Tristate Output Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 2, 4, 13, 27, 33, 42, 44
EN
Z
A
OUTPUT PIN
MAX LOAD
Z
100pF
D98AU904
2) CMOS Bidir Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 3, 31
EN
IO
INPUT
PIN
CAPACITANCE
OUTPUT
PIN
MAX LOAD
IO
5pF
IO
100pF
A
ZI
c
u
d
D98AU905
3) CMOS Inpud Pad Buffer / Pin numbers 24, 26, 32, 34, 36, 40
A
e
t
le
INPUT PIN
Z
A
D98AU906
o
s
b
O
-
)
s
t(
o
r
P
CAPACITANCE
3.5pF
4) CMOS Inpud Pad Buffer with Active Pull-Up / Pin numbers 22, 25, 28, 38
A
(s)
ct
u
d
o
r
P
e
Z
INPUT PIN
CAPACITANCE
A
3.5pF
D98AU907
5) CMOS Schmitt Trigger Bidir Pad Buffer with active Pull-up, 4mA, with slew rate control/
Pin numbers 14, 16, 18, 20, 35, 37, 39, 41, 43
t
e
l
o
EN
O
bs
IO
INPUT
PIN
CAPACITANCE
OUTPUT
PIN
MAX LOAD
IO
5pF
IO
100pF
A
ZI
D00AU1150
45/56
STA015
6.3 TIMING DIAGRAMS
6.3.1 Audio DAC Interface
a) OCLK in output. The audio PLL is used to clock the DAC
OCLK (OUTPUT)
SDO
tsdo
SCKT
tsckt
LRCLK
tlrclk
c
u
d
D98AU969
tsdo = 3.5 + pad_timing (Cload_SDO) - pad_timing (Cload_ OCLK)
tsckt = 4 + pad_timing (Cload_SCKT) - pad_timing (Cload_ OCLK)
tlrckt = 3.5 + pad_timing (Cload_LRCCKT) - pad_timing (Cload_ OCLK)
e
t
le
Pad-timing versus load
Load (pF)
25
)
s
t(
o
r
P
Pad_timing
o
s
b
O
-
2.90ns
50
3.82ns
75
4.68ns
100
5.52ns
)
s
(
ct
Cload_XXX is the load in pF on the XXX output. pad_timing (Cload_XXX) is the propagation delay added
to the XXX pad due to the load.
b) OCLK in input.
u
d
o
OCLK (INPUT)
r
P
e
t
e
l
o
s
b
O
thi
tlo
SDO
tsdo
SCKT
tsckt
LRCLK
tlrclk
toclk
46/56
D98AU970
STA015
Thi min = 3ns
Tlo min = 3ns
Toclk min = 25ns
tsdo = 5.5 + pad_timing (Cload_SDO) ns
tsckt = 6 + pad_timing (Cload_SCKT) ns
tlrckt = 5.5 + pad_timing (Cload_LRCKT) ns
6.3.2 Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 0
BIT_EN
t_biten
t_biten
tsckr_min_period
tsckr_min_low
SCKR
SCLK_POL=0
tsckr_min_high
IGNORED
SDI
VALID
tsdi_setup
c
u
d
IGNORED
tsdi_hold
D98AU971A
o
r
P
6.3.3 Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 1
e
t
le
BIT_EN
t_biten
t_biten
tsckr_min_period
so
tsckr_min_low
SCKR
tsckr_min_high
IGNORED
SDI
IGNORED
)
s
(
ct
tsdi_setup_min = 2ns
tsdi_hold_min = 3ns
b
O
VALID
tsdi_setup
tsdi_hold
)
s
t(
SCLK_POL=4
IGNORED
D99AU1038
u
d
o
tsckr_min_hi = 10ns
tsckr_min_low = 10ns
r
P
e
tsckr_min_lperiod = 50ns
t_biten (min) = 2ns
t
e
l
o
6.3.4 SRC_INT
O
bs
This is an asynchronous input used in "broadcast’ mode.
SRC_INT is active low
SRC_INT
t_src_hi
t_src_low
D98AU972
t_src_low min duration is 50ns (1DSP clock period)
t_src_high min duration is 50ns (1DSP clock period)
47/56
STA015
6.3.5 XTI,XTO and CLK_OUT timings
thi
XTI (INPUT)
tlo
XTO
txto
CLK_OUT
tclk_out
D98AU973
txto = 1.40 + pad_timing (Cload_XTO) ns
tclk_out = 4 + pad_timing (Cload_CLK_OUT) ns
Note: In "multimedia" mode, the CLK_OUT pad is DATA_REQ. In that case, no timing is given between the XTI input and this pad.
6.3.6 RESET
c
u
d
The Reset min duration (t_reset_low_min) is 100ns
RESET
treset_low_min
o
r
P
D98AU974
e
t
le
6.4 CONFIGURATION FLOW EXAMPLE
HW RESET
set
PCM-DIVIDER
set
PCM-CONF.
)
s
(
ct
o
r
P
e
t
e
l
o
s
b
O
du
set { PLL FRAC_441_H,
PLL FRAC_441_L,
PLL FRAC_H,
PLL FRAC_L }
PCM OUTPUT
INTERFACE
CONFIGURATION
PLL
CONFIGURATION
FOR:
set { MFS DF_441,
MFSDF }
• { 48, 44.1, 32
29, 22.05, 16
12, 11.025, 8 } KHz
set
PLL CTRL
• MULTIMEDIA
MODE see
{TAB 5 to TAB12}
set
SCKR_POL
set
CHIP_MODE
set
REQ_POL
set
48/56
o
s
b
O
-
RUN
INPUT SERIAL
CLOCK POLARITY
CONFIGURATION
SELECT
OPERATIONAL
MODE
DATA REQUEST
POLARITY
CONFIGURATION
D00AU1146A
)
s
t(
STA015
Table 2.
Table 4.
PLL Configuration Sequence For
PLL Configuration Sequence For
10MHz Input Clock
14.31818MHz Input Clock
256 Oversapling Clock
256 Oversapling Rathio
REGISTER
ADDRESS
NAME
VALUE
REGISTER
ADDRESS
NAME
VALUE
6
reserved
18
6
reserved
12
11
reserved
3
11
reserved
3
97
MFSDF (x)
15
97
MFSDF (x)
15
80
MFSDF-441
16
80
MFSDF-441
16
101
PLLFRAC-H
169
101
PLLFRAC-H
187
82
PLLFRAC-441-H
49
82
PLLFRAC-441-H
103
100
PLLFRAC-L
42
100
PLLFRAC-L
81
PLLFRAC-441-L
60
81
PLLFRAC-441-L
5
PLLCTRL
161
5
PLLCTRL
o
r
P
Table 3.
Table 5.
PLL Configuration Sequence For
PLL Configuration Sequence For
10MHz Input Clock
14.31818MHz Input Clock
384 Oversapling Rathio
REGISTER
ADDRESS
6
VALUE
reserved
reserved
97
MFSDF (x)
80
MFSDF-441
101
PLLFRAC-H
161
384 Oversapling Rathio
NAME
11
o
s
b
O
-
e
t
le
c
u
d
58
119
17
d
o
r
P
e
VALUE
11
11
reserved
3
97
MFSDF (x)
6
10
80
MFSDF-441
7
110
101
PLLFRAC-H
3
(s)
9
6
NAME
reserved
3
t
c
u
REGISTER
ADDRESS
82
PLLFRAC-441-H
160
82
PLLFRAC-441-H
157
100
PLLFRAC-L
152
100
PLLFRAC-L
211
81
PLLFRAC-441-L
186
81
PLLFRAC-441-L
157
5
PLLCTRL
161
5
PLLCTRL
161
t
e
l
o
)
s
t(
s
b
O
49/56
STA015
Table 6.
Table 8.
PLL Configuration Sequence For
PLL Configuration Sequence For
14.31818MHz Input Clock
14.7456MHz Input Clock
512 Oversapling Rathio
384 Oversapling Rathio
REGISTER
ADDRESS
NAME
VALUE
REGISTER
ADDRESS
NAME
6
reserved
11
6
reserved
10
11
reserved
3
11
reserved
3
97
MFSDF (x)
6
97
MFSDF (x)
8
80
MFSDF-441
7
80
MFSDF-441
9
101
PLLFRAC-H
3
101
PLLFRAC-H
64
82
PLLFRAC-441-H
157
82
PLLFRAC-441-H
124
100
PLLFRAC-L
211
100
PLLFRAC-L
81
PLLFRAC-441-L
157
81
PLLFRAC-441-L
5
PLLCTRL
161
5
PLLCTRL
Table 9.
PLL Configuration Sequence For
PLL Configuration Sequence For
14.7456MHz Input Clock
14.7456MHz Input Clock
256 Oversapling Rathio
512 Oversapling Rathio
REGISTER
ADDRESS
NAME
6
reserved
12
11
reserved
3
97
MFSDF (x)
80
MFSDF-441
101
PLLFRAC-H
82
PLLFRAC-441-H
o
r
P
e
(s)
15
du
ct
o
s
b
O
REGISTER
ADDRESS
NAME
0
161
VALUE
6
reserved
9
11
reserved
2
5
97
MFSDF (x)
16
80
MFSDF-441
6
85
101
PLLFRAC-H
0
4
82
PLLFRAC-441-H
100
PLLFRAC-L
85
100
PLLFRAC-L
81
PLLFRAC-441-L
0
81
PLLFRAC-441-L
5
PLLCTRL
161
5
PLLCTRL
t
e
l
o
50/56
VALUE
e
t
le
0
c
u
d
o
r
P
Table 7.
s
b
O
VALUE
184
0
0
161
)
s
t(
STA015
6.5 STA015 CONFIGURATION FILE FORMAT
The STA015 Configuration File is an ASCII format. An example of the file format is the following:
58 1
42 4
128 15
............
It is a sequence of rows and each one can be interpreted as an I2C command. The first part of the row is
the I2C address (register) and the second one is the I2C data (value). To download the STA015 configuration file into the device, a sequence of write operation to STA015 I2C interface must be performed.
The following program describes the I2C routine to be implemented for the configuration driver:
42
2
4
I C REGISTER VALUE
I2C SUB-ADDRESS
c
u
d
D98AU976
STA015 Configuration Code (pseudo code)
download cfg - file
{
e
t
le
fopen (cfg_file);
fp:=1;
/*set file pointer to first row */
do {
o
s
b
O
-
o
r
P
I2C_start_cond;
/* generate I2C start condition for STA015 device address */
I2C_write_dev_addr;
/* write STA015 device address
I2C_write_subaddress (fp); /* write subaddress
I2C_write_data (fp);
/* write data
)
s
(
ct
I2C_stop_cond;
fp++;
}
while (!EDF)
o
r
P
e
}
du
)
s
t(
*/
*/
*/
/* generate I2C stop condition
*/
/* update pointer to new file row
*/
/* repeat until End of File
*/
/* End routine
*/
Note: 1. STA015 is a device based on an integrated DSP core. Some of the I2C registers default values are loaded after an internal DSP
boot operation. The bootstrap time is 60 micro second. Only after this time lenght, the data in the register can be considered stable
.
2. Refer also to the application note AN1250
t
e
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s
b
O
51/56
STA015
mm
DIM.
MIN.
inch
TYP.
A
MAX.
MIN.
TYP.
2.65
MAX.
0.104
a1
0.1
0.3
0.004
0.012
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.013
C
0.5
0.020
c1
45° (typ.)
D
17.7
18.1
0.697
0.713
E
10
10.65
0.394
0.419
e
1.27
0.050
e3
16.51
0.65
F
7.4
7.6
0.291
0.299
L
0.4
1.27
0.016
0.050
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
52/56
c
u
d
e
t
le
8 ° (max.)
S
s
b
O
OUTLINE AND
MECHANICAL DATA
o
s
b
O
-
o
r
P
SO-28
)
s
t(
STA015
mm
inch
DIM.
A
MAX.
MIN.
TYP.
1.60
0.063
A1
0.05
0.15
0.002
A2
1.35
1.40
1.45
0.053
0.055
0.057
B
0.30
0.37
0.45
0.012
0.015
0.018
C
0.09
0.20
0.004
D
11.80
12.00
12.20
0.464
0.472
0.480
D1
9.80
10.00
10.20
0.386
0.394
0.401
D3
8.00
0.006
0.008
0.315
E
11.80
12.00
12.20
0.464
0.472
0.480
E1
9.80
10.00
10.20
0.386
0.394
0.401
E3
8.00
e
0.45
0.60
L1
0.031
0.75
0.018
1.00
k
0.024
0.030
e
t
le
D
D1
du
o
r
P
o
s
b
O
-
A
A2
A1
23
22
0.10mm
.004
Seating Plane
E1
B
o
r
P
e
bs
(s)
ct
33
34
)
s
t(
TQFP44 (10 x 10 x 1.4mm)
0.039
0˚(min.), 3.5˚(typ.), 7˚(max.)
t
e
l
o
c
u
d
0.315
0.80
L
OUTLINE AND
MECHANICAL DATA
MAX.
B
TYP.
E
MIN.
12
44
11
1
C
e
L
O
K
TQFP4410
0076922 D
53/56
STA015
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN.
TYP.
MAX.
A
MIN.
TYP.
A1
1.700
0.350
0.400
0.450
MAX.
0.067
0.014
0.016
A2
1.100
0.043
b
0.500
0.20
D
8.000
0.315
D1
5.600
0.220
e
0.800
0.031
E
8.000
0.315
E1
5.600
0.220
f
1.200
0.047
0.018
c
u
d
Body: 8 x 8 x 1.7mm
e
t
le
o
r
P
LFBGA64
)
s
(
ct
BALL 1 IDENTIFICATION
D1
8
A
7
6
5
D
4
3
2
1
du
F
G
s
b
O
D
A1
f
t
e
l
o
E
0.15
A
f
o
r
P
e
B
C
o
s
b
O
-
E
E1
H
φ b (64 PLACES)
e
54/56
A2
LFBGA64M
)
s
t(
STA015
7.0 REVISION HISTORY
Date
Revision
16-Mar-2004
4
Changed block diagram pin 28, changed legalcy
Changes
26-Apr-2010
5
Major revision for revalidation process
c
u
d
e
t
le
)
s
(
ct
)
s
t(
o
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P
o
s
b
O
-
u
d
o
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t
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s
b
O
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STA015
c
u
d
Please Read Carefully:
)
s
t(
o
r
P
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
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e
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o
s
b
O
-
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(
ct
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r
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e
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b
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e
l
o
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