® PCM1740 PCM 174 0 For most current data sheet and other product information, visit www.burr-brown.com Stereo Audio DIGITAL-TO-ANALOG CONVERTER with VCXO and PLL TM FEATURES DESCRIPTION ● COMPLETE DELTA-SIGMA STEREO DAC ● VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR: 27MHz ±150ppm Output with 0V to 3V Input ● PROGRAMMABLE PLL 256fS or 384fS Audio System Clock Output ● DYNAMIC PERFORMANCE: Dynamic Range: 94dB SNR: 94dB THD+N: –89dB ● SAMPLING FREQUENCIES: 16kHz, 22.05kHz, 24kHz 32kHz, 44.1kHz, 48kHz 64kHz, 88.2kHz, 96kHz ● SERIAL AUDIO INTERFACE: Standard or I2S Data Formats 16-, 20-, or 24-Bit Data ● I2C-BUS® INTERFACE FOR CONTROL REGISTERS(1): Slave Receiver Operation 7-Bit Addressing Standard Transfer Rate (up to 100kbps) ● PROGRAMMABLE CONTROLS: Digital Attenuation (256 steps) Soft Mute Infinite Zero Detect Mute De-Emphasis (32kHz, 44.1kHz, 48kHz) DAC Output Mode ● SINGLE +5V SUPPLY ● SMALL SSOP-24 PACKAGE The PCM1740 is a complete stereo audio digital-to-analog converter with on-chip PLL and VCXO. The PCM1740 is designed specifically for set-top box applications requiring high-quality audio playback, a precision tuned 27MHz master clock source, and support for multiple audio-sampling frequencies. The stereo D/A converter utilizes multi-bit, delta-sigma architecture, which includes an 8x interpolation filter, thirdorder noise shaping, 5-level amplitude quantization, and an analog low-pass filter. The PCM1740 includes a number of user-programmable functions, which are accessed via a standard I2C-Bus interface. APPLICATIONS ● SET-TOP BOXES ● DIGITAL BROADCAST RECEIVERS BCK LRCK DATA PCM Audio I/F SCL SDA AD1 AD0 I2C I/F and REGs XT1 27MHz Crystal VOUTL Low-Pass Filter and Amp DAC (R) VCOM VOUTR ZERO Counter N XTUN DAC (L) 8x Oversampling Digital Filter and Sub-Functions Process Counter M Phase Detector SCKO (256fS / 384fS) LPF VCO MCKO (27MHz) VCXO XT2 RST Reset Power Supply VPP PGND VCC AGND VDD DGND NOTE: (1) I 2C-Bus ® is a registered trademark of Philips Semiconductor. International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 2000 Burr-Brown Corporation PDS-1551A 1 Printed in U.S.A. February, 2000 PCM1740 SPECIFICATIONS All specifications at TA = +25°C, VCC = VDD = VPP = 5.0V, fS = 44.1kHz, system clock = 384fS, 16-bit data, unless otherwise noted. PCM1740E PARAMETER CONDITIONS MIN RESOLUTION TYP MAX 16 DATA FORMAT Audio Interface Format Audio Data Bit Length Audio Data Format Sampling Frequency (fS) Internal System Clock Frequency DIGITAL INPUT/OUTPUT Logic Family High Level Input Voltage: VIH(1), (2) Low Level Input Voltage: VIL(1), (2) High Level Input Current: IIH(1), (2) Low Level Input Current: IIL(1) IIL(2) High Level Output Voltage: VOH(3) Low Level Output Voltage: VOH(3) VOL(4) DIGITAL INPUT/OUTPUT of I2C-BUS INTERFACE High Level Input Voltage: VIH(5) Low Level Input Voltage: VIL(5) Low Level Output Voltage: VOL(6) Output Fall Time: tOF (7) Input Logic Current: II(8) Capacitance for each I/O pin: CI(5) VCXO CHARACTERISTICS (MCKO) Crystal Clock Frequency (9) Crystal Clock Accuracy(9) XTUN Tuning Voltage Range(10) XTUN Input Impedance(10) Output Clock Frequency Output Clock Accuracy VCXO Tuning Range Output Clock Duty Cycle Output Clock Jitter Output Rise Time Output Fall Time Response Time(11) Power Up Time(12) PLL AC CHARACTERISTICS (SCKO) Output Clock Frequency Output Clock Duty Cycle Output Clock Jitter Output Rise Time Output Fall Time Frequency Transition Time(13) Power Up Time(14) Bits Standard/I2S Selectable 16/20/24 Selectable MSB First, Two’s Binary Complement 32 44.1 48 16 22.05 24 64 88.2 96 256fS /384fS Standard (fS) Half (fS) Double (fS) Input Logic UNITS Bits kHz kHz kHz TTL Compatible 2.0 0.8 ±10 VIH = VDD VIL = 0V VIL = 0V IOH = –2mA ±10 –120 µA µA VDC 0.5 0.5 VDC VDC 1.5 0.4 250 10 10 V V V ns µA pF VDD – 0.5V IOL = 4mA IOL = 2mA 3.0 –0.3 0 10% to 90% of VDD –10 VDC VDC µA 27MHz, Fundamental Crystal 27.0000 ±30 0 XTUN = 1.3V XTUN = 1.3V XTUN = 0V – 3V 10pF Load Standard Deviation 20% to 80% VDD, 10pF Load 80% to 20% VDD, 10pF Load 35 3.0 60 27.0000 ±50 300 45 100 4 4 55 10 5 MCKO = 27.0MHz 10pF Load Standard Deviation 20% to 80% VDD, 10pF Load 80% to 20% VDD, 10pF Load 4.096 40 50 150 4 4 15 36.864 60 20 30 MHz ppm V kΩ MHz ppm ppm % ps ns ns µs ms MHz % ps ns ns ms ms DYNAMIC PERFORMANCE(15) THD+N: VOUT = 0dB VOUT = –60dB Dynamic Range Signal-to-Noise Ratio(16) Channel Separation Level Linearity Error fS = 44.1kHz fS = 96kHz fS = 44.1kHz fS = 96kHz fS = 44.1kHz, EIAJ, A-Weighted fS = 96kHz, A-Weighted fS = 44.1kHz, EIAJ, A-weighted fS = 96kHz, A-weighted fS = 44.1kHz fS = 96kHz VOUT = –90dB ® PCM1740 2 90 90 88 0.0035 0.007 0.0035 0.007 94 90 94 90 92 88 ±1.0 0.01 0.01 % % % % dB dB dB dB dB dB dB SPECIFICATIONS All specifications at TA = +25°C, VCC = VDD = VPP = 5.0V, fS = 44.1kHz, system clock = 384fS, 16-bit data, unless otherwise noted. PCM1740E PARAMETER CONDITIONS MIN DC ACCURACY Gain Error Gain Mismatch, Channel-to-Channel Bipolar Zero Error ANALOG OUTPUT Voltage Range Center Voltage Load Impedance Full Scale (0dB) AC Coupled POWER SUPPLY REQUIREMENTS Voltage Range Supply Current, IDD + ICC + IPP Power Dissipation MAX UNITS ±1.0 ±1.0 ±1.0 ±3.0 ±3.0 % of FSR % of FSR % of FSR Vp-p VDC kΩ 0.62 VCC 0.5 VCC 5 DIGITAL FILTER PERFORMANCE Passband Stopband Passband Ripple Stopband Attenuation De-Emphasis Error Delay Time ANALOG FILTER PERFORMANCE Frequency Response TYP 0.445 fS 11.125 / fS Hz Hz dB dB dB sec –0.16 –0.6 dB dB 0.555 fS ±0.17 –35 –0.2 20Hz to 20kHz 20Hz to 40kHz VDD, VCC, VPP VDD = VCC = VPP = +5V VDD = VCC = VPP = +5V TEMPERATURE RANGE Operation Storage Thermal Resistance, θJA +4.5 +0.55 +5 25 125 –25 –55 +5.5 30 150 VDC mA mW +85 +125 °C °C °C/W 100 NOTES: (1) Pins 6, 7, 18, 19: AD0, AD1, BCK, DATA, LRCK (Schmitt trigger input). (2) Pin 10: RST (Schmitt trigger input with internal pull-up resistor). (3) Pins 5, 21: MCKO, SCKO. (4) Pin 16: ZERO (open drain output). (5) Pins 8, 9: SCL, SDA. (6) Pin 9: SDA (open drain output, IOL = 3mA). (7) Pin 9: SDA (from VIHMIN to VILMAX with a bus capacitance from 10pF to 400pF). (8) Pins 8, 9: SCL, SDA (input current each I/O pin with an input voltage between 0.1VDD and 0.9VDD). (9) This characteristic is the requirement for crystal oscillator. (10) Pin 3: XTUN. (11) The maximum response time when the XTUN is changed. (12) The maximum delay time from power on to oscillation. (13) The maximum lock up time when the PLL frequency is changed. (14) The maximum delay time from power on to lock up. (15) Dynamic performance specifications are tested with a 20kHz low-pass filter using a Shibasoku distortion analyzer 725°C with 30kHz LPF, 400Hz HPF, Average-Mode. (16) SNR is tested with infinite zero detection circuit disabled. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 PCM1740 PIN CONFIGURATION PIN ASSIGNMENTS Top View SSOP XT1 1 24 XT2 PGND 2 23 DGND PIN NAME I/O FUNCTION 1 XT1 — 27MHz Crystal connection. 2 PGND — PLL and VCXO ground. 3 XTUN IN VCXO tune, tuning voltage range from 0V to 3V. PLL and VCXO power supply, +5V. 4 VPP — 5 MCKO OUT Buffered clock output of VCXO. XTUN 3 22 VDD 6 AD0 IN Device address pin for I2C-BUS.(1) VPP 4 21 SCKO 7 AD1 IN Device address pin for I2C-BUS.(1) 8 SCL IN Bit clock input for I2C-BUS interface. RSV 9 SDA LRCK 10 RST IN 11 VOUTR OUT 12 AGND — Analog ground. Analog power supply, +5V. MCKO AD0 5 20 6 19 PCM1740 AD1 7 18 DATA SCL 8 17 BCK 9 16 ZERO RST 10 15 VCOM VOUTR 11 14 VOUTL AGND 12 13 SDA VCC IN/OUT Serial data for I2C-BUS interface. Reset, active LOW.(2) Right-channel analog voltage output. 13 VCC — 14 VOUTL OUT Left-channel analog voltage output. 15 VCOM — DC common-mode voltage output. 16 ZERO OUT 17 BCK IN Bit clock input for serial audio data.(1) 18 DATA IN Serial audio data input.(1) 19 LRCK IN Left and right word clock, equal to the sampling rate (fS).(1) Reserved must be open. Zero flag output, active LOW.(3) 20 RSV — 21 SCKO OUT 22 VDD — Digital power supply, +5V. 23 DGND — Digital ground. 24 XT2 — 27MHz Crystal connection. System clock output, 256/384 fS. NOTES: (1) Schmitt trigger input. (2) Schmitt trigger input with internal pull-up resistor. (3) Open drain output. ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Power Supply Voltage(1) ................................................................... +6.5V Supply Voltage Differences(2) ........................................................... ±0.1V GND Voltage Differences(3) .............................................................. ±0.1V Digital Input Voltage ................................................. –0.3V to (VDD + 0.3V) Analog Input Voltage ................................................ –0.3V to (VCC + 0.3V) Input Current (any pins except supplies) ........................................ ±10mA Operating Temperature Range ......................................... –25°C to +85°C Storage Temperature ...................................................... –55°C to +125°C Junction Temperature .................................................................... +150°C Lead Temperature (soldering, 5s) .................................................. +260°C Package Temperature (IR reflow, peak, 10s) ................................ +235°C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTES: (1) VCC, VDD, VPP. (2) Among VCC, V DD, VPP. (3) Among AGND, DGND, and PGND. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER PCM1740E " SSOP-24 " 338 " SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(1) TRANSPORT MEDIA –25°C to +85°C " PCM1740E PCM1740E PCM1740E PCM1740E/2K Rails Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “PCM1740E/2K” will get a single 2000-piece Tape and Reel. ® PCM1740 4 TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = +5V, fS = 44.1kHz, FSCKO = 384fS = 16.9344MHz, and 16-bit data, unless otherwise noted. PASSBAND RIPPLE (De-emphasis OFF, fS = 44.1kHz) 0 0 –20 –0.2 Level (dB) Level (dB) FREQUENCY RESPONSE (De-emphasis OFF, fS = 44.1kHz) –40 –60 –80 –0.4 –0.6 –0.8 –100 –1 0 1 2 3 4 0 0.1 0.2 fS 5k 10k 15k 20k 25k 0 3628 15k 20k 25k 0 4999.8375 15k 14999.5125 19999.35 DE-EMPHASIS ERROR (48kHz) Error (dB) Level (dB) DE-EMPHASIS FREQUENCY RESPONSE (48kHz) 10k 9999.675 Frequency (Hz) 0 –2 –4 –6 –8 –10 –12 5k 14512 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 Frequency (Hz) 0 10884 DE-EMPHASIS ERROR (44.1kHz) Error (dB) Level (dB) DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz) 10k 7256 Frequency (Hz) 0 –2 –4 –6 –8 –10 –12 5k 0.5 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 Frequency (Hz) 0 0.4 DE-EMPHASIS ERROR (3kHz) Error (dB) Level (dB) DE-EMPHASIS FREQUENCY RESPONSE (3kHz) 0 –2 –4 –6 –8 –10 –12 0 0.3 fS 20k 25k 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 0 Frequency (Hz) 5442 10884 16326 21768 Frequency (Hz) ® 5 PCM1740 TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, VCC = VDD = +5V, fS = 44.1kHz, FSCKO = 384fS = 16.9344MHz, and 16-bit data, unless otherwise noted. ANALOG FILTER (1Hz to 10MHz) ANALOG FILTER (1Hz to 20kHz) 20 0.05 0 0 Level (dB) Level (dB) –20 –40 –0.05 –60 –0.1 –80 –100 –0.15 0.1 0.1 0.2 0.3 0.4 0.4 0.5 1 10 100 1k Log Frequency (Hz) THD+N (FS), DYNAMIC RANGE, and SNR vs SUPPLY VOLTAGE (Temperature = 25°C, 384fS, fS = 44.1kHz) THD+N (FS), DYNAMIC RANGE, and SNR vs TEMPERATURE (VCC = VDD = VPP = 5V, 384fS, fS = 44.1kHz) 0.005 95 0.005 0.003 93 Dynamic Range THD+N 0.002 92 0.001 91 4.75 5 5.25 0.004 THD+D (FS) (%) THD+D (FS) (%) 94 Dynamic Range, SNR (dB) SNR 0.004 4.5 90 5.75 5.5 94 0.003 93 Dynamic Range THD+N 0.002 92 0.001 91 0.000 –50 –25 0 Supply Voltage (V) 96 0.006 92 SNR 0.004 90 0.002 88 Dynamic Range 0.000 Supply Current (mA) 94 THD+N 86 64 88.2 30 25 20 96.0 32 Sampling Frequency (kHz) 44.1 48 64 88.2 Sampling Frequency (kHz) ® PCM1740 75 35 Dynamic Range, SNR (dB) THD+D (FS) (%) 0.008 48 50 SUPPLY CURRENT vs SAMPLING FREQUENCY 0.010 44.1 25 Temperature (°C) THD+N (FS), DYNAMIC RANGE, and SNR vs SAMPLING FREQUENCY 32 100k 95 SNR 0.000 4.25 10k Log Frequency (Hz) 6 96.0 90 100 Dynamic Range, SNR (dB) 0 STEREO DIGITAL-TO-ANALOG CONVERTER 3rd ORDER ∆Σ MODULATOR 20 The stereo D/A converters of the PCM1740 utilize a multilevel delta-sigma architecture. Based upon a third-order noise shaper and a 5-level amplitude quantizer, this section converts the 8x oversampled, 18-bit input data from the interpolation filter to a 5-level delta-sigma format. A block diagram of the multi-level delta-sigma modulator is shown in Figure 1. This architecture has the advantage of improved stability and increased tolerance to clock jitter when compared to the one-bit (2-level) delta-sigma D/A converters. 0 Gain (–dB) –20 + 8fS 18-Bit –80 –120 –140 –160 0 5 10 – 20 25 FIGURE 2. Quantization Noise Spectrum. rily used for de-coupling purposes. See the “Applications Information” section of this data sheet for more information regarding the use of the VCOM output for biasing external circuitry. VOLTAGE CONTROLLED CRYSTAL OSCILLATOR (VCXO) The PCM1740 includes an on-chip voltage-controlled crystal oscillator, or VCXO, which is used to generate the 27MHz master clock required by most digital broadcast and MPEG-2 decoding applications. + Z–1 15 Frequency (kHz) The PCM1740 includes two analog outputs, VOUTL (pin 14) and VOUTR (pin 11), corresponding to the left and right audio outputs. The full-scale output amplitude is 0.62 • VCC, or 3.1Vp-p with a +5V supply and an AC coupled load of 5kΩ or greater. The analog outputs are centered about the DC common mode voltage, which is typically VCC / 2. The DC common-mode voltage is made available at the VCOM output (pin 15). This is an unbuffered output, prima- + –60 –100 The combined oversampling rate of the delta-sigma modulator and the 8x interpolation filter is 48fS for a 384fS system clock, and 64fS for a 256fS system clock. The theoretical quantization noise performance for the 5-level delta-sigma modulator is shown in Figure 2. The output of the delta-sigma modulator is low-pass filtered and buffered by an on-chip output amplifier. For best performance, an external low-pass filter is recommended. Refer to the “Applications Information” section of this data sheet for details regarding DAC output filter recommendations. In –40 + + + Z–1 Z–1 – + + 5-level Quantizer + 4 3 Out 48fS (384fS) 64fS (256fS) 2 1 0 FIGURE 1. 5-Level ∆Σ Modulator Block Diagram. ® 7 PCM1740 The 27MHz clock is available at the MCKO output (pin 5). The VCXO output frequency can be precisely tuned using a control voltage at the XTUN input (pin 3). The tuning range is 27MHz ±150ppm typical for a 0V to +3V control voltage range. Figure 3 shows the VCXO equivalent circuit, while Figure 4 shows the typical tuning curve. VCXO Output Frequency (MHz) 27.005 At power up, the VCXO requires 5ms start up time. The VCXO also exhibits a 10µs settling time in response to changes in the XTUN control voltage. VCXO operation and the MCKO output are not effected by the power on or external reset functions, continuing to operate during the initialization sequence. 27.004 27.003 27.002 27.001 27.000 26.999 26.998 26.997 26.996 26.995 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Tuning Voltage (V) FIGURE 4. VCXO Output Frequency (MCKO) versus Tuning Voltage (XTUN). 27MHz Tuned Clock XT1 Crystal Selection The VCXO connects to an external 27MHz crystal via XT1 (pin 1) and XT2 (pin 24). The crystal should be AT-cut, fundamental mode with ±30ppm accuracy and less than 50Ω motional resistance. Crystal shunt capacitance should be 3pF maximum, while load capacitance should be less than 7pF. Miniature lead type or surface-mount devices are recommended. External load capacitors are not needed, since they are provided on-chip. The crystal should be placed as close as possible to the XT1 and XT2 pins to reduce effects of parasitic capacitance and land resistance. 1 27MHz Crystal XT2 Voltage Range 0 to 3V XTUN 24 3 CLV CL PROGRAMMABLE PHASE LOCKED LOOP (PLL) The PCM1740 includes an on-chip PLL for generating a 256fS or 384fS audio system clock from the 27MHz VCXO output. A block diagram of the PLL section is shown in Figure 5. The PLL output clock is used by the digital filter and delta-sigma modulator circuitry, and is made available at the SCKO output (pin 21) for use with additional audio converters and signal processors. FIGURE 3. VCXO Equivalent Circuit. PLL Frequency Selection Control Register 3 N Counter Phase Detector and Loop Filter Frequency Selection ROM M Counter VCO SCKO 256/384fS 27MHz Crystal MCKO 27MHz ±150ppm VCXO XTUN 0V to +3V FIGURE 5. PLL Block Diagram. ® PCM1740 8 RESET OPERATION The PLL can generate one of nine pre-programmed system clock rates for either 256fS or 384fS output. The PLL output and sampling frequencies are programmed using Control Register 3. Table I shows the available sampling frequencies and the corresponding PLL output clock rates. The reset default condition for the PLL is fS = 44.1kHz with SCKO = 384fS, or 16.9344MHz. POWER ON RESET The PCM1740 includes power-on reset circuitry for start up initialization. The initialization sequence starts when VDD exceeds 2.2V (typical). The initialization sequence requires 1024 PLL output (or SCKO) clock cycles for completion. During initialization, both VOUTL and VOUTR are forced to VCC / 2. Figure 6 shows the power on reset timing, while Table II shows the reset default settings for user-programmable functions. The user should not attempt to write control registers via the I2C-Bus interface during the initialization sequence. At power up, the PLL requires 30ms start up time for stabilization. The PLL also exhibits a settling time of 20ms in response to changes in sampling frequency selection. The PLL output continues to operate during power on or external reset sequences, with the sampling frequency set to fS = 44.1kHz and SCKO = 384fS. SAMPLING FREQUENCY (LRCK) INTERNAL SYSTEM Clock - 256fS EXTERNAL RESET The PCM1740 includes an external reset input, RST (pin 10). This input may be used to force an initialization sequence. As shown in Figure 7, the RST pin must be held low for a minimum of 20ns. The initialization sequence will then start on the rising edge of RST. Initialization requires 1024 PLL output (or SCKO) clock cycles for completion. During initialization, both VOUTL and VOUTR are forced to VCC / 2. Table II shows the reset default settings for user-programmable functions. The user should not attempt to write control registers via the I2C-Bus interface during the initialization sequence. INTERNAL SYSTEM Clock - 384fS 16kHz Half 4.096MHz 6.144MHz 32kHz Normal 8.192MHz 12.288MHz 24.576MHz 64kHz Double 16.384MHz 22.05kHz Half 5.6448MHz 8.4672MHz 44.1kHz Normal 11.2896MHz 16.9344MHz 88.2kHz Double 22.5792MHz 33.8688MHz 24kHz Half 6.144MHz 9.216MHz 48kHz Normal 12.288MHz 18.432MHz 96kHz Double 24.576MHz 36.864MHz TABLE I. PLL Sampling and System Clock Frequencies. 2.4V VCC / VDD 2.2V 2.0V Reset Reset Removal Internal Reset 1024 System Clock Periods System Clock (SCKO) FIGURE 6. Power-On Reset Operation. tRST ≥ 20ns tRST RST tRST Reset Reset Removal Internal Reset 1024 System Clock Periods System Clock (SCKO) FIGURE 7. External Reset Operation. ® 9 PCM1740 ZERO FLAG OUTPUT The PCM1740 includes a zero flag output, ZERO (pin 16). This is an open-drain output, and a 10kΩ pull-up resistor connected to VDD is recommended when using the ZERO flag as a logic output. The PCM1740 includes an infinite zero detection function that monitors the audio data at the DATA input (pin 18). If the audio data for both the left and right channels is all zeros for 65,536 continuous BCK clock cycles, the zero flag will be activated, turning on a MOSFET switch and connecting the ZERO pin to ground. This provides an active low output that may be used to control an external mute circuit, or as a logic indicator for an audio DSP/decoder or microprocessor. Audio DSP/Decoder PCM1740 Frame Sync LRCK Serial Bit Clock BCK Serial Data Output DATA Audio Clock SCKO FIGURE 8. Interfacing the PCM1740 to an Audio DSP. The LRCK input is operated at the sampling frequency, fS. The BCK input is operated at 32, 48, or 64 times the sampling frequency. Both LRCK and BCK must be synchronous with the SCKO output for proper operation. AUDIO SERIAL INTERFACE The PCM1740 includes a three-wire serial audio interface. This includes LRCK (pin 19), BCK (pin 17), and DATA (pin 18). The LRCK input is the audio left/right clock, which is used as a latch signal for the interface. The BCK input is used to clock audio data into the serial port. The DATA input carries multiplexed data for the left and right audio channels. Audio data must be Two’s Complement, MSB first formatted. Figure 8 shows the typical connection between the PCM1740 audio serial interface and an audio DSP or decoder. Data Formats The PCM1740 supports two audio interface formats: Standard and I2S. These formats are shown in Figure 9. The audio data word length for the Left and Right channels may be 16-, 20-, or 24-bits. The audio data word length and format are programmed using Control Registers 2 and 3. The reset default condition is Standard format with 16-bit audio data. Timing Requirements Figure 10 shows the audio interface timing requirements. LRCK and BCK Rates (a) Standard Right - Justified Format 1/fs L_ch R_ch LRCIN (pin 4) BCKIN (pin 6) AUDIO DATA WORD = 16-BIT DIN (pin 5) 14 15 16 1 2 MSB AUDIO DATA WORD = 20-BIT DIN (pin 5) 18 19 20 1 2 23 24 1 2 15 16 1 LSB 18 3 MSB AUDIO DATA WORD = 24-BIT DIN (pin 5) 14 3 22 MSB 14 3 MSB 19 20 1 2 LSB 3 2 LSB 18 3 MSB 23 24 1 2 LSB 19 20 LSB 22 3 MSB (b) I2S Format 15 16 23 24 LSB 1/fs L_ch LRCIN (pin 4) R_ch BCKIN (pin 6) AUDIO DATA WORD = 16-BIT DIN (pin 5) 1 2 MSB AUDIO DATA WORD = 20-BIT DIN (pin 5) 1 2 3 MSB AUDIO DATA WORD = 24-BIT DIN (pin 5) 3 1 2 3 MSB 14 15 16 1 LSB 3 MSB 18 19 20 1 2 LSB 22 3 MSB 23 24 1 LSB 2 3 MSB FIGURE 9. Audio Interface Formats. ® PCM1740 2 10 14 1 2 19 20 1 2 23 24 1 2 15 16 LSB 18 LSB 22 LSB LRCKIN 1.4V tBCH tBCL tLB BCKIN 1.4V tBL tBCY 1.4V DIN tDS BCKIN Pulse Cycle Time : tBCY : 100ns (min) BCKIN Pulse Width High : tBCH : 50ns (min) BCKIN Pulse Width Low : tBCL : 50ns (min) BCKIN Rising Edge to LRCIN Edge : tBL : 30ns (min) LRCIN Edge to BCKIN Rising Edge : tLB : 30ns (min) DIN Set-up Time : tDS : 30ns (min) DIN Hold Time : tDH : 30ns (min) tDH FIGURE 10. Audio Interface Timing. Loss of Synchronization Ideally, LRCK and BCK will be derived from the SCKO output, ensuring synchronous operation. For other cases, the PCM1740 includes circuitry to detect loss of synchronization between the LRCK and the system clock, SCKO. A loss of synchronization condition is detected when the phase relationship between SCKO and LRCK exceeds ±6 BCK cycles during one sample period, or 1/fS. If a loss of synchronization condition is detected, the DAC operation will halt within one sample period and the analog outputs will be forced to VCC / 2 until re-synchronization between LRCK and SCKO is completed. Figure 11 shows the state of the analog outputs given a loss of synchronization event. During the undefined states, as well as transitions between normal and undefined states, the analog outputs may generate audible noise. This section describes the control registers, while the I2C-Bus interface is described in a later section. Table II lists the available functions and their corresponding reset default condition. Register Map The control register map is shown in Table III. Sub-address bits B8 through B10 are used to specify the register that is being written. All reserved bits, shown as “res”, must be set to ‘0’. Register Descriptions The following pages provide detailed descriptions of the five control registers and their associated functions. All reserved bits, shown as “res”, must be set to ‘0’. USER PROGRAMMABLE FUNCTIONS The PCM1740 includes a number of programmable functions, which are configured using five control registers. These registers are accessed using the I2C-Bus interface. State of Synchronous Synchronization Synchronous Asynchronous within 1/fS Undefined Data VOUT VCOM (= 0.5 VCC) Normal 22.2/fS Undefined Data Normal FIGURE 11. Loss of Synchronization and Analog Output State. FUNCTION MODE BY DEFAULT Audio Data Format Select: Standard Format /I2S Format Standard Format Audio Data Word Select: 16-Bit /20-Bit /24-Bit 16-Bit Polarity of LR-clock Selection Left/Right = HIGH/LOW De-emphasis Control: OFF, 32kHz, 44.1kHz, 48kHz OFF Soft Mute Control OFF Attenuation Data for Left-channel 0dB Attenuation Data for Right-channel 0dB Attenuation Data Mode Control Left-channel, Right-channel Individually Analog Output Mode Select Stereo Mode Infinity Zero Detect Mute Control OFF DACs Operation Control ON System Clock Select: 256f S /384fS 384fS Sampling Frequency Select: 32kHz Group, 44.1kHz Group, 48kHz Group 44.1kHz Group Sampling Frequency Multiplier: Normal/ Double/ Half Normal, x1 TABLE II. User-Programmable Functions. DATA BYTE SUB ADDRESS BYTE REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 0 res res res res res A2 A1 A0 AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 Register 1 res res res res res A2 A1 A0 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 Register 2 res res res res res A2 A1 A0 PL3 PL2 PL1 PL0 IW1 IW0 DEM MUT Register 3 res res res res res A2 A1 A0 SF1 SF0 DSR1 DSR0 SYS ATC LRP IIS Register 4 res res res res res A2 A1 A0 res res res res res OPE IZD LD TABLE III. Control Register Map. ® 11 PCM1740 REGISTER DEFINITIONS Register 0 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 res res res res res 0 0 0 AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 Left Channel Attenuation Data Default: AL[7:0] = FFHEX Register 0 is used to set the digital attenuation level for the Left Channel. If the ATC bit in Register 3 is set to “1”, then this data is also used to control the Right Channel attenuation. The attenuation level is defined by the following relationships: Attenuation (dB) = 20 x log (AL[7:0]DEC ÷ 256), when AL[7:0] = 01HEX (1DEC) through FEHEX (254DEC) Attenuation (dB) = –∞ (or Mute), when AL[7:0] = 00HEX Attenuation (dB) = 0dB, when AL[7:0] = FFHEX The Attenuation Load bit, LD, in Register 4 must be set to “1” in order to update attenuation settings. If LD is set to “0”, the attenuation remains at the previously programmed level, ignoring the new data until LD is set to “1”. Register 1 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 res res res res res 0 0 1 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 Right Channel Attenuation Data Default: AR[7:0] = FFHEX Register 1 is used to set the digital attenuation level for the Right Channel. If the ATC bit in Register 3 is set to ‘1’, then the Left Channel attenuation data in Register 1 is used to control the Right Channel attenuation. The attenuation level is defined by the following relationships: Attenuation (dB) = 20 x log (AR[7:0]DEC ÷ 256), when AR[7:0] = 01HEX (1DEC) through FEHEX (254DEC) Attenuation (dB) = –∞ (or Mute), when AR[7:0] = 00HEX Attenuation (dB) = 0dB, when AR[7:0] = FFHEX The Attenuation Load bit, LD, in Register 4 must be set to 1 in order to update attenuation settings. If LD is set to “0”, the attenuation remains at the previously programmed level, ignoring the new data until LD is set to “1”. Register 2 MUT B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 res res res res res 0 1 0 PL3 PL2 PL1 PL0 IW1 IW0 DEM MUT Soft Mute Control The MUT bit controls the soft mute function. Soft mute changes the digital attenuation level for both the Left and Right channels, stepping from the currently programmed value to infinite attenuation one step per sample period, or 1/fS. This provides a quiet muting of the outputs without audible noise. MUT = 0 MUT = 1 DEM Soft Mute Disabled (default) Soft Mute Enabled Digital De-Emphasis The DEM bit controls the digital de-emphasis function, which is valid only for 32kHz, 44.1kHz, and 48kHz sampling frequencies. The de-emphasis plots are shown in the Typical Performance Curves section of this data sheet. DEM = 0 DEM = 1 De-Emphasis OFF (default) De-Emphasis ON ® PCM1740 12 IW0 Audio Data Word Length IW1 The IW0 and IW1 bits are used to select the data word length for the audio serial interface. The audio data format is selected using the IIS bit in Register 3. IW1 0 0 1 1 PL[3:0] Register 3 IIS IW0 0 1 0 1 Analog Output Mode Select Bits PL[3:0] are used to set the output mode for the analog outputs. Refer to the table below. PL3 PL2 PL1 PL0 VOUTL VOUTR Notes 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Mute Mute Mute Left Left Left Left Right Right Right Right (L+R)/2 (L+R)/2 (L+R)/2 (L+R)/2 Mute Reverse Stereo (default) Mono B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 res res res res res 0 1 1 SF1 SF0 DSR1 DSR0 SYS ATC LRP IIS Audio Data Format The IIS bit is used to select the audio data format, either Standard Right Justified or I2S. IIS = 0 IIS = 1 LRP Word Length 16-bits (default) 20-bits 24-bits Reserved Standard Right Justified (default) I2S LRCK Polarity The LRP bit selects the polarity of left/right clock input (LRCK) when using the Standard Right Justified audio data format. This bit has no effect when using the I2S audio data format. LRP = 0 LRP = 1 ATC Left Channel when LRCK = High; Right Channel when LRCK = Low (default) Left Channel when LRCK = Low; Right Channel when LRCK = High Attenuation Mode Control The ATC bit is used to select independent or common attenuation data for the Left and Right channels. ATC = 0 ATC = 1 Independent: Left Channel uses Register 0 and Right Channel uses Register 1 (default) Common: Left and Right Channels both use Register 0 ® 13 PCM1740 SYS Audio System Clock (or SCKO) The SYS bit is used to select the system clock (or SCKO) frequency, either 256fS or 384fS. SYS = 0 SYS = 1 DSR0 DSR1 384fS (default) 256fS Sampling Frequency Multiplier The DSR0 and DSR1 bits are used to select the multiplier used in conjunction with the SF0 and SF1 bits. DSR1 0 0 1 1 SF0 SF1 DSR0 0 1 0 1 Multiplier Normal, x1 (default) Double, x2 Half, x 1/ 2 Reserved Sampling Frequency Select The SF0 and SF1 bits are used to select the sampling frequency group (32kHz, 44.1kHz, or 48kHz). The DSR0 and DSR1 bits, described previously, are used to select the multiplier. Register 4 LD SF1 0 0 SF0 0 1 Sampling Frequency Group 44.1kHz Group ( 22.05kHz, 44.1kHz, or 88.2kHz) (default) 48 kHz Group (24kHz, 48kHz, or 96kHz) 1 1 0 1 32 kHz Group (16kHz, 32kHz, or 64kHz) Reserved B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 res res res res res 1 0 0 res res res res res OPE IZD LD Attenuation Data Load Control The LD bit is used to simultaneously set the Left and Right digital attenuation data. When LD is set to “1”, the digital attenuation data given by Registers 0 and 1 is loaded for the Left and Right channels. When LD is set to “0”, updates to Registers 0 and 1 are ignored, and the attenuation settings remain as previously programmed until LD is set to “1”. LD = 0 LD = 1 IZD Disabled Enabled: Left and Right Attenuation Data Updated Simultaneously Infinite Zero Detect Mute The IZD bit is used to enable/disable the infinite zero detect mute function. The PCM1740 includes infinite zero detection logic that monitors the audio data at the DATA input (pin 18). If the audio data for both the Left and Right channels is all zeros for 65,536 continuous BCK clock cycles, the zero flag will be activated and output amplifier will be disconnected from the output of the delta-sigma modulator. The output amplifier’s input is switched to the DC common mode voltage. This forces VOUTL and VOUTR to VCC/ 2. The ZERO output flag (pin 16) is not affected by the setting of this bit. IZD = 0 IZD = 1 OPE Disabled (default) Enabled DAC Operation Control The OPE bit is used to enable/disable the operation of the D/A converters. When enabled, the DAC outputs are connected to the output amplifier for normal operation. When disabled, the output amplifier is disconnected from the DAC output and switched to the DC common mode voltage. This forces VOUTL and VOUTR to VCC / 2. OPE = 0 OPE = 1 Enabled: Normal Operation(default) Disabled: Outputs forced to VCC /2 ® PCM1740 14 I2C-BUS INTERFACE DESCRIPTION Bus Operation The PCM1740 includes an I2C-Bus interface for writing the internal control registers. This provides an industry standard method for interfacing a host CPU control port to the PCM1740. The PCM1740 operates as a Slave receiver on the bus, and supports data transfer rates up to 100 kilobitsper-second (kbps). The I2C-Bus interface is comprised of four signals: SDA (pin 9), SCL (pin 8), AD0 (pin 6), and AD1 (pin 7). The SCL input is the serial data clock, while SDA is the serial data input. SDA carries start/stop, slave address, sub-address (or register address), register, and acknowledgment data. The AD0 and AD1 inputs form the lower two bits of the slave address. Figure 13 shows the typical configuration of the PCM1740 on the I2C-Bus. The Master transmitter or transmitter/receiver is typically a microcontroller, or an audio DSP/decoder. The Master device controls the data transfers on the bus. The PCM1740 operates as a Slave receiver, and accepts data from the Master when it is properly addressed. The data transfer may be comprised of an unlimited number of bytes, or 8-bit data words. Figure 14 shows the message transfer protocol. For normal bit transfer on the bus, data on SDA must be static while SCL is High. Data on SDA may change High/ Low states when SCL is Low. The exception to this rule is the Start and Stop conditions. The Start condition is defined by a High-to-Low transition on SDA while SCL is High, and is denoted with an “S” in Figure 12. The Stop condition is defined by a Low-to-High transition on SDA while SCL is High, and is denoted with a “P” in Figure 12. The Start and Stop conditions are always generated by the Master. All data transfers from Master to Slave begin with a Start condition and end with a Stop condition. The bus is considered to be busy after the Start condition, and becomes free some time after the Stop condition. Slave Address The PCM1740 Slave address consists of seven bits, as shown in Figure 12. The five most significant bits are fixed, while the two least significant bits, named A0 and A1, are defined by the logic levels present at the AD0 and AD1 input pins. This allows four PCM1740’s to reside on the same I2C-Bus. Start from Master Acknowledge from Slave MSB S 1 Acknowledge from Slave Not Acknowledge R/W 0 0 1 1 A1 A0 0 A B15 B14 B13 B12 B11 B10 B09 B08 A B07 B06 B05 B04 B03 B02 B01 B00 A Sub Address Byte Slave Address Data Byte P Stop from Master Internal Strobe for Data Latching FIGURE 12. Control Data Format. SDA SCL Master Transmitter/ Receiver Slave Receiver (PCM1740) Slave Transmitter/ Receiver Master Transmitter/ Receiver FIGURE 13. Typical I2C-Bus Configuration. SDA SCL Start Condition 1-7 8 9 Address R/W ACK 1-7 8 Data 9 ACK Start Condition 1-7 8 9 Address R/W ACK Stop NOTES: (1) Clock LOW (min) = 4.7µs; clock HIGH (min) = 4µs. (2) The dased line is the acknoweledgement of the receiver. (3) Mark-to space ratio = 1:1 (LOW-to-HIGH). (4) Maximum number of bytes is unrestriced. (5) Premature termination of transfer is allowed by generation of STOP condition. (6) Acknowledge clock bit must be provided by master. FIGURE 14. I2C Bus Data Transfer. ® 15 PCM1740 Data transfer begins with a Start condition, and is immediately followed by the Slave address and Read/ Write bit. The Read/ Write bit is set to “0” for the PCM1740, in order to write data to the control register specified by the subaddress. This is followed by an acknowledgment from the PCM1740, the sub-address (i.e., control register address), another acknowledgment from the PCM1740, the control register data, and another acknowledgment from the PCM1740. What happens after this depends upon if the user wants to continue writing additional control registers, or if they want to terminate the data transfer. If the user wants to continue, the acknowledgment is followed by a Start condi- tion for the next write sequence. If the user decides to terminate the data transfer, then a Stop condition is generated by the Master. The I2C-Bus specification defines timing requirements for devices connected to the bus. Timing requirements for the PCM1740 are shown in Figure 15. Reference For additional information regarding the I2C-Bus, please refer to the I2C-Bus Specification, Version 2.0, published in December 1998 by Philips Semiconductors. SDA tBUF tLOW tF tSU, DAT tHD; STA tR tR tF SCL tHD; DAT tHD; STA S tHIGH tSU; STA S: START condition Sr: repeated START condition P: STOP condition SYMBOL fSCL tHD; STA tSU; STO Sr DESCRIPTION MIN SCL Clock Frequency Hold time (repeated) START condition, after this period, the first clock pulse is generated TYP P MAX UNITS 100 kHz 4.0 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4.0 µs tSU:STA Set-up time for a repeated START condition 4.7 tHD;DAT Data hold time for I2C-BUS devices tSU;DAT Data set-up time 0 µs 3.45(2) 250 µs ns tR Rise time of both SDA and SCL signals 1000 ns tF Fall time of both SDA and SCL signals 300 ns Set-up time for STOP condition 4.0 µs tBUF Bus free time between a STOP and START condition 4.7 µs tSU;STO CB Capacitive load for each bus line VNL Noise margin at the LOW level for each connected device (including hysteresis) 0.1 VDD V VNH Noise margin at the HIGH level for each connected device (including hysteresis) 0.2 VDD V 400 FIGURE 15. I2C Bus Timing. ® PCM1740 16 pF S APPLICATIONS INFORMATION inductor or ferrite bead should be placed in series with the +5V supply connection to reduce or eliminate high-frequency noise on the supply line. Basic Connection Diagram A basic connection diagram is shown in Figure 16. Power supply and reference de-coupling capacitors should be located as close as possible to the PCM1740 package. The 27MHz crystal should also be located as close as possible to the package, to reduce the effects of parasitic capacitance on VCXO operation. In cases where overshoot or ringing is present on the LRCK or BCK signals, a series resistance of 25Ω to 100Ω should be added. The resistor forms a simple RC filter with the device input and PCB parasitic capacitance, dampening the overshoot and ringing effects, while reducing high-frequency noise emissions. Typical Application Diagram A single +5V supply is recommended, to avoid issues with power-supply sequencing and SCR latch-up. It is recommended that this supply be separate from the system’s digital power supply. In cases where this is not practical, an Figure 17 shows the PCM1740 being used as part of the audio sub-system in a set-top box application. C1 to C6 = 1µF to 10µF Capacitors ( Aluminum Electrolytic or tantalum) +5V 27MHz Crystal PCM1740 1 XT2 XT1 2 VCXO Control Voltage (0V to +3V) 27MHz Master Clock PGND DGND XTUN VDD 3 C1 4 + 5 RSV MCKO 6 AD0 LRCK AD1 DATA 7 I2C BUS and Reset Control from µP 9 SCL BCK SDA ZERO RST VCOM 8 C5 Buffer(1) VOUTR VOUTL AGND VCC X From Audio Decoder Serial Interface Zero Flag + 10kΩ + C4 C6 + Low Pass Filter (2) Right Channel Output 256/384fS to AudioDecoder and Data Converters C3 10 + + SCKO VPP Buffer(1) C2 Low Pass Filter (2) NOTES: (1) Use buffer when driving multiple nodes. (2) See applications information section for filter recommendations. Analog Ground Left Channel Output FIGURE 16. Basic Connection Diagram. BCIN LRCIN DIN Audio Decoder I2C-bus SCL SDA GPIO MPEG System Controller AD1 AD0 XTUN 27MHz Reference Generated by Receive Counter VCOM Low-Pass Filter and Output Amp DAC (R) VOUTR ZERO I2C I/F and REGs Counter N LPF Line-Out_L Low-Pass Filter and Analog Mute SCKO VCO Counter M XTI RST VOUTL DAC (L) 8x Interpolation Filter and Programmable Functions PD 27MHz Crystal XTO Phase Detec. Audio Serial I/F MCKO VCXO Reset Line-Out_R To Audio Decoder and Data Converters To Other Devices Power Supply LPF VCP PGND VCC AGND VDD DGND VCXO Control Voltage FIGURE 17. Typical Application Diagram. ® 17 PCM1740 The VTUN control voltage is generated by the MPEG-2 controller, which compares the MCKO output clock from the PCM1740 with the clock count received from the transmitter. VTUN is adjusted to retain clock synchronization between the transmitted and received signals. The SCKO output is used as the audio master clock for the audio decoder and additional data converters. The PCM1740 includes an on-chip low-pass filter as part of the output amplifier stage. The frequency response for the filter is shown in the Typical Performance Curves section of this data sheet. The –3dB cutoff frequency is fixed at 100kHz. Figure 19 shows the recommended external low-pass active filter circuits for dual and single-supply applications. These circuits are second-order Butterworth filters using the Multiple Feedback (MFB) circuit arrangement. Both filters have a cutoff frequency of 30kHz. Figure 19(a) is a dual-supply filter with a gain of 1.85 (for a standard 2 VRMS line output level). Figure 19(b) is a single-supply filter with a gain of 1. Values for the filter components may be calculated using the FilterPro program, available from the Burr-Brown web site (www.burr-brown.com) and local sales offices. For more information regarding MFB active filter design and the FilterPro program, please refer to Burr-Brown Applications Bulletin, AB-034. Since the overall system performance is defined primarily by the quality of the D/A converters and their associated analog output circuitry, op amps designed specifically for audio applications are recommended for the active filters. Burr-Brown’s OPA2134, OPA2353, and OPA2343 dual op amps are ideal for use with the PCM1740. VCOM Output The unbuffered DC common-mode voltage output, VCOM (pin 15), is brought out mainly for de-coupling purposes. VCOM is nominally biased to VCC/2. The VCOM output may be used to bias external circuits, but it must be connected to a high-impedance node or buffered using a voltage follower. Figure 18 shows examples of the proper use of the VCOM output for external biasing applications. DAC Output Filtering Delta-Sigma D/A converters utilize noise shaping techniques to improve in-band signal-to-noise (SNR) performance at the expense of generating increased out of band noise above the Nyquist frequency, or fS/2. The out of band noise must be low-pass filtered in order to provide optimal converter performance. This is accomplished by a combination of on-chip and external low-pass filtering. (b) Using a Buffer to Provide Bias for Multiple or Low Input Impedance Nodes (a) Biasing an External Active Filter Stage Non-Polarized 1µF PCM1740 VOUT Use voltage follower to buffer VCOM VCC PCM1740 OPA343 VCOM + VCOM + 1-10µF FIGURE 18. Using VCOM To Bias External Circuitry. ® PCM1740 18 1-10µF OPA337 To Bias Nodes PCM1740 VOUTR/L 1µF to 10µF R1 3.16kΩ R2 5.76kΩ R3 10kΩ C1 220pF +VA + Filtered Output C2 2200pF OPA134 Series –VA (a) Dual-Supply Filter Circuit PCM1740 VOUTR/L 1µF to 10µF R2 3.83kΩ R1 3.83kΩ R3 15kΩ C1 220pF VCC + C2 2200pF 1µF to 10µF + Filtered Output OPA343/353 Series VCOM 4.7µF to 10µF VCC 2 (b) Single-Supply Filter Circuit FIGURE 19. Recommended Output Filter Circuits. ® 19 PCM1740 PACKAGE DRAWING ® PCM1740 20