STA516B 60 V 6 A quad power half bridge Features ■ Minimum input output pulse width distortion ■ 200 mΩ RdsON complementary DMOS output stage ■ CMOS compatible logic inputs ■ Thermal protection ■ Thermal warning output ■ Under voltage protection Power SO36 slug up Description STA516B is a monolithic quad half bridge stage in Multipower BCD Technology. The device can be used as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability, and as half bridge (Binary mode) with half current capability. The device is particularly designed to make the output stage of a stereo all-digital high efficiency (DDX™) amplifier capable to deliver 160 + 160 W @ THD = 10 % at Vcc 50 V output power on 8 Ω load and 320 W @ THD = 10 % at Vcc 50V on 4 Ω load in single BTL configuration. The input pins have threshold proportional to VL pin voltage. Table 1. Device summary Part number Package Packaging STA516B Power SO36 slug up Tube STA516B13TR Power SO36 slug up Tape and reel March 2007 Rev 2 1/13 www.st.com 1 Contents STA516B Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Power supply and control sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 Mechanical and package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/13 STA516B 1 Introduction Introduction Figure 1. Application circuit (dual BTL) +VCC VCC1A IN1A 29 VL 23 M3 IN1A +3.3V PWRDN R57 10K R59 10K C58 100nF TH_WAR CONFIG 24 PWRDN 25 FAULT 27 26 17 16 M2 PROTECTIONS & LOGIC TRI-STATE M5 TH_WAR 28 IN1B 30 VDD 21 VDD 22 VSS 33 C53 100nF VSS 34 C60 100nF VCCSIGN IN2A IN2A GND-Reg GND-Clean IN2B GND1A 12 VCC1B M4 REGULATORS GND1B 7 VCC2A IN2B GNDSUB 8 M15 31 20 M16 1 C32 1µF 4 VCC2B OUT2B OUT2B M14 5 8Ω C21 100nF C110 100nF C109 330pF R103 6 C33 1µF 3 R100 6 C99 100nF C23 470nF C101 100nF L113 22µH OUT2A GND2A R98 6 L19 22µH OUT2A 6 2 32 R63 20 OUT1B 13 9 19 C52 330pF OUT1B 35 36 C20 100nF C31 1µF 11 C55 1000µF L18 22µH OUT1A OUT1A M17 VCCSIGN C30 1µF 14 10 IN1B C58 100nF 15 R104 20 R102 6 C107 100nF C108 470nF C106 100nF 8Ω C111 100nF L112 22µH GND2B D00AU1148B 3/13 Pin lists 2 STA516B Pin lists Table 2. Pin function Number 4/13 Pin Description 1 GND-SUB Substrate ground 2, 3 OUT2B Output half bridge 2B 4 Vcc2B Positive supply 5 GND2B Negative supply 6 GND2A Negative supply 7 Vcc2A Positive supply 8, 9 OUT2A Output half bridge 2A 10, 11 OUT1B Output half bridge 1B 12 Vcc1B Positive supply 13 GND1B Negative supply 14 GND1A Negative supply 15 Vcc1A Positive supply 16, 17 OUT1A Output half bridge 1A 18 NC Not connected 19 GND-clean Logical ground 20 GND-Reg Ground for regulator Vdd 21, 22 Vdd 5 V regulator referred to ground 23 VL High logical state setting voltage 24 CONFIG Configuration pin 25 PWRDN Stand-by pin 26 TRI-STATE Hi-Z pin 27 FAULT Fault pin advisor 28 TH-WAR Thermal warning advisor 29 IN1A Input of half bridge 1A 30 IN1B Input of half bridge 1B 31 IN2A Input of half bridge 2A 32 IN2B Input of half bridge 2B 33, 34 Vss 5 V regulator referred to +Vcc 35, 36 Vcc sign Signal positive supply STA516B Pin lists Table 3. Functional pin status Pin name FAULT Logical value Status 0 Fault detected (short circuit or thermal for example) 1 Normal operation TRI-STATE 0 All powers in Hi-Z state TRI-STATE 1 Normal operation PWRDN 0 Low absorption PWRDN 1 Normal operation THWAR 0 Temperature of the IC =130 oC THWAR(1) 1 Normal operation CONFIG 0 Normal operation CONFIG(2) 1 OUT1A=OUT1B; OUT2A=OUT2B (IF IN1A = IN1B; IN2A = IN2B) FAULT (1) 1. The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. 2. To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd) Figure 2. Pin connection VCCSign 36 1 GND-SUB VCCSign 35 2 OUT2B VSS 34 3 OUT2B VSS 33 4 VCC2B IN2B 32 5 GND2B IN2A 31 6 GND2A IN1B 30 7 VCC2A IN1A 29 8 OUT2A TH_WAR 28 9 OUT2A FAULT 27 10 OUT1B TRI-STATE 26 11 OUT1B PWRDN 25 12 VCC1B CONFIG 24 13 GND1B VL 23 14 GND1A VDD 22 15 VCC1A VDD 21 16 OUT1A GND-Reg 20 17 OUT1A GND-Clean 19 18 N.C. D01AU1273 5/13 Electrical characteristics STA516B 3 Electrical characteristics Table 4. Absolute maximum ratings Symbol Parameter Value Unit VCC DC supply voltage (Pins 4,7,12,15) 60 V Vmax Maximum voltage on pins 23 to 32 5.5 V Top Operating temperature range 0 to 70 °C Tstg, Tj Storage and junction temperature -40 to 150 °C Table 5. Thermal data Symbol Parameter Min. Typ. Max. Unit Tj-case Thermal resistance junction to case (thermal pad) 1 TjSD Thermal shut-down junction temperature 150 °C Twarn Thermal warning temperature 130 °C thSD Thermal shut-down hysteresis 25 °C Table 6. 2.5 °C/W Electrical characteristics (VL= 3.3 V; Vcc = 50 V; Tamb = 25 °C unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit RdsON Power Pchannel/Nchannel MOSFET RdsON Idss Power Pchannel/Nchannel leakage Idss gN Power Pchannel RdsON matching Id=1A 95 % gP Power Nchannel RdsON matching Id=1A 95 % Dt_s Low current dead time (static) see Figure 4 Dt_d High current dead time (dynamic) L=22µH, C = 470nF Rl = 8 Ω, Id=4.5A see Figure 5 50 td ON Turn-on delay time Resistive load 100 ns td OFF Turn-off delay time Resistive load 100 ns tr Rise time Resistive load see Figure 4 25 tf Fall time Resistive load see Figure 4 25 VCC Supply operating voltage VIN-High High level input voltage VIN-Low Low level input voltage IIN-H High level Input current Pin voltage = VL 1 µA IIN-L Low level input current Pin voltage = 0.3 V 1 µA 6/13 Id=1A 200 240 100 10 20 mΩ µA ns ns 10 VL/2 -300mV ns ns 52 V VL/2 +300mV V V STA516B Electrical characteristics Table 6. Electrical characteristics (continued) (VL= 3.3 V; Vcc = 50 V; Tamb = 25 °C unless otherwise specified) Symbol Parameter Test conditions IPWRDN-H High level PWRDN pin input current Min. VL= 3.3 V VLow Low logical state voltage VL (pin PWRDN, TRISTATE)(seeTable 7) VL = 3.3 V VHigh High logical state voltage VH (pin PWRDN, TRISTATE)(seeTable 7) VL = 3.3 V IVCC- Supply current from Vcc in power down PWRDN = 0 Typ. Max. Unit µA 35 V 0.8 V 1.7 mA 3 PWRDN IFAULT Output current pins FAULT -TH-WARN when FAULT CONDITIONS Vpin = 3.3 V 1 IVCC-hiz Supply current from Vcc in Tristate Tristate = 0 22 IVCC Supply current from Vcc in operation both channel switching) Input pulse width = 50 % duty Switching frequency = 384 Khz; No LC filters IOUT-SH Over current protection threshold Isc (short circuit current limit)1(1) VUV Under voltage protection threshold VOV Over voltage protection threshold tpw_min Output minimum pulse width mA mA mA 70 6 8 A 10 7 No load V 60 70 V 25 40 ns 1. See specific application note number: AN1994. Table 7. VLow, VHigh variation with VL VL VLow min VHigh max Unit 2.7 0.7 1.5 V 3.3 0.8 1.7 V 5 0.85 1.85 V Table 8. Logic truth table (see Figure 2) Tristate INxA INxB Q1 Q2 Q3 Q4 Output mode 0 x x OFF OFF OFF OFF Hi-Z 1 0 0 OFF OFF ON ON DUMP 1 0 1 OFF ON ON OFF NEGATIVE 1 1 0 ON OFF OFF ON POSITIVE 1 1 1 ON ON OFF OFF Not used 7/13 Power supply and control sequencing 4 STA516B Power supply and control sequencing To guarantee correct operation and reliability, a correct turn on/off sequence must be followed. Figure 3 shows the correct power on sequence. Figure 3. Correct power-on sequence V Vcc VL Vcc > VL t PWRDN IN t t Vcc must turn on before VL in order to prevent uncontrolled current flowing through an internal protection diode connected between VL (logic supply) and Vcc (high power supply). Failure to do so could result in damage to the device. PWRDN must be released after VL is switched on. An input signal can then be sent to the power stage. 8/13 STA516B 5 Test Test Figure 4. Test circuit OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t DTr Duty cycle = 50% DTf M58 OUTxY INxY R 8Ω M57 V67 = vdc = Vcc/2 + - gnd Figure 5. D03AU1458 Current dead time test circuit High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B DTout(A) M58 DTin(A) Q1 Q2 INxA Iout=4.5A M57 Q3 DTout(B) Rload=8Ω OUTxA L67 22µ C69 470nF L68 22µ C71 470nF C70 470nF M64 DTin(B) OUTxB INxB Iout=4.5A Q4 Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure M63 D00AU1162 9/13 Test STA516B Figure 6. Typical single BTL configuration to obtain 320 W @ THD 10 %, RL = 4 W, VCC = 50 V (a) VL +3.3V GND-Clean GND-Reg 100nF X7R 10K 23 18 N.C. 12µH 100nF VDD VDD CONFIG TH_WAR TH_WAR PWRDN nPWRDN FAULT 10K IN1A IN1B IN1A IN2A IN2B IN1B VSS VSS 100nF X7R 16 20 11 10 21 VCCSIGN 100nF X7R VCCSIGN Add. GNDSUB OUT1A 100nF FILM OUT1A OUT1B 22Ω 1/2W OUT1B 6.2 1/2W OUT2A 22 9 24 OUT2A 330pF 8 6.2 1/2W OUT2B 28 3 25 15 26 29 12 30 7 31 4 4Ω 12µH VCC1A +36V 1µF X7R VCC1B 2200µF 63V VCC2A +36V 1µF X7R 32 33 100nF X7R 680nF FILM 100nF X7R 100nF FILM OUT2B 2 27 TRI-STATE 100nF 17 19 VCC2B GND1A 34 14 GND1B 35 13 36 6 1 5 GND2A GND2B D04AU1545 Figure 7. Typical quad half bridge configuration +VCC VCC1P IN1A M3 29 IN1A +3.3V PWRDN R57 10K R59 10K C58 100nF TH_WAR VL 23 CONFIG 24 PWRDN 25 FAULT 27 26 16 M2 PROTECTIONS & LOGIC TRI-STATE M5 TH_WAR 28 IN1B 30 C58 100nF C53 100nF C60 100nF VDD 21 22 VSS 33 VSS 34 VCCSIGN IN2A GND-Reg GND-Clean IN2B PGND1P 12 VCC1N C51 1µF REGULATORS 13 7 PGND1N VCC2P C71 100nF R51 6 C81 100nF C61 100nF OUTNL OUTNL M4 R41 20 C41 330pF R42 20 C42 330pF C72 100nF R52 6 C82 100nF IN2B GNDSUB 9 36 M15 31 20 19 M16 1 OUTPR 6 PGND2P 4 VCC2N 3 2 32 OUTPR C52 1µF 5 C43 330pF PGND2N D03AU1474 C73 100nF R53 6 C83 100nF C62 100nF OUTNR OUTNR M14 R43 20 C44 330pF R66 5K R67 5K L14 22µH R44 20 R64 5K R65 5K L13 22µH 8 35 R62 5K R63 5K L12 22µH M17 VCCSIGN IN2A OUTPL OUTPL 11 R61 5K L11 22µH 14 10 IN1B VDD 15 17 C74 100nF R54 6 C84 100nF R68 5K C21 2200µF C31 820µF C91 1µF 4Ω C32 820µF C92 1µF 4Ω C33 820µF C93 1µF 4Ω C34 820µF C94 1µF 4Ω For more information, refer to the application note “ST50X and STA51X digital power amplifiers”. a. A PWM modulator as driver is required. This result was obtained using the STA30X+STA50X demo board. 10/13 STA516B 6 Mechanical and package data Mechanical and package data Figure 8. Power SO36 (slug up) mechanical data and package dimension DIM. A A2 A4 A5 a1 b c D D1 D2 E E1 E2 E3 E4 e e3 G H h L N s MIN. 3.25 3.1 0.8 mm TYP. MAX. 3.43 3.2 1 MIN. 0.128 0.122 0.031 -0.040 0.38 0.32 16 9.8 0.0011 0.008 0.009 0.622 0.37 14.5 11.1 2.9 6.2 3.2 0.547 0.429 0.2 0.030 0.22 0.23 15.8 9.4 5.8 2.9 0.8 OUTLINE AND MECHANICAL DATA -0.0015 0.015 0.012 0.630 0.38 0.039 0.57 0.437 0.114 0.244 1.259 0.228 0.114 0.65 11.05 0 15.5 MAX. 0.135 0.126 0.039 0.008 1 13.9 10.9 inch TYP. 0.026 0.435 0.075 15.9 1.1 1.1 10˚ 8˚ 0 0.61 0.031 0.003 0.625 0.043 0.043 10˚ 8˚ PowerSO36 (SLUG UP) (1) “D and E1” do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006”) (2) No intrusion allowed inwards the leads. 7183931 D 11/13 Revision history 7 STA516B Revision history Table 9. Date 12/13 Document revision history Revision Changes 01-Feb-2007 1 Initial release 19-Mar-2007 2 Update to reflect product maturity. STA516B Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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