STA510 60V 5A POWER FULL BRIDGE PRODUCT PREVIEW ■ MINIMUM INPUT OUTPUT PULSE WIDTH DISTORTION MULTIPOWER BCD TECHNOLOGY ■ 150mΩ RdsON NDMOS OUTPUT STAGE ■ CMOS COMPATIBLE LOGIC INPUTS ■ THERMAL PROTECTION ■ WARNING OUTPUT: THERMAL, OVERLOAD ■ UNDER VOLTAGE PROTECTION ON VREG ■ OVERVOLTAGE PROTECTION ■ TWO LEVELS CURRENT PROTECTION Flexiwatt27 ORDERING NUMBER: STA510 DESCRIPTION STA510 is a monolithic full bridge stage in Multipower BCD Technology. The device is particularly designed to make the output stage of classD audio amplifier capable to deliver 100W undistorted output power on 8Ω load. The input pins have threshold proportional to VIbias pin voltage. The commutation speed of the output stage is settable with an extenal resistor (Curref pin) to choice for each application the best compromise of THD versus EMI and current spikes. The overcurrent protection works in two steps, the first one, at a lower value limits the current terminating the pulse (independently to the input) when the current in the power output MOS reaches a first threshold: it is aimed to act in case of overload and its effect is to stabilize the mean current in the load to a limit value. The second step shuts down completely the device and restarts the power on sequence if the current reaches a second (higher) threshold: it is aimed to act in case of short circuit, when the first limitation can fail. AUDIO APPLICATION CIRCUIT SUB_GND INL VIBIAS +3.3V R1 10K R2 10K 1,27 4 26 PWRDIN 3 FAULT 5 TRISTATE 6 WARNING C2 470nF R3 48K DRIVER L PROTECTIONS & LOGIC 2 INR 24 VSS 25 VREGBOOT 24 VCC_REG 23 VREG 20 22 VCCL 10 OUTL 11 OUTL 14 SUB 12 PWGNDL 13 PWGNDL Q4 C12 1µF C11 1000µF L1 22µH C6 100nF R4 20Ω 19 BOOTR 21 VCCR C4 17 OUTR 18 OUTR 15 PWGNDR 16 PWGNDR R5 6Ω C5 330pF C7 100nF C10 470nF 8Ω 100nF C16 100nF Q2 DRIVER R C3 100nF VCC C15 100nF - REGULATOR CURREF BOOTL 7 Q1 + Q3 C1 100nF 9 C13 1µF R6 6Ω C8 100nF C9 100nF L2 22µH D03AU1508 July 2003 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/7 STA510 PIN FUNCTION N° Pin Description 1, 27 SUB_GND Substrate (frame) and signal ground 2 WARNING Warning advisor 3 PWRDN St-by input pin 4 INL Input left arm 5 FAULT Fault adviosor 6 TRISTATE Hi-Z input pin 7 VCCL 8 VREG_BOOT 9 BOOTL 10, 11 OUTL 12,13 PWRGNDL 14 SUB 15, 16 PWRGNDR 17, 18 OUTR 19 BOOTR 20 VREG Regulator output (for filtering) 21 VCCR Positive power supply right arm 22 CURREF Resistor for commutation speed setting 23 VCC_REG Positive power supply for the regulator 24 INR Input right arm 25 VSS Input logic ground 26 VIBIAS Positive power supply left arm VREG input for bootstrap charging Bootstrap cap. left arm Output left arm Power GND left arm Substrate (plug near powers) Power GND right arm Output right arm Bootstrap cap. right arm High logic state setting voltage FUNCTIONAL PIN STATUS PIN NAME Logical value IC -STATUS FAULT 0 Fault detected (Short circuit, or Thermal ..) FAULT* 1 Normal Operation TRI-STATE 0 All powers in Hi-Z state TRI-STATE 1 Normal operation PWRDN 0 Low absorpion PWRDN 1 Normal operation WARNING 0 Temperature of the IC =130°C; overload WARNING* 1 Normal operation * : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. 2/7 STA510 PIN CONNECTION VIBIAS INR VSS VCC_REG VCCR CURREF VREG OUTR BOOTR OUTR PWRGNDR SUB PWRGNDR PWRGNDL OUTL PWRGNDL OUTL BOOTL VCCL VREG_BOOT TRISTATE INL FAULT PWRDN SUB_GND WARNING SUB_GND 27 1 D03AU1455 ABSOLUTE MAXIMUM RATINGS Symbol Parameter VCE DC Supply Voltage (VCCR, VCCL, VCC_REG) Vmax Logic Voltage (INL, INR, VIBIAS, TRISTATE, PWRDN) VREG Regulator Voltage (VREG, VREG_BOOT, CURREF) vod Voltage on Open Drain Pins (WARNING, FAULT) Top Operating Temperature Range Tstg, Tj Storage and Junction Temperature Value Unit 60 V 5.5* V 8 V 60 V 0 to 70 °C -40 to 150 °C *: referred to VSS ELECTRICAL CHARACTERISTCS (VIbias = 3.3V; Vcc = 45V; Tamb = 25°C unless otherwise specified referred to “AUDIO APPLICATION CIRCUIT” pag. 1) Symbol Typ. Max. Unit Power Nchannel MOSFET RdsON Id=1A; 0.15 0.20 Ω Idss Power Nchannel leakage Idss TBD GNH Power Nchannel RdsON Matching Id = 1A; High Right with High Left 95 % GNL Power Nchannel RdsON Matching Id = 1A; Low Right with Low Left 95 % Dt-s Low current Dead Time (static) Dt-d High current Dead Time (dinamic) Id = 5A; see fig 3 td ON Turn-on delay time td OFF Turn-off delay time RdsON Parameter Test conditions see test circuit in fig. 1 Min. µA 20 40 ns 40 80 ns Resistive load 100 ns Resistive load; 100 ns 3/7 STA510 ELECTRICAL CHARACTERISTCS (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit tr Rise time Resistive load; 50 ns tf Fall time Resistive load; 50 ns 55 V VCC Supply voltage operating range 11 VIN-H High level input voltage VIN-L Low level input voltage IIN-H Hi level Input current Pin voltage = VIbias 1 µA IIN-L Low level input current Pin voltage = 0.3V 1 µA V Ibias/2 VIbias/2 +150mV +300mV VIbias/2 VIbias/2 -300mV -130mV IPWRDN-H Hi level PWRDN pin input current Ibias = 3.3V V 35 µA 1 V VL Low logical state voltage (pin PWRDN, TRISTATE) Ibias = 3.3V VH High logical state voltage (pin PWRDN, TRISTATE) Ibias = 3.3V 1.9 IVCCPWRDN Supply current from Vcc in Power Down PWRDN = 0; TRISTATE = 0 0.25 mA IVCC-hiz Supply current from Vcc in Tristate PWRDN = 1; Tri-state=0; TBD mA Supply current from Vcc in operation No LOAD Input pulse width = 50% Duty; Switching Frequency = 384Khz; No LC filters; 100 mA IVCC 0.8 V 2.2 V Ilim Current Limit (Overload) 6 7 8 A Isc Short circuit current threshold 7 8 9 A VUV Undervoltage protection threshold on VREG VOV Overvoltage protection threshold on VCC VDROP 55 Dropout from VCC to VREG 7 V 60 V 4 V LOGIC TRUTH TABLE (see fig. 2) TRI-STATE INL INR HSL (Q1) HSR (Q2) LSL (Q3) LSR (Q4) OUTPUT MODE 0 x x OFF OFF OFF OFF Hi-Z 1 0 0 OFF OFF ON ON DUMP 1 0 1 OFF ON ON OFF NEGATIVE 1 1 0 ON OFF OFF ON POSITIVE 1 1 1 ON ON OFF OFF Not used 4/7 STA510 Figure 1. Test Circuit. OUTx Vcc (3/4)Vcc Dt_s = Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t DTr Duty cycle = 50% OUTx INx DTf R 8Ω + - gnd vdc = Vcc/2 D03AU1507 Figure 2. +VCC Q1 Q2 OUTL INL OUTR Q3 INR Q4 GND D03AU1456 Figure 3. Dt_d = High Current Dead time for Bridge application = ABS(DTout(L)-DTin(L))+ABS(DTOUT(R)-DTin(R)) +VCC Duty cycle=A Duty cycle=B DTout(L) Q1 DTin(A) Q2 Rload=8Ω OUTL INL Iout=5A Q3 DTout(R) 22µH 470nF 22µH 470nF 470nF DTin(R) OUTR INR Iout=5A Q4 Duty cycle A and B: Fixed to have DC output current of 5A in the direction shown in figure D03AU1457 5/7 STA510 DIM. MIN. 4.45 1.80 A B C D E F (1) G G1 H (2) H1 H2 H3 L (2) L1 L2 (2) L3 L4 L5 M M1 N O R R1 R2 R3 R4 V V1 V2 V3 0.75 0.37 0.80 25.75 28.90 22.07 18.57 15.50 7.70 3.70 3.60 mm TYP. 4.50 1.90 1.40 0.90 0.39 1.00 26.00 29.23 17.00 12.80 0.80 22.47 18.97 15.70 7.85 5 3.5 4.00 4.00 2.20 2 1.70 0.5 0.3 1.25 0.50 MAX. 4.65 2.00 MIN. 0.175 0.070 1.05 0.42 0.57 1.20 26.25 29.30 0.029 0.014 22.87 19.37 15.90 7.95 0.869 0.731 0.610 0.303 4.30 4.40 0.145 0.142 0.031 1.014 1.139 inch TYP. 0.177 0.074 0.055 0.035 0.015 0.040 1.023 1.150 0.669 0.503 0.031 0.884 0.747 0.618 0.309 0.197 0.138 0.157 0.157 0.086 0.079 0.067 0.02 0.12 0.049 0.019 MAX. 0.183 0.079 OUTLINE AND MECHANICAL DATA 0.041 0.016 0.022 0.047 1.033 1.153 0.904 0.762 0.626 0.313 0.169 0.173 5˚ (Typ.) 3˚ (Typ.) 20˚ (Typ.) 45˚ (Typ.) Flexiwatt27 (vertical) (1): dam-bar protusion not included (2): molding protusion included V C B V H H1 V3 A H2 O H3 R3 L4 R4 V1 R2 L2 N L3 R L L1 V1 V2 R2 D R1 L5 Pin 1 R1 R1 E G G1 F FLEX27ME M M1 7139011 6/7 STA510 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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