STA502 40V 4A DOUBLE POWER HALF BRIDGE ■ MINIMUM INPUT OUTPUT PULSE WIDTH DISTORTION ■ 200mΩ RdsON COMPLEMENTARY DMOS OUTPUT STAGE ■ CMOS COMPATIBLE LOGIC INPUTS ■ THERMAL PROTECTION ■ THERMAL WARNING OUTPUT ■ UNDER VOLTAGE PROTECTION MULTIPOWER BCD TECHNOLOGY PowerSO36 ORDERING NUMBER: STA502 DESCRIPTION STA502 is a monolithic dual half bridge stage in Multipower BCD Technology. The device is particularly designed to make the output stage of a mono All-Digital High Efficiency (DDX™) amplifier capable to deliver 60W @ THD = 10% at Vcc 32V output power on 8Ω load. The input pins have threshold proportional to Ibias pin voltage. AUDIO APPLICATION CIRCUIT +3.3V PWRDN R57 10K R59 10K 23 CONFIG 24 PWRDN FAULT 15 14 25 27 26 PROTECTIONS & LOGIC 12 13 TRI-STATE C58 100nF TH_WAR C58 100nF IBIAS C53 100nF C60 100nF TH_WAR 28 VDD 21 VDD 22 VSS 33 VSS 34 30 16 REGULATORS C30 1µF VCCB GND GND N.C. 17 N.C. 7 VCCA INA GND-Reg GND-Clean 9 36 M15 31 20 19 M16 INB INB GNDSUB 32 C32 1µF 10 6 GNDA 4 VCCB N.C. 11 C110 100nF C109 330pF R103 6 C33 1µF 3 2 OUTB OUTB M14 L113 22µH OUTA OUTA 1 N.C. C31 1µF GND 8 35 C55 1000µF GND M17 VCCSIGN VCCSIGN INA 29 +VCC VCC 5 R104 20 R102 6 C107 100nF C108 470nF C106 100nF C111 100nF L112 22µH GNDB D02AU1447 September 2003 1/8 STA502 PIN FUNCTION N° Pin 1 GND-SUB 35 ; 36 Vcc Sign 15 VCC Positive Supply 12 VCC Positive Supply 7 VCC Positive Supply 4 VCC Positive Supply 14 GND Negative Supply 13 GND Negative Supply 6 GND Negative Supply 5 GND Negative Supply 16 ; 17 N.C. 10 ; 11 N.C. 8;9 OUTA Output half bridge 2;3 OUTB Output half bridge 29 GND 30 GND 31 INA Input of half bridge 32 INB Input of half bridge 21 ; 22 Vdd 5V Regulator referred to ground 33 ; 34 VSS 5V Regulator referred to + VCC 25 PWRDN 26 TRI-STATE 27 FAULT 24 GND 28 TH-WAR 19 GND-Clean 23 IBIAS 18 NC 20 GND-Reg 2/8 Description Substrate ground Signal Positive supply Stand-by pin Hi-Z pin Fault pin advisor Thermal warning advisor Logical ground High logical state setting voltage Not connected Ground for regulator Vdd STA502 FUNCTIONAL PIN STATUS PIN NAME Logical value IC -STATUS FAULT 0 Fault detected (Short circuit, or Thermal ..) FAULT * 1 Normal Operation TRI-STATE 0 All powers in Hi-Z state TRI-STATE 1 Normal operation PWRDN 0 Low absorpion PWRDN 1 Normal operation THWAR 0 Temperature of the IC =130°C THWAR* 1 Normal operation * : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. PIN CONNECTION VCCSign 36 1 GND-SUB VCCSign 35 2 OUTB VSS 34 3 OUTB VSS 33 4 VCC INB 32 5 GND INA 31 6 GND GND 30 7 VCC GND 29 8 OUTA TH_WAR 28 9 OUTA FAULT 27 10 N.C TRI-STATE 26 11 N.C. PWRDN 25 12 VCC GND 24 13 GND IBIAS 23 14 GND VDD 22 15 VCC VDD 21 16 N.C. GND-Reg 20 17 N.C. GND-Clean 19 18 N.C. D02AU1449 THERMAL DATA Symbol Description Rth j-case Thermal Resistance Junction-case Value Unit max 1.5 °C/W 3/8 STA502 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCE DC Supply Voltage (Pin 4,7,12,15) 40 V Vmax Maximum Voltage on pins 23 to 32 5.5 V Ptot Power Dissipation (Tcase = 70°C) 50 W Top Operating Temperature Range 0 to 70 °C -40 to 150 °C Tstg, Tj Storage and Junction Temperature THERMAL DATA Symbol Tj-case Parameter Min. Typ. Thermal Resistance Junction to Case (thermal pad) Max. Unit 2.5 °C/W TjSD Thermal shut-down junction temperature 150 °C Twarn Thermal warning temperature 130 °C thSD Thermal shut-down hysteresis 25 °C ELECTRICAL CHARACTERISTCS (Ibias = 3.3V; VCC = 30V; Tamb = 25°C unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit 200 270 mΩ 50 µA RdsON Power Pchannel/Nchannel MOSFET RdsON Id=1A; Idss Power Pchannel/Nchannel leakage Idss VCC=35V; gN Power Pchannel RdsON Matching Id=1A; 95 % gP Power Nchannel RdsON Matching Id=1A; 95 % Dt_s Low current Dead Time (static) see test circuit no.1; see fig. 1 Dt_d 20 ns High current Dead Time (dinamic) L=22µH; C = 470nF; Rl = 8 Ω Id=3.5A; see fig. 3 50 ns td ON Turn-on delay time Resistive load 100 ns td OFF Turn-off delay time Resistive load 100 ns tr Rise time Resistive load; as fig.1 25 ns tf Fall time Resistive load; as fig. 1 25 ns 36 V Ibias/2 +300mV V VCC Supply voltage operating voltage VIN-H High level input voltage VIN-L Low level input voltage IIN-H Hi level Input current 4/8 10 10 Ibias/2 -300mV Pin voltage = Ibias V 1 µA STA502 ELECTRICAL CHARACTERISTCS (continued) Symbol IIN-L Parameter Test conditions Low level input current IPWRDN-H Hi level PWRDN pin input current Min. Typ. Max. Unit Pin voltage = 0.3V 1 µA Ibias = 3.3V 35 µA VL Low logical state voltage VL (pin PWRDN, TRISTATE) (note 1) Ibias = 3.3V VH High logical state voltage VH (pin PWRDN, TRISTATE) (note 1) Ibias = 3.3V 1.7 V IVCCPWRDN Supply current from Vcc in Power Down PWRDN = 0 3 mA IFAULT Output Current pins FAULT -TH-WARN when FAULT CONDITIONS IVCC-hiz IVCC IVCC-q VOUT-SH VOV 0.8 V Vpin = 3.3V 1 mA Supply current from Vcc in Tristate Tri-state=0; 22 mA Supply current from Vcc in operation (both channel switching) Input pulse width = 50% Duty; Switching Frequency = 384KHz; No LC filters; 80 mA Isc (short circuit current limit) 4 Undervoltage protection threshold Output minimum pulse width 6 8 A 7 No Load 70 V 150 ns Notes: 1. The following table explains the VL, VH variation with Ibias Ibias VLmin VHmax Unit 2.7 0.7 1.5 V 3.3 0.8 1.7 V 5 0.85 1.85 V LOGIC TRUTH TABLE (see fig. 2) TRI-STATE INA INB Q1 Q2 Q3 Q4 OUTPUT MODE 0 x x OFF OFF OFF OFF Hi-Z 1 0 0 OFF OFF ON ON DUMP 1 0 1 OFF ON ON OFF NEGATIVE 1 1 0 ON OFF OFF ON POSITIVE 1 1 1 ON ON OFF OFF Not used 5/8 STA502 Figure 1. Test Circuit. OUTY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t DTr Duty cycle = 50% DTf M58 OUTY INY R 8Ω M57 + - gnd V67 = vdc = Vcc/2 D02AU1448 Figure 2. +VCC Q1 Q2 OUTA INA OUTB Q3 INB Q4 GND D02AU1450 Figure 3. High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B DTout(A) M58 DTin(A) Q1 Q2 Rload=8Ω OUTA INA Iout=4A M57 Q3 DTout(B) L67 22µ C69 470nF L68 22µ C71 470nF C70 470nF DTin(B) OUTB INB Iout=4A Q4 Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure 6/8 M64 M63 D03AU1517 STA502 DIM. A A2 A4 A5 a1 b c D D1 D2 E E1 E2 E3 E4 e e3 G H h L N s MIN. 3.25 mm TYP. 0.8 MAX. 3.5 3.3 1 MIN. 0.128 0.075 0.38 0.32 16 9.8 0 0.008 0.009 0.622 0.37 14.5 11.1 2.9 6.2 3.2 0.547 0.429 0.031 0.2 0 0.22 0.23 15.8 9.4 5.8 2.9 0.8 OUTLINE AND MECHANICAL DATA 0.003 0.015 0.012 0.630 0.38 0.039 0.57 0.437 0.114 0.244 1.259 0.228 0.114 0.65 11.05 0 15.5 MAX. 0.138 0.13 0.039 0.008 1 13.9 10.9 inch TYP. 0.026 0.435 0.075 0 15.9 0.61 1.1 1.1 0.031 10˚ (max) 8˚ (max) 0.003 0.625 0.043 0.043 PowerSO36 (SLUG UP) (1) “D and E1” do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006”) (2) No intrusion allowed inwards the leads. 7183931 7/8 STA502 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. 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