STMICROELECTRONICS STA529

STA529
2 x 100 mW class-D amplifier with analog or digital input
2.0 multichannel digital audio processor with FFX
Features
■
Up to 96 dB dynamic range
■
Sample rates from 8 kHz to 192 kHz
■
FFXTM class-D driver
■
1.5 V to 1.95 V digital power supply
■
1.5 V to 1.95 V analog power supply
■
18-bit audio processing and class-D FFXTM
modulator
■
Digital volume control:
– +36 dB to 105 dB in 0.5 dB steps
– Software volume update
■
Individual channel and master gain/attenuation
■
Automatic invalid input detect mute
■
2-channel I2S input/output data interface
■
Digitally controlled POP-free operation
■
Input and output channel mapping
■
250 mΩ output CMOS Rdson
■
> 90% efficiency
■
Stereo headphone plus mono speaker
application:
– 50 mW stereo into 32 Ω headphone
– 100 mW stereo into 16 Ω headphone
TFBGA48
VFQFPN52
Order codes
January 2007
Part number
Package
STA529B
TFBGA48 (tube)
STA529Q
VFQFPN52 (tube)
Rev 1
1/58
www.st.com
1
Contents
STA529
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Connection diagrams and pin descriptions . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
3
4
5
6
2.1.1
Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VFQFPN52 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.1
Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
Maximum and recommended operating conditions . . . . . . . . . . . . . . . . . 11
3.2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
Lock time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4
ADC performance values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Digital processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1
Signal processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2
I2C interface disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3
Volume control and gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2
Configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1
2/58
TFBGA48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.1
Digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.2
High-pass filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1.3
Programmable gain amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2
Application scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3
Configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STA529
7
Contents
Driver configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1
8
9
Serial audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.1
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.2
Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.3
Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.4
Serial formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11
12
8.4.1
DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.4.2
I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.4.3
PCM/IF (non-delayed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.4.4
PCM/IF (delayed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.1
Data transition and change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.2
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.3
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.4
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.5
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.6
Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.7
10
I2S bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.6.1
Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.6.2
Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.7.1
Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.7.2
Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.7.3
Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.7.4
Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.1
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.2
General registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.1
Package TFBGA48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.2
Package VFQFPN52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3/58
Introduction
1
STA529
Introduction
The STA529 is a digital stereo class-D audio amplifier. It includes an audio DSP, a ST
proprietary high-efficiency class-D driver and CMOS power output stage. It is intended for
high-efficiency digital-to-power-audio conversion for portable applications. The STA529 also
provides output capabilities for FFXTM. In conjunction with a power device, the STA529
provides high-quality digital amplification.
The STA529 contains an on-chip volume/gain control.
The PWM amplifier achieves greater than 90% efficiency for longer battery life for portable
systems.
The innovative class-D modulation, allows the STA529 to work without external LC filters
and without a heatsink.
The STA529 I2CDIS pin disables the audio DSP functions to provide a direct conversion of
the input signal into output power (the I2C interface is disabled). This conversion is done
without the microcontroller.
The STA529 is designed for low-power operation with extremely low-current consumption in
standby mode. It is available in two packages: the TFBGA48 and the VFQFPN52. These are
very thin packages (1.2 mm thick) intended for small portable applications.
VCC1
VCC2
GND1
GND2
VCC33
GND33
VDDIO
GNDIO
MUTE
POWERFAULT/
EADP
TM
RST_N
STBY
SDATAI
SDATAO/PWM2A
LRCLKI
LRCLKO/PWM1B
BICLKI
BICLKO/PWM1A
GND
Block diagram
VDD
Figure 1.
Serial digital
audio interface
MUX
CLKOUT/
PWM2B
GNDPLL
Divider
FILT
VDDPLL
MCLK33
PLL
XTI
XTO
AGND
AVCC
OSC
4/58
OUT2B
Control
interface
I2CDIS
ADC
INR
OUT1B
PWM out I/F
PGA
SELCLK33
VLO
OUT2A
SCL
VCM
Power
driver
SDA
ADC
MUX
MUX
INL
VHI
OUT1A
FFX
modulator
Digital
volume
VBIAS
Power
driver
STA529
2
Connection diagrams and pin descriptions
Connection diagrams and pin descriptions
This section includes connection diagrams and pin descriptions for the following packages:
●
TFBGA48
●
VFQFPN52
2.1
TFBGA48 package
2.1.1
Connection diagram
Figure 2 shows the connection diagram for the TFBGA48 package.
Figure 2.
Package: TFBGA48
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
5/58
Connection diagrams and pin descriptions
2.1.2
Pin description
Table 1.
6/58
STA529
Package: TFBGA48
Pin #
Name
Type
Description
D7
RST_N
Digital input
Reset (active low)
D1
XTI
Digital input
Crystal input or master clock input
E1
MCLK33
Digital input
Master clock input 3.3 V capable
XTI: crystal input or master clock input 3.3 V capable
G3
SELCLK33
Digital input
Master clock input selector:
SELCLK33 = 1 -> MCLK33 selected
SELCLK33 = 0 -> XTI selected
D2
XTO
Digital output
Crystal output
C7
CLKOUT/
PWM2B
Digital output
Buffered clock output / PWM2B FFXTm
F1
SCL
Digital input
I2C serial clock
G1
SDA
Digital
input/output
I2C serial data
G2
I2CDIS
Digital input
I2C disable pin (active high)
G8
STBY
Digital input
Standby (active high)
B7
MUTE
Digital input
Mute (active high)
H6
BICLKI
Digital
input/output
Input serial audio interface bit-clock
H5
LRCLKI
Digital
input/output
Input serial audio interface L/R-clock
E2
SDATAI
Digital input
Input serial audio interface data
G6
BICLKO/
PWM1A
Digital
input/output
Output serial audio interface bit-clock
(volume DOWN when I2CDIS = 1) / PWM1A FFXTm
G5
LRCLKO/
PWM1B
Digital
input/output
Output serial audio interface L/R-clock
(volume UP when I2CDIS = 1) / PWM1B FFXTm
G4
SDATAO/
PWM2A
Digital output
Output serial audio interface data / PWM2A FFXTm
H2
TM
Digital input
Test mode (active high)
H7
INL
Analog input
ADC left channel line input or microphone input
H8
INR
Analog
input/output
ADC right channel line input
G7
VBIAS
Analog
input/output
ADC microphone bias voltage
D8
VCM
Analog
input/output
ADC common mode voltage
F8
AVDD
Supply
ADC analog supply
E8
AGND
Ground
ADC analog ground
STA529
Connection diagrams and pin descriptions
Table 1.
Pin #
Name
F7
VHI
Analog input
ADC high reference voltage
E7
VLO
Analog input
ADC low reference voltage
H1
FILT
Analog
input/output
PLL loop filter terminal
H4
VDDPLL
Supply
PLL analog supply
H3
GNDPLL
Ground
PLL analog ground
A6
OUT1A
Analog output
Channel 1 half-bridge A output
B6
OUT1A
Analog output
Channel 1 half-bridge A output
A5
OUT1B
Analog output
Channel 1 half-bridge B output
B5
OUT1B
Analog output
Channel 1 half-bridge B output
A3
OUT2A
Analog output
Channel 2 half-bridge A output
B3
OUT2A
Analog output
Channel 2 half-bridge A output
A4
OUT2B
Analog output
Channel 2 half-bridge B output
B4
OUT2B
Analog output
Channel 2 half-bridge B output
F2
2.1.3
Package: TFBGA48 (continued)
Type
POWERFAULT/
Digital output
EADP
Description
Power fault signal (active high) /
external audio power-down signal
A8
VCC1
Supply
Channel 1 power supply
A1
VCC2
Supply
Channel 2 power supply
A7
GND1
Ground
Channel 1 power ground
A2
GND2
Ground
Channel 2 power ground
C2
VCC33
Supply
Pre-driver supply
B2
GND33
Ground
Pre-driver ground
C8
VDD
Supply
Digital supply
B8
GND
Ground
Digital ground
C1
VDDIO
Supply
I/O ring supply
B1
GNDIO
Ground
I/O ring ground
Thermal data
Table 2 gives the thermal resistance specifications for the TFBGA48 and the VFQFPN52.
Table 2.
Device
Thermal data
Parameter
Min
Typ
Max
Unit
TFBGA48
Thermal resistance junction to ambient
72
oC/W
VFQFPN52
Thermal resistance junction to ambient
22
oC/W
7/58
Connection diagrams and pin descriptions
2.2
VFQFPN52 package
2.2.1
Connection diagram
STA529
Figure 3 shows the connection diagram for the VFQFPN52 package.
Figure 3.
Package: VFQFPN52
27
26
40
14
52
13
8/58
39
1
STA529
2.2.2
Connection diagrams and pin descriptions
Pin description
Table 3.
Package: VFQFPN52
Pin #
Name
Type
Description
10
RST_N
Digital input
Reset (active low)
38
XTI
Digital input
Crystal input or master clock input
37
MCLK33
Digital input
Master clock input 3.3 V capable
XTI: crystal input or master clock input 3.3 V capable
36
SELCLK33
Digital input
Master clock input selector:
SELCLK33 = 1 -> MCLK33 selected
SELCLK33 = 0 -> XTI selected
39
XTO
Digital output
Crystal output
11
CLKOUT
Digital output
Buffered clock output
34
SCL
Digital input
I2C serial clock
35
SDA
Digital
input/output
I2C serial data
33
I2CDIS
Digital input
I2C disable pin (active high)
1
STBY
Digital input
Standby (active high)
14
MUTE
Digital input
Mute (active high)
51
BICLKI
Digital
input/output
Input serial audio interface bit-clock
47
LRCLKI
Digital
input/output
Input serial audio interface L/R-clock
45
SDATAI
Digital input
Input serial audio interface data
52
BICLKO
Digital
input/output
Output serial audio interface bit-clock
(volume DOWN when I2CDIS=1)
48
LRCLKO
Digital
input/output
Output serial audio interface L/R-clock
(volume UP when I2CDIS=1)
46
SDATAO
Digital output
Output serial audio interface data
32
TM
Digital input
Test mode (active high)
2
INL
Analog input
ADC left channel line input or microphone input
3
INR
Analog
input/output
ADC right channel line input
4
VBIAS
Analog
input/output
ADC microphone bias voltage
9
VCM
Analog
input/output
ADC Common mode voltage
5
AVDD
Supply
ADC analog supply
8
AGND
Ground
ADC analog ground
6
VHI
Analog input
ADC High reference voltage
9/58
Connection diagrams and pin descriptions
Table 3.
Package: VFQFPN52 (continued)
Pin #
Name
7
VLO
Analog input
ADC Low reference voltage
40
FILT
Analog
input/output
PLL loop filter terminal
42
VDDPLL
Supply
PLL analog supply
41
GNDPLL
Ground
PLL analog ground
16
OUT1A
Analog output
Channel 1 half-bridge A output
19
OUT1B
Analog output
Channel 1 half-bridge B output
25
OUT2A
Analog output
Channel 2 half-bridge A output
22
OUT2B
Analog output
Channel 2 half-bridge B output
31
10/58
STA529
Type
POWERFAULT/
Digital output
EADP
Description
Power fault signal (active high)/external audio power
down signal
15
VCC1A
Supply
Channel 1 half-bridge A power supply
20
VCC1B
Supply
Channel 1 half-bridge B power supply
26
VCC2A
Supply
Channel 2 half-bridge A power supply
21
VCC2B
Supply
Channel 2 half-bridge B power supply
17
GND1A
Ground
Channel 1 half-bridge A power ground
18
GND1B
Ground
Channel 1 half-bridge B power ground
24
GND2A
Ground
Channel 2 half-bridge A power ground
23
GND2B
Ground
Channel 2 half-bridge B power ground
30
VCC33
Supply
Pre-driver supply
27
GND33
Ground
Pre-driver ground
13
VDD1
Supply
Digital supply
12
GND1
Ground
Digital ground
44
VDD2
Supply
Digital supply
43
GND2
Ground
Digital ground
29
VDDIO1
Supply
I/O ring supply
28
GNDIO1
Ground
I/O ring ground
50
VDDIO2
Supply
I/O ring supply
49
GNDIO2
Ground
I/O ring ground
STA529
3
Electrical specifications
Electrical specifications
This section includes the electrical specifications for the STA529.
3.1
Maximum and recommended operating conditions
Table 4 provides the maximum ratings and Table 5 the recommended operating conditions.
Table 4.
Absolute maximum ratings
Signal
Note:
Description
Min
Max
Unit
VDD/VDD1/VDD2
Digital supply voltage
-0.5
+2.5
V
AVDD
ADC supply voltage
-0.5
+4
V
VDDPLL
PLL analog supply voltage
-0.5
+2.5
V
VCC1A/1B/2A/2B
Power stage supply voltage
-0.5
+4
V
VCC33
Pre-driver supply
-0.5
+4
V
VDDIO
Digital I/O supply
-0.5
+4
V
VDI
Voltage range digital in
-0.5
VDDIO +0.3
V
VAI
Voltage range analog in
-0.5
AVDD +0.3
V
Vo
Voltage on output pins
-0.5
VDDIO +0.3
V
TSTG
Storage temperature
-40
150
oC
TAMB
Ambient operating temperature
-20
85
oC
Min
Typ
Max
Unit
All grounds must be within 0.3 V of each other.
Table 5.
Recommended operating conditions
Symbol
Parameter
VDD/VDD1/VDD2
Digital supply voltage
1.55
1.8
1.95
V
AVDD
ADC supply voltage
1.8
3.3
3.6
V
VDDPLL
PLL analog supply voltage
1.55
1.8
1.95
V
VCC1A/1B/2A/2B
Power stage supply voltage
1.8
3.3
3.6
V
VCC33
Pre-driver supply
1.8
3.3
3.6
V
GND1, GND2,
GND33
Channel 1 and 2 power
ground, pre-driver ground
TAMB
Ambient operating
temperature
0
0
25
70
o
C
11/58
Electrical specifications
3.2
STA529
Electrical characteristics
Table 6 lists the device’s electrical characteristics (see also Table 5 for supply voltages).
Table 6.
Electrical characteristics
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
Eff
Output power efficiency
90
%
Rdson
Output stage N/PMOS onresistance
250
mΩ
IstbyL
Logic power supply current at
standby
1.3
µA
IstbyP
Bridges power supply current in
standby
0.7
µA
IddL
Logic power supply current at
operating
15
mA
IddP
Bridges power supply current at
operating
0.5
mA
Tds
Low current dead time (static)
1
ns
Tdd
High current dead time
(dynamic)
2.5
ns
Tr
Rise time
3
ns
Tf
Fall time
3
ns
THDN
Total harmonic distortion
0 dBFS input, 32 Ω load
headphone
0.1
%
THDN
Total harmonic distortion
-6 dBFS input, 32 Ω load
headphone
0.05
%
Note:
12/58
LRCLKI frequency (Fs) = 48 kHz, input frequency = 1 kHz, and Rload = 32 Ω unless
otherwise specified.
STA529
Electrical specifications
The following tables give the distortion values for headphones and speakers.
Table 7.
3.3
Load power at 1% distortion headphone mode
Load (Ω)
P (mW) at 1.8 V
P (mW) at 3.3 V
P (mW) at 3.6 V
16
20
70
80
32
10
32
40
Lock time
Table 8 gives the typical lock time of the PLL using the suggested loop filter, 1.8 V supply
voltage and 30 oC junction temperature.
Table 8.
PLL lock time
Parameter
Value
Lock time
200 µs
13/58
Electrical specifications
3.4
STA529
ADC performance values
Table 9.
Programmable gain performance
Parameter
Min
Typ
Dynamic range 1 kHz 1.8 V supply
Dynamic range 1 kHz 1.8 V supply A-weighted
Unit
dB
84
SNDR 1 kHz 1.8 V supply
dB
dB
SNDR 1 kHz 1.8 V supply A-weighted
84
dB
THD 1 kHz (-1 dB input) 1.8 V supply
75
dB
Deviation from linear phase
14/58
Max
degree
Pass band
kHz
Pass band ripple
dB
Stop band
kHz
Stop band attenuation
dB
Group delay 8 kHz
ms
Group delay 48 kHz
ms
Cross talk 1.8 V
dB
Cross talk 3.3 V
dB
STA529
4
Digital processing
Digital processing
The STA529 processor block is a digital block providing two channels of audio processing
and channel-mapping capability.
4.1
Signal processing flow
I2S or stereo ADC data can be selected. The I2S frequency range is from 8 kHz to 192 kHz.
ADC sampling frequency can be selected from 8 kHz to 48 kHz.
4.2
I2C interface disabled
When pin I2CDIS = 1, the SDA, SCL, LRCLKO and BICLKO pins can be pulled high or low
to change certain parameters of operation.
●
SDA = 0: FFX input comes from ADC
SDA = 1: FFX input comes from digital audio interface
●
SCL = 0: binary output mode (binary soft start/stop enabled)
SCL = 1: phase shift output mode
●
LRCLKO = 0: no volume change
LRCLKO = 1: volume up
●
BICLKO = 0: no volume change
BICLKO = 1: volume down
At power up, the master volume is set to -60 dB. When holding pin LRCLKO = 1 and pin
BICLKO = 1 simultaneously, the master volume is set to 0 dB. A high pulse on pin LRCLKO
causes a master volume change of +0.5 dB and a high pulse on pin BICLKO causes a
master volume change of -0.5 dB.
15/58
Digital processing
4.3
STA529
Volume control and gain
The volume control structure of the STA529 consists of individual volume registers for each
channel and a master volume register that provides an offset to each channel’s volume
setting. The individual channel volumes are adjustable in 0.5 dB steps from +36 dB to
-91.5 dB. As an example, if register LVOL = 0x00 or +36 dB and register MVOL = 0x18 or
-12 dB, then the total gain for the left channel is +24 dB.
When the mute bit is set to 1, all channels are muted. The volume control provides a soft
mute with the volume ramping down to mute in 4096 samples from the maximum volume
setting at the internal processing rate (~48 kHz).
Table 10.
Table 11.
16/58
Master volume offset as a function of register MVOL
MVOL[7:0]
Volume offset from channel value
0x00
0 dB
0x01
-0.5 dB
0x02
-1dB
…
…
0x78
-60 dB
…
…
0xFE
-105 dB
0xFF
Hard master mute
Channel volume as a function of registers LVOL and RVOL
LVOL/RVOL[7:0]
Volume
0x00
+36 dB
0x01
+35.5 dB
0x02
+35 dB
…
…
0x47
+0.5 dB
0x48
0 dB
0x49
-0.5 dB
…
…
…
…
0xFF
-91.5 dB
STA529
PLL
5
PLL
Figure 4 shows the main components of the PLL.
Figure 4.
PLL block diagram
INFIN
CLKIN
Input frequency
divider
FBCLK
LOCKP
Lock detect
IDF
FILT
INFIN
Buffer
INFOUT
REFOUT
Phase
frequency
divider
(PFD)
LF
Charge
pump and
loop filter
VCONT
FBCLK
VCO
FVCO
Loop frequency divider
STRB
STRB_
BYPASS
FRAC_CTRL
DITHER_DISABLE
FRAC_INPUT
Fractional controller
Output
frequency
divider
PHI
NDIV
17/58
PLL
5.1
STA529
Functional description
Phase/frequency detector
The phase/frequency detector (PFD) compares the phase difference between the
corresponding rising edges of INFIN and FBCLK, (clock output from the loop frequency
divider) by generating voltage pulses with widths proportional to the input phase error.
Charge pump and loop filter
This block converts the voltage pulses from the phase/frequency detector to current pulses
which charge the loop filter and generate the control voltage for the voltage-controlled
oscillator. The loop filter is placed external to the PLL on pin FILT.
Voltage controlled oscillator
The voltage controlled oscillator (VCO) is the oscillator inside the PLL. It produces a
frequency output (FVCO) proportional to the input control voltage.
Input frequency divider
This frequency divider divides the PLL input clock CLKIN by a factor called the input division
factor (IDF) to generate the PFD input frequency INFIN.
Loop frequency divider
This frequency divider is present within the PLL for dividing FVCO by a factor called the loop
division factor (LDF). The output of this block is the FBCLK.
Output frequency divider
The PLL output PHI is generated by dividing the FVCO by the output division factor (ODF).
The divider that divides the FVCO to generate the clock to the core is called the output
frequency divider. In the STA529, the ODF is fixed to be divisible by 2 and cannot be
configured.
Lock-detect circuit
The output of this block (the LOCKP signal) is asserted high when the PLL enters the state
of COARSE LOCK in which the output frequency is within +/-10% (approximately) of the
desired frequency. The LOCKP signal is refreshed every 32 cycles of the INFIN. The
generated value is based on the result of comparing the number of FBCLK cycles in a
window of 14 INFIN cycles. The different cases generated after comparison are as follows.
18/58
●
If LOCKP is already at 0, then in the next refresh cycle LOCKP goes to 1 if the number
of FBCLK cycles in the 14-cycle INFIN window is 13, 14, or 15. Otherwise LOCKP
stays at 0.
●
If LOCKP is already at 1, then in the next refresh cycle LOCKP goes to 0 if the number
of FBCLK cycles in the 25-cycle INFIN window is less than 11 or higher than 17,
otherwise LOCKP stays at 1.
●
If LOCKP is already at 1 and CLKIN is lost (no longer present on the input pin), LOCKP
stays at 1. In this case, the PLL is unlocked.
STA529
PLL
PLL filter
Figure 5 shows the PLL filter scheme. Recommended values are R1 = 12.5 kΩ,
C1 = 250 pF, and C2 = 82 pF.
Figure 5.
PLL filter scheme
Vc
R1
C2
C1
Ground
Table 8 on page 13 gives a typical lock time value for the PLL.
5.2
Configuration examples
The STA529 PLL can be configured in two ways:
●
default startup configuration
●
direct PLL programming
The default startup configuration reads the device’s defaults. With this configuration, it is not
necessary to program the PLL dividers directly as some presets are used. In this mode, the
oversampling ratio between pins XTI (or MCLK33) and LRCLKI is fixed to 256.
The direct PLL programming bypasses the automatic presets allowing direct programming
of the PLL dividers.
The output PLL frequency can be determined as following:
Output division factor:
ODF = 2
Relation between input and output clock frequency:
FINFIN = FXTI / IDF
If register bit PLLCFG0.FRAC_CTRL = 1
FVCO = FINFIN * (LDF + FRACT/216 + 1/217)
FPHI = FVCO / ODF
When register bit PLLCFG0.DITHER_DISABLE[1] = 1, the 1/217 factor is not in the
multiplication. This is recommended in order to keep register bit
PLLCFG0.DITHER_DISABLE[1] = 0, otherwise there can be spurious signals in the output
clock spectrum.
19/58
PLL
STA529
If register bit PLLCFG0.FRAC_CTRL = 0, then:
FVCO = FINFIN * LDF
FPHI = FVCO / ODF
In the above equations:
FRACT = Decimal equivalent of register bit PLLCFG1.FRAC_INPUT[15:0]
IDF = Input division factor (refer to previous formulas)
LDF = Loop division factor (refer to previous formulas)
ODF = Output division factor = 2
FINFIN = INFIN frequency
FXTI = XTI frequency
FVCO = VCO frequency
FPHI = Frequency of the PLL output clock
When selecting the value of IDF, LDF and FRACT make sure the following limits are
maintained:
2.048 MHz < FXTI < 49.152 MHz
2.048 MHz < FINFIN < 16.384 MHz
65.536 MHz < FVCO < 98.304 MHz
There are also some additional constraints on IDF and LDF. IDF should be greater than 0,
LDF should be greater than 5 if FRAC_CTRL = 0 and greater than 8 if FRAC_CTRL = 1.
When automatic settings are not used, the PLL must be configured to generate an internal
frequency of N * Fs, where Fs is the LRCLKI pin frequency. Values of N are given in
Table 12.
Table 12.
20/58
Oversampling table
Fs (kHz)
N
FPHI (MHz)
8
4096
32.768
11.025
4096
45.1584
12
4096
49.152
16
2048
32.768
22.05
2048
45.1584
24
2048
49.152
32
1024
32.768
44.1
1024
45.1584
48
1024
49.152
64
512
32.768
88.2
512
45.1584
96
512
49.152
128
256
32.768
176.4
256
45.1584
192
256
49.152
STA529
PLL
Example 1:
FXTI = 13 MHz
Fs = 44.1 kHz
IDF should be equal to 3 otherwise LDF become less than 8 (FRAC_CTRL must be 1):
LDF = floor(45.1584/(13/IDF)) = 10
FRACT = round([(45.1584/(13/ IDF))-floor(45.1584/(13/ IDF))]*216) = 27602
(where:
floor: rounded towards zero
round: rounded real number to nearest integer)
Using the above configuration, the system clock is 45.15841675 MHz, the approximate
static error is 16 Hz (that is, 0.5 ppm).
Example 2:
FXTI = 19.2 MHz
Fs = 48 kHz
IDF should be equal to 4 otherwise LDF become less than 8 (FRAC_CTRL must be 1):
LDF = floor(49.152/(19.2/IDF)) = 10
FRACT = round([(49.152/(19.2/IDF))-floor(49.152/(19.2/IDF))]*216) = 15728
Using the above configuration, the system clock is 49.151953125 MHz, the approximate
static error is 47 Hz (that is, 1 ppm).
21/58
ADC
6
STA529
ADC
This section describes the analog-to-digital converter (ADC).
6.1
Functional description
The STA529 analog input is provided through a low power, low voltage, stereo audio analogto-digital converter front-end designed for audio applications. It includes a programmable
gain amplifier, anti-aliasing filter, low-noise microphone biasing circuit, a third-order
MASH2-1 delta-sigma modulator, digital decimating filter, and a first-order DC-removal filter.
This device is fabricated using a 0.18 µm CMOS process, where high-speed precision
analog circuits are combined with high-density logic circuits.
The ADC works in a microphone input (mic-in) mode and in a line-input mode.
If the line input mode is selected, the ADC is configured in stereo and all conversion
channels are active.
If the microphone input mode is selected, the ADC is configured in mono. The mono
channel is routed through the left conversion path, and the right conversion path is kept in
power-down mode to minimize power consumption. A programmable gain amplifier (PGA) is
available in mic-in mode, giving the possibility to amplify the signal from 0 to +42 dB in steps
of 6 dB.
6.1.1
Digital filter characteristics
The digital filter characteristics are shown in Table 13.
Table 13.
Digital filter characteristics
Parameter
Passband
Passband ripple:
Fs mode
Fs_by_2 mode
Fs_by_4 mode
Stop band attenuation:
Fs mode
Fs_by_2 mode
Fs_by_4 mode
Group delay:
Fs mode
Fs_by_2 mode
Fs_by_4 mode
22/58
Typical
Unit
0.4535 * Fs
kHz
0.08 at 44.1 kHz
0.08 at 22.05 kHz
0.08 at 11.025 kHz
dB
dB
dB
45 at 44.1 kHz
45 at 22.05 kHz
45 at 11.025 kHz
dB
dB
dB
0.4 at 32 kHz
0.7 at 16 kHz
1.4 at 8 kHz
ms
ms
ms
STA529
6.1.2
ADC
High-pass filter characteristics
Table 14.
High-pass filter characteristics
Parameter
Typical
Unit
7
50
Hz
Hz
Phase deviation at 20 Hz
19.35
degree
Passband ripple
0.08
dB
Frequency response:
-3 dB
-0.08 dB
6.1.3
Programmable gain amplifier
The programmable gain amplifier (PGA) is available in mic-in mode only. It is possible to
amplify the input signal from 0 to 42 db in steps of 6 db. The setting is done through PGA
bits of the ADCCFG register (see ADCCFG on page 49 for details).
See Table 9 on page 14 for performance values.
6.2
Application scheme
Figure 6 shows the filter circuit.
Figure 6.
Block diagram
C9
AC coupled
INL
DC coupled
C0
AC coupled
INR
DC coupled
1.8 V supply
AVDD
VSSA
C5
R1
VHI
VSSA
VCM
3 V, 3 A must be a
low-noise supply and
separate from
other supplies
C3
VBIAS
C8
VSSA plane must be
different from other
ground plane
C2
VLO
C7
C5, C6, C7 = 33 µF
(Low ESR and ESL
capacitors are
recommended)
C1
AGND
C6
C1, C2, C3, C4 = 10 nF
(These capacitors must be
placed very close to their
respective pins)
R1 = 500 Ω
C8 = 10 µF
C9, C0 = 1 µF
C4
23/58
ADC
6.3
STA529
Configuration examples
The ADC sampling frequency can be selected from three values:
●
normal (from 32 kHz to 48 kHz)
●
low (from 16 kHz to 24 kHz)
●
very-low (from 8 kHz to 12 kHz)
The setting is done through register bits MISC.ADC_FS_RANGE (see MISC on page 50 for
details). For all other settings, register ADCCFG is used (see ADCCFG on page 49 for
details).
24/58
STA529
7
Driver configuration
Driver configuration
A driver configuration is available that allows PWM commands to be used on an external
power device. For this purpose, the output serial audio interface is disabled and the
respective pins have an alternative name and new functionality, as shown in Table 15.
Table 15.
Pin functionality in driver-configuration mode
Pin
Alternative pin name and functionality
BICLKO
PWM1A (external bridge PWM command for output 1A)
LRCLKO
PWM1B (external bridge PWM command for output 1B)
SDATAO
PWM2A (external bridge PWM command for output 2A)
CLKOUT
PWM2B (external bridge PWM command for output 2B)
POWERFAULT
EADP (external audio power-down signal)
The driver configuration is selected with two programmable registers PWMINT1 = 0x93 and
PWMINT2 = 0x81 (see PWMINT1 on page 51 and PWMINT2 on page 51).
7.1
I2S bypass
A configuration is available which allows the bypassing of the I2S input signal straight to the
I2S output signal.
This configuration is set using two programmable registers PWMINT1 = 0x93 and
PWMINT2 = 0x80 (see PWMINT1 on page 51 and PWMINT2 on page 51).
25/58
Serial audio interface
8
STA529
Serial audio interface
This section includes information about the audio interface.
8.1
Specifications
The serial-to-parallel interface and the parallel-to-serial interface can have different
sampling rates.
The following terms are used in this section:
26/58
●
BICLK active edge: Pins SDATAI, SDATAO, LRCLKI, LRCLKO always change
synchronously with BITCLK active edges. The active edge can be configured to a rising
or falling edge via register programming.
●
BICLK strobe edge: Pins SDATAI, SDATAO, LRCLKI, LRCLKO should be stable near
BICLK strobe edges, the slave device is able to use strobe edges to latch serial data
internally.
STA529
8.2
Serial audio interface
Master mode
In this mode, pins BICLKI/BICLKO and pins LRCLKI/LRCLKO are configured as outputs.
Figure 7.
Master mode
BICLKI/
BICLKO
tDL
LRCLKI/
LRCLKO
tDDA
SDATAO
SDATAI
tDST
Table 16.
tDHT
Master mode
Parameter
Symbol
Min
LRCLKI/LRCLKO propagation delay from BICLK active
edge
tDL
SDATAI propagation delay from BICLKI/O active edge
Typ
Max
Unit
0
10
ns
tDDA
0
15
ns
Sdatao setup time to BICLKI/O strobing edge
tDST
10
ns
Sdatao hold time from BICLKI/O strobing edge
tDHT
10
ns
27/58
Serial audio interface
8.3
STA529
Slave mode
In this mode, pins BICLKI/O and pins LRCLKI/O are configured as inputs.
Figure 8.
Slave mode
tBCH
tBCL
BICLKI/
BICLKO
tBCY
LRCLKI/
LRCLKO
tDS
tLRH
tLRSU
SDATAO
tDH
SDATAI
tDD
Table 17.
Slave mode
Parameter
28/58
Symbol
Min
Typ
Max
BICLK cycle time
tBCY
50
ns
BICLK pulse width high
tBCH
20
ns
BICLK pulse width low
tBCL
20
ns
LRCLKI/LRCLKO setup time to BICLK strobing edge
tLRSU
10
ns
LRCLKI/LRCLKO hold time to BICLK strobing edge
tLRH
10
ns
SDATAO setup time to BICLK strobing edge
tDS
10
ns
SDATAO hold time to BICLK strobing edge
tDH
10
ns
SDATAI propagation delay from BICLK active edge
tDD
0
10
Unit
ns
STA529
8.4
Serial audio interface
Serial formats
Different audio formats are supported in both master and slave modes. Clock and data
configurations can be customized to match most of the serial audio protocols available on
the market.
Data length can be customized for 8-, 16-, 24-, and 32-bit.
Figure 9.
Right justified
LRCLKI/
LRCLKO
BICLKI/
BICLKO
SDATAI/
SDATAO
n-1 n
1 2 3
n-1 n
1 2 3
Figure 10. Left justified
LRCLKI/
LRCLKO
BICLKI/
BICLKO
SDATAI/
SDATAO
1 2 3
n-1 n
1 2 3
n-1 n
29/58
Serial audio interface
8.4.1
STA529
DSP
Figure 11. DSP
LRCLKI/
LRCLKO
BICLKI/
BICLKO
Left
SDATAI/
SDATAO
8.4.2
1 2 3
Right
n-1 n 1 2 3
n-1 n
I2S
Figure 12. I2S
LRCLKI/
LRCLKO
BICLKI/
BICLKO
SDATAI/
SDATAO
30/58
1 2 3
n-1 n
1 2 3
n-1 n
STA529
8.4.3
Serial audio interface
PCM/IF (non-delayed mode)
●
MSB first
●
16-bit data
Figure 13. PCM/IF (non delayed mode)
Any width
LRCLKI/
LRCLKO
BICLKI/
BICLKO
SDATAI/
SDATAO
8.4.4
1 2 3
n-1 n
PCM/IF (delayed mode)
●
MSB first
●
16-bit data
Figure 14. PCM/IF (delayed mode)
LRCLKI/
LRCLKO
BICLKI/
BICLKO
SDATAI/
SDATAO
1 2 3
n-1 n
31/58
I2C interface
9
STA529
I2C interface
This section describes the communication protocol of the I2C interface.
9.1
Data transition and change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition
while the clock is high is used to identify a start or stop condition.
9.2
Start condition
A start condition is identified by a high to low transition of the data bus SDA signal while the
clock signal SCL is stable in the high state. A start condition must precede any command for
data transfer.
9.3
Stop condition
A stop condition is identified by low to high transition of the data bus SDA signal while the
clock signal SCL is stable in the high state. A stop condition terminates communication
between the STA529 and the master bus.
9.4
Data input
During data input, the STA529 samples the SDA signal on the rising edge of clock SCL. For
correct device operation the SDA signal must be stable during the rising edge of the clock
and the data can change only when the SCL line is low.
9.5
Device addressing
To start communication between the master and the STA529, the master must initiate with a
start condition. Following this, the master sends onto the SDA line 8 bits (MSB first)
corresponding to the device select address and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I2C bus
definition. In the STA529, the I2C interface has the device address 0x34.
The 8th bit (LSB) identifies read or write operation (R/W), this bit is set to 1 in read mode
and 0 in write mode. After a start condition, the STA529 identifies on the bus the device
address and if a match is found, it acknowledges the identification on SDA bus during the
9th bit time. The byte following the device identification byte is the internal space address.
32/58
I2C interface
STA529
9.6
Write operation
Following the start condition the master sends a device select code with the R/W bit set to 0.
The STA529 acknowledges this and the writes to the byte of the internal address. After
receiving the internal byte address, the STA529 responds with an acknowledgement.
9.6.1
Byte write
In the byte-write mode the master sends one data byte. This is acknowledged by the
STA529. The master then terminates the transfer by generating a stop condition.
9.6.2
Multi-byte write
The multi-byte write modes can start from any internal address. The master generates a
stop condition which terminates the transfer.
9.7
Read operation
9.7.1
Current address byte read
Following the start condition the master sends a device select code with the R/W bit set
to 1. The STA529 acknowledges this and then responds by sending one byte of data. The
master then terminates the transfer by generating a stop condition.
9.7.2
Current address multi-byte read
The multi-byte read modes can start from any internal address. Sequential data bytes are
read from sequential addresses within the STA529. The master acknowledges each data
byte read and then generates a stop condition terminating the transfer.
9.7.3
Random address byte read
Following the start condition the master sends a device select code with the R/W bit set to 0.
The STA529 acknowledges this and then the master writes the internal address byte. After
receiving the internal byte address, the STA529 again responds with an acknowledgement.
The master then initiates another start condition and sends the device select code with the
R/W bit set to 1. The STA529 acknowledges this and then responds by sending one byte of
data. The master then terminates the transfer by generating a stop condition.
33/58
I2C interface
9.7.4
STA529
Random address multi-byte read
The multi-byte read modes could start from any internal address. Sequential data bytes are
read from sequential addresses within the STA529. The master acknowledges each data
byte read and then generates a stop condition terminating the transfer.
Figure 15. I2C write operations
ACK
ACK
Byte
Write
Start
Dev address
R/W
Sub address
Start
Dev address
R/W
Data in
Stop
ACK
ACK
Multibyte
Write
ACK
ACK
Sub address
ACK
Data in
Data in
Stop
Figure 16. I2C read operations
ACK
Current
address
read Start
Dev address
R/W
No ACK
Data
ACK
Random
address
read Start
Dev address
R/W
ACK
Sub address
ACK
Sequential
current
read Start
Dev address
R/W=High
Dev address
R/W
ACK
Start
Dev address
ACK
No ACK
Data
ACK
Dev address
R/W
Data
ACK
Data
34/58
Stop
ACK
ACK
Start
Stop
No ACK
Data
ACK
Sub address
R/W
Data
Data
ACK
Sequential
random
read Start
Stop
No ACK
Data
Stop
STA529
10
Registers
Registers
This section includes register information.
10.1
Summary
Table 18.
Register summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
0x00
FFXCFG0
MUTE
POW_STBY
SOFT_
VOL_ON
BIN_SOFTS
TART
0x01
FFXCFG1
L1_R2
MUTE_ON_
INVALID
0x02
MVOL
SET_VOL_MASTER[7:0]
0x03
LVOL
SET_VOL_LEFT[7:0]
0x04
RVOL
SET_VOL_RIGHT[7:0]
0x05
TTF0
TIM_TS_FAULT[15:8]
0x06
TTF1
TIM_TS_FAULT[7:0]
0x07
TTP0
TIM_TS_POWUP[15:8]
0x08
TTP1
TIM_TS_POWUP[7:0]
0x0A
S2PCFG0
BICLK_
STRB
0x0B
S2PCFG1
PDATA_LENGTH[1:0]
0x0C
P2SCFG0
BICLK_
STRB
0x0D
P2SCFG1
PDATA_LENGTH[1:0]
0x14
PLLCFG0
0x15
PLLCFG1
FRAC_INPUT[15:8]
0x16
PLLCFG2
FRAC_INPUT[7:0]
0x17
PLLCFG3
STRB
STRB_BYP
ASS
0x18
PLLPFE
PLL_BYP_
UNL
BICLK2PLL
PLL_PWDN
0x19
PLLST
PLL_UNLO
CK
PLL_PWD_
STATE
PLL_BYP_
STATE
0x1E
ADCCFG
0x1F
CKOCFG
CLKOUT_
DIS
0x20
MISC
OSC_DIS
0x21
PADST0
Reserved
0x22
PADST1
Reserved
0x23
FFXST
0x28
BISTRUN
PLL_DIREC
T_PROG
LRCLK_
LEFT
Bit 3
SDATAO_
ACT
MSB_FIRST
MASTER_
MODE
DATA_FORMAT[2:0]
MAP_L[1:0]
MSB_FIRST
MAP_R[1:0]
MASTER_
MODE
DATA_FORMAT[2:0]
BICLK_OS[1:0]
FRAC_
CTRL
Bit 0
PWM_SHIFT[1:0]
BICLK_OS[1:0]
LRCLK_
LEFT
Bit 1
TIM_SOFT_VOL[3:0]
PWM_MODE[1:0]
SHARE_
BILR
Bit 2
MAP_L[1:0]
DITHER_DISABLE[1:0]
MAP_R[1:0]
IDF[3:0]
NDIV[5:0]
PGA[2:0]
PFE1A
PFE1B
PFE2A
PFE2B
INSEL
STBY
BYPASS_
CALIB
CLKENBL
RESET_FA
ULT
CLKOUT_SEL[1:0]
P2P_FS_RANGE[2:0]
ADC_FS_RANGE[1:0]
INVALID_
INP_FBK
P2P_IN_
ADC
CORE_
CLKENBL
MUTE_
INT_FBK
BINSS_FBK
Reserved
35/58
Registers
STA529
Table 18.
Register summary (continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0x29
BISTST0
Reserved
0x2A
BISTST1
Reserved
0x2B
BISTST2
Reserved
0x2D
PWMINT1
PWM_INT[15:8]
0x2E
PWMINT2
0x32
10.2
Bit 1
POW_
TRISTATE
POW_
FAULT1A
POW_
FAULT1B
POW_
FAULT2A
POW_
FAULT2B
General registers
FFXCFG0
Bit 7
MUTE
FFX configuration register 0
Bit 6
POW_STBY
Address:
0x00
Type:
R/W
Buffer:
No
Reset:
0x75
Bit 5
Bit 4
SOFT_VOL_ON
BIN_
SOFTSTART
Bit 3
Bit 2
Bit 1
TIM_SOFT_VOL[3:0]
Description:
7 MUTE:
0: default
1: FFX output is zero
6 POW_STBY:
0: FFX bridge is in power-up mode
1: FFX bridge is put in standby mode (default)
5 SOFT_VOL_ON:
0: smooth transition not active
1: smooth transition when changing volume control (default)
4 BIN_SOFTSTART:
Reserved (1: default)
3:0 TIM_SOFT_VOL: volume control time step for any 0.5 dB volume change
Time is (2TIM_SOFT_VOL) * 20.83 µs
Default is 666.66 µs
36/58
Bit 0
PWM_INT[7:0]
POWER
DOWN
POWST
Bit 2
Bit 0
STA529
Registers
FFXCFG1
Configuration register 1
Bit 7
Bit 6
L1_R2
MUTE_ON_
INVALID
Address:
0x01
Type:
R/W
Buffer:
No
Reset:
0xf8
Bit 5
Bit 4
PWM_MODE[1:0]
Bit 3
Bit 2
Bit 1
Bit 0
PWM_SHIFT[1:0]
Description:
7 L1_R2: channel mapping:
0: right channel is mapped to output channel 1 and left channel is mapped to output
channel 2
1: left channel is mapped to output channel 1 and right channel is mapped to output
channel 2 (default)
6 MUTE_ON_ INVALID: mutes PWM outputs if invalid digital data is received:
0: outputs are not muted
1: outputs are muted (default)
5:4 PWM_MODE[1:0]:
00: binary (output B is opposite of output A)
01: binary headphones (output B is 50 % duty cycle)
10: ternary
11: phase shift (default)
3:2 PWM_SHIFT[1:0]:
10: default
PWM period-shift between channels 1 and 2
Value is N * 90o
Default is 180o
1:0 Reserved (00: default)
MVOL
Bit 7
Master volume control register
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SET_VOL_MASTER[7:0]
Address:
0x02
Type:
R/W
Buffer:
No
Reset:
0x00
Description:
7:0 SET_VOL_MASTER[7:0]: master volume control:
From 0 dB to -127.5 dB in 0.5 dB steps
37/58
Registers
STA529
LVOL
Bit 7
Left channel volume control register
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SET_VOL_LEFT[7:0]
Address:
0x03
Type:
R/W
Buffer:
No
Reset:
0x48
Description:
7:0 SET_VOL_LEFT[7:0]: left channel volume control:
0100 1000: default
Left channel volume control (from +36 dB to -91.5 dB in 0.5 dB steps)
Default value corresponds to 0 dB
RVOL
Bit 7
Right channel volume control register
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
SET_VOL_RIGHT[7:0]
Address:
0x04
Type:
R/W
Buffer:
No
Reset:
0x48
Description:
7:0 SET_VOL_RIGHT[7:0]: right channel volume control:
0100 1000: default
Right channel volume control (from +36 dB to -91.5 dB in 0.5 dB steps)
Default value corresponds to 0 dB
38/58
Bit 1
Bit 0
STA529
Registers
TTF0
Bit 7
Tri-state time-after-fault register 0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 1
Bit 0
TIM_TS_FAULT[15:8]
Address:
0x05
Type:
R/W
Buffer:
No
Reset:
0x00
Description:
7:0 MSBs of TIM_TS_FAULT[15:8]:
See TTF1 on page 39.
TTF1
Bit 7
Tri-state time-after-fault register 1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
TIM_TS_FAULT(7:0)
Address:
0x06
Type:
R/W
Buffer:
No
Reset:
0x02
Description:
7:0 LSBs of TIM_TS_FAULT[7:0]: time in which power is held in tri-state mode after a fault
signal:
Time is TIM_TS_FAULT * 83.33 µs.
Default value corresponds to 166.66 µs tri-state time after fault
39/58
Registers
STA529
TTP0
Bit 7
Tri-state time-after-power-up register 0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TIM_TS_POWUP[15:8]
Address:
0x07
Type:
R/W
Buffer:
No
Reset:
0x00
Description:
7:0 MSBs of TIM_TS_POWUP[15:8]:
See register TTP1.
TTP1
Bit 7
Tri-state time-after-power-up register 1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TIM_TS_POWUP[7:0]
Address:
0x08
Type:
R/W
Buffer:
No
Reset:
0x02
Description:
7:0 LSBs of TIM_TS_POWUP[7:0]: time in which power is held in tri-state mode after a powerup signal:
Time is TIM_TS_POWUP * 83.33 µs
Default value corresponds to 166.66 µs tri-state time after power-up
40/58
STA529
Registers
S2PCFG0
Bit 7
BICLK_STRB
Serial-to-parallel audio interface configuration
register 0
Bit 6
LRCLK_LEFT
Address:
0x0A
Type:
R/W
Buffer:
No
Reset:
0xD2
Bit 5
SHARE_BILR
Bit 4
MSB_FIRST
Bit 3
Bit 2
Bit 1
DATA_FORMAT[2:0]
Bit 0
MASTER_
MODE
Description:
7 BICLK_STRB:
0: bit clock strobe edge is falling edge, bit clock active edge is rising edge
1: bit clock strobe edge is rising edge, bit clock active edge is falling edge (default)
6 LRCLK_LEFT:
0: left/right clock is low for left channel, high for right channel
1: left/right clock is high for left channel, low for right channel (default)
5 SHARE_BILR:
0: default
1: left/right clock and bit clock are shared between serial-parallel interface and parallel-toserial interface, BICLKI and LRCLKI are used
4 MSB_FIRST:
0: LSB first
1: MSB first (default)
3:1 DATA_FORMAT[2:0]: serial interface protocol format:
000: left Justified
001: I2S (default)
010: right justified
100: PCM no delay
101: PCM delay
111: DSP
001: default
0 MASTER_MODE:
0: default
1: serial interface is in master mode
41/58
Registers
STA529
S2PCFG1
Bit 7
Serial-to-parallel audio interface configuration
register 1
Bit 6
PDATA_LENGTH[1:0]
Address:
0x0B
Type:
R/W
Buffer:
No
Reset:
0x91
Bit 5
Bit 4
BICLK_OS[1:0]
Bit 3
Bit 2
MAP_L[1:0]
Description:
7:6 PDATA_LENGTH[1:0]: serial-to-parallel interface data length:
10: default
Length is (N+1) * 8 bit
Default is 24 bit
5:4 BICLK_OS[1:0]: bit clock oversampling:
01: default
Value is (N+1) * 32 fs (where fs = sampling frequency)
Default is 64 fs
3:2 MAP_L[1:0]: left data-mapping slot:
00: default
Value is nth slot
Default is slot0
1:0 MAP_R[1:0]: right data-mapping slot:
01: default
Value is nth slot
Default is slot
42/58
Bit 1
Bit 0
MAP_R[1:0]
STA529
Registers
P2SCFG0
Bit 7
BICLK_ STRB
Parallel-to-serial audio interface configuration
register 0
Bit 6
LRCLK_LEFT
Address:
0x0C
Type:
R/W
Buffer:
No
Reset:
0xD3
Bit 5
SDATAO_ACT
Bit 4
MSB_FIRST
Bit 3
Bit 2
DATA_FORMAT[2:0]
Bit 1
Bit 0
MASTER_
MODE
Description:
7 BICLK_STRB: defines the bit clock edges:
0: strobe is falling edge, active edge is rising
1: strobe is rising edge, active edge is falling (default)
6 LRCLK_LEFT: defines the channel for the LR clock:
0: clock is low for left channel, high for right channel
1: clock is high for left channel, low for right channel (default)
5 SDATAO_ ACT: sets the behavior of pin SDATAO:
0: output is tri-stated when no data is sent (default)
1: output is never in tri-state (it is 0 when no data is sent)
4 MSB_FIRST: data alignment in the protocol for SDATAI and SDATAO:
0: LSB is the first bit
1: MSB is the first bit (default)
3:1 DATA_FORMAT[2:0]: serial interface protocol format:
000: left justified
001: I2S (default)
010: right justified
100: PCM no delay
101: PCM delay
111: DSP
0 MASTER_ MODE: selects serial interface master/slave mode:
0: slave
1: master (default)
43/58
Registers
STA529
P2SCFG1
Bit 7
Parallel-to-serial audio interface configuration
register 1
Bit 6
PDATA_LENGTH[1:0]
Address:
0x0D
Type:
R/W
Buffer:
No
Reset:
0x91
Bit 5
Bit 4
Bit 3
BICLK_OS[1:0]
Bit 2
MAP_L[1:0]
Description:
7:6 PDATA_LENGTH[1:0]: serial-to-parallel interface data length:
10: default
Length is (PDATA_LENGTH+1) * 8 bit
Default is 24 bits
5:4 BICLK_OS[1:0]: bit clock oversampling:
01: default
Value is (BICLK_OS+1) * 32 fs
Default is 64 fs
3:2 MAP_L[1:0]: left data-mapping slot:
00: default
Value is nth slot
Default is slot0
1:0 MAP_R[1:0]: right channel data-mapping slot:
01: default
Value is nth slot
Default is slot1
44/58
Bit 1
Bit 0
MAP_R[1:0]
STA529
Registers
PLLCFG0
PLL configuration register 0
Bit 7
Bit 6
PLL_DIRECT_
PROG
FRAC_CTRL
Address:
0x14
Type:
R/W
Buffer:
No
Reset:
0x00
Bit 5
Bit 4
Bit 3
Bit 2
DITHER_DISABLE[1:0]
Bit 1
Bit 0
Bit 1
Bit 0
IDF[3:0]
Description:
7 PLL_DIRECT_PROG: PLL programming:
0: default
1: PLL is programmed according to the PLLCFG register settings
6 FRAC_CTRL:
0: default
1: PLL fractional-frequency synthesis is enabled
5:4 DITHER_DISABLE[1:0]:
00: default
MSB = 1: disables rectangular PDF dither input to SDM
LSB = 1: disables triangular PDF dither input to SDM
3:0 IDF[3:0]: PLL input division factor:
0000: IDF = 1 (default)
0001: IDF = 1
0010: IDF = 2
…
1111: IDF = 15
PLLCFG1
Bit 7
PLL configuration register 1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
FRAC_INPUT[15:8]
Address:
0x15
Type:
R/W
Buffer:
No
Reset:
0x00
Description:
7:0 FRAC_INPUT[15:8]: 16 bits are used to set the fractional part of PLL multiplication factor:
0000 0000: default
45/58
Registers
STA529
PLLCFG2
Bit 7
PLL configuration register 2
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FRAC_INPUT[7:0]
Address:
0x16
Type:
R/W
Buffer:
No
Reset:
0x00
Description:
7:0 FRAC_INPUT[7:0]: 16 bits are used to set the fractional part of PLL multiplication factor:
0000 0000: default
PLLCFG3
PLL configuration register 3
Bit 7
Bit 6
STRB
STRB_BYPASS
Address:
0x17
Type:
R/W
Buffer:
No
Reset:
0x00
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
NDIV[5:0]
Description:
7 STRB: asynchronous strobe input to the fractional controller:
0: default
6 STRB_BYPASS: standby bypass:
0: STRB signal is not bypassed (default)
1: STRB signal is bypassed
5:0 NDIV[5:0]: PLL multiplication factor (integral part) named as loop division factor:
0000 XX: LDF = NA
0001 00: LDF = NA
0001 01: LDF = 5
...
1101 11: LDF = 55
111X XX: LDF = NA
0000 00: default
46/58
Bit 0
STA529
Registers
PLLPFE
PLL/POP-free configuration register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PLL_BYP_UNL
BICLK2PLL
PLL_PWDN
PFE1A
PFE1B
PFE2A
PFE2B
RESET_FAULT
Address:
0x18
Type:
R/W
Buffer:
No
Reset:
0x00
Description:
7 PLL_BYP_UNL: PLL bypass:
0: PLL is not bypassed (default)
1: PLL is bypassed when not locked
6 BICLK2PLL:
0: default
1: BICLKI is input to PLL
5 PLL_PWDN:
0: default
1: PLL is put in power-down mode
4 PFE1A:
0: default
1: POP-free resistances are connected to output 1A
3 PFE1B:
0: default
1: POP-free resistances are connected to output 1B
2 PFE2A:
0: default
1: POP-free resistances are connected to output 2A
1 PFE2B:
0: default
1: POP-free resistances are connected to output 2B
0 RESET_FAULT:
0: default
1: fault signal in the i2c register POWST is reset
47/58
Registers
STA529
PLLST
PLL status register (RO)
Bit 7
Bit 6
Bit 5
PLL_UNLOCK
PLL_PWD_
STATE
PLL_BYP_
STATE
Address:
0x19
Type:
RO
Buffer:
No
Reset:
Undefined
Bit 4
Bit 3
Description:
7 PLL_UNLOCK: PLL unlock state:
0: PLL is not in unlock state
1: PLL is in unlock state
6 PLL_PWD_ STATE: PLL power-down state:
0: PLL is not in power-down state
1: PLL is in power-down state
5 PLL_BYP_STATE: PLL bypass state:
0: PLL is not in bypass state
1: PLL is in bypass state
4:0 Reserved
48/58
Bit 2
Bit 1
Bit 0
STA529
Registers
ADCCFG
Bit 7
ADC configuration register
Bit 6
Bit 5
PGA[2:0]
Address:
0x1E
Type:
RO
Buffer:
No
Reset:
Undefined
Bit 4
Bit 3
Bit 2
Bit 1
INSEL
STBY
BYPASS_CALIB
CLKENBL
Bit 0
Description:
7:5 PGA[2:0]: gain selection bits for the ADC programmable gain amplifier:
000: default
Values are from 0 to 42 dB in 6 dB steps
4 INSEL:
0: line input selected (default)
1: microphone input selected (it must be applied to INL line)
3 STBY: ADC standby mode:
0: ADC in power-up mode (default)
1: ADC in standby mode
2 BYPASS_CALIB:
0: ADC DC-removal block not bypassed (default)
1: ADC DC-removal block bypassed
1 CLKENBL: Clock enable:
0: system clock not enabled
1: system clock available at ADC input (default)
0 Reserved
CKOCFG
Bit 7
CLKOUT_DIS
Clock-out configuration register
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CLKOUT_SEL[1:]]
Address:
0x1F
Type:
R/W
Buffer:
No
Reset:
Undefined
Description:
7 CLKOUT_DIS: CLKOUT PAD disabled
0: default
1: enabled
6:5 CLKOUT_SEL[1:0]:
00: default
The CLKOUT output frequency is the PLL output frequency divided by 2CLKOUT_SEL.
4:0 Reserved
49/58
Registers
STA529
MISC
Bit 7
Miscellaneous configuration register
Bit 6
OSC_DIS
Bit 5
P2P_FS_RANGE[2:0]
Address:
0x20
Type:
R/W
Buffer:
No
Reset:
0x21
Bit 4
Bit 3
Bit 2
ADC_FS_RANGE[1:0]
Description:
7 OSC_DIS: enable/disable crystal oscillator:
0: default
1: disabled
6:4 P2P_FS_RANGE[2:0]: FFX audio frequency range:
000: very low (fs = 8 to 12 kHz) (default)
001: low (fs = 16 to 24 kHz) (default)
010: normal (fs = 32 to 48 kHz)
011: high (fs = 64 to 96 kHz)
1X: very high (fs = 128 to 192 kHz)
3:2 ADC_FS_RANGE[2:0]: ADC audio frequency range:
00: normal (fs = 32 to 48 kHz)
00: low (fs = 16 to 24 kHz)
1X: very low (fs = 8 to 12 kHz)
00: default
1 P2P_IN_ADC: FFX input:
0: FFX input is from serial-to-parallel audio interface (default)
1: FFX input is from ADC
0 CORE_CLKENBL: availability of system clock:
0: FFX system clock disabled
1: FFX system clock enabled (default)
50/58
Bit 1
Bit 0
P2P_IN_ADC
CORE_
CLKENBL
STA529
Registers
FFXST
Bit 7
FFX status register
Bit 6
Address:
0x23
Type:
RO
Buffer:
No
Reset:
Undefined
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
INVALID_INP_
FBK
MUTE_INT_FBK
Bit 0
Description:
7:3 Reserved
2 INVALID_INP_FBK: invalid input status:
1: invalid input sent to FFX
1 MUTE_INT_FBK: FFX mute status
1: FFX is in mute state
0 Reserved
PWMINT1
Bit 7
PWM driver configuration register 1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWM_INT1[7:0]
Address:
0x2D
Type:
R/W
Buffer:
No
Reset:
0x00
Description:
7:0 PWM_INT1[7:0]: see Section 7: Driver configuration on page 25:
0000 0000: default
PWMINT2
Bit 7
PWM driver configuration register 2
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWM_INT1[7:0]
Address:
0x2E
Type:
R/W
Buffer:
No
Reset:
0x00
Description:
7:0 PWM_INT1[7:0]: see Section 7: Driver configuration on page 25:
0000 0000: default
51/58
Registers
STA529
POWST
Power bridge status register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
POW_
POWERDOWN
POW_
TRISTATE
POW_FAULT1A
POW_FAULT1B
POW_FAULT2A
POW_FAULT2B
Address:
0x32
Type:
RO
Buffer:
No
Reset:
Undefined
Description:
7 POW_POWERDOWN: power-down bridge:
0: not in power-down state
1: power-down state
6 POW_TRISTATE:
1: power bridge is in tri-state
5 POW_FAULT1A:
1: power bridge 1A is in fault state
4 POW_FAULT1B:
1: power bridge 1B is in fault state
3 POW_FAULT2A:
1: power bridge 2A is in fault state
2 POW_FAULT2B:
1: power bridge 2B is in fault state
1:0 Reserved
52/58
Bit 1
Bit 0
STA529
11
Package information
Package information
This section includes packaging information for the following packages:
●
TFBGA48
●
VFQFPN52
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These package have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
11.1
Package TFBGA48
Figure 17. Mechanical data (TFBGA48)
53/58
Package information
STA529
Table 19 gives the package dimensions.
Table 19.
Package dimensions (TFBGA48)
Databook mm
Reference
Min
Typical
A
A1
1.20
0.15
A2
0.785
A3
0.20
A4
0.60
b
0.25
0.30
0.35
D
4.85
5.00
5.15
D1
E
54/58
Max
3.50
4.85
5.00
E1
3.50
e
0.50
F
0.75
5.15
ddd
0.08
eee
0.15
fff
0.05
STA529
11.2
Package information
Package VFQFPN52
Figure 18. Mechanical data (VFQFPN52)
55/58
Package information
STA529
Table 20 gives the package dimensions.
Table 20.
Package dimensions (VFQFPN52)
Databook mm
Reference
Min
Typical
Max
A
0.800
0.900
1.000
A1
0.020
0.050
A2
0.650
1.000
A3
0.250
b
0.180
0.230
0.300
D
7.875
8.000
8.125
D2
2.750
5.700
6.250
E
7.875
8.000
8.125
E2
2.750
5.700
6.250
e
0.450
0.500
0.550
L
0.350
0.550
0.750
ddd
56/58
0.080
STA529
12
Revision history
Revision history
Table 21.
Date
10-Jan-2007
Document revision history
Revision
1
Changes
Initial release
57/58
STA529
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right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
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