Preliminary PT4312 800 MHz ~ 920 MHz Wireless Headphone Receiver IC DESCRIPTION FEATURES The PT4312 is a single-chip UHF stereo FM-audio receiver for portable wireless applications with fully-integrated intermediate frequency (IF) selectivity and demodulation and which requires few external components while supporting a receive frequency range from 800 to 900 MHz. Automatic gain control Built-in FM de-emphasis (75 s or 50 s) Built-in stereo audio DAC Auto-mute function to detect the FM stereo signal Fractional-N synthesizer for flexible selection 2 QFN-48, 6 x 6 mm APPLICATIONS The PT4312 employs a low-noise RF-to-low-IF image-reject down-converter. After down-conversion, the IF signal is first filtered and amplified by the on-chip programmable gain amplifier (PGA) and subsequently digitized by a low power, high resolution ADC before the digital signal processing (DSP) block performs channel selection, FM demodulation, and stereo audio processing. The final left- and right-channel audio outputs are produced by an on-chip stereo DAC. Portable radios Consumer electronics Wireless headphones Stereo FM audio systems 2 The PT4312 is housed in a 48-pin 6 × 6 mm QFN package. BLOCK DIAGRAM AGC Controller A PG LNA LNA Buffer DAC L DAC R ADC Base Band IQ Mixer A PG ADC I2S I2S I2S Quadrature /4 PT4312 Feedback Divider (FracN) VCO Chip Control Charge Pump Phase/Freq. Detector Reference Buffer 3 wires control Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, No. 233-1, Baociao Rd., Sindian Dist., New Taipei City 23145, Taiwan PT4312 APPLICATION CIRCUITS PRE1.0 2 March 2014 PT4312 HEADPHONE AMPLIFER AND HEADPHONE CONNECTOR PRE1.0 3 March 2014 PT4312 ORDER INFORMATION Valid Part Number PT4312-X Package Type 48 Pins, QFN Top Code PT4312-X PIN CONFIGURATION XI 37 GND 38 GND 39 GND 40 GND 41 PLLOUT 42 VTUNE 43 NC 44 NC 45 NC 46 1 36 XO NC 2 35 NC AVDD 3 34 NC GND 4 33 GND GND 5 32 LOUT LNAIN 6 PT4312 GND 7 Wireless Audio Receiver F2 8 29 ST F1 9 28 EN 31 ROUT 30 VD 4 NC 24 NC 23 SPI_MOSI 22 SPI_CLK 21 SPI_SS 20 SPI_MISO 19 25 NC VOLP 18 NC 12 VOLM 17 26 NC GND 16 NC 11 RESET 15 27 TVDD NC 14 F0 10 NC 13 PRE1.0 NC 47 NC 48 NC March 2014 PT4312 PIN DESCRIPTION Pin Name NC NC AVDD GND GND LNAIN GND F2 F1 F0 NC NC NC NC RESETN GND VOLM VOLP SPI_MISO SPI_SS SPI_CLK SPI_MOSI NC NC NC NC TVDD EN ST VD ROUT LOUT GND NC NC XO XI GND GND GND GND PLLOUT VTUNE NC NC NC NC NC I/O — — P G G I G I I I — — — — I G I I O I I I — — — — P I O O O O G — — O I G G G G O I — — — — — Description No connection No connection Supply voltage (analog circuitry) Ground (analog circuitry) Ground (analog circuitry) LNA input Ground (analog circuitry) Pre-programmed frequency select pins No connection No connection No connection No connection Digital baseband reset control input Ground (analog circuitry) Audio output volume control input (decrease volume) Audio output volume control input (increase volume) SPI slave output SPI master/slave select input SPI clock input SPI master input No connection No connection No connection No connection Supply voltage (digital circuitry) Power-down control input Stereo indicator 1.8 V digital regulator output DAC output (right channel) DAC output (left channel) Ground (analog circuitry) No connection No connection Crystal oscillator output * Crystal oscillator input Ground (analog circuitry) Ground (analog circuitry) Ground (analog circuitry) Ground (analog circuitry) Charge pump output VCO tuning voltage input No connection No connection No connection No connection No connection Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Note: *=Crystal specification: Nominal frequency=16.384MHz; Hold Type= HC-49U/S; Oscillator Mode= Fundamental Frequency Tolerance= ±30ppm; Frequency Stability= ±50ppm; Load Capacitance= 20pf; Shunt Capacitance=7pf maximum PRE1.0 5 March 2014 PT4312 FUNCTION DESCRIPTION PRE-PROGRAMMED DEFAULT FREQUENCY SELECT Frequency Select Pins (F2, F1, F0) Control Table F2 F1 F0 Default Value 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 Unused 863.530 MHz 864.030 MHz 864.530 MHz Programmable CONFIGURATION REGISTERS 4-WIRE SERIAL PERIPHERAL INTERFACE A Serial Peripheral Interface (SPI) system consists of one master device and one or more slave devices. The master is defined as a microcontroller providing the SPI clock and the slave is any integrated circuit receiving the SPI clock from the master. The SPI has a 4-wire synchronous serial interface. Data communication is enabled with a low active Slave Select (SS). Data is transmitted with a 3-wire interface consisting of wires for serial data input (MOSI), serial data output (MISO) and serial clock (SCK). SS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK DATA IN MOSI 7 6 5 HIGH IMPEDANCE 3 2 1 0 3 2 1 0 DATA OUT MISO PRE1.0 4 7 6 6 5 4 March 2014 PT4312 REGISTER ADDRESS MAPPING Address R/W 0x05h R/W 0x18h 0x19h 0x1Ah 0x1Bh 0x1Ch 0x1Dh 0x20h Data[7] Data[6] Data[5] Data[4] Data[3] Data[2] Data[1] Data[0] * * * DTUNE[4] DTUNE[3] DTUNE[2] DTUNE[1] DTUNE[0] 0 0 0 1 0 0 0 0 * * * CPMODE[1] CPMODE[0] CPCUR[2] CPCUR[1] CPCUR[0] 0 0 0 0 0 1 0 0 NK[23] NK[22] NK[21] NK[20] NK[19] NK[18] NK[17] NK[16] 1 1 0 1 0 0 1 0 NK[15] NK[14] NK[13] NK[12] NK[11] NK[10] NK[9] NK[8] 1 1 0 0 1 0 1 0 NK[7] NK[6] NK[5] NK[4] NK[3] NK[2] NK[1] NK[0] 1 0 1 0 0 0 0 0 * * * SPUR FEC[11] FEC[10] FEC[9] FEC[8] 0 0 0 0 0 0 0 0 FEC[7] FEC[6] FEC[5] FEC[4] FEC[3] FEC[2] FEC[1] FEC[0] 0 0 0 0 0 0 0 0 * * * * * AUTO_MUTE AU_MUTE AU_STEREO_EN 0 0 0 0 0 1 1 1 * * * * R/W R/W R/W R/W R/W R/W R/W BLEND_EN 0x21h 0x22h 0 0 0 0 0 0 0 * * * PGACEN* * * * * 0 0 0 1 0 0 0 0 MAX_GAIN_VAL MIN_GAIN_VAL MT ST LNA_CTRL_GAIN <RO> <RO> <RO> <RO> <RO> OVR_PWR_LVL LOW_PWR_LVL <RO> <RO> <RO> <RO> <RO> * * * * 0 0 0 0 0x45h <RO> <RO> <RO> <RO> <RO> <RO> * EXT_I2S_EN INT_I2S_EN I2S_IF_EN 0 0 1 1 * * 0 0 1 * * FM_DEM_GAIN[1;0] 0 0 0 0 1 1 1 0 0 0 0 0 0 * * 0 0 RSSI_POWER[5:0] R R/W R/W LOW_AU_PWR_ BLEND_EN 0 0x29h PGA_CTRL_GAIN[2:0] R 0x26h 0x28h 0 R/W 0x25h 0x27h BLEND_ADJ[2:0] R/W R/W BLEND_ADJ2[2:0] 0 LNA_HG_ BLEND_EN 1 1 BLEND_ADJ3[2:0] 0 0 1 1 VOLCTRL_EN * * * 0 0 0 0 I2S_SRMOD[1:0] 1 VOL_CTRL[3:0] R/W 1 RSSI_UPDATE_RATE[7:0] 0x48h R/W 0 0 0 0 1 RSSI_UPDATE_RATE[15:8] 0x49h 0x4Eh R/W 0 0 0 0 * PASS_EXPANDE R * * 0 0 0 0 R/W 0x60h PRE1.0 R 0 DEEMPH_50US PASS_EDDMPH 0 0 RSSI_OUT[7:0] 7 March 2014 PT4312 Address R/W Data[7] Data[6] Data[5] Data[4] Data[3] Data[2] Data[1] Data[0] <RO> <RO> <RO> <RO> <RO> <RO> <RO> <RO> * * * 0 0 0 0 <RO> <RO> <RO> <RO> <RO> <RO> <RO> <RO> <RO> <RO> <RO> <RO> <RO> <RO> <RO> <RO> <RO> <RO> <RO> * 0x61h BLEND_STATUS[2:0] R 0 <RO> <RO> <RO> FM_PWR[7:0] 0x62h R <RO> <RO> <RO> <RO> FM_PWR[15:8] 0x63h R <RO> <RO> <RO> <RO> <RO> AVG_DC_VALUE[7:0] 0x64h R <RO> <RO> <RO> <RO> <RO> AVG_DC_VALUE[15:8] 0x65h R <RO> <RO> <RO> <RO> <RO> AU_PWR[7:0] 0x66h R <RO> <RO> <RO> <RO> <RO> AU_PWR[15:8] 0x67h R <RO> PRE1.0 <RO> <RO> <RO> 8 <RO> March 2014 PT4312 LO SUB-SYSTEM CONTROL BIT DEFINITIONS Default values are set for the 863.530 MHz frequency band. Bit Name Default Value Description VCO CONTROL VCO output frequency 10000b DTUNE<1:0> 00000b = lowest frequency sub-band selection thru 11111b = highest frequency sub-band selection PLL CONTROL Chare pump mode select 00b = normal operation CPMODE<1:0> 00b 01b = pump-down only 11b = pump-up only 10b = high-Z state Chare pump current gain select 000b = 20 A 001b = 40 A 010b = 60 A CPCUR<2:0> 000b 011b = 80 A 100b = 100 A 101b = 120 A 110b = 140 A 111b = 160 A 8 MSBs of frequency control word (integer modulus) 1101 0010b NK<23:16> minimum divide ratio = 64 (210dec) maximum divide ratio = 255 1100 1010 1010 0000b NK<15:0> 16 LSBs of frequency control word (fractional modulus) (51872dec) SDM dither mode select SPUR 0b 0 = dither (low spur mode) 1 = no dither Frequency error correction 2’s complement control word (12-bit) FEC<11:0> PRE1.0 0000 0000 0000b Frequency error correction = 9 f ref FEC 11: 0 16 2 dec Hz March 2014 PT4312 FM AUDIO AND BASEBAND CONTROL BIT DEFINITIONS Bit Name Default Value AUTO_MUTE 1b AU_MUTE 0b BLEND_EN 0b BLEND_ADJ<2:0> 000b PGACEN 1b MAX_GAIN_VAL MIN_GAIN_VAL MT ST <RO> <RO> <RO> <RO> LNA_CTRL_GAIN <RO> PGA_CTRL_GAIN<2:0> OVR_PWR_LVL LOW_PWR_LVL RSSI_POWER<5:0> <RO> <RO> <RO> <RO> EXT_I2S_EN 0b INT_I2S_EN 1b I2S_IF_EN 1b LOW_AU_PWR_BLEND_EN BLEND_ADJ2<2:0> 0b 011b I2S_SRMOD<1:0> 11b LNA_HG_BLEND BLEND_ADJ3<2:0> 011b PRE1.0 0b Description 0b = Auto mute off 1b = Auto mute on 0b = Audio on 1b = Audio mute 0b = Manual Blending 1b = Auto Blending When BLEND_EN = 1, read only otherwise blending factor setting. 0b = PGA control disable 1b = PGA control enable Maximum PGA gain value Minimum PGA gain value Mute indicator Stereo indicator Monitor LNA gain mode 0b = Low gain mode 1b = High gain mode Monitor PGA gain RSSI power level over high threshold RSSI power level under low threshold Monitor RSSI power level 0b = Disable external I2S signal output 1b = Enable external I2S signal output 0b = Disable internal I2S signal output 1b = Enable internal I2S signal output 0b = Disable all I2S signal output 1b = Enable all I2S signal output Enable low power level of audio signal blending Blend factor of audio signal in low power level Audio output data rate 00b = 32 Ksps 01b = 64 Ksps 10b = 128 Ksps 11b = 256 Ksps Enable LNA high gain mode blend Blend factor of LNA in high gain mode 10 March 2014 PT4312 FM AUDIO AND BASEBAND CONTROL BIT DEFINITIONS (CONT’D) Bit Name Default Value FM_DEM_GAIN<1:0> 00b VOLCTRL_EN VOL_CTRL<3:0> 0b 111b 0000 0000 0000 0100b 0b 0b 0b <RO> <RO> <RO> <RO> <RO> RSSI_UPDATE_RATE<15:0> PASS_EXPANDER DEEMPH_50US PASS_DEEMPH RSSI_OUT<7:0> BLEND_STATUS<2:0> FM_PWR<15:0> AVG_DC_VALUE<2:0> AU_PWR PRE1.0 Description FM demodulation output gain 00b = x1 01b = x0.5 10b = x0.25 11b = x0.125 Enable keypad control volume Volume control level RSSI update rate Bypass expander function De-emphasis time constant select (50 s) Bypass de-emphasis function RSSI value Blend control status FM demodulation signal power Average dc value Audio power value 11 March 2014 PT4312 PLL FREQUENCY PROGRAMMING EXAMPLE For a specific RF input frequency (fRF) and intermediate frequency (fIF), the PT4312 Receiver IC’s LO frequency (fLO) may be given by the expression fLO = fRF - fIF. Given an fRF of 820.128 MHz and for the system-specified fIF of 128 KHz, fLO = 820.128 – 0.128 = 820.000 [MHz]. Now, to generate the desired fLO, the required VCO frequency (fVCO) may be calculated using the expression fVCO = 4 × fLO. For fLO = 820 MHz, the required synthesized fVCO = 4 × 820 MHz = 3280 MHz. Given a reference oscillator frequency (fREF) = 16.384 MHz, the on-chip PLL’s feedback divider modulus (N.K) required to synthesize the desired fVCO = 3280MHz is given by the expression N .K fVCO 3280 200.1953125 . The integer f REF 16.384 portion of the divider modulus is represented as N. Here, N = 200. The fractional portion of the divider modulus is represented by K. Here, K = 0.1953125. From the register table definition, the frequency control word is NK<23:0>. The 8 MSBs (NK<23:16>) of the frequency control word are used to represent the integer portion of the divider modulus. Hence, for N = 200, NK<23:16> = 1100 1000b. The 16 LSBs (NK<15:0>) of the frequency control word are used to represent the fractional portion of the divider 16 modulus and are nominally related to K by the expression NK<15:0> = K × 2 . For K = 0.1953125, NK<15:0> = 0.1953128 × 65536 = 12800 = 0011 0010 0000 0000b. PRE1.0 12 March 2014 PT4312 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Range Analog I/O Voltage Digital I/O Voltage Operating Temperature Range Storage Temperature Range Symbol AVDD — — TA TSTG Min. –0.3 –0.3 –0.3 –40 –40 Max. 4 4 4 +85 +150 Unit V V V °C °C PACKAGE THERMAL CHARACTERISTIC Parameter From Chip Conjunction Dissipation to External Environment From Chip Conjunction Dissipation to Package Surface PRE1.0 Symbol Condition Rja Min. Typ. Max. — 37.15 — — 1 1.8 TA = 27 °C Rjc 13 Unit °C/W March 2014 PT4312 ELECTRICAL CHARACTERISTICS Nominal conditions: AVDD = TVDD = 2.2 to 3.6 V, AVSS = TVSS = 0 V, TA = +27°C unless otherwise noted. Parameter Symbol Conditions Min. Typ. Max. Unit General Characteristics Supply Voltage V Operating Current I Operating Frequency Supply voltage applied to AVDD and TVDD pin only Internal VCO case, CE = EN fRF 2.2 3.0 3.6 V 34 800 mA 900 MHz Internal VCO case Stereo SNR 56 Stereo THD 0.5 Sensitivity –98 PRE1.0 14 dB 1 % dBm March 2014 PT4312 PACKAGE INFORMATION 48 Pins, QFN (4.5 × 4.5 mm Body Size, 0.40 mm Pitch Size and 0.75 mm Thick Body) Symbol Min. Nom. Max. A 0.70 0.75 0.80 A1 A3 b D D2 E - 0.02 0.20 REF. 0.20 6.00 BSC 4.40 6.00 BSC 0.05 4.40 0.40 BSC 0.40 4.50 E2 e L 0.15 4.30 4.30 0.35 0.25 4.50 0.45 Notes: 1. Refer to JEDEC MO-220. 2. Unit: mm PRE1.0 15 March 2014 PT4312 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian Dist., New Taipei City 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw PRE1.0 16 March 2014