STMICROELECTRONICS STMPE811

STMPE811
8-bit port expander with advanced touchscreen controller
Preliminary Data
Features
■
8 GPIOs
■
1.8 - 3.3 V operating voltage
■
Integrated 4-wire touchscreen controller
■
Interrupt output pin
■
Wakeup feature on each I/O
■
SPI and I2C interface
■
Up to 2 devices sharing the same bus in I2C
mode (1 address line)
■
8-input 12-bit ADC
■
128-depth buffer touchscreen controller
■
Touchscreen movement detection algorithm
■
25 kV air-gap ESD protection (system level)
■
4 kV HBM ESD protection (device level)
Applications
■
Portable media players
■
Game consoles
■
Mobile and smart phones
QFN16
Description
The STMPE811 is a GPIO (general purpose
input/output) port expander able to interface a
main digital ASIC via the two-line bidirectional bus
(I2C). A separate GPIO expander is often used in
mobile multimedia platforms to solve the
problems of the limited amount of GPIOs typically
available on the digital engine.
The STMPE811 offers great flexibility, as each I/O
can be configured as input, output or specific
functions. The device has been designed with
very low quiescent current and includes a wakeup
feature for each I/O, to optimize the power
consumption of the device.
A 4-wire touchscreen controller is built into the
STMPE811. The touchscreen controller is
enhanced with a movement tracking algorithm to
avoid excessive data, 128 x 32 bit buffer and a
programmable active window feature.
Table 1.
June 2008
Device summary
Order code
Package
Packaging
STMPE811QTR
QFN16
Tape and reel
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/54
www.st.com
54
Contents
STMPE811
Contents
1
STMPE811 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin configuration and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
3
I2C and SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
4
5
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Interface selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1
I2C features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3
Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1
5.2
SPI protocol definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.1
Register read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.2
Register write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.3
Termination of data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SPI timing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.1
SPI timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6
STMPE811 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7
System and identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8
Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9
Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10
Touchscreen controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.1
11
2/54
Driver and switch control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Touchscreen controller programming sequence . . . . . . . . . . . . . . . . . 41
STMPE811
Contents
12
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13
GPIO controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.0.1
14
Power-up reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
14.1
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
15
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
16
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3/54
STMPE811 functional overview
1
STMPE811
STMPE811 functional overview
The STMP811 consists of the following blocks:
●
I2C and SPI interface
●
Analog-to-digital converver (ADC)
●
Touchscreen controller (TSC)
●
Driver and switch control unit
●
Temperature sensor
●
GPIO controller
Figure 1.
STMPE811 functional block diagram
GPIO 0-7
/ADC IN 0-7
/MODE
/REF-, REF+
GPIO
controller
Switches
and drivers
RC oscillator
ADC , TSC
INT
2
Data in
A0/Data out
I C / SPI
interface
SCLK/CLK
SDAT/CS
Thermal
sense
GND VCC
4/54
VREF
TSC: Touchscreen controller
STMPE811
2
Pin configuration and functions
Pin configuration and functions
Figure 2.
STMPE811 pin configuration (top through view)
12
11
10
9
13
8
14
7
STMPE811
15
6
16
5
1
Table 2.
2
3
4
Pin assignments
Pin
Name
Function
1
Y-
2
INT
3
A0/Data Out
4
SCLK
I2C/SPI clock
5
SDAT
I2C data/SPI CS
6
VCC
7
Data in
SPI Data In
8
IN0
IN0/GPIO-0
9
IN1
IN1/GPIO-1/MODE
In RESET state, MODE selects the type of serial interface
"0" - I2C
"1" - SPI
10
GND
11
IN2
IN2/GPIO-2
12
IN3
IN3/GPIO-3
13
X+
X+/GPIO-4
14
Vio
Supply for touchscreen driver and GPIO
15
Y+
Y+/GPIO-5
16
X-
X-/GPIO-6
Y-/GPIO-7
Interrupt output
I2C address in Reset, Data out in SPI mode
1.8
− 3.3 V supply voltage
Ground
5/54
Pin configuration and functions
2.1
STMPE811
Pin functions
The STMPE811 is designed to provide maximum features and flexibility in a very small pincount package. Most of the pins are multi-functional. The following table shows how to
select the pin’s function.
Table 3.
Pin configuration
GPIO alternate function register
Pin
0
1
ADC control 1 bit 1 (RefSel)
0
1
IN0
GPIO-0
ADC
IN1
GPIO-1
ADC
IN2
GPIO-2
ADC
External reference +
IN3
GPIO-3
ADC
External reference -
TSC control 1 bit 0 (EN)
6/54
0
1
X+
GPIO-4
ADC
TSC X+
Y+
GPIO-5
ADC
TSC Y+
X-
GPIO-6
ADC
TSC X-
Y-
GPIO-7
ADC
TSC Y-
STMPE811
I2C and SPI interface
3
I2C and SPI interface
3.1
Interface selection
The STMPE811 interfaces with the host CPU via a I2C or SPI interface. The pin IN_1 allows
the selection of interface protocol at reset state.
Figure 3.
STMPE811 interface
DIN
SPI I/F
module
DOUT
CLK
CS
MUX
unit
I2C I/F
module
Table 4.
SDAT
SCLK
A0
Interface selection pins
Pin
I2C function
SPI function
Reset state
3
Address 0
Data out
CPHA for SPI
4
CLOCK
CLOCK
5
SDATA
CS
7
−
9
MODE
CPOL_N for SPI
Data in
I2C
set to ‘0’
Set to ‘1’ for SPI
7/54
I2C interface
4
STMPE811
I2C interface
The addressing scheme of STMPE811 is designed to allow up to 2 devices to be connected
to the same I2C bus.
Figure 4.
STMPE811 I2C interface
GND
VCC
SCLK
SCLK
SDAT
SDAT
STMPE811
ADDR0
Table 5.
I2C address
ADDR0
Address
0
0 x 82
1
0 x 88
Note
For the bus master to communicate to the slave device, the bus master must initiate a Start
condition and be followed by the slave device address. Accompanying the slave device
adress, is a read/write bit (R/W). The bit is set to 1 for read and 0 for write operation. If a
match occurs on the slave device address, the corresponding device gives an acknowledge
on the SDA during the 9th bit time. If there is no match, it deselects itself from the bus by not
responding to the transaction.
Figure 5.
I2C timing diagram
SDA
tBUF
tHD:STA
tR
tHD:STA
tF
SCL
tHIGH
P
S
tLOW
tSU:DAT
tHD:DAT
SR
tSU:STA
P
tSU:STO
AI00589
8/54
STMPE811
I2C interface
Table 6.
I2C timing
Symbol
Min
Typ
Max
Uni
400
kHz
fSCL
SCL clock frequency
tLOW
Clock low period
1.3
μs
tHIGH
Clock high period
600
ns
tF
0
SDA and SCL fall time
300
ns
tHD:STA
START condition hold time (after this
period the first clock is generated)
600
ns
tSU:STA
START condition setup time (only relevant
for a repeated start period)
600
ns
tSU:DAT
Data setup time
100
ns
tHD:DAT
Data hold time
0
μs
tSU:STO
STOP condition setup time
600
ns
Time the bus must be free before a new
transmission can start
1.3
μs
tBUF
4.1
Parameter
I2C features
The features that are supported by the I2C interface are listed below:
●
I2C slave device
●
Operates at 1.8 V
●
Compliant to Philips I2C specification version 2.1
●
Supports standard (up to 100 Kbps) and fast (up to 400 Kbps) modes
Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.
A Start condition must precede any data/command transfer. The device continuously
monitors for a Start condition and does not respond to any transaction unless one is
encountered.
Stop condition
A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state. A
Stop condition terminates communication between the slave device and the bus master. A
read command that is followed by NoAck can be followed by a Stop condition to force the
slave device into idle mode. When the slave device is in idle mode, it is ready to receive the
next I2C transaction. A Stop condition at the end of a write command stops the write
operation to registers.
Acknowledge bit
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls
the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave
the SDATA in high state if it does not acknowledge the receipt of the data.
9/54
I2C interface
4.2
STMPE811
Data input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA
signal must be stable during the rising edge of SCLK and the SDATA signal must change
only when SCLK is driven low.
Table 7.
Operating modes
Mode
Byte
Programming sequence
Start, Device address, R/W = 0, Register address to be read
Restart, Device address, R/W = 1, Data Read, Stop
≥1
Read
If no Stop is issued, the Data Read can be continuously performed. If
the register address falls within the range that allows an address autoincrement, then the register address auto-increments internally after
every byte of data being read.
Start, Device address, R/W = 0, Register address to be written, Data
Write, Stop
≥1
Write
Slave
10/54
Data to
Write + 2
Ack
Stop
Data to
Write + 1
Stop
Data
Read + 2
No Ack
Data
Read + 1
Ack
Stop
No Ack
Ack
Data
Read
Ack
Ack
Restart
Data to
Write
Ack
Reg
Address
R/W=1
Ack
Restart
Data
to be
written
Ack
Reg
Address
R/W=1
Ack
Restart
Device
Address
Data
Read
Ack
Stop
Ack
Restart
Reg
Address
Ack
Ack
R/W=0
Master
Ack
R/W=0
R/W=0
Device
Address
Device
Address
Ack
Device
Address
Reg
Address
Ack
Device
Address
R/W=0
More than one byte
Read
Start
One byte
Write
Start
More than one byte
Read
Device
Address
Start
One byte
Read
Read and write modes (random and sequential)
Start
Figure 6.
If no Stop is issued, the Data Write can be continuously performed. If
the register address falls within the range that allows address autoincrement, then the register address auto-increments internally after
every byte of data being written in. For those register addresses that
fall within a non-incremental address range, the address will be kept
static throughout the entire write operation. Refer to the memory map
table for the address ranges that are auto and non-increment.
STMPE811
4.3
I2C interface
Read operation
A write is first performed to load the register address into the Address Counter but without
sending a Stop condition. Then, the bus master sends a reStart condition and repeats the
Device Address with the R/W bit set to 1. The slave device acknowledges and outputs the
content of the addressed byte. If no additional data is to be read, the bus master must not
acknowledge the byte and terminates the transfer with a Stop condition.
If the bus master acknowledges the data byte, then it can continue to perform the data
reading. To terminate the stream of data bytes, the bus master must not acknowledge the
last output byte, and be followed by a Stop condition. If the address of the register written
into the Address Counter falls within the range of addresses that has the auto-increment
function, the data being read will be coming from consecutive addresses, which the internal
Address Counter automatically increments after each byte output. After the last memory
address, the Address Counter 'rolls-over' and the device continues to output data from the
memory address of 0x00. Similarly, for the register address that falls within a non-increment
range of addresses, the output data byte comes from the same address (which is the
address referred by the Address Counter).
Acknowledgement in read operation
For the above read command, the slave device waits, after each byte read, for an
acknowledgement during the ninth bit time. If the bus master does not drive the SDA to a
low state, then the slave device terminates and switches back to its idle mode, waiting for
the next command.
4.4
Write operations
A write is first performed to load the register address into the Address Counter without
sending a Stop condition. After the bus master receives an acknowledgement from the slave
device, it may start to send a data byte to the register (referred by the Address Counter).
The slave device again acknowledges and the bus master terminates the transfer with a
Stop condition.
If the bus master needs to write more data, it can continue the write operation without
issuing the Stop condition. Whether the Address Counter autoincrements or not after each
data byte write depends on the address of the register written into the Address Counter.
After the bus master writes the last data byte and the slave device acknowledges the receipt
of the last data, the bus master may terminate the write operation by sending a Stop
condition. When the Address Counter reaches the last memory address, it 'rolls-over' to the
next data byte write.
11/54
SPI interface
5
STMPE811
SPI interface
The SPI interface in STMPE811 uses a 4-wire communication connection (DATA IN, DATA
OUT, CLK, CS). In the diagram, “Data in” is referred to as MOSI (master out slave in) and
“DATA out” is referred to as MISO (master in slave out).
5.1
SPI protocol definition
The SPI (serial peripheral interface) follows a byte sized transfer protocol. All transfers begin
with an assertion of CS_n signal (falling edge). The protocol for reading and writing is
different and the selection between a read and a write cycle is dependent on the first
captured bit on the slave device. A '1' denotes a read operation and a '0' denotes a write
operation. The SPI protocol defined in this section is shown in Figure 3.
The following are the main features supported by this SPI implementation.
5.1.1
●
Support of 1 MHz maximum clock frequency.
●
Support for autoincrement of address for both read and write.
●
Full duplex support for read operation.
●
Daisy chain configuration support for write operation.
●
Robust implementation that can filter glitches of up to 50 ns on the CS_n and SCL pins.
●
Support for all 4 modes of SPI as defined by the CPHA, CPOL bits on SPICON.
Register read
The following steps need to be followed for register read through SPI.
12/54
1.
Assert CS_n by driving a '0' on this pin.
2.
Drive a '1' on the first SCL launch clock on MOSI to select a read operation.
3.
The next 7 bits on MOSI denote the 7-bit register address (MSB first).
4.
The next address byte can now be transmitted on the MOSI. If the autoincrement bit is
set, the following address transmitted on the MOSI is ignored. Internally, the address is
incremented. If the autoincrement bit is not set, then the following byte denotes the
address of the register to be read next.
5.
Read data is transmitted by the slave device on the MISO (MSB first), starting from the
launch clock following the last address bit on the MOSI.
6.
Full duplex read operation is achieved by transmitting the next address on MOSI while
the data from the previous address is available on MISO.
7.
To end the read operation, a dummy address of all 0's is sent on MOSI.
STMPE811
5.1.2
SPI interface
Register write
The following steps need to be followed for register write through SPI.
5.1.3
1.
Assert CS_n by driving a '0' on this pin.
2.
Drive a '0' on the first SCL launch clock on MOSI to select a write operation.
3.
The next 7 bits on MOSI denote the 7-bit register address (MSB first).
4.
The next byte on the MOSI denotes data to be written.
5.
The following transmissions on MOSI are considered byte-sized data. The register
address to which the following data is written depends on whether the autoincrement
bit in the SPICON register is set. If this bit has been set previously, the register address
is incremented for data writes.
Termination of data transfer
A transfer can be terminated before the last launch edge by deasserting the CS_n signal. If
the last launch clock is detected, it is assumed that the data transfer is successful.
5.2
SPI timing modes
The SPI timing modes are defined by CPHA and CPOL,CPHA and CPOL are read from the
"SDAT" and "A0" pins during power-up reset. The following four modes are defined
according to this setting.
Table 8.
SPI timing modes
CPOL_N (SDAT pin)
CPOL
CPHA (ADDR pin)
Mode
0
1
0
0
0
1
1
1
1
0
0
2
1
0
1
3
The clocking diagrams of these modes are shown in ON reset. The device always operates
in mode 0. Once the bits are set in the SPICON register, the mode change takes effect on
the next transaction defined by the CS_n pin being deasserted and asserted.
13/54
SPI interface
5.2.1
STMPE811
SPI timing definition
Table 9.
SPI timing specification
Timing
Symbol
Description
Unit
Min
tCSS
14/54
CS_n falling to
first capture
clock
Typ
Max
1
μs
tCL
Clock low
period
500
ns
tCH
Clock high
period
500
ns
tLDI
Launch clock
to MOSI data
valid
20
ns
tLDO
Launch clock
to MISO data
valid
330
μs
tDI
Data on MOSI
valid
1
μs
tCCS
Last clock
edge to CS_n
high
1
μs
tCSH
CS_n high
period
2
μs
tCSCL
CS_n high to
first clock edge
300
ns
tCSZ
CS_n high to
tri-state on
MISO
1
μs
STMPE811
SPI interface
Figure 7.
SPI timing specification
15/54
STMPE811 registers
6
STMPE811
STMPE811 registers
This section lists and describes the registers of the STMPE811 device, starting with a
register map and then provides detailed descriptions of register types.
Table 10.
Address
16/54
Register summary map table
Register name
Bit
Type
Reset value
Function
0x00
CHIP_ID
16
R
0x0811
Device identification
0x02
ID_VER
8
R
0x01
Revision number
0x01 for engineering sample
0x02 for final silicon
0x03
SYS_CTRL1
8
R/W
0x00
Reset control
0x04
SYS_CTRL2
8
R/W
0x0F
Clock control
0x08
SPI_CFG
8
R/W
0x01
SPI interface configuration
0x09
INT_CTRL
8
R/W
0x00
Interrupt control register
0x0A
INT_EN
8
R/W
0x00
Interrupt enable register
0x0B
INT_STA
8
R
0x10
interrupt status register
0x0C
GPIO_EN
8
R/W
0x00
GPIO interrupt enable
register
0x0D
GPIO_INT_STA
8
R
0x00
GPIO interrupt status
register
0x0E
ADC_INT_EN
8
R/W
0x00
ADC interrupt enable
register
0x0F
ADC_INT_STA
8
R
0x00
ADC interrupt status register
0x10
GPIO_SET_PIN
8
R/W
0x00
GPIO set pin register
0x11
GPIO_CLR_PIN
8
R/W
0x00
GPIO clear pin register
0x12
GPIO_MP_STA
8
R/W
0x00
GPIO monitor pin state
register
0x13
GPIO_DIR
8
R/W
0x00
GPIO direction register
0x14
GPIO_ED
8
R/W
0x00
GPIO edge detect register
0x15
GPIO_RE
8
R/W
0x00
GPIO rising edge register
0x16
GPIO_FE
8
R/W
0x00
GPIO falling edge register
0x17
GPIO_AF
8
R/W
0x00
Alternate function register
0x20
ADC_CTRL1
8
R/W
0x9C
ADC control
0x21
ADC_CTRL2
8
R/W
0x01
ADC control
0x22
ADC_CAPT
8
R/W
0xFF
To initiate ADC data
acquisition
0x30
ADC_DATA_CH0
16
R
0x0000
ADC channel 0
0x32
ADC_DATA_CH1
16
R
0x0000
ADC channel 1
STMPE811
STMPE811 registers
Table 10.
Register summary map table (continued)
Address
Register name
Bit
Type
Reset value
Function
0x34
ADC_DATA_CH2
16
R
0x0000
ADC channel 2
0x36
ADC_DATA_CH3
16
R
0x0000
ADC channel 3
0x38
ADC_DATA_CH4
16
R
0x0000
ADC channel 4
0x3A
ADC_DATA_CH5
16
R
0x0000
ADC channel 5
0x3C
ADC_DATA_CH6
16
R
0x0000
ADC channel 6
0x3E
ADC_DATA_CH7
16
R
0x0000
ADC channel 7
0x40
TSC_CTRL
8
R/W
0x90
4-wire touchscreen
controller setup
0x41
TSC_CFG
8
R/W
0x00
Touchscreen controller
configuration
0x42
WDW_TR_X
16
R/W
0x0FFF
Window setup for top right X
0x44
WDW_TR_Y
16
R/W
0x0FFF
Window setup for top right Y
0x46
WDW_BL_X
16
R/W
0x0000
Window setup for bottom left
X
0x48
WDW_BL_Y
16
R/W
0x0000
Window setup for bottom left
Y
0x4A
FIFO_TH
8
R/W
0x00
FIFO level to generate
interrupt
0x4B
FIFO_STA
8
R/W
0x20
Current status of FIFO
0x4C
FIFO_SIZE
8
R
0x00
Current filled level of FIFO
0x4D
TSC_DATA_X
16
R
0x0000
Data port for touchscreen
controller data access
0x4F
TSC_DATA_Y
16
R
0x0000
Data port for touchscreen
controller data access
0x51
TSC_DATA_Z
8
R
0x0000
Data port for touchscreen
controller data access
0x52
TSC_DATA_XYZ
32
R
0x00000000
Data port for touchscreen
controller data access
0x56
TSC_FRACT_X
YZ
8
0x57
TSC_DATA
8
R
0x00
0x58
TSC_I_DRIVE
8
R/W
0x00
0x59
TSC_SHIELD
8
R/W
0x00
0x60
TEMP_CTRL
8
R/W
0x00
Temperature sensor setup
0x61
TEMP_DATA
8
R
0x00
Temperature data access
port
0x62
TEMP_TH
8
R/W
0x00
Threshold for temperature
controlled interrupt
0x00
Data port for touchscreen
controller data access
17/54
System and identification registers
7
STMPE811
System and identification registers
Table 11.
System and identification registers map
Address
Register name
Bit
Type
Reset
0x00
CHIP_ID
16
R
0x0811
0x02
ID_VER
8
R
0x01
Revision number
0x01 for engineering sample
0x03
SYS_CTRL1
8
R/W
0x00
Reset control
0x04
SYS_CTRL2
8
R/W
0x0F
Clock control
0x08
SPI_CFG
8
R/W
0x01
SPI interface configuration
CHIP_ID
Device identification
Address:
0x00
Type:
R
Reset:
0x0811
Description:
16-bit device identification
ID_VER
Revision number
Address:
0x02 (0x01 for engineering samples)
Type:
R
Reset:
0x01
Description:
16-bit revision number
18/54
Function
Device identification
STMPE811
System and identification registers
SYS_CTRL1
7
Reset control
6
5
4
3
2
RESERVED
Address:
0x03
Type:
R/W
Reset:
0x00
Description:
The reset control register enables to reset the device
1
0
SOFT_RESET
HIBERNATE
[7:2] RESERVED
[1] SOFT_RESET: Reset the STMPE811 using the serial communication interface
[0] HIBERNATE: Force the device into hibernation mode.
Forcing the device into hibernation mode by writing ‘1’ to this bit would disable the hot-key
feature. If the hot-key feature is required, use the default auto-hibernation mode.
SYS_CTRL2
Clock control
7
6
5
4
3
2
1
0
−
−
−
−
TS_OFF
GPIO_OFF
TSC_OFF
ADC_OFF
Address:
0x04
Type:
R/W
Reset:
0x0F
Description:
This register enables to switch off the clock supply
[7:4] RESERVED
[3] TS_OFF: Switch off the clock supply to the temperature sensor
1: Switches off the clock supply to the temperature sensor
[2] GPIO_OFF: Switch off the clock supply to the GPIO
1: Switches off the clock supply to the GPIO
[1] TSC_OFF: Switch off the clock supplyto the touchscreen controller
1: Switches off the clock supply to the touchscreen controller
[0] ADC_OFF: Switch off the clock supply to the ADC
1: Switches off the clock supply to the ADC
19/54
System and identification registers
SPI_CFG
7
STMPE811
SPI interface configuration
6
5
4
3
RESERVED
Address:
0x08
Type:
R/W
Reset:
0x01
Description:
SPI interface configuration register
2
1
0
AUTO_INCR
SPI_CLK_MOD1
SPI_CLK_MOD0
[7:3] RESERVED
[2] AUTO_INCR: Bitfield description
This bit defines whether the SPI transaction follows an addressing scheme that internally
autoincrements or not
[1] SPI_CLK_MOD1: Bitfield description
This bit reflects the value of the SCAD/A0 pin during power-up reset
[0] SPI_CLK_MOD0: Bitfield description
This bit reflects the value of the SCAD/A0 pin during power-up reset
20/54
STMPE811
8
Interrupt system
Interrupt system
The STMPE811 uses a 2-tier interrupt structure. The ADC interrupts and GPIO interrupts
are ganged as a single bit in the “interrupt status register”. The interrupts from the
touchscreen controller and temperature sensor can be seen directly in the interrupt status
register.
Figure 8.
Interrupt system diagram
FIFO status,
TSC touch,
Temp sensor
Interrupt
status
AND
GPIO
interrupt
status
Interrupt
enable
AND
GPIO
interrupt
enable
ADC
interrupt
status
AND
ADC
interrupt
enable
21/54
Interrupt system
STMPE811
INT_CTRL
7
Interrupt control register
6
5
RESERVED
4
3
2
1
0
INT_POLARITY
INT_TYPE
GLOBAL_INT
Address:
0x09
Type:
R/W
Reset:
0x00
Description:
The interrupt control register is used to enable the interruption from a system-related
interrupt source to the host.
[7:3] RESERVED
[2] INT_POLARITY: This bit sets the INT pin polarity
1: Active high/rising edge
0: Active low/falling edge
[1] INT_TYPE: This bit sets the type of interrupt signal required by the host
1: Edge interrupt
0: Level interrupt
[0] GLOBAL_INT: This is master enable for the interrupt system
1: Global interrupt
0: Stops all interrupts
22/54
STMPE811
Interrupt system
INT_EN
Interrupt enable register
7
6
GPIO
ADC
5
4
TEMP_SENS FIFO_EMPTY
3
2
1
0
FIFO_FULL
FIFO_0FLOW
FIFO_TH
TOUCH_DET
Address:
0x0A
Type:
R/W
Reset:
0x00
Description:
The interrupt enable register is used to enable the interruption from a system related
interrupt source to the host.
[7] GPIO: Any enabled GPIO interrupts
[6] ADC: Any enabled ADC interrupts
[5] TEMP_SENS: Temperature threshold triggering
[4] FIFO_EMPTY: FIFO is empty
[3] FIFO_FULL: FIFO is full
[2] FIFO_OFLOW: FIFO is overflowed
[1] FIFO_TH: FIFO is above threshold
[0] TOUCH_DET: Touch is detected
INT_STA
Interrupt status register
7
6
GPIO
ADC
5
4
TEMP_SENS FIFO_EMPTY
3
2
1
0
FIFO_FULL
FIFO_OFLOW
FIFO_TH
TOUCH_DET
Address:
0x0B
Type:
R
Reset:
0x10
Description:
The interrupt status register monitors the status of the interruption from a particular
interrupt source to the host. Regardless of whether the INT_EN bits are enabled, the
INT_STA bits are still updated. Writing '1' to this register clears the corresponding
bits. Writing '0' has no effect.
[7] GPIO: Any enabled GPIO interrupts
[6] ADC: Any enabled ADC interrupts
[5] TEMP_SENS: Temperature threshold triggering
[4] FIFO_EMPTY: FIFO is empty
[3] FIFO_FULL: FIFO is full
[2] FIFO_OFLOW: FIFO is overflowed
[1] FIFO_TH: FIFO is above threshold
[0] TOUCH_DET: Touch is detected
23/54
Interrupt system
STMPE811
GPIO interrupt enable register
GPIO_INT_EN
7
6
5
4
3
2
1
0
IEG[x]
Address:
0x0C
Type:
R/W
Reset:
0x10
Description:
The interrupt status register monitors the status of the interruption from a particular
interrupt source to the host. Regardless of whether the IER bits are enabled, the ISR
bits are still updated. Writing '1' to this register clears the corresponding bits. Writing
'0' has no effect.
[7:0] IEG[x]: Interrupt enable GPIO mask (where x = 7 to 0)
1: Writing ‘1’ to the IE[x] bit enables the interruption to the host
GPIO interrupt status register
GPIO_INT_STA
7
6
5
4
3
2
1
0
ISG[x]
Address:
0x0D
Type:
R/W
Reset:
0x00
Description:
The GPIO interrupt status register monitors the status of the interruption from a
particular GPIO pin interrupt source to the host. Regardless of whether or not the
GPIO_STA bits are enabled, the GPIO_STA bits are still updated. The ISG[7:0] bits
are the interrupt status bits corresponding to the GPIO[7:0] pins. Writing '1' to this
register clears the corresponding bits. Writing '0' has no effect.
[7:0] ISG[x]: GPIO interrupt status (where x = 7 to 0)
Read:
Interrupt status of the GPIO[x]. Reading the register will clear any bits that have been set to '1'
Write:
Writing to this register has no effect
24/54
STMPE811
9
Analog-to-digital converter
Analog-to-digital converter
An 8-input,12-bit analog-to-digital converter (ADC) is integrated in the STMPE811. The ADC
can be used as a generic analog-to-digital converter, or as a touchscreen controller capable
of controlling a 4-wire resistive touchscreen.
AddINT_EN
Table 12.
ADC controller register summary table
Address
Register name
Size
Description
0x20
ADC_CTRL1
8
ADC control
0x21
ADC_CTRL2
8
ADC control
0x22
ADCCapture
8
To initiate ADC data acquisition
0x30
ADC_DATA_CH0
8
ADC channel 0 (IN3/GPIO-3)
0x32
ADC_DATA_CH1
8
ADC channel 1 (IN2/GPIO-2)
0x34
ADC_DATA_CH2
8
ADC channel 2 (IN1/GPIO-1)
0x36
ADC_DATA_CH3
8
ADC channel 3 (IN0-GPIO-0)
0x38
ADC_DATA_CH4
8
ADC channel 4 (TSC)
0x3A
ADC_DATA_CH5
8
ADC channel 5 (TSC)
0x3C
ADC_DATA_CH6
8
ADC channel 6 (TSC)
0x3E
ADC_DATA_CH7
8
ADC channel 7 (TSC)
25/54
Analog-to-digital converter
STMPE811
ADC_CTRL1
7
RESERVED
ADC control 1
6
5
4
SAMPLE_TIME2 SAMPLE_TIME1 SAMPLE_TIME0
Address:
0x20
Type:
R/W
Reset:
0x9C
Description:
ADC control register
3
2
1
0
MOD_12B
RESERVED
REF_SEL
RESERVED
[7] RESERVED
[6:4] SAMPLE_TIMEn: ADC conversion time in number of clock
000: 36
001: 44
010: 56
011: 64
100: 80
101: 96
110: 124
111: Not valid
[3] MOD_12B: Selects 10 or 12-bit ADC operation
1: 12 bit ADC
0: 10 bit ADC
[2] RESERVED
[1] REF_SEL: Selects between internal or external reference for the ADC
1: External reference
0: Internal reference
[0] RESERVED
26/54
STMPE811
Analog-to-digital converter
ADC_CTRL2
7
ADC control 2
6
5
4
3
2
RESERVED
Address:
0x21
Type:
R/W
Reset:
0x01
Description:
ADC control.
1
0
ADC_FREQ_1
ADC_FREQ_0
[7] RESERVED
[6] RESERVED
[5] RESERVED
[4] RESERVED
[3] RESERVED
[2] RESERVED
[1:0] ADC_FREQ: Selects the clock speed of ADC
00: 1.625 MHz typ.
01: 3.25 MHz typ.
10: 6.5 MHz typ.
11: 6.5 MHz typ.
ADC channel data capture
ADC_CAPT
7
6
5
4
3
2
1
0
CH[7:0]
Address:
0x22
Type:
R/W
Reset:
0xFF
Description:
To initiate ADC data acquisition
[7:0] CH[7:0]: ADC channel data capture
Write '1' to initiate data acquisition for the corresponding channel. Writing '0' has no effect.
Reads '1' if conversion is completed. Reads '0' if conversion is in progress.
27/54
Analog-to-digital converter
STMPE811
ADC channel data registers
ADC_DATA_CHn
11
10
9
8
7
6
5
4
3
2
1
0
DATA[11:0]
Address:
Add address
Type:
R/W
Reset:
0x0000
Description:
ADC data register 0-7 (DATA_CHn=0 -7)
[11:0] DATA[11:0]: ADC channel data
If TSC is enabled, CH3-0 is used for TSC and all readings to these channels give 0x0000
The ADC in STMPE811 operates on an internal RC clock with a typical frequency of
6.5 MHz. The total conversion time in ADC mode depends on the "SampleTime" setting,
and the clock division field 'Freq'.
The following table shows the conversion time based on 6.5 MHz, 3.25 MHz and 1.625 MHz
clock.
Table 13.
28/54
ADC conversion time
Sample time
setting
Conversion time
6.5 MHz
3.25 MHz
1.625 MHz
in ADC clock
(154 ns)
(308 ns)
(615 ns)
000
36
5.5 μs (180 kHz)
11 μs (90 kHz)
22 μs (45 kHz)
001
44
6.8 μs (147 kHz)
13.6 μs (74 kHz)
27 μs (36 kHz)
010
56
8.6 μs (116 kHz)
17.2 μs (58 kHz)
34.4 μs (29 kHz)
011
64
9.9 μs (101 kHz)
19.8 μs (51 kHz)
39.6 μs (25 kHz)
100
80
12.3 μs (81.5 kHz) 24.6 μs (41 kHz)
49.2 μs (20 kHz)
101
96
14.8 μs (67.6 kHz) 28.8 μs (33 kHz)
59.2 μs (17 kHz)
110
124
19.1 μs (52.3 kHz) 38.2 μs (26 kHz)
56.4 μs (13 kHz)
STMPE811
10
Touchscreen controller
Touchscreen controller
The STMPE811 is integrated with a hard-wired touchscreen controller for 4-wire resistive
type touchscreen. The touchscreen controller is able to operate completely autonomously,
and will interrupt the connected CPU only when a pre-defined event occurs.
Figure 9.
Touchscreen controller block diagram
Movement
&
window tracking
10/12 bit
ADC
s
FIFO
FIFO
&
interrupt control
10.1
Switch
&
drivers
Driver
&
switch control
Driver and switch control unit
The driver and switch control unit allows coordination of the ADC and the MUX/switch. With
the coordination of this unit, a stream of data is produced at a selected frequency.
The touchscreen drivers can be configured with 2 current ratings: 20 mA or 50 mA. In the
case where multiple touch-down on the screen is causing a short, the current from the driver
is limited to these values. Tolerance of these current setting is +/- 25%.
Movement tracking
The "Tracking Index" in the TSC_CTRL register specifies a value, which determines the
distance between the current touch position and the previous touch position. If the distance
is shorter than the tracking index, it is discarded.
The tracking is calculated by summation of the horizontal and vertical movement. Movement
is only reported if:
(Current X - Previously Reported X) + (Current Y - Previously Reported Y) > Tracking Index
If pressure reporting is enabled (X/Y/Z), an increase in pressure will override the movement
tracking and report the new data set, even if X/Y is within the previous tracking index. This is
to ensure that a slow touch will not be discarded.
If pressure data is not used, select X/Y mode in touchscreen data acquisition. (Opmode field
in TSCControl register).
29/54
Touchscreen controller
STMPE811
Window tracking
The -WDW_X and WDW_Y registers allow to pre-set a sub-window in the touchscreen such
that any touch position that is outside the sub-window will be discarded.
Figure 10. Window tracking
Top right coordinates
Active window
Bottom left coordinates
FIFO
FIFO has a depth of 128 sectors. This is enough for 128 sets of touch data at maximum
resolution (2 x 12 bits). FIFO can be programmed to generate an interrupt when it is filled to
a pre-determined level.
Sampling
The STMPE811 touchscreen controller has an internal 100 kHz, 12-bit ADC able to execute
autonomous driving/sampling. Each "sample" consists of 4 ADC readings that provide the X
and Y locations, as well as the touch pressure.
Figure 11. Sampling
ADC
takes X reading
Drive X
30/54
Settling
period
ADC
takes Y reading
Drive Y
Settling
period
STMPE811
Touchscreen controller
Oversampling and averaging function
The STMPE811 touchscreen controller can be configured to oversample by 2/4/8 times and
provide the averaged value as final output. This feature helps to reduce the effect of
surrounding noise.
Table 14.
Address
Touchscreen controller register summary table
Register name
Bit
Type
Function
0x40
TSC_CTRL
8
R/W
4-wire touchscreen controller setup
0x41
TSC_CFG
8
R/W
TSC configuration register
0x42
WDW_TR_X
16
R/W
Window setup for top right X
0x44
WDW_TR_Y
16
R/W
Window setup for top right Y
0x46
WDW_TR_X
16
R/W
Window setup for bottom left X
0x48
WDW_TR_Y
16
R/W
Window setup for bottom left Y
0x4A
FIFO_TH
8
R/W
FIFO level to generate interrupt
0x4B
FIFO_CTRL_STA
8
R/W
Current status of FIFO
0x4C
FIFO_SIZE
8
R
Current filled level of FIFO
0x4D
TSC_DATA_X
16
R
Data port for TSC data access
0x4F
TSC_DATA_Y
16
R
Data port for TSC data access
0x51
TSC_DATA_Z
8
R
Data port for TSC data access
0x52
TSC_DATA_XYZ
32
R
Data port for TSC data access
0x56
TSC_FRACT_Z
8
0x57
TSC_DATA
8
R
0x58
TSC_I_DRIVE
8
R/W
TSC_I_DRIVE
0x59
TSC_SHIELD
8
R/W
TSC_SHIELD
TSC_FRACT_Z
TSC data access port
31/54
Touchscreen controller
STMPE811
TSC_CTRL
7
Touchscreen controller control register
6
5
TSC_STA
4
3
TRACK
Address:
0x40
Type:
R/W
Reset:
0x90
Description:
4-wire touchscreen controller (TSC) setup.
[7] TSC_STA: TSC status
Reads '1' when touch is detected
Reads '0' when touch is not detected
Writing to this register has no effect
[6:4] TRACK: Tracking index
000: No window tracking
001: 4
010: 8
011: 16
100: 32
101: 64
110: 92
111: 127
[3:1] OP_MOD: TSC operating mode
000: X, Y, Z acquisition
001: X, Y only
010: X only
011: Y only
100: Z only
This field cannot be written on, when EN = 1
[0] EN: Enable TSC
32/54
2
OP_MOD
1
0
EN
STMPE811
Touchscreen controller
TSC_CFG
7
Touchscreen controller configuration register
6
5
AVE_CTRL_1 AVE_CTRL_0
4
3
TOUCH_DET TOUCH_DET TOUCH_DET
_DELAY_2
_DELAY_1
_DELAY_0
2
1
0
SETTLING_2
SETTLING_1
SETTLING_0
Address:
0x41
Type:
R/W
Description:
Touchscreen controller configuration register.
[7] AVE_CTRL_1: Average control
00 = 1 sample
01 = 2 samples
10 = 4 samples
11 = 8 samples
[6] AVE_CTRL_0: Average control
00 = 1 sample
01 = 2 samples
10 = 4 samples
11 = 8 samples
[5] TOUCH_DET_DELAY_2: Touch detect delay
000 = 10 μs
001 = 50 μs
[4] TOUCH_DET_DELAY_1: Touch detect delay
000 = 10 μs
001 = 50 μs
[3] TOUCH_DET_DELAY_0: Touch detect delay
010 = 100 μs
011 = 500 μs
100 = 1 ms
101 = 5 ms
110 = 10 ms
111 = 50 ms
[2:0] SETTLING: Panel driver settling time(1)
000 = 10 μs
001 = 100 μs
010 = 500 μS
011 =1 ms
100 = 5 ms
101 = 10 ms
110 = 50 ms
111 =100 ms
1. For large panels (> 6”), a capacitor of 10 nF is recommended at the touchscreen terminals for noise filtering.
In this case, settling time of 1 ms or more is recommended.
33/54
Touchscreen controller
WDW_TR_X
STMPE811
Window setup for top right X
7
6
5
4
3
2
1
0
2
1
0
TR_X [11:0]
Address:
0x42
Type:
R/W
Reset:
0x0FFF
Description:
Window setup for top right X coordinates
[11:0] TR_X: Bit 11:0 of top right X coordinates
WDW_TR_Y
Window setup for top right Y
7
6
5
TR_Y [11:0]
Address:
0x44
Type:
R/W
Reset:
0x0FFF
Description:
Window setup for top right Y coordinates
[11:0] TR_X: Bit 11:0 of top right Y coordinates
34/54
4
3
STMPE811
Touchscreen controller
WDW_BL_X
Window setup for bottom left X
7
6
5
4
3
2
1
0
1
0
BL_X [11:0]
Address:
0x46
Type:
R/W
Reset:
0x0000
Description:
Window setup for bottom left X coordinates
[11:0] BL_X: Bit 11:0 of bottom left X coordinates
WDW_BL_Y
Window setup for bottom left Y
7
6
5
4
3
2
BL_Y [11:0]
Address:
0x48
Type:
R/W
Reset:
0x0000
Description:
Window setup for bottom left Y coordinates
[11:0] BL_X: Bit 11:0 of bottom left Y coordinates
FIFO_TH
7
FIFO threshold
6
5
4
3
2
1
0
FIFO_TH
Address:
0x4A
Type:
R/W
Reset:
0x00
Description:
Triggers an interrupt upon reaching or exceeding the threshold value. This field must not be set
as zero.
[7:0] FIFO_TH: Touchscreen controller FIFO threshold
35/54
Touchscreen controller
STMPE811
FIFO_CTRL_STA
FIFO threshold
7
6
5
4
FIFO_OFLOW
FIFO_FULL
FIFO_EMPTY
FIFO_TH_TRIG
Address:
0x4B
Type:
R/W
Reset:
0x20
Description:
Current status of FIFO..
3
2
1
0
RESERVED
FIFO_RESET
[7] FIFO_OFLOW:
1: Reads 1 if FIFO is overflow
[6] FIFO_FULL:
[5] FIFO_EMPTY:
[4] FIFO_TH_TRIG:
[3:1] RESERVED
[0] FIFO_RESET:
FIFO_SIZE
7
FIFO size
6
5
4
3
RESERVED
2
1
0
FIFO_SIZE
Address:
0x4C
Type:
R
Reset:
0x00
Description:
Current number of samples available
[7:0] FIFO_SIZE: Number of samples available
TSC_DATA_X
11
10
TSC_DATA_X
9
8
7
6
5
DATAY[11:0]
Address:
0x4D
Type:
R
Reset:
0x0000
Description:
Bit 11:0 of Y data
[11:0] DATAY[11:0]: Bit 11:0 of Y data
36/54
4
3
2
1
0
STMPE811
Touchscreen controller
TSC_DATA_Y
11
10
TSC_DATA_Y
9
8
7
6
5
4
3
2
1
0
DATAY[11:0]
Address:
0x4F
Type:
R
Reset:
0x0000
Description:
Bit 11:0 of Y data
[11:0] DATAY[11:0]: bit 11:0 of Y data
TSC_DATA_Z
7
TSC_DATA_Z
6
5
4
3
2
1
0
DATAZ[7:0]
Address:
0x51
Type:
R
Reset:
0x0000
Description:
Bit 7:0 of Z data
[7:0] DATAZ[7:0]: bit 7:0 of Z data
37/54
Touchscreen controller
STMPE811
TSC_DATA
Touchscreen controller DATA
7
6
5
4
3
2
1
0
DATA
Address:
0x57 (auto-increment), 0x07 (non-auto-increment)
Type:
R
Reset:
0x00
Description:
Data port for TSC data access
[11:0] DATA: data bytes from TSC FIFO
The data format from the TSC_DATA register depends on the setting of "OpMode" field in
TSC_CTRL register. The samples acquired are accessed in "packed samples". The size of
each "packed sample" depends on which mode the touchscreen controller is operating in.
The TSC_DATA register can be accessed in 2 modes:
●
Autoincrement
●
Non autoincrement
To access the 128-sets buffer, the non autoincrement mode should be used.
Table 15.
Touchscreen controller DATA register
TSC_CTRL in
operation
mode
38/54
Number of
bytes to read
from
TSC_DATA
Byte0
Byte1
Byte2
000
4
[11:4] of X
[3:0] of X
[11:8] of Y
[7:0] of Y
001
3
[11:4] of X
[3:0] of X
[11:8] of Y
[7:0] of Y
010
2
[11:4] of X
[3:0] of X
011
2
[11:4] of Y
[3:0] of Y
100
1
[7:0] of Z
Byte3
[7:0] of Z
STMPE811
Touchscreen controller
TSC_FRACTION_Z
7
6
Touchscreen controller FRACTION_Z
5
4
3
RESERVED
2
1
0
FRACTION_Z
Address:
0x56
Type:
R
Reset:
0x00
Description:
This register allows to select the range and accuracy of the pressure measurement
[7:3] RESERVED
[2:0] FRACTION_Z:
000: Fractional part is 0, whole part is 8
001: Fractional part is 1, whole part is 7
010: Fractional part is 2, whole part is 6
011: Fractional part is 3, whole part is 5
100: Fractional part is 4, whole part is 4
101: Fractional part is 5, whole part is 3
110: Fractional part is 6, whole part is 2
111: Fractional part is 7, whole part is 1
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Touchscreen controller
STMPE811
TSC_I_DRIVE
7
Touchscreen controller drive I
6
5
4
3
2
1
RESERVED
0
DRIVE
Address:
0x58
Type:
R/W
Reset:
0x00
Description:
This register sets the current limit value of the touchscreen drivers
[7:1] RESERVED
[0] DRIVE: maximum current on the touchscreeb controller (TSC) driving channel
0: 20 mA typical, 35 mA max
1: 50 mA typical, 80 mA max
TSC_SHIELD
7
Touchscreen controller shield
6
5
RESERVED
4
3
2
1
0
X+
X-
Y+
Y-
Address:
0x59
Type:
R
Reset:
0x00
Description:
Writing each bit would ground the corresponding touchscreen wire
[7:4] RESERVED
[3:0] SHIELD[3:0]:
Write 1 to GND X+, X-, Y+, Y- lines
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STMPE811
11
Touchscreen controller programming sequence
Touchscreen controller programming sequence
The following are the steps to configure the touchscreen controller (TSC):
a)
Disable the clock gating for the touchscreen controller and ADC in the SYS_CFG2
register.
b)
Configure the touchscreen operating mode and the window tracking index.
c)
A touch detection status may also be enabled through enabling the corresponding
interrupt flag. With this interrupt, the user is informed through an interrupt when
the touch is detected as well as lifted.
d)
Configure the TSC_CFG register to specify the “panel voltage settling time”, touch
detection delays and the averaging method used.
e)
A windowing feature may also be enabled through TSCWdwTRX, TSCWdwTRY,
TSCWdwBLX and TSCWdwBLY registers. By default, the windowing covers the
entire touch panel.
f)
Configure the TSC_FIFO_TH register to specify the threshold value to cause an
interrupt. The corresponding interrupt bit in the interrupt module must also be
enabled. This interrupt bit should be masked off during data fetching from the
FIFO in order to prevent an unnecessary trigger of this interrupt. Upon completion
of the data fetching, this bit can be re-enabled
g)
By default, the FIFO_RESET bit in the TSC_FIFO_CTRL_STA register holds the
FIFO in Reset mode. Upon enabling the touchscreen controller (through the EN
bit in TSC_CTRL), this FIFO reset is automatically deasserted. The FIFO status
may be observed from the TSC_FIFO_CTRL_STA register or alternatively through
the interrupt.
h)
Once the data is filled beyond the FIFO threshold value, an interrupt is triggered
(assuming the corresponding interrupt is being enabled). The user is required to
continuously read out the data set until the current FIFO size is below the
threshold, then, the user may clear the interrupt flag. As long as the current FIFO
size exceeds the threshold value, an interrupt from the touchscreen controller is
sent to the interrupt module. Therefore, even if the interrupt flag is cleared, the
interrupt flag will automatically be asserted, as long as the FIFO size exceeds the
threshold value.
i)
The current FIFO size can be obtained from the TSC_FIFO_Sz register. This
information may assists the user in how many data sets are to be read out from
the FIFO, if the user intends to read all in one shot. The user may also read a data
set by a data set.
j)
The TSC_DATA_X register holds the X-coordinates. This register can be used in
all touchscreen operating modes.
k)
The TSC_DATA_Y register holds the Y-coordinates. TSC_DATA_Y register holds
the Y-coordinates.
l)
The TSC_DATA_Z register holds the Z value. TSC_DATA_Z register holds the Zcoordinates.
m) The TSCDATA_XYZ register holds the X, Y and Z values. These values are
packed into 4 bytes. This register can only be used when the touchscreen
operating mode is 000 and 001. This register is to facilitate less byte read.
n)
For the TSC_FRACT_Z register, the user may configure it based on the
touchscreen panel resistance. This allows the user to specify the resolution of the
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Touchscreen controller programming sequence
STMPE811
Z value. With the Z value obtained from the register, the user simply needs to
multiply the Z value with the touchscreen panel resistance to obtain the touch
resistance.
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o)
The TSC_DATA register allows facilitation of another reading format with minimum
I2C transaction overhead by using the non autoincrement mode (or equivalent
mode in SPI). The data format is the same as TSC_DATA_XYZ, with the
exception that all the data fetched are from the same address.
p)
Enable the EN bit of the TSC_CTRL register to start the touch detection and data
acquisition.
q)
During the auto-hibernate mode, a touch detection can cause a wake-up to the
device only when the TSC is enabled and the touch detect status interrupt mask is
enabled.
r)
In order to prevent confusion, it is recommended that the user not mix the data
fetching format (TSC_DATA_X, TSC_DATA_Y, TSC_DATA_Z, TSC_DATA_XYZ
and TSC_DATA) between one reading and the next.
s)
It is also recommended that the user should perform a FIFO reset and TSC
disabling when the ADC or TSC setting are reconfigured.
STMPE811
12
Temperature sensor
Temperature sensor
The STMPE811 internal temperature sensor can be used as a reference for compensation
of the touchscreen parameters. Temperature measurement is optimised for temperature
from 0 ° C to 85 ° C.
Table 16.
Touchscreen parameters
Address
Register name
Function
0x60
TEMP_CTRL
8
Temperature sensor setup
0x61
TEMP_DATA
16
Temperature data access port
0x62
TEMP_TH
16
Threshold for temperature controlled interrupt
TEMP_CTRL
7
Bit
Temperature sensor setup
6
5
RESERVED
4
3
2
1
0
THRES_RANGE
THRES_EN
ACQ_MOD
ACQ
ENABLE
Address:
0x60
Type:
R/W
Reset:
0x00
Description:
Temperature sensor setup
[7:5] RESERVED
[4] THRES_RANGE:
'0' assert interrupt if temperature is >= threshold
'1' assert interrupt if otherwise
[3] THRES_EN: temperature threshold enable
[2] ACQ_MOD:
'0' to acquire temperature for once only
'1' to acquire temperature every 10mS
[1] ACQ
[0] ENABLE
43/54
Temperature sensor
STMPE811
TEMP_DATA
11
10
Temperature data
9
8
7
6
5
4
3
2
1
0
1
0
TEMPERATURE
Address:
0x61
Type:
R
Reset:
0x00
Description:
Temperature data access port
[11:0] TEMPERATURE: Temperature reading
Absolute temperature
= ( VIO * temperature [11:0] ) / 7.51 (12-bit ADC)
= ( VIO * temperature [9:0] ) / 7.51 (10-bit ADC)
Note that VIO is used as a reference in temperature acquisition.
Variations in VIO will directly affect the accuracy of temperature acquired.
TEMP_TH
11
Temperature threshold
10
9
8
7
6
5
4
TEMP_TH
Address:
0x62
Type:
R/W
Reset:
0x00
Description:
Threshold for temperature controlled interrupt
[11:0] TEMP_TH: temperature treshold
44/54
3
2
STMPE811
13
GPIO controller
GPIO controller
A total of 8 GPIOs are available in the STMPE811 port expander device. Most of the GPIOs
share physical pins with some alternate functions. The GPIO controller contains the
registers that allow the host system to configure each of the pins into either a GPIO, or one
of the alternate functions. Unused GPIOs should be configured as outputs to minimize
power consumption.
A group of registers are used to control the exact function of each of the 8 GPIOs. The
registers and their respective addresses are listed in the following table.
Table 17.
GPIO control registers
Address
Size
Register name
Function
(bit)
0x10
GPIO_SET_PIN
8
Set pin register
0x11
GPIO_CLR_PIN
8
Clear pin state
0x12
GPIO_MP_STA
8
Monitor pin state
0x13
GPIO_DIR
8
Set pin direction
0x14
GPIO_ED
8
Edge detect status
0x15
GPIO_RE
8
Rising edge
0x16
GPIO_FE
8
Falling edge
0x17
GPIO_ALT_FUNCT
8
Alternate function
register
All GPIO registers are named as GPIO-x, where x represents the functional group.
7
6
5
4
3
2
1
0
GPIO-7
GPIO-6
GPIO-5
GPIO-4
GPIO-3
GPIO-2
GPIO-1
GPIO-0
45/54
GPIO controller
STMPE811
GPIO_SET_PIN
GPIO set pin register
Address:
0x10
Type:
R/W
Reset:
0x00
Description:
GPIO set pin register.
Writing 1 to this bit causes the corresponding GPIO to go to 1 state.
Writing 0 has no effect.
GPIO_CLR_PIN
Clear pin state register
Address:
0x11
Type:
R/W
Reset:
0x00
Description:
GPIO clear pin state register.
Writing ‘1’ to this bit causes the corresponding GPIO to go to 0 state.
Writing ‘0’ has no effect.
GPIO_MP_STA
GPIO monitor pin state register
Address:
0x12
Type:
R/W
Reset:
0x00
Description:
GPIO monitor pin state.
Reading this bit yields the current state of the bit. Writing has no effect.
46/54
STMPE811
GPIO controller
GPIO_DIR
GPIO set pin direction
Address:
0x13
Type:
R/W
Reset:
0x00
Description:
GPIO set pin direction register.
Writing ‘0’ sets the corresponding GPIO to input state, and ‘1’ sets it to output state.
All bits are ‘0’ on reset.
GPIO_ED_STA
GPIO edge detect status
Address:
0x14
Type:
R/W
Reset:
0x00
Description:
GPIO edge detect status register. An edge transition has been detected.
GPIO_RE
Rising edge register
Address:
0x15
Type:
R/W
Reset:
0x00
Description:
GPIO rising edge register. Rising edge has been detected.
47/54
GPIO controller
STMPE811
GPIO_FE
Falling edge
Address:
0x16
Type:
R/W
Reset:
0x00
Description:
Falling edge has been detected.
GPIO_ALT_FUNCT
Alternate function register
Address:
0x17
Type:
R/W
Reset:
0x0F
Description:
Alternate function register. "‘0’ sets the corresponding GPIO to function as GPIO, and
‘1’ sets it to Touch Key Direct Output mode.
On power-up reset, all GPIOs are set as input.
Power supply
The STMPE811 GPIO operates from a separate supply pin (VIO). This dedicated supply pin
provides a level-shifting feature to the STMPE811. The GPIO remains valid until VIO is
removed.
The host system may choose to turn off Vcc supply while keeping VIO supplied. However it is
not allowed to turn off supply to VIO, while keeping the Vcc supplied.
The touchscreen is always powered by VIO. For better resolution and noise immunity, VIO
above 2.8 V is advised.
13.0.1
Power-up reset (POR)
The STMPE811 is equipped with an internal POR circuit that holds the device in reset state,
until the VIO supply input is valid. The internal POR is tied to the VIO supply pin.
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STMPE811
14
Maximum rating
Maximum rating
Stressing the device above the ratings listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only, and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 18.
Absolute maximum ratings
Symbol
Value
Unit
VCC
Supply voltage
4.5
V
VIO
GPIO supply voltage
4.5
V
ESD
ESD protection on each GPIO pin (air discharge)
8
kV
Operating temperature
-40 - 85
°C/W
Storage temperature
-65 - 155
°C/W
TBD
°C/W
T
TSTG
TJ
14.1
Parameter
Thermal resistance junction-ambient
Recommended operating conditions
Table 19.
Power consumption
Value
Symbol
VCC
Parameter
Test conditions
Core supply voltage
Unit
Min
Typ
Max
1.65
−
3.6
V
ICC max
Operating current
TSC running at 1 kHz
400
1000
μA
ICC
suspend
Operating current
No I2C/SPI/ADC activity
0.5
1
μA
49/54
Electrical specifications
15
STMPE811
Electrical specifications
Table 20.
DC electrical characteristics (-40 ° C to 85 ° C, all GPIOs comply to JEDEC
standard JESD-8-7)
Value
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
VIL
Input voltage low state
VCC =1.8 −3.3 V
-0.3 V
0.20 VIO
V
VIH
Input voltage high state
VCC =1.8 −3.3 V
0.80 VIO
VIO + 0.3 V
V
VOL
Output voltage low state
VCC =1.8 −3.3 V,
IOL = 8 mA
-0.3 V
0.15 VIO
V
VOH
Output voltage high state
VCC =1.8 −3.3 V
IOL = 8 mA
0.85 VIO
VOL
Output voltage low state
(I2C/SPI)
VCC =1.8 −3.3 V
IOL = 8 mA
-0.3 V
0.15 VCC
V
VOH
2
(I C/SPI)
VCC =1.8 −3.3 V
IOL = 8 mA
0.85 VCC
VCC +0.3V
v
Table 21.
Output voltage high state
V
AC electrical characteristics (-40 ° C to 85 ° C)
Value
Symbol
Parameter
Test condition
Unit
Min
CLKI2Cmax I2C maximum SCLK
CLKSPImax SPI maximum clock
50/54
Typ
Max
VCC = 1.8 - 3.3 V
400
KHz
VCC = 1.8 V
800
KHz
VCC = 3.3 V
1000
KHz
STMPE811
Electrical specifications
Table 22.
ADC specification (-40 ° C to 85 ° C)
Value
Parameter
Test condition
Unit
Min
Full-scale input span
Typ
0
Absolute input range
Max
Vref
V
VCC +0.2
V
Input capacitance
25
pF
Leakage current
0.1
μA
Resolution
12
Bits
No missing codes
11
Bits
Integral linearity error
±4
±6
Bits
Offset error
±5
±7
LSB
Gain error
±14
±18
LSB
70
μVrms
Power supply rejection ratio
50
dB
Throughput rate
180
ksps
Noise
Including internal Vref
Table 23.
Switch drivers specification
Value
Parameter
Test condition
Unit
Min
Typ
Max
ON resistance X+, Y+
5.5
Ω
ON resistance X-, Y-
7.3
Ω
Drive current
Table 24.
Duration 100 ms
50
mA
Voltage reference specification
Value
Parameter
Test condition
Internal reference voltage
Internal reference drift
Unit
Min
Typ
Max
2.45
2.50
2.55
V
25
Ppm/C
Internal reference ON
300
Ω
Internal reference OFF
1
GΩ
Output impedance
51/54
Package mechanical data
16
STMPE811
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 12. QFN16L (3 x 3 mm) package outline
E
E2
A
K
A1
e
D2
D
b
A3
K
L
r
1. Drawing not to scale.
Table 25.
QFN16 (3 x 3 mm) package mechanical data
millimeters
inches
Symbol
Min
Typ
Max
Min
Typ
Max
0.80
0.90
1.00
0.032
0.035
0.039
A1
0.02
0.05
0.001
0.002
A3
0.20
A
b
0.18
D
D2
52/54
0.30
0.007
3.00
1.55
E
E2
0.25
0.008
1.70
1.70
1.80
0.061
0.067
1.80
0.061
0.067
0.50
0.020
K
0.20
0.008
0.30
r
0.09
0.40
0.071
0.118
e
L
0.012
0.118
3.00
1.55
0.010
0.50
0.012
0.006
0.016
0.071
0.020
STMPE811
17
Revision history
Revision history
Table 26.
Document revision history
Date
Revision
09-June-2008
1
Changes
Initial release.
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STMPE811
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