STMICROELECTRONICS STMPE2401TBR

STMPE2401
24-bit Enhanced port expander with Keypad and PWM controller
Xpander logic
Features
■
24 GPIOs
■
Operating voltage 1.8V
■
Hardware key pad controller (8*12 matrix max)
■
3 PWM (8 bit) output for LED brightness control
and blinking
■
Interrupt output (open drain) pin
■
Configurable hotkey feature on each GPIO
■
Ultra-low Standby-mode current
■
Package TFBGA - 36 pins 3.6x3.6mm, pitch
0.5mm
TFBGA
Description
The STMPE2401 is a GPIO (General Purpose
Input / output) port expander able to interface a
Main Digital ASIC via the two-line bidirectional
bus (I2C); separate GPIO Expander IC is often
used in Mobile-Multimedia platforms to solve the
problems of the limited amounts of GPIOs usually
available on the Digital Engine.
The STMPE2401 offers great flexibility as each
I/Os is configurable as input, output or specific
functions; it's able to scan a keyboard, also
provides PWM outputs for brightness control in
backlight, rotator decoder interface and GPIO.
This device has been designed very low
quiescent current, and is including a wake up
feature for each I/O, to optimize the power
consumption of the IC.
Potential application of the STMPE2401 includes
portable media player, game console, mobile
phone, smart phone
Figure 1.
May 2007
Device summary
Part number
Package
Packaging
STMPE2401TBR
TFBGA36
Tape and reel
Rev 2
1/55
www.st.com
55
Contents
STMPE2401
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
4
5
2/55
2.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2
Pin assignment and TFBGA ball location . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3
GPIO Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Pin mapping to TFBGA ( bottom view, balls up) . . . . . . . . . . . . . . . . . . . . . 9
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2
I/O DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3
DC input specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4
DC output specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STMPE2401
6
7
8
Contents
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.4
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.5
Slave device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.6
Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.7
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
System controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1
Identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2
System control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.3
States of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clocking system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.1
9
10
Programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.1
Register map of interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.2
Interrupt control register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.3
Interrupt enable mask register (IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.4
Interrupt status register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.5
Interrupt enable GPIO mask register (IEGPIOR) . . . . . . . . . . . . . . . . . . . 25
9.6
Interrupt status GPIO register (ISGPIOR) . . . . . . . . . . . . . . . . . . . . . . . . 26
9.7
Programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
GPIO controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10.1
GPIO control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.2
GPIO alternate function register (GPAFR) . . . . . . . . . . . . . . . . . . . . . . . . 30
10.3
Hot key feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.3.1
Programming sequence for hot key . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.3.2
Minimum pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/55
Contents
11
STMPE2401
PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11.1
Registers in the PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11.2
PWM control and status register (PWMCS) . . . . . . . . . . . . . . . . . . . . . . . 35
11.3
PWM instruction channel x (PWMICx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
12
PWM commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
13
Keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
14
15
13.1
Registers in keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
13.2
KPC_col register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.3
KPC_row_msb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.4
KPC_row_lsb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13.5
KPC_ctrl_msb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13.6
KPC_ctrl_lsb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13.7
Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13.7.1
Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
13.7.2
Using the keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Rotator controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
14.1
Rotator_Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
14.2
Rotator_Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Miscellaneous features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
15.1
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
15.2
Under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
15.3
Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
16
Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4/55
STMPE2401
1
Block diagram
Block diagram
Figure 1.
Block diagram
5/55
Pin settings
STMPE2401
2
Pin settings
2.1
Pin connection
Figure 2.
Pin connection
TFBGA
2.2
Pin assignment and TFBGA ball location
Table 1. Pin assignment
6/55
Ball
Name
Type
C3
GND
-
Name and function
C2
KP_X0
IO
C1
Reset_N
I
B1
KP_X1
IO
GPIO
A1
KP_X2
IO
GPIO
B2
KP_X3
IO
GPIO
A2
KP_X4
IO
GPIO
B3
KP_X5
IO
GPIO
A3
KP_X6
IO
GPIO
C4
GND
-
A4
VCC1
-
GPIO
External reset input, active LOW
1.8V Input
STMPE2401
Pin settings
Table 1. Pin assignment
Ball
Name
Type
Name and function
B3
KP_X7
IO
GPIO
A5
KP_Y5
IO
GPIO
A6
KP_Y4
IO
GPIO
B5
KP_Y3
IO
GPIO
B6
KP_Y2
IO
GPIO
C5
KP_Y1
IO
GPIO
C6
KP_Y0
IO
GPIO
D3
GND
-
D6
ADDR0
IO
D5
KP_Y9
A/IO
GPIO
E6
KP_Y10
A/IO
GPIO
F6
KP_Y11
A/IO
GPIO
E5
PWM3
A/IO
GPIO and I2C ADDR 1 (in reset)
F5
PWM2
A/IO
GPIO
E4
PWM1
A/IO
GPIO
F4
VCC2
-
D4
GND
-
F3
INT
O
Open drain interrupt output pin
E3
KP_Y8
IO
GPIO
F2
KP_Y7
IO
GPIO
F1
KP_Y6
IO
GPIO
E2
SDATA
A
I2C DATA
E1
SCLK
A
I2C Clock
D2
XTALIN
A
XTAL Oscillator or External 32KHz input
D1
XTALOUT
A
XTAL Oscillator
GPIO and I2C ADDR 0 (in reset)
1.8V Input
7/55
Pin settings
2.3
STMPE2401
GPIO Pin functions
Table 2. GPIO Pin functions
8/55
Primary
Alternate Function 1 Alternate Function 2 Alternate Function 3
Function
Pin N°
Name
2
KP_X0
GPIO 0
Keypad input 0
4
KP_X1
GPIO 1
Keypad input 1
5
KP_X2
GPIO 2
Keypad input 2
6
KP_X3
GPIO 3
Keypad input 3
7
KP_X4
GPIO 4
Keypad input 4
8
KP_X5
GPIO 5
Keypad input 5
9
KP_X6
GPIO 6
Keypad input 6
12
KP_X7
GPIO 7
Keypad input 7
13
KP_Y5
GPIO 13
Keypad output 5
14
KP_Y4
GPIO 12
Keypad output 4
15
KP_Y3
GPIO 11
Keypad output 3
16
KP_Y2
GPIO 10
Keypad output 2
17
KP_Y1
GPIO 9
Keypad output 1
18
KP_Y0
GPIO 8
Keypad output 0
20
ADDR0
GPIO 15
21
KP_Y9
GPIO 18
Keypad output 9
Rotator 0
22
KP_Y10
GPIO 19
Keypad output 10
Rotator 1
23
KP_Y11
GPIO 20
Keypad output 11
Rotator 2
24
PWM3
GPIO 23
Channel 3
25
PWM2
GPIO 22
Channel 2
26
PWM1
GPIO 21
Channel 1
30
KP_Y8
GPIO 17
Keypad output 8
31
KP_Y7
GPIO 16
Keypad output 7
32
KP_Y6
GPIO 14
Keypad output 6
ClkOut
STMPE2401
2.4
Pin settings
Pin mapping to TFBGA ( bottom view, balls up)
Table 3. Pin mapping to TFBGA
A
B
C
D
E
F
1
KP-X2
KP-X1
Reset_N
XTALOUT
SCLK
KP-Y6
2
KP-X4
KP-X3
KP-X0
XTALIN
SDATA
KP-Y7
3
KP-X6
KP-X5
GND
GND
KP-Y8
INT
4
VCC
KP-X7
GND
GND
PWM-1
VCC
5
KP-Y5
KP-Y3
KP-Y1
KP-Y9
PWM-3
PWM-2
6
KP-Y4
KP-Y2
KP-Y0
ADDR0
KP-Y10
KP-Y11
9/55
Maximum rating
3
STMPE2401
Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
3.1
Absolute maximum rating
Table 4. Absolute maximum rating
Symbol
Value
Unit
VCC
Supply voltage
2.5
V
VIN
Input voltage on GPIO pin
2.5
V
VI2C
Input voltage on I2C pin
(SDATA,SCLK, INT)
4.5
V
2
KV
VESD (HBM)
3.2
Parameter
ESD protection on each GPIO pin
Thermal data
Table 5. Thermal data
Symbol
RthJA
10/55
Parameter
Min
Thermal resistance junction-ambient
Typ
Max
100
Unit
°C/W
TA
Operating ambient temperature
-40
25
85
°C
TJ
Operating junction temperature
-40
25
125
°C
STMPE2401
Electrical specification
4
Electrical specification
4.1
DC electrical characteristics
Table 6. DC electrical characteristics
Value
Symbol
4.2
Parameter
Test conditions
Unit
Min.
Typ.
Max.
1.65
1.8
1.95
V
VCC1,2
1.8V supply voltage
IHIBERNATE
HIBERNATE mode
current
6
12
uA
ISLEEP
SLEEP mode current
15
50
uA
Icc
Operating current
(FSM working – No
peripheral activity)
0.5
1.0
mA
IO_INT
Open drain output
current
V_INT
Voltage level at INT pin
4
mA
3.6
V
I/O DC electrical characteristics
The 1.8V I/O complies to the EIA/JEDEC standard JESD8-7.
Table 7. I/O DC electrical characteristic
Value
Symbol
Parameter
Unit
Min.
Vil
Vih
Vhyst
4.3
Typ.
Low level input voltage
Max.
0.35*Vcc
= 0.63
High level input voltage
0.65*Vcc
= 1.17
Schmitt trigger hysteresis
V
V
0.10
V
DC input specification
(1.55V < VDD < 1.95V)
Table 8. DC input specification
Value
Symbol
Parameter
Test conditions
Unit
Min.
Vol
Low level output voltage
Iol = 4mA
Voh
High level output voltage
Ioh = 4mA
Typ.
Max.
0.45
Vcc - 0.45
= 1.35
V
V
11/55
Electrical specification
4.4
STMPE2401
DC output specification
(1.55V < vdd < 1.95V)
Table 9. DC output specification
Symbol
Parameter
Test
conditions
Value
Unit
Min.
Typ.
Max.
Ipu
Pull-up current
Vi = 0V
15
35
65
µA
Ipd
Pull-down current
Vi = vdd
14
35
60
µA
Rup
Equivalent pull-up resistance
Vi = 0V
30
50
103.3
KΩ
Rpd
Equivalent pull-down resistance
Vi = vdd
32.5
50
110.7
KΩ
Note:
Pull-up and Pull-down characteristics
4.5
AC characteristics
Table 10. AC characteristics
Value
Symbol
Parameter
Unit
Min.
12/55
FO
Frequency
CL
Load capacitance
16
Typ.
Max.
32
kHz
27
pF
STMPE2401
5
Register map
Register map
All registers have the size of 8-bit. Some of the registers are composed of 2-byte to form 16bit registers. For each of the module, their registers are residing within the given address
range.
Table 11. Register map
Address
Module registers
Description
Auto-Increment
(during read/write)
0x00 – 0x07
0x80 – 0x81
Clock and Power
Manager module
Clock and Power Manager register
range.
Yes
0x10 – 0x1F
Interrupt Controller
module
Interrupt Controller register range
Yes
0x30 – 0x37
PWM Controller Module PWM Controller register range
Yes
0x38 – 0x3F
PWM Controller register range
No
Keypad Controller register range
Yes
Keypad Controller register range
No
Rotator Controller register range
Yes
0x60 – 0x67
Keypad Controller
Module
0x68 – 0x6F
0x70 – 0x77
Rotator Controller
Module
0x82 – 0xBF
GPIO Controller Module GPIO Controller register range
Yes
13/55
I2C Interface
6
STMPE2401
I2C Interface
The features that are supported by the I2C interface are as below:
●
I2C Slave device
●
SDAT and SCLK operates from 1.8V to 3.3V
●
Compliant to Philip I2C specification version 2.1
●
Supports Standard (up to 100kbps) and Fast (up to 400kbps) modes.
●
7-bit device addressing mode
●
General Call
●
Start/Restart/Stop
●
Address up to 4 STMPE2401 devices via I2C
The address is selected by the state of two pins. The state of the pins will be read upon
reset and then the pins can be configured for normal operation. The pins will have a pull-up
or down to set the address. The I2C interface module allows the connected host system to
access the registers in the STMPE2401.
6.1
Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.
A Start condition must precede any data/command transfer. The device continuously
monitors for a Start condition and will not respond to any transaction unless one is
encountered.
6.2
Stop condition
A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state.
A Stop condition terminates communication between the slave device and bus master. A
read command that is followed by NoAck can be followed by a Stop condition to force the
slave device into idle mode. When the slave device is in idle mode, it is ready to receive the
next I2C transaction. A Stop condition at the end of a write command stops the write
operation to registers.
6.3
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls
the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave
the SDATA in high state if it would to not acknowledge the receipt of the data.
14/55
STMPE2401
6.4
I2C Interface
Data input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA
signal must be stable during the rising edge of SCLK and the SDATA signal must change
only when SCLK is driven low.
6.5
Slave device address
The slave device address is a 7 address, where the least significant 2-bit are programmable.
These 2-bit values will be loaded in once upon reset and after that these 2 pins no longer be
needed with the exception during General Call. Up to 4 STMPE2401 devices can be
connected on a single I2C bus.
Table 12. Slave device address
6.6
ADDR 1
ADDR 0
Address
0
0
0x84
0
1
0x86
1
0
0x88
1
1
0x8A
Memory addressing
For the bus master to communicate to the slave device, the bus master must initiate a Start
condition and followed by the slave device address. Accompanying the slave device
address, there is a Read/Write bit (R/W). The bit is set to 1 for Read and 0 for Write
operation.
If a match occurs on the slave device address, the corresponding device gives an
acknowledgement on the SDA during the 9th bit time. If there is no match, it deselects itself
from the bus by not responding to the transaction.
15/55
I2C Interface
6.7
STMPE2401
Operation modes
Table 13. Operating modes
Mode Bytes
Programming sequence
START, Device Address, R/W = 0, Register Address to be read
RESTART, Device Address, R/W = 1, Data Read, STOP
Read
≥1
If no STOP is issued, the Data Read can be continuously preformed. If the register
address falls within the range that allows address auto-increment, then register
address auto-increments internally after every byte of data being read. For register
address that falls within a non-incremental address range, the address will be kept
static throughout the entire read operations. Refer to the Memory Map table for the
address ranges that are auto and non-increment. An example of such a nonincrement address is FIFO.
START, Device Address, R/W=0, Register Address to be written, Data Write, STOP
Write
Figure 3.
16/55
≥1
If no STOP is issued, the Data Write can be continuously performed. If the register
address falls within the range that allows address auto-increment, then register
address auto-increments internally after every byte of data being written in. For
register address that falls within a non-incremental address range, the address will
be kept static throughout the entire write operations. Refer to the Memory Map table
for the address ranges that are auto and non-increment. An example of a nonincrement address is Data Port for initializing the PWM commands.
Master/slave operation modes
STMPE2401
I2C Interface
Figure 4.
I2C timing
Table 14. I2C address
Symbol
Parameter
Min
Typ
Max
Unit
400
kHz
fSCL
SCL clock frequency
tLOW
Clock low period
1.3
µs
tHIGH
Clock high period
600
ns
tF
0
SDA and SCL fall time
300
ns
tHD:STA
START condition hold time
(After this period the first clock is generated)
600
ns
tSU:STA
START condition setup time
(Only relevant for a repeated start period)
600
ns
tSU:DAT
Data setup time
100
ns
tHD:DAT
Data hold time
0
µs
tSU:STO
STOP condition setup time
600
ns
Time the bust must be free before a new
trasmission can start
1.3
µs
tBUF
17/55
System controller
7
STMPE2401
System controller
The system controller is the heart of the STMPE2401. It contains the registers for power
control, and the registers for chip identification.
The system registers are:
Table 15. System controller
7.1
Address
Register_Name
0x00
Reserved (Reads 0x00)
0x01
Reserved (Reads 0x00)
0x80
CHIP_ID
0x81
VERSION_ID
0x82
Reserved (Reads 0x00)
0x02
SYSCON
Identification register
Table 16. CHIP_ID
Bit
7
6
5
4
3
2
1
0
8-bit LSB of Chip ID
Read/Write(IIC)
R
R
R
R
R
R
R
R
Reset Value
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
Table 17. VERSION_ID
Bit
8-bit Version ID
18/55
Read/Write(IIC)
R
R
R
R
R
R
R
R
Reset Value
0
0
0
0
0
0
0
1
STMPE2401
7.2
System controller
System control register
Table 18. System control register
Bit
7
6
Soft_Reset
-
5
4
3
2
1
0
Disable_32KHz Sleep Enable_GPIO Enable_PWM Enable_KPC Enable_ROT
Read/Writ
e (IIC)
W
RW
RW
RW
RW
RW
RW
Read/Writ
e(HW)
RW
R
RW
R
R
R
R
Reset
Value
0
0
0
1
1
1
1
Table 19. System control register writing
Bits
Name
Description
0
Enable_ROT
Writing a ‘0’ to this bit will gate off the clock to the Rotator module, thus stopping
its operation
1
Enable_KPC
Writing a ‘0’ to this bit will gate off the clock to the Keypad Controller module,
thus stopping its operation
2
Enable_PWM
Writing a ‘0’ to this bit will gate off the clock to the PWM module, thus stopping
its operation
3
Enable_GPIO
Writing a ‘0’ to this bit will gate off the clock to the GPIO module, thus stopping
its operation
4
Sleep
Writing a ‘1’ to this bit will put the device in sleep mode. When in sleep mode, all
the units which need to work on clocks synchronous to 32KHz will get the clocks
derived from the 32K domain. The RC Oscillator will be shut off.
5
Disable_32KHz
6
-
7
Soft_Reset
Set this bit to disable the 32KHz OSC, thus putting the device in hibernate
mode. Only a Reset or a wakeup on IIC will reset this bit
Writing a ‘1’ to this bit will do a soft reset of the device. Once the reset is done,
this bit will be cleared to ‘0’ by the HW.
19/55
System controller
7.3
STMPE2401
States of operation
The device has three main modes of operation:
Caution:
●
Operational Mode: This is the mode, whereby normal operation of the device takes
place. In this mode, the RC clock is available and the Main FSM Unit routes this clock
and the 32 KHz clock to all the device blocks that are enabled. In this mode, individual
blocks that need not be working can be turned off by the master by programming the
bits 3 to 0 of the SYSCON register.
●
Sleep Mode: In this low-power mode, the RC Oscillator is powered down. All the blocks
which need clocks derived from the 32KHz clock will continue getting a 32KHz clock. In
this mode also, individual blocks can be turned off by the master by programming the
bits 3 to 0 of the SYSCON register. However, the master needs to program the
SYSCON register before coming into this mode, as in the sleep mode, the IIC interface
is not active except to detect traffic for wakeup. Any activity on the I2C port or Wakeup
pin or Hotkey activity will cause the device to leave this mode and go into the
Operational mode. When leaving this mode, the I2C will need to hold the SCLK till the
RC clock is ready.
●
Hibernate Mode: This mode is entered when the system writes a ‘1’ to bit 5 of the
SYSCON register. In this mode, the device is completely inactive as there is absolutely
no clock. Only a Reset or a wakeup on IIC will bring back the System to operational
mode. All I2C activities are ignored.
Hotkey detection is not possible in hibernate mode.
Figure 5.
20/55
State of operation
STMPE2401
8
Clocking system
Clocking system
Figure 6.
Clocking system
The decision on clocks is based on the bits written into SYSCON registers. Bits 0 to 4 of the
SYSCON register control the gating of clocks to the Rotator, Keypad Controller, PWM and
GPIO respectively in the operational mode. When in sleep mode, the operating clock is cut
off from every functional blocks (including the I2C) except Keypad Controller and GPIO.
8.1
Programming sequence
To put the device in sleep mode, the following needs to be done by the host:
1.
Write a ‘1’ to bit 4 of the SYSCON register.
2.
To wakeup the device, the following needs to be done by the host:
3.
Assert a wakeup routine on the I2C bus by sending the Start Bit, followed by the device
address and the R/W bit.
4.
If there’s a NOACK, keep sending the wakeup routine till there is an ACK from the
slave.
5.
To do a soft reset to the device, the host needs to do the following:
6.
Write a ‘1’ to bit 7 of the SYSCON register.
7.
This bit is automatically cleared upon reset.
8.
To go into Hibernate mode, the following needs to be done by the host:
9.
Set the Disable_32K bit to ‘1’
10. To come out of the Hibernate mode, the following needs to be done by the host:
11. Assert a system reset or
12. Put a wakeup on the I2C
21/55
Interrupt system
9
STMPE2401
Interrupt system
STMPE2401 uses a highly flexible interrupt system. It allows host system to configure the
type of system events that should result in an interrupt, and pinpoints the source of interrupt
by status register. The INT pin could be configured as ACTIVE HIGH, or ACTIVE LOW.
32KHz clock input or crystal must be available for the interrupt system to be functional.
INT pin is 3.3V tolernat.
Once asserted, the INT pin would de-assert only if the corresponding bit in the
InterruptStatus register is cleared.
Figure 7.
9.1
Interrupt system
Register map of interrupt system
Table 20. Register map of interrupt system
Address
Register Name
0x10
ICR_msb
Description
Auto-Increment
(during sequential R/W)
Yes
Interrupt Control Register
0x11
ICR_lsb
0x12
IER_msb
Yes
Yes
Interrupt Enable Mask Register
0x13
IER_lsb
0x14
ISR_msb
Yes
Yes
Interrupt Status Register
22/55
0x15
ISR_lsb
0x16
IEGPIOR_msb
Yes
Yes
Interrupt Enable GPIO Mask
Register
0x17
IEGPIOR_mid
0x18
IEGPIOR_lsb
Yes
0x19
IEGPIOR_msb
Yes
0x1A
ISGPIOR_mid
0x1B
ISGPIOR_lsb
Interrupt Status GPIO Register
Yes
Yes
Yes
STMPE2401
9.2
Interrupt system
Interrupt control register (ICR)
ICR register is used to configure the Interrupt Controller. It has a global enable interrupt
mask bit that controls the interruption to the host.
ICR_msb
Bit
15
14
13
12
ICR_lsb
11
10
9
8
7
6
5
4
3
Reserved
2
1
0
IC2
IC1
IC0
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
RW
RW
RW
Reset
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 21. ICR
9.3
Bits
Name
Description
0
IC[0]
Global Interrupt Mask bit
When this bit is written a ‘1’, it will allow interruption to the host. If it is written
with a ‘0’, then, it disables all interruption to the host. Writing to this bit does not
affect the IER value.
1
IC[1]
output Interrupt Type
‘0’ = Level interrupt
‘1’ = Edge interrupt
2
IC[2]
output Interrupt Polarity
‘0’ = Active Low / Falling Edge
‘1’ = Active High / Rising Edge
Interrupt enable mask register (IER)
IER register is used to enable the interruption from a particular interrupt source to the host.
IER_msb
Bit
15
14
13
12
11
IER_lsb
10
9
Reserved
8
7
6
5
4
3
2
1
0
IE8
IE7
IE6
IE5
IE4
IE3
IE2
IE1
IE0
R/W
R
R
R
R
R
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
23/55
Interrupt system
STMPE2401
Table 22. IER
9.4
Bits
Name
8:0
IE[x]
Description
Interrupt Enable Mask (where x = 8 to 0)
IE0 = Wake-up Interrupt Mask
IE1 = Keypad Controller Interrupt Mask
IE2 = Keypad Controller FIFO Overflow Interrupt Mask
IE3 = Rotator Controller Interrupt Mask
IE4 = Rotator Controller Buffer Overflow Interrupt Mask
IE5 = PWM Channel 0 Interrupt Mask
IE6 = PWM Channel 1 Interrupt Mask
IE7 = PWM Channel 2 Interrupt Mask
IE8 = GPIO Controller Interrupt Mask
Writing a ‘1’ to the IE[x] bit will enable the interruption to the host.
Interrupt status register (ISR)
ISR register monitors the status of the interruption from a particular interrupt source to the
host. Regardless whether the IER bits are enabled or not, the ISR bits are still updated.
ISR_msb
Bit
15
14
13
12
11
ISR_lsb
10
9
Reserved
8
7
6
5
4
3
2
1
0
IS8
IS7
IS6
IS5
IS4
IS3
IS2
IS1
IS0
R/W
R
R
R
R
R
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 23. ISR
24/55
Bits
Name
8:0
IS[x]
Description
Interrupt Status (where x = 8 to 0)
Read:
IS0 = Wake-up Interrupt Status
IS1 = Keypad Controller Interrupt Status
IS2 = Keypad Controller FIFO Overflow Interrupt Status
IS3 = Rotator Controller Interrupt Status
IS4 = Rotator Controller Buffer Overflow Interrupt Status
IS5 = PWM Channel 0 Interrupt Status
IS6 = PWM Channel 1 Interrupt Status
IS7= PWM Channel 2 Interrupt Status
IS8 = GPIO Controller Interrupt Status
Write:
A write to a IS[x] bit with a value of ‘1’ will clear the interrupt and a write with a
value of ‘0’ has no effect on the IS[x] bit.
STMPE2401
9.5
Interrupt system
Interrupt enable GPIO mask register (IEGPIOR)
IEGPIOR register is used to enable the interruption from a particular GPIO interrupt source
to the host. The IEG[15:0] bits are the interrupt enable mask bits correspond to the
GPIO[15:0] pins.
IEGPIOR_msb
Bit
23
22
21
20
19
18
17
16
IEG IEG IEG IEG IEG IEG IEG IEG
23 22 21 20 19 18 17 16
R/W
RW RW RW RW RW RW RW RW
Reset
Value
0
0
0
0
0
0
0
0
2
1
0
IEGPIOR _lsb
Bit
15
14
13
12
11
10
IEG
15
IEG
14
IEG
13
IEG
12
IEG
11
IEG IEG IEG IEG IEG IEG IEG IEG IEG IEG IEG
10
9
8
7
6
5
4
3
2
1
0
R/W
RW
RW
RW
RW
RW
RW RW RW RW RW RW RW RW RW RW RW
Reset
Value
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
0
0
0
Table 24. GPIO
Bits
Name
23:0
IEG[x]
Description
Interrupt Enable GPIO Mask (where x = 23 to 0)
Writing a ‘1’ to the IE[x] bit will enable the interruption to the host.
25/55
Interrupt system
9.6
STMPE2401
Interrupt status GPIO register (ISGPIOR)
ISGPIOR register monitors the status of the interruption from a particular GPIO pin interrupt
source to the host. Regardless whether the IEGPIOR bits are enabled or not, the ISGPIOR
bits are still updated. The ISG[15:0] bits are the interrupt status bits correspond to the
GPIO[15:0] pins.
ISGPIOR _lsb
Bit
23
22
21
20
19
18
17
16
IEG IEG IEG IEG IEG IEG IEG IEG
23 22 21 20 19 18 17 16
R/W
RW RW RW RW RW RW RW RW
Reset
Value
0
0
0
ISGPIOR_msb
Bit
0
0
0
0
0
2
1
0
ISGPIOR _lsb
15
14
13
12
11
10
ISG
15
ISG
14
ISG
13
ISG
12
ISG
11
ISG ISG ISG ISG ISG ISG ISG ISG ISG ISG ISG
10
9
8
7
6
5
4
3
2
1
0
R/W
RW
RW
RW
RW
RW
RW RW RW RW RW RW RW RW RW RW RW
Reset
Value
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
0
0
0
Table 25. GPIO
26/55
Bits
Name
Description
23:0
ISG[x] Interrupt Status GPIO (where x = 23 to 0)
Read:
Interrupt Status of the GPIO[x].
Write:
A write to a ISG[x] bit with a value of ‘1’ will clear the interrupt and a write with a
value of ‘0’ has no effect on the ISG[x] bit.
STMPE2401
9.7
Interrupt system
Programming sequence
To configure and initialize the Interrupt Controller to allow interruption to host, observe the
following steps:
●
Set the IER and IEGPIOR registers to the desired values to enable the interrupt
sources that are to be expected to receive from.
●
Configure the output interrupt type and polarity and enable the global interrupt mask by
writing to the ICR.
●
Wait for interrupt.
●
Upon receiving an interrupt, the INT pin is asserted.
●
The host comes to read the ISR through I2C interface. A ‘1’ in the ISR bits indicates
that the corresponding interrupt source is triggered.
●
If the IS8 bit in ISR is set, the interrupt is coming from the GPIO Controller. Then, a
subsequent read is performed on the ISGPIOR to obtain the interrupt status of all 16
GPIOs to locate the GPIO that triggers the interrupt. This is a feature so-called ‘Hot
Key’.
●
After obtaining the interrupt source that triggers the interrupt, the host performs the
necessary processing and operations related to the interrupt source.
●
If the interrupt source is from the GPIO Controller, two write operations with value of ‘1’
are performed to the ISG[x] bit (ISGPIOR) and the IS[8] (ISR) to clear the
corresponding GPIO interrupt.
●
If the interrupt source is from other module, a write operation with value of ‘1’ is
performed to the IS[x] (ISR) to clear the corresponding interrupt.
●
Once the interrupt is being cleared, the INT pin will also be de-asserted if the interrupt
type is level interrupt. An edge interrupt will only assert a pulse width of 250ns.
●
When the interrupt is no longer required, the IC0 bit in ICR may be set to ‘0’ to disable
the global interrupt mask bit.
27/55
GPIO controller
10
STMPE2401
GPIO controller
A total of 24 GPIOs are available in the STMPE2401 port expander IC. Most of the GPIOs
are sharing physical pins with some alternate functions. The GPIO controller contains the
registers that allow the host system to configure each of the pins into either a GPIO, or one
of the alternate functions. Unused GPIOs should be configured as outputs to minimize the
power consumption.
Table 26. GPIO controller
Address
28/55
Register name
Description
Auto-Increment
(during sequential R/W)
0xA2
GPMR_msb
Yes
0xA3
GPMR_csb
0xA4
GPMR_lsb
Yes
0x83
GPSR_msb
Yes
0x84
GPSR_csb
0x85
GPSR_lsb
Yes
0x86
GPCR_msb
Yes
0x87
GPCR_csb
0x88
GPCR_lsb
Yes
0x89
GPDR_msb
Yes
0x8A
GPDR_csb
0x8B
GPDR_lsb
Yes
0x8C
GPEDR_msb
Yes
0x8D
GPEDR_csb
0x8E
GPEDR_lsb
Yes
0x8F
GPRER_msb
Yes
0x90
GPRER_csb
0x91
GPRER_lsb
Yes
0x92
GPFER_msb
Yes
0x93
GPFER_csb
0x94
GPFER_lsb
Yes
0x95
GPPUR_msb
Yes
0x96
GPPUR_csb
0x97
GPPUR_lsb
Yes
0x98
GPPDR_msb
Yes
0x99
GPPDR_csb
0x9A
GPPDR_lsb
GPIO Monitor Pin State Register
GPIO Set Pin State Register
GPIO Clear Pin State Register
GPIO Set Pin Direction Register
GPIO Edge Detect Status Register
GPIO Rising Edge Register
GPIO Falling Edge Register
GPIO Pull Up Register
GPIO Pull Down Register
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
STMPE2401
GPIO controller
Table 26. GPIO controller
Address
Register name
0x9B
GPAFR_U_msb
0x9C
GPAFR_U_csb
0x9D
GPAFR_U_lsb
0x9E
GPAFR_L_msb
0x9F
GPAFR_L_csb
0xA0
GPAFR_L_lsb
0xA5 – 0xAF RESERVED
10.1
Auto-Increment
(during sequential R/W)
Description
Yes
GPIO Alternate Function Register
(Upper Bit)
Yes
Yes
Yes
GPIO Alternate Function Register
(Lower Bit)
Yes
Yes
Reserved
Yes
GPIO control registers
A group of registers are used to control the exact function of each of the 24 GPIO. All GPIO
registers are named as GPxxx_yyy, where
Xxx represents the functional group
Yyy represents the byte position of the GPIO
Lsb registers controls GPIO[7:0]
Csb registers controls GPIO[15:8]
Msb registers controls GPIO[23:16]
Table 27. Register
Note:
Bit
7
6
5
4
3
2
1
0
GPxxx_msb
IO-23
IO-22
IO-21
IO-20
IO-19
IO-18
IO-17
IO-16
GPxxx_csb
IO-15
IO-14
IO-13
IO-12
IO-11
IO-10
IO-9
IO-8
GPxxx_lsb
IO-7
IO-6
IO-5
IO-4
IO-3
IO-2
IO-1
IO-0
This convention does not apply to the GPIO Alternate Function Registers
The function of each bit is shown in the following table:
Table 28. Bit’s function
Register name
Function
GPIO Monitor Pin State
Reading this bit yields the current state of the bit. Writing has no effect.
GPIO Set Pin State
Writing ‘1’ to this bit causes the corresponding GPIO to go to ‘1’ state.
Writing ‘0’ has no effect.
GPIO Clear Pin State
Writing ‘1’ to this bit causes the corresponding GPIO to go to ‘0’ state.
Writing ‘0’ has no effect.
GPIO Set Pin Direction
‘0’ sets the corresponding GPIO to input state, and ‘1’ sets it to output
state
29/55
GPIO controller
STMPE2401
Table 28. Bit’s function
Register name
10.2
Function
GPIO Edge Detect Status
Set to ‘1’ by hardware when there is a rising/falling edge on the corresponding GPIO. Writing ‘1’ clears the bit. Writing ‘0’ has no effect.
GPIO Rising Edge
Set to ‘1’ to enable rising edge detection on the corresponding GPIO.
GPIO Falling Edge
Set to ‘1’ to enable falling edge detection on the corresponding GPIO.
GPIO Pull Up
Set to ‘1’ to enable internal pull-up resistor
GPIO Pull Down
Set to ‘1’ to enable internal pull-down resistor
GPIO alternate function register (GPAFR)
GPAFR is to select the functionality of the GPIO pin. To select a function for a GPIO pin, a
bit-pair in the register (GPAFR_U or GPAFR_L) has to be set.
GPAFR_U_msb
Bit
23
22
21
AF23
20
19
AF22
18
17
AF21
16
AF20
R/W
RW
RW
RW
RW
RW
RW
RW
RW
Reset
Value
0
0
0
0
0
0
0
0
10
9
8
GPAFR_U_csb
Bit
15
14
13
AF19
12
11
AF18
AF17
AF16
R/W
RW
RW
RW
RW
RW
RW
RW
RW
Reset
Value
0
0
0
0
0
0
0
0
2
1
0
GPAFR_U_lsb
Bit
7
6
5
AF15
30/55
4
3
AF14
AF13
AF12
R/W
RW
RW
RW
RW
RW
RW
RW
RW
Reset
Value
0
0
0
0
0
0
0
0
STMPE2401
GPIO controller
Table 29. Bit description
Bits
Name
23:0
AF[x]
Description
GPIO Pin ‘x’ Alternate Function Select (where x = 23 to 12).
‘00’ – The corresponding GPIO pin (GPIO[x]) is configured to Primary
Function.
‘01’ – The corresponding GPIO pin (GPIO[x]) is configured to Alternate
Function 1.
‘10’ – The corresponding GPIO pin (GPIO[x]) is configured to Alternate
Function 2.
‘11’ – The corresponding GPIO pin (GPIO[x]) is configured to Alternate
Function 3.
GPAFR_L_msb
Bit
23
22
21
AF11
20
19
AF10
18
17
AF9
16
AF8
R/W
RW
RW
RW
RW
RW
RW
RW
RW
Reset
Value
0
0
0
0
0
0
0
0
10
9
8
GPAFR_L_csb
Bit
15
14
13
AF7
12
11
AF6
AF5
AF4
R/W
RW
RW
RW
RW
RW
RW
RW
RW
Reset
Value
0
0
0
0
0
0
0
0
2
1
0
GPAFR_L_lsb
Bit
7
6
5
AF3
4
3
AF2
AF1
AF0
R/W
RW
RW
RW
RW
RW
RW
RW
RW
Reset
Value
0
0
0
0
0
0
0
0
31/55
GPIO controller
STMPE2401
Table 30. Bit description
10.3
Bits
Name
23:0
AF[x]
Description
GPIO Pin ‘x’ Alternate Function Select (where x = 11 to 0).
‘00’ – The corresponding GPIO pin (GPIO[x]) is configured to Primary
Function.
‘01’ – The corresponding GPIO pin (GPIO[x]) is configured to Alternate
Function 1.
‘10’ – The corresponding GPIO pin (GPIO[x]) is configured to Alternate
Function 2.
‘11’ – The corresponding GPIO pin (GPIO[x]) is configured to Alternate
Function 3.
Hot key feature
A GPIO is known as ‘Hot Key’ when it is configured to trigger an interruption to the host
whenever the GPIO input is being asserted. This feature is applicable in Operational mode
(RC clock is present) as well as Sleep mode (32kHz clock is present).
10.3.1
Programming sequence for hot key
1.
Configures the GPIO pin into GPIO mode by setting the corresponding bits in the
GPAFR.
2.
Configures the GPIO pin into input direction by setting the corresponding bit in GPDR.
3.
Set the GPRER and GPFER to the desired values to enable the rising edge or falling
edge detection.
4.
Configures and enables the interrupt controller to allow the interruption to the host.
5.
Now, the GPIO Expander may be put into Sleep mode if it is desired.
6.
Upon any Hot Key being asserted, the device will wake-up and issue an interrupt to the
host.
Below are the conditions to be fulfilled in order to configure a Hot Key:
10.3.2
1.
The pin is configured into GPIO mode and as input pin.
2.
The global interrupt mask bit is enabled.
3.
The corresponding GPIO interrupt mask bit is enabled.
Minimum pulse width
The minimum pulse width of the assertion of the Hot Key must be at least 62.5us. Any pulse
width less than the stated value may not be registered.
32/55
STMPE2401
11
PWM controller
PWM controller
The STMPE2401 PWM controller provides 3 independent PWM outputs used to generate
light effect; if the PWM outputs are not used, these pins can be used as GPIO.
Figure 8.
PWM controller
Instructions are downloaded into the memory via the I2C connection.
33/55
PWM controller
11.1
STMPE2401
Registers in the PWM controller
The main system registers are:
Table 31. Main system registers
Register Name
0x30
PWMCS
PWM Control and Status register
Yes
PWMIC0
PWM instructions are initialized through this
data port. Every instruction is 16-bit width and
therefore, the MSB of the first word is written
first, then, followed by LSB of the first word.
Subsequently, MSB of second word and LSB
of second word and so on.
No
PWMIC1
PWM instructions are initialized through this
data port. Every instruction is 16-bit width and
therefore, the MSB of the first word is written
first, then, followed by LSB of the first word.
Subsequently, MSB of second word and LSB
of second word and so on.
No
PWMIC2
PWM instructions are initialized through this
data port. Every instruction is 16-bit width and
therefore, the MSB of the first word is written
first, then, followed by LSB of the first word.
Subsequently, MSB of second word and LSB
of second word and so on.
No
0x38
0x39
0x3A
34/55
Description
Auto-Increment
(during
Read/Write)
Address
STMPE2401
11.2
PWM controller
PWM control and status register (PWMCS)
Bit
7
6
Reserved
5
4
3
2
1
0
II2
II1
II0
EN2
EN1
EN0
Read/Write
R
R
R
R
R
RW
RW
RW
Reset Value
0
0
0
0
0
0
0
0
Table 32. Bit description
Bits
Name
Description
0
EN0
PWM Channel 0 Enable bit.
‘1’ – Enable the PWM Channel 0
‘0’ – Reset the PWM Channel 0. Only when the PWM channel is in reset
state, the stream of commands can be written into its data port, which in
this case is PWM_Command_Channel_0.
1
EN1
PWM Channel 1 Enable bit.
‘1’ – Enable the PWM Channel 1
‘0’ – Reset the PWM Channel 1. Only when the PWM channel is in reset
state, the stream of commands can be written into its data port, which in
this case is PWM_Command_Channel_1.
2
EN2
PWM Channel 2 Enable bit.
‘1’ – Enable the PWM Channel 2
‘0’ – Reset the PWM Channel 2. Only when the PWM channel is in reset
state, the stream of commands can be written into its data port, which in
this case is PWM_Command_Channel_2.
3
II0
PWM Invalid Instruction Status bit for PWM Channel 0
‘0’ – No invalid command encountered during the instruction execution.
‘1’ – Invalid command encountered and this puts the PWM Channel 0 into
reset state.
4
II1
PWM Invalid Instruction Status bit for PWM Channel 1
‘0’ – No invalid command encountered during the instruction execution.
‘1’ – Invalid command encountered and this puts the PWM Channel 1 into
reset state.
5
II2
PWM Invalid Instruction Status bit for PWM Channel 2
‘0’ – No invalid command encountered during the instruction execution.
‘1’ – Invalid command encountered and this puts the PWM Channel 2 into
reset state.
35/55
PWM controller
11.3
STMPE2401
PWM instruction channel x (PWMICx)
This PWMICx is the dataport that allows the instructions to be loaded into the PWM
channel. The loading of the instructions is achieved by continuously writing to this dataport.
As this dataport address falls on the non-auto increment region, continuous write operation
on I2C will write into the same dataport address. The ‘x’ value is from 0 to 2 as there are 3
independent PWM channels. To access these dataports, the corresponding ENx in the
PWMCS register must be set to 0 first to put the PWM channel in reset state.
Bit
Read/Write
7
6
5
4
3
2
1
0
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
Reset Value 0
Table 33. Pin description
36/55
Bits
Name
Description
7:0
IB[x]
PWM Instruction Channel x, where x is 7 to 0
As an instruction is 16-bit width, writing the instruction into this 8-bit
PWMICx dataport requires two 8-bit data write. The most significant byte
of the 16-bit instruction is to be written in first and followed by the least
significant byte of the instruction. The same effect applies to the read
operation.
STMPE2401
12
PWM commands
PWM commands
The STMPE2401 PWM Controller works as a simple MCU, with program space of 64
instructions and a simple instruction set. The instructions are all 16 bits in length. The 3
most significant bits are used to identify the commands.
Table 34. PWM commands
Instruction
RAMP
Set Maximum
(SMAX)
Description
This instruction starts the PWM counters and set the pwm_x_out with the
result from the counting.
Load the PWM counter with the value of 0xff and the pwm_x_out will result in
logic level low.
Set Minimum (SMIN) Load the PWM counter with the value of 0x0 and the pwm_x_out will result in
logic level high.
Go to Start (GTS)
BRANCH
END
Trigger (TRIG)
Branch to the address 0x0 and execute from 0x0 and onwards.
Branch to a relative or an absolute address to execute with the looping
capability. There are 4 loop counters available and these allow 4 nested
loops.
End the instruction execution by resetting and interrupting to the host.
Capable of waiting as well as sending triggers to another PWM channel.
Table 35. Identification of instructions
Instruction
Bit 15
Bit 14
Bit 13
Ramp
0
-
-
SetFullScale
0
-
-
SetMinimum
0
-
-
GoToStart
0
-
-
Branch
1
0
1
End
1
1
0
Trigger
1
1
1
Reserved
1
0
0
37/55
PWM commands
STMPE2401
Table 36. Instruction
Bit
Instruction
Timing in 2kHz
15
RAMP
0
14
Prescale
0=16
1=512
13
12
11
10
Step Time
0 - 63
0 = immediate action
9
8
7
6
5
4 3 2 1
0
Sign
Increment
0=step- 1 – 126
up
1=stepdown
Increment value
of 0 is not
allowed.
prescale = 16 :Consumes
[(step
time)(1)(increme
nt)] cycles
prescale = 512 :Consumes
[(32)(1) (step
time)(1)(increme
nt)] cycles
SMAX
0
x(2)
0
0
127
Consumes 1
cycle
SMIN
0
x(2)
0
1
127
Consumes 1
cycle
GTS
0
0
0
0
0
Consumes 1
cycle
BRANCH
1
01
Loop Counter to Loop Count
use
0 – 15
0-3
0 = forever
loop
0=absol Step Size
ute step 0 – 63(1)
size
1=relativ
e step
size(1)
Consumes 1
cycle
Once the loop
count has been
reached, the
loop counter
resets.
END
1
10
Interr Reset
upt to instructi
host on
counter
and
output
level to
zero
TRIG
1
11
Wait for Trigger
on channel 0 – 2
Continues if all selected triggers
present.
Each bit signifies wait for the
corresponding channel.
reserved
1
00
RESERVED
RESERVED
Consumes 1
cycle
Send Trigger
on channel 0 – 2
Continues if no Wait
for Trigger in this
instruction.
x
(2)
Consumes 1 or
more cycles
Reserved.
1. Absolute Branch jumps to the absolute address (relative to address 0x0) using the value of step size. The Relative Branch
jumps in a backward manner relative to the current address location, ie. 1 means jump to the previous instruction location
and 0 means NOP.
2.
Don’t care.
38/55
STMPE2401
PWM commands
In order to enable a PWM channel, the programming sequence below should be observed.
●
The ENx of the PWMCS register should be kept in ‘0’. By default, it has a value of ‘0’.
●
Loads the instructions into the PWM channel x by writing the corresponding PWMICx.
●
The PWM channel x has a 64-word depth (16-bit width). Any instructions of size less
than or equal to 64 words can be loaded into the channel. Any attempt to load beyond
64 words will result in internal address pointer to roll-over (0x1f ◊ 0x00) and the excess
instructions to be over-written into the first address location of the channel and
onwards.
●
After the instructions are loaded in, then, the PWM channel x can be enabled by setting
a ‘1’ to the ENx bit.
●
Enables the corresponding interrupt mask bit to allow interruption to the host.
39/55
Keypad controller
13
STMPE2401
Keypad controller
The main operations of the keypad controller are controlled by four dedicated key controllers
that support up to four simultaneous dedicated key presses and a key scan controller and
two normal key controllers that support a maximum of 12x8 key matrix with detection of two
simultaneous key presses.
Four of the column inputs can be configured as dedicated keys through the setting of
Dkey0~3 bits of KPC_ctrl register.
The normal key matrix size is configurable through the setting of KPC_row and KPC_col
registers. The scanning of each individual row output and column input can be enabled or
masked to support a key matrix of variable size from 1x1 to 12x8.
The operation of the keypad controller is enabled by the SCAN bit of KPC_ctrl register.
Every key activity detected will be de-bounced for a period set by the DB_0~7 bits of
KPC_ctrl register before a key press or key release is confirmed and updated into the output
FIFO. The key data, indicating the key coordinates and its status (up or down), is loaded into
the FIFO at the end of a specified number of scanning cycles (set by ScanCount0~3 bits of
KPC_row_msb register). An interrupt will be generated when a new set of key data is
loaded. The FIFO has a capacity for four sets of key data. Each set of key data consists of
three bytes of information when any of the four dedicated keys is enabled. It is reduced to
two bytes when no dedicated key is involved. When the FIFO is full before its content is
read, an overflow signal will be generated while the FIFO will continue to hold its content but
forbid loading of new key data set.
Figure 9.
40/55
Keypad controller
STMPE2401
Keypad controller
The keypad column inputs enabled by the KPC_col register are normally ‘HIGH’, with the
corresponding input pins pulled up by resistors internally. After reset, all the keypad row
outputs enabled by the KPC_row register are driven ‘LOW’. If a key is pressed, its
corresponding column input will become ‘LOW’ after making contact with the ‘LOW’ voltage
on its corresponding row output.
Once the key scan controller senses a ‘LOW’ input on any of the column inputs, the
scanning cycles will then start to determine the exact key that has been pressed. The twelve
row outputs will be driven ‘LOW’ one by one (if the row output is enabled) during each
scanning cycle. While one row is driven ‘LOW’, the other rows are driven ‘HIGH’. (The pullups and pull-downs of row outputs are always disabled). If there is any column input sensed
as ‘LOW’ when a row is driven ‘LOW’, the key scan controller will then decode the key
coordinates (its corresponding row number and column number), save the key data into a
de-bounce buffer if available, confirm if it is a valid key press after de-bouncing, and update
the key data into output data FIFO if valid.
13.1
Registers in keypad controller
Table 37. Register in keypad controller
Address
Register name
Description
Auto-Increment
(during sequential
R/W)
0x60
KPC_col
Keypad column scanning register
Yes
0x61
KPC_row_msb
Keypad row scanning register
Yes
0x62
KPC_row_lsb
0x63
KPC_ctrl_msb
0x64
KPC_ctrl_lsb
0x68
KPC_data_byte0
0x69
KPC_data_byte1
No
0x6A
KPC_data_byte2
No
Yes
Keypad control register
Yes
Yes
Keypad data register
No
41/55
Keypad controller
13.2
STMPE2401
KPC_col register
Table 38. KPC_col Register
Bit
7
6
5
4
Name
13.3
3
2
1
0
Input Column 0 ~ 7
Read/Write
W
W
W
W
W
W
W
W
Reset Value
0
0
0
0
0
0
0
0
Bit
Name
Description
7
Input Column 7
‘1’ to turn on scanning of column 7; ‘0’ to turn off
6
Input Column 6
‘1’ to turn on scanning of column 6; ‘0’ to turn off
5
Input Column 5
‘1’ to turn on scanning of column 5; ‘0’ to turn off
4
Input Column 4
‘1’ to turn on scanning of column 4; ‘0’ to turn off
3
Input Column 3
‘1’ to turn on scanning of column 3; ‘0’ to turn off
2
Input Column 2
‘1’ to turn on scanning of column 2; ‘0’ to turn off
1
Input Column 1
‘1’ to turn on scanning of column 1; ‘0’ to turn off
0
Input Column 0
‘1’ to turn on scanning of column 0; ‘0’ to turn off
KPC_row_msb register
Table 39. KPC_row_msb register
42/55
Bit
7
6
5
4
3
2
1
0
Name
ScanPW1
ScanPW0
-
-
Read/Write
-
-
-
-
W
W
W
W
Reset Value
1
1
0
0
0
0
0
0
Output Row 8 ~ 11
Bit
Name
Description
7
ScanPW1
6
ScanPW0
5
-
-
4
-
-
3
Output Row 11
‘1’ to turn on scanning of row 11; ‘0’ to turn off
2
Output Row 10
‘1’ to turn on scanning of row 10; ‘0’ to turn off
1
Output Row 9
‘1’ to turn on scanning of row 9; ‘0’ to turn off
0
Output Row 8
‘1’ to turn on scanning of row 8; ‘0’ to turn off
Pulse width setting of keypad scanning. Use “11” at all
times
STMPE2401
13.4
Keypad controller
KPC_row_lsb register
Table 40. KPC_row_lsb register
Bit
7
6
5
Name
13.5
4
3
2
1
0
output Row 0 ~ 7
Read/Write
W
W
W
W
W
W
W
W
Reset Value
0
0
0
0
0
0
0
0
Bit
Name
Description
7
output Row 7
‘1’ to turn on scanning of row 7; ‘0’ to turn off
6
output Row 6
‘1’ to turn on scanning of row 6; ‘0’ to turn off
5
output Row 5
‘1’ to turn on scanning of row 5; ‘0’ to turn off
4
output Row 4
‘1’ to turn on scanning of row 4; ‘0’ to turn off
3
output Row 3
‘1’ to turn on scanning of row 3; ‘0’ to turn off
2
output Row 2
‘1’ to turn on scanning of row 2; ‘0’ to turn off
1
output Row 1
‘1’ to turn on scanning of row 1; ‘0’ to turn off
0
output Row 0
‘1’ to turn on scanning of row 0; ‘0’ to turn off
KPC_ctrl_msb register
Table 41. KPC_ctrl_msb register
Bit
7
Name
6
5
4
3
ScanCount0 ~ 3
2
1
0
DKey_0 ~ 3
Read/Write
W
W
W
W
W
W
W
W
Reset Value
0
0
0
0
0
0
0
0
Bit
Name
Description
7
ScanCount3
Number of key scanning cycles elapsed before a confirmed
key data is updated into output data FIFO (0 ~ 15 cycles)
6
ScanCount2
5
ScanCount1
4
ScanCount0
3
DKey_3
Set ‘1’ to use Input Column 3 as dedicated key
2
DKey_2
Set ‘1’ to use Input Column 2 as dedicated key
1
DKey_1
Set ‘1’ to use Input Column 1 as dedicated key
0
DKey_0
Set ‘1’ to use Input Column 0 as dedicated key
43/55
Keypad controller
13.6
STMPE2401
KPC_ctrl_lsb register
Table 42. KPC_ctrl_lsb register
Bit
7
6
5
Name
13.7
4
3
2
1
0
DB_0 ~ 5
SCAN
Read/Write
W
W
W
W
W
W
W
W
Reset Value
0
0
0
0
0
0
0
0
Bit
Name
7
DB_6
6
DB_5
5
DB_4
4
DB_3
3
DB_2
2
DB_1
1
DB_0
0
SCAN
Description
0-128ms of de-bounce time
‘1’ to start scanning; ‘0’ to stop
Data registers
The KPC_DATA register contains three bytes of information. The first two bytes store the key
coordinates and status of any two keys from the normal key matrix, while the third byte store
the status of dedicated keys.
Table 43. KPC_data_byte0 register
44/55
Bit
7
6
5
4
3
2
1
0
Name
Up/Down
R3
R2
R1
R0
C2
C1
C0
Read/Write
R
R
R
R
R
R
R
R
Reset Value
1
1
1
1
1
0
0
0
Bit
Name
7
Up/Down
6
R3
5
R2
4
R1
3
R0
2
C2
1
C1
0
C0
Description
‘0’ for key-down, ‘1’ for key-up
row number of key 1 (valid range : 0-11)
0x1111 for No Key
column number of key 1 (valid range : 0-7)
STMPE2401
Keypad controller
Table 44. KPC_data_byte1 register
Bit
7
6
5
4
3
2
1
0
Name
Up/Down
R3
R2
R1
R0
C2
C1
C0
Read/Write
R
R
R
R
R
R
R
R
Reset Value
1
1
1
1
1
0
0
0
Bit
Name
7
Up/Down
6
R3
5
R2
4
R1
3
R0
2
C2
1
C1
0
C0
Description
‘0’ for key-down, ‘1’ for key-up
row number of key 2 (valid range : 0-11)
0x1111 for No Key
column number of key 2 (valid range : 0-7)
Table 45. KPC_data_byte2 register
Bit
7
6
5
4
3
2
1
0
Name
-
-
-
-
Read/Write
R
R
R
R
R
R
R
R
Reset
Value
0
0
0
0
1
1
1
1
Dedicated Key 0 ~ 3
Bit
Name
Description
7
-
-
6
-
-
5
-
-
4
-
-
3
Dedicated Key 3
‘0’ for key-down, ‘1’ for key-up
2
Dedicated Key 2
‘0’ for key-down, ‘1’ for key-up
1
Dedicated Key 1
‘0’ for key-down, ‘1’ for key-up
0
Dedicated Key 0
‘0’ for key-down, ‘1’ for key-up
45/55
Keypad controller
13.7.1
STMPE2401
Resistance
Maximum resistance between keypad output and keypad input, inclusive of switch
resistance, protection circuit resistance and connection, must be less than 3.2 KΩ
13.7.2
Using the keypad controller
Before enabling the keypad controller operation, proper setup should be done by configuring
the input and output ports involved. This is achieved by programming the corresponding
GPIO control registers that determine the port direction and the necessary internal pull-up
or pull-down. For the GPIO ports that are used as keypad inputs, internal pull-up should be
enabled. For those that are used as keypad outputs, no internal pull-up or pull-down should
be enabled.
The scanning of column inputs should then be enabled for those GPIO ports that are
configured as keypad inputs by writing ‘1’s to the corresponding bits in the KPC_col register.
If any of the first three column inputs is to be used as dedicated key input, the corresponding
bits in the KPC_ctrl_msb register should be set to ‘1’. The bits in the KPC_row_msb and
KPC_row_lsb registers should also be set correctly to enable the row output scanning for
the corresponding GPIO ports programmed as keypad outputs.
The scan count and de-bounce count should also be programmed into the keypad control
registers before enabling the keypad controller operation. To enable the keypad controller
operation, the Enable_KPC bit in the system control register must be set to ‘1’ to provide the
required clock signals. The keypad controller will then start its operation by setting the
SCAN bit in the KPC_ctrl_lsb register to ‘1’.
The keypad controller operation can be disabled by setting the SCAN bit back to ‘0’. To
further reduce the power consumption, the clock signals can be cut off from the keypad
controller by setting the Enable_KPC bit to ‘0’.
ScanCount value is programmable to any value between 1-15 by writing into the scancount
register. If scan count is programmed to N, the Keypad Controller scans the entire matrix for
N times, collecting up to 2 matrix key and 4 dedicated keys, loads the keys into 1 set of
keypad data buffer and interrupts the host system.
46/55
STMPE2401
14
Rotator controller
Rotator controller
Rotator controller consists of 3 terminal, each capable of becoming an input with internal
pull-up, or and output. At any moment, 2 terminals are inputs and one terminal is output.
Figure 10. Rotator controller
The Rotator Controller is responsible for the detection of the direction of rotator and the
reporting of these direction sequences. The direction of a rotator can be either up or down.
A rotator has 3 contacts and detection of shorts on these contacts is used to determine the
direction of rotation. Following diagram shows the definition of the direction of rotation and
how the FSM states and driven outputs correspond to rotation.
Table 46. 3 possible conditions: A-B short, B-C short, C-A short.
Current State
Next State
LO
Input
State
Output
Input
Input
State
Output
Input
Input
C
1
A
B
C
2
B
A
C
Up
B
1
A
B
C
3
C
A
B
Down
A
2
B
A
C
3
C
A
B
Down
C
2
B
A
C
1
A
B
C
Up
A
3
C
A
B
2
B
A
C
Up
B
3
C
A
B
1
A
B
C
Down
Result
Figure 11. Possible conditions
47/55
Rotator controller
STMPE2401
Table 47. Registers for rotator control
14.1
Address
Register name
Register Size
0x70
Rotator_Control
8
0x72
Rotator_Buffer
8
Rotator_Control
Bit
Read/Write
7
6
Start_FSM
Reserved
RW
R
0
Reset Value 0
14.2
Bits
Name
7
Start_FSM
5
4
3
2
1
0
R
R
R
R
R
R
0
0
0
0
0
0
Description
Rotator FSM start bit.
‘1’ – Activate the FSM
‘0’ – Stop sampling rotator symbols
Rotator_Buffer
Bit
7
6
5
4
Symbol_Type
2
1
0
Symbol_Count
Read/Write
R
R
R
R
R
R
R
R
Reset Value
0
0
0
0
0
0
0
0
Bits
Name
7
Symbol_Type
6~0
48/55
3
Description
Symbol type to be reported
‘1’ – Down
‘0’ – Up
Symbol_Count Number of symbols of the type specified by bit 7
Minimum of 0 (b’0000000) to
Maximum of 127 (b’1111111)
STMPE2401
Rotator controller
The host should do the following on the I2C bus to start the Rotator controller:
1.
The host writes to GPIO Controller to configure the PU/PD bit and select the Rotator
Bits on the relevant IO.
2.
Write Rotator_Control data register to start the rotator controller. A maximum of 2
rotations later, the correct initial state on the rotator FSM is obtained. Scanning for
rotator movement continues.
3.
The host waits for interrupt from the rotator controller.
4.
The host reads Rotator_Buffer
5.
The host can stop rotator controller operation by writing to Rotator_Control register.
49/55
Miscellaneous features
15
Miscellaneous features
15.1
Reset
STMPE2401
STMPE2401 is equipped with an internal POR circuit that holds the device in reset state,
until the clock is steady and VCC input is valid. Host system may choose to reset the
STMPE2401 by asserting Reset_N pin.
15.2
Under voltage lockout
STMPE2401 is equipped with an internal UVLO circuit that generates a RESET signal,
when the main supply voltage falls below the allowed threshold.
15.3
Clock output
STMPE2401 provides a buffered 32KHz clock output at one of the GPIO as alternate
function. This clock could be used for cascading of multiple port expander devices, using
just 1 XTAL unit.
50/55
STMPE2401
16
Mechanical data
Mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
51/55
Mechanical data
STMPE2401
Table 48. TFBGA Mechanical data
mm.
inch
Dim.
A
Min
Typ
Max
Min
Typ
Max
1.1
1
1.16
0.043
0.039
0.046
A1
0.25
A2
0.78
0.86
0.031
0.034
b
0.30
0.25
0.35
0.012
0.010
0.014
D
3.60
3.50
3.70
0.142
0.138
0.146
D1
3.50
E
3.50
0.138
0.146
E1
2.50
0.098
e
0.50
0.020
F
0.55
0.022
0.138
3.60
Figure 12. Package dimensions
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0.010
3.70
0.142
STMPE2401
Mechanical data
Figure 13. Recommended footprint
Figure 14. Tape and reel information
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Revision history
17
STMPE2401
Revision history
Table 49. Revision history
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Date
Revision
Changes
08-Jan-2007
1
Initial release
29-May-2007
2
Cover page updated
STMPE2401
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