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ST-NXP Wireless 34.807IRELESS www.stnwireless.com STn8810 Mobile multimedia application processor Data Brief Nomadik is a registered trademark of STMicroelectronics Features ■ ■ ■ – Embedded medium trace module – (ETM Medium+) Video performance – Real-time MPEG4 decoding up to VGA 30 fps – WM9/VC-1 encode/decode support – H.264, H.263 encode/decode support – JPEG encode or decode, up to 4080 x 4080 pixels Audio performance – Extensive digital-audio software library – Ultra low-power multimedia Camera interfaces – Serial interface up to 416 Mbit/s (MIPI legacy CSI) – Parallel camera CCIR-656 interface up to 66 MHz (MIPI legacy CPI) ■ Color LCD controller ■ TV output ■ Advanced power management unit ■ ARM926EJ 32-bit RISC CPU at 264 MHz – 32-Kbyte instruction/16-Kbyte data caches Figure 1. ■ Advanced security – Comprehensive security framework – Protected access to secured ROM and RAM ■ 16-bit DDR/SDR-SDRAM memory controller ■ NOR Flash/NAND Flash/CompactFlash/CF+ controller ■ MultiMediaCard/SD card host controller ■ Full set of IO peripherals ■ TFBGA 12 mm x 12 mm, 0.5 mm pitch Description The STn8810 application processor enables smart phones, mobile multimedia consumer, internet appliances and in-car entertainment systems to play back media content, record pictures and video clips, receive mobile-TV and perform bidirectional audio-visual communication in real time. STn8810 block diagram Host port interface Color LCD controller Display interfaces Multichannel DMA Secured controller RAM/ROM TV output Camera interfaces x2 USB-OTG I²C x2 SD/MMC HSI eSRAM Smart video Smart audio accelerator accelerator MSP x3 buffer NAND/NOR Flash UART x3 controller SSP DDR SDRAM Power controller management Timers FIrDA ARM926EJ System controller Security toolbox Dcache Interrupt controller PLLs Icache 1-Wire/HDQ interface Watchdog RTC February 2008 Rev 3 For further information contact your local STMicroelectronics sales office. JTAG/trace GPIO x96 1/15 www.st.com 15 Contents STn8810 Contents 1 2/15 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 Smart video accelerator (SVA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 Smart audio accelerator (SAA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 Advanced power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 ARM926EJ processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.5 Embedded memory units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.6 Advanced security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.7 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.8 SDRAM memory controller (SDMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.9 Real time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.10 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.11 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.12 Vectored interrupt controller (VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.13 System and reset controller (SRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.14 Direct memory access (DMA) controllers . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.15 Universal asynchronous receivers-transmitters (UARTs) . . . . . . . . . . . . . . 7 1.16 Synchronous serial port (SSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.17 Camera interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.18 TV interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.19 Liquid crystal display controller (LCDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.20 Master display interface (MDIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.21 Pulse width light modulator (PWL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.22 General purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.23 MultiMediaCard/secure data card interface (MMC/SD) . . . . . . . . . . . . . . . 9 1.24 USB On-The-Go interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.25 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.26 Fast IrDA interface (FIrDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.27 Multichannel serial ports (MSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.28 High-speed serial interface (HSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.29 Host port interface (HPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 STn8810 Contents 2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3/15 Overview 1 STn8810 Overview The STn8810 platform comprises an industry-standard ARM CPU supported by smart audio and video accelerators, on-chip memory and controllers, a rich set of peripheral interfaces, and a power management system. The processors, controllers, memory and peripheral interfaces are connected by a multi-layer advanced microcontroller bus architecture (AMBA) for efficient data transport between the components. The overall STn8810 architecture is illustrated in Figure 2. Figure 2. STn8810 block diagram LCD panel (STN/TFT/module) Backup RAM 1 KB NOR NAND Flash control Camera (parallel or TV serial) output MDIF LCD controller controller Trace JTAG ETM/JTAG I/D cache 32/16 Kbytes eROM 64 Kbytes secured ARM926EJ eRAM 16 Kbytes secured Boot ROM 32 Kbytes DDRSDRAM memory control Smart video accelerator eSRAM Vector interrupt controller 40 Kbytes Security toolbox Interconnect (data/instruction, memory/peripherals) HPI SSP 96 GPIOs 32 kHz System control Smart audio UART (x3) accelerator RTC Timers (x8) FIrDA interface PWL Watchdog MSP (x3) Power manager Secure watchdog SD/MMC interface I²C interface (x2) RTT USB-OTG PLL 13/19.2 MHz 4/15 CPU/buses/peripherals Clocks HSI STn8810 1.1 Overview Smart video accelerator (SVA) Using leading-edge technology, this block is a low-power, high-performance video accelerator that supports the following features: 1.2 ● MPEG-4 simple profile level 0 codec video encoder and decoder; real time up to VGA 30 fps (encode only or decode only) ● H.263 profile 0 level 10 video codec; real time subQCIF or QCIF 15 fps for videoconferencing ● H.263 profile 0 level 30 video encoder or decoder; real-time up to CIF 30 fps ● JPEG baseline accelerated encoder or decoder, up to 4080 x 4080 pixels ● Programmable DSP (MMDSP+) for intermediate level processing, clocked at 66 MHz ● Picture pre-/post-processing ● Low-power implementation Smart audio accelerator (SAA) This high-performance block is a flexible sophisticated audio accelerator based on the MMDSP+ programmable audio DSP, clocked at 133 MHz, and features: ● 24-bit data path ● Ultra-low power implementation The audio accelerator features: 1.3 ● MP3, AAC, AAC+ (SBR) decoding, and more ● Speech codecs: AMR (WB, NB), and more ● Audio sample rates of 32 kHz, 44.1 kHz and 48 kHz ● Noise reduction and echo cancelling ● Stereo enhancements and surround effects Advanced power management unit (PMU) The dynamic PMU optimizes power consumption of the STn8810. It delivers all the platform clocks, and handles reset management. It also manages GPIO levels during sleep mode and emergency self-refresh of SDRAM. The PMU controls the external voltage regulator, in order to change its settings in different modes. In deep-sleep mode, only GPIOs, the real-time clock (RTC), system and reset controller (SRC), PMU and secured RAM remain in operation. The PMU also controls the embedded 1.2 V voltage switch that switches off the logic supply after the platform has entered sleep mode. The family of power manager ICs, STw481x companion chips, seamlessly interface with the Nomadik STn8810 and optimize global system power consumption leveraging on the PMU. 5/15 Overview 1.4 STn8810 ARM926EJ processor The STn8810 CPU is an ARM926EJ reduced instruction set computer (RISC) processor. This 32-bit processor core supports 32-bit ARM® and 16-bit Thumb instruction sets, enabling the user to trade off between high performance and high code density. The cached ARM CPU features a memory management unit (MMU) and is clocked at 264 MHz. It has a 32-Kbyte instruction cache and a 16-Kbyte data cache, and supports the Jazelle™ extensions for Java acceleration. It also includes an embedded trace module (ETM Medium+) for real-time CPU activity tracing and debugging. It supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed trace mode, with normal or half-rate clock. 1.5 1.6 Embedded memory units ● 32 Kbytes of public ROM (for boot purposes) ● 64 Kbytes of secured ROM (for security purposes) ● 40 Kbytes of public RAM ● 16 Kbytes of secured RAM (for security code and/or data) ● 1 Kbyte backup Advanced security The device contains 64 Kbytes of ROM and 16 Kbytes of RAM that are only accessible when the system is in a trusted environment. An advanced security framework enables Mcommerce as well as authentication applications drawing on ST smartcard expertize: 1.7 ● SHA-1/DES/3DES hardware accelerators ● True random number generator (RNG) ● Secured watchdog timer ● Unique die identification Flexible static memory controller (FSMC) The FSMC interfaces to off-chip multiplexed burst NOR Flash memory devices and NAND Flash memory devices, and to CompactFlash/CF+ cards. The FSMC manages up to 3 chipselects of NOR Flash memories, and up to 2 chip-selects of NAND Flash memories or CompactFlash/CF+ devices. The memory controller features error code correction accelerated by hardware that reduces host CPU workload to support NAND Flash very fast read/write transfers. 1.8 SDRAM memory controller (SDMC) The SDMC is used to interface with single-data rate SDRAM (SDR-SDRAM) at 100 MHz and double-data rate SDRAM (DDR-SDRAM) at 133 MHz. The SDMC manages up to two chip-selects of 16-bit wide SDR-SDRAM or DDR-SDRAM. It can address up to 256 Mbytes of SDRAM. 6/15 STn8810 1.9 Overview Real time clock (RTC) The RTC provides a 1-second resolution clock. This keeps time when the system is inactive and can be used to wake the system up when a programmed alarm time is reached. It has a clock trimming feature to compensate for the accuracy of the 32.768 kHz crystal and a secured time update. 1.10 Timers The STn8810 provides eight 16- or 32-bit (configurable) timers, as two groups of four. They generate the periodic and timed interrupts required by OS services. 1.11 Watchdog timer This OS resource is used to trigger a system reset in the event of software failure. 1.12 Vectored interrupt controller (VIC) The VIC allows the OS interrupt handler to quickly dispatch interrupt service routines in response to peripheral interrupts. There are 32 interrupt lines and the VIC uses a separate bit position for each interrupt source. Software controls each request line to generate software interrupts. 1.13 System and reset controller (SRC) The SRC provides a control interface for clock generation components external to the subsystem. It also controls system-wide and peripheral-specific energy management features. 1.14 Direct memory access (DMA) controllers Direct memory accesses can be employed for data transfers involving DMA peripherals. A DMA controller services FIFO fill/empty requests from these peripherals immediately without CPU interaction. Peripheral-to-peripheral and memory-to-memory DMAs are also supported. A multichannel DMA controller is provided for efficient and concurrent data transfers. 1.15 Universal asynchronous receivers-transmitters (UARTs) The STn8810 provides three autobaud UARTs, one of which offers all modem control/status signals. They are enhanced versions of the industry-standard 16C550 UART with a high data rate up to 3.692 Mbit/s. 7/15 Overview 1.16 STn8810 Synchronous serial port (SSP) The STn8810 provides one SSP for synchronous serial communication with external peripherals. SPI, MicroWire and T.I. protocols are supported, with programmable word length of up to 32 bits and data rate up to 24 Mbit/s. The SSP has the following features in both master and slave configurations: 1.17 1.18 ● Parallel-to-serial conversion of data written to an internal, 32-bit wide, 32-location deep, transmit FIFO ● Serial-to-parallel conversion of received data, which is buffered in a 32-bit wide, 32-location deep, receive FIFO ● Programmable data frame size from 4 to 32 bits ● Programmable clock bit rate and prescaler ● Programmable clock phase and polarity in SPI mode ● Support for direct memory accesses ● Support for several LCD smart panels Camera interface ● Serial MIPI CSI camera interface, up to 416 Mbit/s data/strobe ● Parallel CCIR-656 camera interface, up to 66 MHz with embedded/external sync ● High resolution camera modules, up to 4 Mpixels TV interface The STn8810 interfaces seamlessly with the Imagik companion-chip, which performs YUV to RGB signal conversion and connects directly to a TV set. 1.19 Liquid crystal display controller (LCDC) This interface drives LCD panels, and supports the following displays: ● STN displays: single- or dual-panel with 8-bit color and 4- or 8-bit monochrome ● TFT displays: 12-, 16-, 18- and 24-bit color The resolution can be set as follows: 8/15 ● 1-, 2- or 4-bits-per-pixel (bpp) palettized for mono STN ● 1-, 2-, 4- or 8-bpp palettized for color STN and TFT ● 16-bpp true-color non-palettized for color STN and TFT ● 24-bpp packed and non-packed true-color (non-palettized) for color TFT STn8810 1.20 Overview Master display interface (MDIF) This interface drives LCD display modules, that is, panels that include their own display memory and perform LCD panel refresh themselves. The MDIF is a parallel bidirectional interface that can send commands or data to or read data from the display panel logic. It has a DMA engine to automatically fetch data/commands from main memory without CPU intervention. 1.21 Pulse width light modulator (PWL) The PWL provides control of LCD backlighting. It produces a series of pulses that are fed to the backlighting, where the width (or duty cycle) of the pulses determines the perceived lighting level. An 8-bit random sequence generator decreases the spectral power at the modulator harmonic frequencies. 1.22 General purpose inputs/outputs (GPIOs) The STn8810 provides 96 programmable inputs or outputs that have switchable pull-up and pull-down resistors and are controllable in two modes: ● Software mode through an APB bus interface ● Hardware mode through a hardware control interface The GPIO interface provides the following individually programmable functions: 1.23 ● Any number of pins may be configured as interrupt sources ● Debouncing logic can be enabled for each GPIO to filter out glitches on I/Os ● Any GPIO may be used to wake up the device from sleep mode independent of interrupt programming, and the input level that triggers wake-up is definable for each enabled GPIO. MultiMediaCard/secure data card interface (MMC/SD) This interface can directly control one SD card (without encryption/decryption logic), or one MultiMediaCard. It also supports several of each card type using the GPIOs for card selection. 1.24 USB On-The-Go interface The STn8810 USB interface is USB 2.0 compliant, with On-The-Go standard extension (rev 1.0) compliance. The USB-OTG features: ● Supports full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) signaling bit rate ● Supports session request protocol (SRP) and host negotiation protocol (HNP) ● 7 bidirectional endpoints plus control endpoint 0 ● Digital interface to external PHY ● Fully compatible with STw4810 power manager companion chip 9/15 Overview 1.25 STn8810 I²C bus interface The STn8810 provides two I²C bus interfaces that support the following features: ● Slave transmitter/receiver and master transmitter/receiver modes ● Multi-master capability ● 10-bit addressing ● Standard (100 kHz) and fast (400 kHz) speeds ● Compliance with I²C and DDC standards In addition to receiving and transmitting data, the interface converts data from serial to parallel format and vice-versa using an interrupt or polled handshake. The interrupts are enabled and disabled in software. 1.26 Fast IrDA interface (FIrDA) This interface supports IrDA half-duplex communications. It performs modulation and demodulation of infrared signals, and the wrapping of IrLAP frames. The IrDA interface supports the following infrared modes and baud rates: 1.27 ● Serial infrared (SIR): 9.6 Kbit/s, 19.2 Kbit/s, 38.4 Kbit/s, 57.6 Kbit/s and 115.2 Kbit/s ● Medium infrared (MIR): 576 Kbit/s and 1.152 Mbit/s ● Fast infrared (FIR): 4 Mbit/s Multichannel serial ports (MSP) The STn8810 provides three multichannel serial ports. These are synchronous receive and transmit serial interfaces that support a data rate of up to 48 Mbit/s with the following features: ● Philips I²S format: left aligned with one cycle between leading edge of frame synchronization and first data bit, 16 or 24 bits per sample ● Sony format: right aligned, 48 cycles per frame, 16 or 24 bits per sample ● Matsushita format: right aligned, 64 cycles per frame, 16 or 24 bits per sample ● Programmable number of bitclock cycles per frame: 32, 48 or 64 ● Programmable polarity of bitclock and frame synchronization ● Programmable number of bits per sample: 16, 18, 20 or 24 bits It also provides: 1.28 ● µ-Law and A-Law compressing/expanding ● Independent framing and clocking for receive and transmit ● External shift clock or an internal, programmable frequency shift clock for data transfer ● Support for DMA transfers High-speed serial interface (HSI) The STn8810 includes a full-duplex high-speed serial interface (MIPI legacy HSI). This highspeed, 8-channel modem interface operates at up to 108 Mbit/s. 10/15 STn8810 1.29 Overview Host port interface (HPI) The host port interface features: ● 16-bit parallel data bus ● Multiplexed and non-multiplexed address/data bus ● Indirect host access ● Direct host access to a segment of STn8810 memory in multiplexed mode 11/15 Package mechanical data 2 STn8810 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 3. TFBGA outline (bottom and side views) D C D1 f e A2 D e D1 f AB AA Y W V U T R P N M L K J H G F E D C B A A1 1 3 2 5 4 7 6 A1 ball pad corner 9 8 11 13 15 17 19 21 10 12 14 16 18 20 22 A φb (288+36 = 324 balls) ddd (see note) Bottom view Note: 12/15 Seating plane C Side view The terminal A1 corner is identified on the top surface by using a corner chamfer, ink or metallized markings. STn8810 Package mechanical data Table 1. Package dimensions Databook (mm) Ref. Drawing (mm) Min Typ Max Min Typ Max A 1.010 - 1.200 - - 1.160(1) A1 0.150 - - 0.200 0.250 0.300 A2 - 0.820 - - 0.820 - b 0.250 0.300 0.350 0.250 0.300 0.350 D 11.750 12.000 12.150 11.900 12.000 12.100 D1 - 10.500 - - 10.500 - e 0.450 0.500 0.550 0.450 0.500 0.550 f 0.600 0.750 0.900 0.650 0.750 0.850 - - 0.080 - - 0.080 ddd 1. Maximum mounted height is 1.120 mm, based on a 0.28 mm ball pad diameter. Solder paste is 0.15 mm thick and 0.28 mm in diameter. 13/15 Ordering information 3 STn8810 Ordering information Table 2. Ordering information Order codes 4 Packing STN8810B3HPBE TFBGA 12x12x1.2 288+36 4R22 0.5 Tray STN8810B3HSBE TFBGA 12x12x1.2 288+36 4R22 0.5 Tray Revision history Table 3. 14/15 Package Document revision history Date Revision Changes 11-Fev-2005 1 Initial release. 19-Dec-2006 2 Removed references to other part numbers than STn8810. Updated the overview. Added the ordering information. 08-Feb-2008 3 Removed references to SDIO card. STn8810 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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