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VT82C693
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VIA VT82C693
APOLLO PRO-PLUS
66 / 100 MHz
Single-Chip Slot-1/Socket 370 North Bridge
for Desktop and Mobile PC Systems
with AGP and PCI
plus Advanced ECC Memory Controller
supporting SDRAM, VCM, EDO, and FPG
• AGP / PCI / ISA Mobile and Deep Green PC Ready
− GTL+ compliant host bus supports write-combine cycles
− Supports separately powered 3.3V (5V tolerant) interface to system memory, AGP, and PCI bus
− Modular power management and clock control for mobile system applications
− Combine with VIA VT82C596A south bridge chip for state-of-the-art system power management
• High Integration
− Single chip implementation for 64-bit Slot-1/Socket 370 CPU, 64-bit system memory, 32-bit PCI and 32-bit AGP
interfaces
− Apollo Pro-Plus Chipset: VT82C693 system controller and VT82C596A PCI to ISA bridge
− Chipset includes UltraDMA-33 EIDE, USB, and Keyboard / PS2-Mouse Interfaces plus RTC / CMOS on chip
• High Performance CPU Interface
− Supports Slot-1 and Socket 370 (Intel Pentium IITM and CeleronTM) processors
− 66 / 100 MHz CPU Front Side Bus (FSB)
− Built-in PLL (Phase Lock Loop) circuitry for optimal skew control within and between clocking regions
− Five outstanding transactions (four In-Order Queue (IOQ) plus one input latch)
− Supports WC (Write Combining) cycles
− Dynamic deferred transaction support
− Sleep mode support
− System management interrupt, memory remap and STPCLK mechanism
Preliminary Revision 0.3 December 9, 1998
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Features
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VT82C693
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• Full Featured Accelerated Graphics Port (AGP) Controller
− Synchronous and pseudo-synchronous with the host CPU bus with optimal skew control
PCI
33 MHz
33 MHz
−
−
−
−
−
−
−
−
−
−
−
AGP
CPU
66 MHz 100 MHz
66 MHz 66 MHz
Mode
3x synchronous
2x synchronous
AGP v2.0 compliant
Supports SideBand Addressing (SBA) mode (non-multiplexed address / data)
Supports 133MHz 2X mode for AD and SBA signaling
Pipelined split-transaction long-burst transfers up to 533 MB/sec
Eight level read request queue
Four level posted-write request queue
Thirty-two level (quadwords) read data FIFO (128 bytes)
Sixteen level (quadwords) write data FIFO (64 bytes)
Intelligent request reordering for maximum AGP bus utilization
Supports Flush/Fence commands
Graphics Address Relocation Table (GART)
−
−
−
−
One level TLB structure
Sixteen entry fully associative page table
LRU replacement scheme
Independent GART lookup control for host / AGP / PCI master accesses
− Windows 95 OSR-2 VXD and integrated Windows 98 / NT5 miniport driver support
• Concurrent PCI Bus Controller
− PCI buses are synchronous / pseudo-synchronous to host CPU bus
− 33 MHz operation on the primary PCI bus
− 66 MHz PCI operation on the AGP bus
− PCI-to-PCI bridge configuration on the 66MHz PCI bus
− Supports up to five PCI masters
− Peer concurrency
− Concurrent multiple PCI master transactions; i.e., allow PCI masters from both PCI buses active at the same time
− Zero wait state PCI master and slave burst transfer rate
− PCI to system memory data streaming up to 132Mbyte/sec
− PCI master snoop ahead and snoop filtering
− Two lines of CPU to PCI posted write buffers
− Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities
− Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
− Forty-eight levels (double-words) of post write buffers from PCI masters to DRAM
− Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters
− Delay transaction from PCI master accessing DRAM
− Read caching for PCI master reading DRAM
− Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks)
− Symmetric arbitration between Host/PCI bus for optimized system performance
− Complete steerable PCI interrupts
− PCI-2.1 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs
Preliminary Revision 0.3 December 9, 1998
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Features
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• Advanced High-Performance DRAM Controller
− DRAM interface synchronous with host CPU (66/100 MHz) or AGP (66MHz) for most flexible configuration
− Concurrent CPU, AGP, and PCI access
− Supports FP, EDO, SDRAM and VCM SDRAM memory types
− Different DRAM types may be used in mixed combinations
− Different DRAM timing for each bank
− Dynamic Clock Enable (CKE) control for SDRAM power reduction in high speed systems
− Mixed 1M / 2M / 4M / 8M / 16MxN DRAMs
− 8 banks up to 1GB DRAMs (128Mb DRAM technology)
− Flexible row and column addresses
− 64-bit data width only
− 3.3V DRAM interface with 5V-tolerant inputs
− Programmable I/O drive capability for MA, command, and MD signals
− Dual copies of MA signals for improved drive
− Optional bank-by-bank ECC (single-bit error correction and multi-bit error detection)
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
or EC (error checking only) for DRAM integrity
Two-bank interleaving for 16Mbit SDRAM support
Two-bank and four bank interleaving for 64Mbit SDRAM support
Supports maximum 8-bank interleave (i.e., 8 pages open simultaneously); banks are allocated based on LRU
Independent SDRAM control for each bank
Seamless DRAM command scheduling for maximum DRAM bus utilization
(e.g., precharge other banks while accessing the current bank)
Four cache lines (16 quadwords) of CPU to DRAM write buffers
Four cache lines of CPU to DRAM read prefetch buffers
Read around write capability for non-stalled CPU read
Speculative DRAM read before snoop result
Burst read and write operation
x-2-2-2-2-2-2-2 back-to-back accesses for EDO DRAM from CPU or from DRAM controller
x-1-1-1-1-1-1-1 back-to-back accesses for SDRAM
BIOS shadow at 16KB increment
Decoupled and burst DRAM refresh with staggered RAS timing
CAS before RAS or self refresh
• Mobile System Support
− Dynamic power down of SDRAM (CKE)
− Independent clock stop controls for CPU / SDRAM, AGP, and PCI bus
− PCI and AGP bus clock run and clock generator control
− VTT suspend power plane preserves memory data
− Suspend-to-DRAM and Self-Refresh operation
− EDO self-refresh and SDRAM self-refresh power down
− 8 bytes of BIOS scratch registers
− Low-leakage I/O pads
• Built-in NAND-tree pin scan test capability
• 3.3V, 0.35um, high speed / low power CMOS process
• 35 x 35 mm, 492 pin BGA Package
Preliminary Revision 0.3 December 9, 1998
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Features
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OVERVIEW
The Apollo Pro-Plus is a high performance, cost-effective and energy efficient chip set for the implementation of AGP / PCI / ISA
desktop and notebook personal computer systems from 66 MHz to 100 MHz based on 64-bit Socket 370 and Slot-1 (Intel
Pentium-II and Celeron) super-scalar processors.
Slot-1 or Socket 370
Host CPU
HCLK
SMI# / STPCLK# / SLP#
SMIACT#
3D
Graphics
Controller
GCLK
AGP Bus
VT82C693
GCKRUN#
Apollo Pro-Plus
North Bridge
PCKRUN#
PCLK
CKE#
PCI Bus
ISA
IDE ATA/33
BIOS ROM
USB
Keyboard / Mouse
492 BGA
Memory Bus
MCLK
HCLK
PCLK
SDRAM
EDO,
or FPG
Clock
Buffer
SUSCLK,
SUSST1#
VT82C596A
Mobile South
324 BGA
CPUSTP#
PCISTP#
Clock
Generator
SMBus
Power Plane & Peripheral Control
GPIO and ACPI Events
Figure 1. Apollo Pro-Plus System Block Diagram Using the VT82C596A Mobile South Bridge
The Apollo Pro-Plus chip set consists of the VT82C693 system controller (492 pin BGA) and the VT82C596A PCI to ISA bridge
(324 pin BGA). The system controller provides superior performance between the CPU, DRAM, AGP bus, and PCI bus with
pipelined, burst, and concurrent operation.
The VT82C693 supports eight banks of DRAMs up to 1GB. The DRAM controller supports standard Fast Page Mode (FPM)
DRAM, EDO-DRAM, and Synchronous DRAM (SDRAM), in a flexible mix / match manner. The Synchronous DRAM interface
allows zero wait state bursting between the DRAM and the data buffers at 100 MHz. The eight banks of DRAM can be composed
of an arbitrary mixture of 1M / 2M / 4M / 8M / 16MxN DRAMs. The DRAM controller also supports optional ECC (single-bit
error correction and multi-bit detection) or EC (error checking) capability separately selectable on a bank-by-bank basis. The
DRAM controller can run at either the host CPU bus frequency (66 /100 MHz) or at the AGP bus frequency (66 MHz) with built-in
PLL timing control.
The VT82C693 system controller also supports full AGP v2.0 capability for maximum bus utilization including 2x mode transfers,
SBA (SideBand Addressing), Flush/Fence commands, and pipelined grants. An eight level request queue plus a four level postwrite request queue with thirty-two and sixteen quadwords of read and write data FIFO's respectively are included for deep
pipelined and split AGP transactions. A single-level GART TLB with 16 full associative entries and flexible CPU / AGP / PCI
remapping control is also provided for operation under protected mode operating environments. Both Windows-95 VXD and
Windows-98 / NT5 miniport drivers are supported for interoperability with major AGP-based 3D and DVD-capable multimedia
accelerators.
The VT82C693 supports two 32-bit 3.3 / 5V system buses (one AGP and one PCI) that are synchronous / pseudo-synchronous to
the CPU bus. The chip also contains a built-in bus-to-bus bridge to allow simultaneous concurrent operations on each bus. Five
levels (doublewords) of post write buffers are included to allow for concurrent CPU and PCI operation. For PCI master operation,
forty-eight levels (doublewords) of post write buffers and sixteen levels (doublewords) of prefetch buffers are included for
concurrent PCI bus and DRAM/cache accesses. The chip also supports enhanced PCI bus commands such as Memory-Read-Line,
Memory-Read-Multiple and Memory-Write-Invalid commands to minimize snoop overhead. In addition, advanced features are
supported such as snoop ahead, snoop filtering, L1 write-back forward to PCI master, and L1 write-back merged with PCI post
Preliminary Revision 0.3 December 9, 1998
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Overview
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VT82C693
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write buffers to minimize PCI master read latency and DRAM utilization. Delay transaction and read caching mechanisms are also
implemented for further improvement of overall system performance.
The 324-pin Ball Grid Array VT82C596A PCI to ISA bridge supports four levels (doublewords) of line buffers, type F DMA
transfers and delay transaction to allow efficient PCI bus utilization and (PCI-2.1 compliant). The VT82C596A also includes an
integrated keyboard controller with PS2 mouse support, integrated DS12885 style real time clock with extended 256 byte CMOS
RAM, integrated master mode enhanced IDE controller with full scatter / gather capability and extension to UltraDMA-33 / ATA33 for 33MB/sec transfer rate, integrated USB interface with root hub and two function ports with built-in physical layer
transceivers, Distributed DMA support, and OnNow / ACPI compliant advanced configuration and power management interface.
For sophisticated notebook implementations, the Apollo Pro-Plus provides independent clock stop control for the CPU / SDRAM,
PCI, and AGP buses and Dynamic CKE control for powering down of the SDRAM. A separate suspend-well plane is implemented
for the SDRAM control signals for Suspend-to-DRAM operation. Coupled with the VT82C596A south bridge chip, a complete
notebook PC main board can be implemented with no external TTLs.
The Apollo Pro-Plus chipset is ideal for high performance, high quality, high energy efficient and high integration desktop and
notebook AGP / PCI / ISA computer systems.
Preliminary Revision 0.3 December 9, 1998
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Overview