STMICROELECTRONICS STP16DP05TTR

STP16DP05
Low voltage 16-bit constant current
LED sink driver with outputs error detection
Features
■
Low voltage power supply down to 3 V
■
16 constant current output channels
■
Adjustable output current through external
resistor
■
Short and open output error detection
■
Serial Data IN/Parallel data OUT
■
3.3 V micro driver-able
■
Output current: 5-100 mA
■
30 MHz clock frequency
■
Available in high thermal efficiency TSSOP
exposed pad
■
ESD protection 2.5 kV HBM, 200 V MM
QSOP-24
TSSOP24
TSSOP24
(exposed pad)
The data detection results are loaded in the shift
register and shifted out via the serial line output.
Description
The STP16DP05 is a monolithic, low voltage, low
current power 16-bit shift register designed for
LED panel displays. The device contains a 16-bit
serial-in, parallel-out shift register that feeds a
16-bitD-type storage register. In the output stage,
sixteen regulated current sources were designed
to provide 5-100 mA constant current to drive the
LEDs.
The STP16DP05 features open and short LED
detections on the outputs.The STP16DP05 is
backward compatible with STP16C/L596.The
detection circuit checks 3 different conditions that
can occur on the output line: short to GND, short
to VO or open line.
Table 1.
SO-24
The detection functionality is implemented without
increasing the pin count number, through a
secondary function of the output enable and latch
pin (DM1 and DM2 respectively), a dedicated
logic sequence allows the device to enter or leave
from detection mode. Through an external
resistor, users can adjust the STP16DP05 output
current, controlling in this way the light intensity of
LEDs, in addition, user can adjust LED’s
brightness intensity from 0 % to 100 % via
OE/DM2 pin.
The STP16DP05 guarantees a 20 V output
driving capability, allowing users to connect more
LEDs in series. The high clock frequency,
30 MHz, makes the device suitable for high data
rate transmission. The 3.3 V voltage supply is well
useful for applications that interface any 3.3V
micro. Compared with a standard TSSOP
package, the TSSOP exposed pad increases heat
dissipation capability by a 2.5 factor.
Device summary
Order codes
Package
Packaging
STP16DP05MTR
SO-24 (tape and reel)
1000 parts per reel
STP16DP05TTR
TSSOP24 (tape and reel)
2500 parts per reel
STP16DP05XTTR
TSSOP24 exposed pad
(tape and reel)
2500 parts per reel
STP16DP05PTR
QSOP-24
2500 parts per reel
February 2008
Rev 4
1/29
www.st.com
29
Contents
STP16DP05
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
2
Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7
Detection mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1
Phase one: “entering in detection mode“ . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2
Phase two: “error detection” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.3
Phase three: “resuming to normal mode” . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.4
Error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/29
STP16DP05
1
Summary description
Summary description
Table 2.
Typical current accuracy
Current accuracy
Output voltage
≥ 1.3 V
1.1
Between ICs
±1.5 %
±5 %
Output current
VDD
Temperature
20 to 100 mA
3.3 V to 5 V
25 °C
Pin connection and description
Figure 1.
Note:
Between bits
Pin connection
The exposed pad is electrically not connected
Table 3.
Pin description
Pin N°
Symbol
Name and function
1
GND
Ground terminal
2
SDI
Serial data input terminal
3
CLK
4
LE-DM1
Clock input terminal
5-20
OUT 0-15
Output terminal
21
OE-DM2
Input terminal of output enable (active low) - Detect mode 1
(see operation principle)
22
SDO
23
R-EXT
24
VDD
Latch input terminal - Detect mode 1 (see operation principle)
Serial data out terminal
Input terminal of an external resistor for constant current programing
Supply voltage terminal
3/29
Electrical ratings
STP16DP05
2
Electrical ratings
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4.
Absolute maximum ratings
Symbol
2.2
Parameter
Value
Unit
VDD
Supply voltage
0 to 7
V
VO
Output voltage
-0.5 to 20
V
IO
Output current
100
mA
VI
Input voltage
-0.4 to VDD
V
1600
mA
50
MHz
Value
Unit
IGND
GND terminal current
fCLK
Clock frequency
Thermal data
Table 5.
Symbol
Thermal data
Parameter
TOPR
Operating temperature range
-40 to +125
°C
TSTG
Storage temperature range
-55 to +150
°C
60
°C/W
85
°C/W
TSSOP24
Exposed Pad
37.5
°C/W
QSOP-24
72
°C/W
SO-24
TSSOP24
RthJC
Thermal resistance junction-case
(1)
1. The exposed pad should be soldered directly to the PCB to realize the thermal benefits.
4/29
STP16DP05
2.3
Electrical ratings
Recommended operating conditions
Table 6.
Symbol
Recommended operating conditions
Parameter
Test conditions
Min
3.0
Typ
Max
Unit
5.5
V
20
V
100
mA
VDD
Supply voltage
VO
Output voltage
IO
Output current
OUTn
IOH
Output current
SERIAL-OUT
+1
mA
IOL
Output current
SERIAL-OUT
-1
mA
VIH
Input voltage
0.7VDD
VDD+0.3
V
VIL
Input voltage
-0.3
0.3VDD
V
5
twLAT
LE\DM1 pulse width
20
ns
twCLK
CLK pulse width
20
ns
twEN
OE\DM2 pulse width
200
ns
20
ns
15
ns
15
ns
tSETUP(D) Setup time for DATA
VDD = 3.0 V to 5.0 V
tHOLD(D) Hold time for DATA
tSETUP(L) Setup time for LATCH
fCLK
Clock frequency
Cascade operation
(1)
30
MHz
1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer.
Please consider the timings carefully.
5/29
Electrical characteristics
STP16DP05
3
Electrical characteristics
Table 7.
Electrical characteristics
(VDD = 3.3 V to 5 V, T = 25 °C, unless otherwise specified.)
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
VIH
Input voltage high level
0.7VDD
VDD
V
VIL
Input voltage low level
GND
0.3VDD
V
IOH
Output leakage current
VOH = 20 V
10
µA
VOL
Output voltage
(Serial-OUT)
IOL = 1 mA
0.4
V
VOH
Output voltage
(Serial-OUT)
IOH = -1 mA
IOL1
VOH -VDD = -0.4 V
V
VO = 0.3 V, Rext = 3.9 kΩ
4.25
5
5.75
VO = 0.3 V, Rext = 970 Ω
19
20
21
VO = 1.3 V, Rext = 190 Ω
96
100
104
VO = 0.3 VREXT = 3.9 kΩ
±5
±8
VO = 0.3 VREXT = 970 Ω
± 1.5
±3
VO = 1.3 VREXT =190 Ω
± 1.2
±3
150
300
600
KΩ
100
200
400
KΩ
REXT = 970
OUT 0 to 15 = OFF
4
5
IDD(OFF2)
REXT = 240
OUT 0 to 15 = OFF
11.2
13.5
IDD(ON1)
REXT = 970
OUT 0 to 15 = ON
4.5
5
REXT = 240
OUT 0 to 15 = ON
11.7
13.5
IOL2
Output current
IOL3
∆IOL1
∆IOL2
∆IOL3
RSIN(up)
Output current error
between bit
(All Output ON)
Pull-up resistor
RSIN(down) Pull-down resistor
IDD(OFF1)
mA
%
Supply current (OFF)
mA
Supply current (ON)
IDD(ON2)
Thermal
Thermal protection (1)
1. Guaranteed by desing (not tested)
The thermal protection switches OFF only the outputs current
6/29
170
°C
STP16DP05
Table 8.
Symbol
Electrical characteristics
Switching characteristics (VDD = 5 V, T = 25 °C, unless otherwise specified.)
Parameter
Test conditions
Min
Typ
Max
VDD = 3.3 V
70
105
VDD = 5 V
45
65
tPLH1
Propagation delay time,
CLK-OUTn, LE\DM1 = H,
OE\DM2 = L
Propagation delay time,
LE\DM1 -OUTn,
OE\DM2 = L
VDD = 3.3 V
61
90
tPLH2
VDD = 5 V
41
60
Propagation delay time,
OE\DM2-OUTn,
LE\DM1 = H
VDD = 3.3 V
69
105
tPLH3
VDD = 5 V
50
70
Propagation delay time,
CLK-SDO
VDD = 3.3 V
14
20
tPLH
VDD = 5 V
8
12
Propagation delay time,
CLK-OUTn, LE\DM1 = H,
OE\DM2 = L
VDD = 3.3 V
34
50
tPHL1
VDD = 5 V
23
35
Propagation delay time,
LE\DM1 -OUTn,
OE\DM2 = L
VDD = 3.3 V
27
40
tPHL2
VDD = 5 V
22
32
Propagation delay time,
OE\DM2-OUTn,
LE\DM1 = H
VDD = 3.3 V
23
35
tPHL3
VDD = 5 V
20
30
Propagation delay time,
CLK-SDO
VDD = 3.3 V
15
25
tPHL
VDD = 5 V
9
15
Output rise time
10~90% of voltage
waveform
VDD = 3.3 V
42
65
tON
VDD = 5 V
35
55
Output fall time
90~10% of voltage
waveform
VDD = 3.3 V
10
16
tOFF
VDD = 5 V
9
14
Unit
ns
ns
ns
VDD = 3.3 V
VIL = GND
IO = 20 mA
REXT = 1 KΩ
VIH = VDD
CL = 10 pF
VL = 3.0 V
RL = 60 Ω
ns
ns
ns
ns
ns
ns
ns
tr
CLK rise time (1)
5000
ns
tf
CLK fall time (1)
5000
ns
1. In order to achieve high cascade data transfer, please consider tr/tf timings carefully.
7/29
Equivalent circuit and outputs
4
8/29
Equivalent circuit and outputs
Figure 2.
OE\DM2 terminal
Figure 3.
LE\DM1 terminal
Figure 4.
CLK, SDI terminal
STP16DP05
STP16DP05
Equivalent circuit and outputs
Figure 5.
SDO terminal
Figure 6.
Block diagram
9/29
Timing diagrams
5
STP16DP05
Timing diagrams
Table 9.
CLOCK
Note:
Truth table
LE\DM1
OE\DM2
SERIAL-IN
OUT0 ............. OUT7 ................ OUT15
SDO
H
L
Dn
Dn ..... Dn - 7 ..... Dn -15
Dn - 15
L
L
Dn + 1
No change
Dn - 14
H
L
Dn + 2
Dn + 2 ..... Dn - 5 ..... Dn -13
Dn - 13
X
L
Dn + 3
Dn + 2 ..... Dn - 5 ..... Dn -13
Dn - 13
X
H
Dn + 3
OFF
Dn - 13
OUTn = ON when Dn = H OUTn = OFF when Dn = L
Figure 7.
Timing diagram
LE\DM1
OE\DM2
Note:
10/29
The latches circuit holds data when the LE\DM1 terminal is Low.
1
When LE\DM1 terminal is at High level, latch circuit hold the data it passes from the input to
the output.
2
When OE\DM2 terminal is at Low level, output terminals OUT0 to OUT15 respond to the
data, either ON or OFF.
3
When OE\DM2 terminal is at High level, it switches off all the data on the output terminal.
STP16DP05
Timing diagrams
Figure 8.
Clock, serial-in, serial-out
Figure 9.
Clock, serial-in, latch, enable, outputs
LE\DM1
OE\DM2
11/29
Timing diagrams
Figure 10. Outputs
12/29
STP16DP05
STP16DP05
6
Typical characteristics
Typical characteristics
Figure 11. Output current-REXT resistor
Table 10.
Output current-REXT resistor
Rext (Ω)
Output current (mA)
976
20
780
25
652
30
560
35
488
40
433
45
389
50
354
55
325
60
300
65
278
70
259
75
241
80
229
85
215
90
13/29
Typical characteristics
STP16DP05
Conditions:
Temperature = 25 °C, VDD = 3.3 V; 5.0 V, ISET = 3 mA; 5 mA; 10 mA; 20 mA; 50 mA; 80 mA.
Vdrop (mV)
Figure 12. ISET vs drop out voltage (Vdrop)
800
700
600
500
400
300
200
100
0
Avg @ 3.0V
Avg @ 5.0V
0
20
40
60
80
Iset mA)
Table 11.
14/29
ISET vs drop out voltage (Vdrop)
Iout (mA)
Avg @ 3.0 V
Avg @ 5.0 V
3
19.33
22.66
5
36.67
40.33
10
77.33
80
20
158.67
157.33
50
406
406
80
692
668
STP16DP05
Typical characteristics
Figure 13. IDD ON\OFF
14
12
Idd (mA)
10
8
IddON Avg @ 5.5V
IddON Avg @ 3.6V
6
IddOFF Avg @ 5.5V
4
IddOFF Avg @ 3.6V
2
0
0
10
20
30
40 50
Iset (mA)
60
70
80
90
Figure 14. Power dissipation vs temperature package
Note:
The exposed pad should be soldered to the PBC to realize the thermal benefits.
15/29
Detection mode functionality
STP16DP05
7
Detection mode functionality
7.1
Phase one: “entering in detection mode“
From the “normal mode” condition the device can switch to the “error mode“ by a logic
sequence on the OE\DM2 and LE/DM1 pins as showed in the following table and diagram:
Table 12.
Entering in detection truth table
CLK
1°
2°
3°
4°
5°
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
H
L
Figure 15. Entering in detection timing diagram
After these five CLK cycles the device goes into the “error detection mode“ and at the 6th
rise front of CLK the SDI data are ready for the sampling.
16/29
STP16DP05
7.2
Detection mode functionality
Phase two: “error detection”
The 16 data bits must be set “1“ in order to set ON all the outputs during the detection. The
data are latched by LE/DM1 and after that the outputs are ready for the detection process.
When the Micro controller switches the OE\DM2 to LOW, the device drives the LEDs in
order to analyze if an OPEN or SHORT condition has occurred.
Figure 16. Detection diagram
The LEDs status will be detected at least in 1 microsecond and after this time the
microcontroller sets OE\DM2 in HIGH state and the output data detection result will go to
the microprocessor via SDO.
Detection mode and normal mode use both the same format data. As soon as all the
detection data bits are available on the serial line, the device may go back to normal mode
of operation. To re-detect the status the device must go back in normal mode and reentering in error detection mode .
17/29
Detection mode functionality
Figure 17. Timing example for open and/or short detection
18/29
STP16DP05
STP16DP05
7.3
Detection mode functionality
Phase three: “resuming to normal mode”
The sequence for re-entering in normal mode is showed in the following Table and diagram:
Figure 18. Resuming to normal mode timing diagram
CLK
1°
2°
3°
4°
5°
OE/DM2
H
L
H
H
H
LE/DM1
L
L
L
L
L
Note:
For proper device operation the "Entering in detection" sequence must be follow by a
"Resume Mode" sequence, it is not possible to insert consecutive equal sequence.
7.4
Error detection conditions
Table 13.
Note:
Detection conditions (VDD = 3.3 to 5 V temperature range -40 to 125 °C)
SW-1 or
SW-3b
Open line or output
==> IODEC ≤ 0.5 x IO
short to GND detected
No error detected
==> IODEC ≥ 0.5 x IO
SW-2 or
SW-3a
Short on LED or short
==> VO ≥ 2.4 V
to V-LED detected
No error detected
==> VO ≤ 2.2 V
Where: IO = the output current programmed by the REXT , IODEC = the detected output
current in detection mode
Figure 19. Detection circuit
16
STP16DP05
19/29
Detection mode functionality
STP16DP05
Figure 20. Error detection sequence
16 CLK pulse are required to
load the data setting 1 into
shift register
LE and OE Key
Sequence
necessary to Enter
in EDM
20/29
The LE pulse
latch the data
loaded during the
previous state
During the error
detection are
necessary at least
2 CLK signal plus
oneat the end
Every CLK pulse shows the results of
single Output results:Out15;14; 13 etc. etc
After OE signal turn High the
SDO pin show the results of
Error Detection (Open or
Short in this case)
The OE Pulse put
the device from
EDM to Normal
Mode
STP16DP05
8
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
Table 14.
QSOP-24 mechanical data
mm.
inch
Dim.
Min
Typ
Max
Min
Typ
Max
A
1.54
1.62
1.73
0.061
0.064
0.068
A1
0.1
0.15
0.25
0.004
0.006
0.010
A2
1.47
0.058
b
0.31
0.2
0.012
0.008
c
0.254
0.17
0.010
0.007
D
8.56
8.66
8.76
0.337
0.341
0.345
E
5.8
6
6.2
0.228
0.236
0.244
E1
3.8
3.91
4.01
0.150
0.154
0.158
e
0.635
0.025
L
0.4
0.635
0.89
0.016
0.025
0.035
h
0.25
0.33
0.41
0.010
0.013
0.016
<
8°
0°
21/29
Package mechanical data
Figure 21. QSOP-24 package dimensions
22/29
STP16DP05
STP16DP05
Package mechanical data
Table 15.
TSSOP24 mechanical data
mm.
inch
Dim.
Min
Typ
A
A1
Max
Min
Typ
1.1
0.05
A2
0.15
Max
0.043
0.002
0.9
0.006
0.035
b
0.19
0.30
0.0075
0.0118
c
0.09
0.20
0.0035
0.0079
D
7.7
7.9
0.303
0.311
E
4.3
4.5
0.169
0.177
e
0.65 BSC
0.0256 BSC
H
6.25
6.5
0.246
0.256
K
0°
8°
0°
8°
L
0.50
0.70
0.020
0.028
Figure 22. TSSOP24 package dimensions
23/29
Package mechanical data
Table 16.
STP16DP05
Tape and reel TSSOP24
mm.
inch
Dim.
Min
A
Max
Min
330
13.2
Typ
Max
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
0.504
22.4
0.519
0.882
Ao
6.8
7
0.268
0.276
Bo
8.2
8.4
0.323
0.331
Ko
1.7
1.9
0.067
0.075
Po
3.9
4.1
0.153
0.161
P
11.9
12.1
0.468
0.476
Figure 23. Reel dimensions
24/29
Typ
STP16DP05
Package mechanical data
Table 17.
SO-24 mechanical data
mm.
inch
Dim.
Min
Typ
A
a1
Max
Min
Typ
2.65
0.1
0.104
0.2
a2
Max
0.004
0.008
2.45
0.096
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.012
C
0.5
0.020
c1
45°(typ.)
D
15.20
15.60
0.598
0.614
E
10.00
10.65
0.393
0.419
e
1.27
0.050
e3
13.97
0.550
F
7.40
7.60
0.291
0.300
L
0.50
1.27
0.020
0.050
S
°(max.) 8
Figure 24. SO-24 package dimensions
25/29
Package mechanical data
Table 18.
STP16DP05
Tape and reel SO-24
mm.
inch
Dim.
Min
A
Max
Min
330
13.2
Typ
Max
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
0.504
30.4
0.519
1.197
Ao
10.8
11.0
0.425
0.433
Bo
15.7
15.9
0.618
0.626
Ko
2.9
3.1
0.114
0.122
Po
3.9
4.1
0.153
0.161
P
11.9
12.1
0.468
0.476
Figure 25. Reel dimensions
26/29
Typ
STP16DP05
Package mechanical data
Table 19.
TSSOP24 exposed pad
mm
inch
Dim.
Min
Typ
Max
A
1.2
A1
0.15
A2
0.8
b
Typ
Max
0.047
0.004
0.006
0.039
0.041
1.05
0.031
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0089
D
7.7
7.8
7.9
0.303
0.307
0.311
D1
4.7
5.0
5.3
0.185
0.197
0.209
E
6.2
6.4
6.6
0.244
0.252
0.260
E1
4.3
4.4
4.5
0.169
0.173
0.177
E2
2.9
3.2
3.5
0.114
0.126
0.138
e
1
Min
0.65
K
0°
L
0.45
0.60
0.0256
8°
0°
0.75
0.018
8°
0.024
0.030
Figure 26. TSSOP24 dimensions
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Revision history
9
STP16DP05
Revision history
Table 20.
28/29
Document revision history
Date
Revision
Changes
9-Jan-2007
1
First release
21-May-2007
2
Updated Table 7 on page 6
10-Jul-2007
3
Updated Table 9: Truth table on page 10
28-Feb-2008
4
Updated Table 15: TSSOP24 exposed-pad on page 23
Added QSOP-24 package information Table 14 and Figure 21
on page 22
STP16DP05
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