STP1612PW05 16-channel LED driver with 16-bit PWM, 8-bit gain and full LED error detection Preliminary data Features ■ 16 constant current output channels ■ Supply voltage: 3.3 V or 5 V ■ Two PWM selectable counters 12/16-bit of grayscale ■ Selectable enhanced PWM for ghost effect reduction ■ Open and short LED detection ■ 8-bit current gain control by means of 256 steps in two selectable ranges ■ Single resistor to set the current from 3 mA to 60 mA ■ Programmable progressive output delay ■ Thermal protection and thermal flag ■ UVLO ■ Schmitt trigger input ■ Selectable 16-bit or 256-bit serial data-in format ■ Max clock frequency: 30 MHz ■ ESD protection 2.5 kV HBM, 200 V MM ■ Drop-in compatible with STP16CP\S\DP05 series ■ Available in high thermal efficiency TSSOP exposed pad Applications ■ Video display LED panels ■ RGB backlighting ■ Special lighting Table 1. Device summary QFN-24 SO-24 TSSOP24 TSSOP24 exposed pad Description The STP1612PW05 is a 16-channel constant current sink LED driver. The maximum output current value for all the 16 channels is set by a single resistor from 3 mA to 60 mA. The device features 8-bit gain (256 steps) for global LED brightness adjustment with two selectable ranges. This function is accessible via a serial interface. The device has an individual adjustable PWM brightness control for each output channel. The PWM counters are selectable via a serial interface with 4096 or 65536 steps (12 or 16 bit). The STP1612PW05 also provides enhanced pulse-width modulation counting algorithms called e-PWM to reduce flickering effects (ghost visual effects) improving the overall image quality. The device has a dual size 16-bit or 256-bit shift register. All the control and the shift register read back data are accessible via serial interface. The STP1612PW05 has the capability to detect open and short LED failure and overtemperature, reporting the status through SPI line. The device guarantees a 20 V output driving capability, allowing the user to connect more LEDs in series. Order code Package Packaging STP1612PW05QTR QFN-24 4000 parts per reel STP1612PW05MTR SO-24 1000 parts per reel STP1612PW05TTR TSSOP24 2500 parts per reel STP1612PW05XTTR TSSOP24 exposed pad 2500 parts per reel December 2009 Doc ID 15819 Rev 4 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/35 www.st.com 35 Contents STP1612PW05 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 3 Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 Definition of configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 Grey scales data loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9 Setting the PWM gray scale counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.1 PWM data synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.2 Synchronization for PWM counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10 Error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11 Setting output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 12 Current gain adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 13 Delay time of staggered output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 14 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 15 Time-out alert of GCLK disconnection . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/35 Doc ID 15819 Rev 4 STP1612PW05 Contents 16 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Doc ID 15819 Rev 4 3/35 Block diagram Block diagram Block diagram GND SDI CLK LE SDO VDD UVLO & POR Serial interface CTRL command and CTRL logic 16-bit Configuration Register R-EXT Dual range gain 7-bit DAC Gradual outputs delay TSD Shift register dual size mode (16 or 256 bit) PWM data buffer (16x16 bit) Open/short error detection PWM and e-PWM 12/16 bit counter and SYNC control PWCLK 4/35 Doc ID 15819 Rev 4 1----------16 Figure 1. Constant current output channels 1 STP1612PW05 STP1612PW05 2 Summary description Summary description Table 2. Typical current accuracy at 5 V Current accuracy Output voltage Output current Between bits Between ICs ≥ 1.0 ± 1.5% ± 6% 15 to 60 ≥ 0,2 ± 1.5% ± 6% 3 to 15 Table 3. VDD temp. 5V 25 °C VDD temp. 3.3 V 25 °C Typical current accuracy at 3.3 V Current accuracy Output voltage Output current Between bits Between ICs ≥ 1.0 ± 1.5% ± 6% 15 to 60 ≥ 0,3 ± 1.5% ± 6% 3 to 15 Doc ID 15819 Rev 4 5/35 Summary description Pin connection and description Note: SDO PWCLK R-EXT 17 OUT14 OUT1 3 16 OUT13 OUT2 4 15 OUT12 OUT3 5 14 OUT11 OUT4 6 OUT10 OUT9 GND 8 OUT8 7 13 9 10 11 12 OUT7 2 OUT0 OUT5 OUT15 1 OUT6 24 23 22 21 20 19 18 LE The exposed pad should be electrically connected to a metal land electrically isolated or connected to ground Table 4. 6/35 VDD Pin connection CLK Figure 2. SDI 2.1 STP1612PW05 Pin description Pin n° Symbol Name and function 1 GND Ground terminal 2 SDI Serial data input terminal 3 CLK Clock input terminal used to shift data on rising edge and carries command information when LE is asserted. 4 LE 5-20 OUT 0-15 21 PWCLK 22 SDO 23 R-EXT 24 VDD Data strobe terminal and controlling command with CLK Output terminals Gray scale clock terminal. Reference clock for grey scale PWM counter. Serial data out terminal Input terminal of an external resistor for constant current programing Supply voltage terminal Doc ID 15819 Rev 4 STP1612PW05 Electrical ratings 3 Electrical ratings 3.1 Absolute maximum ratings Stressing the device above the rating listed in the Table 5 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5. Absolute maximum ratings Symbol Parameter Value Unit VDD Supply voltage 0 to 7 V VO Output voltage -0.5 to 20 V IO Output current 60 mA VI Input voltage -0.4 to VDD V 1300 mA 50 MHz -40 to + 170 °C Value Unit Operating free-air temperature range -40 to +125 °C Operating thermal junction temperature range -40 to +150 °C Storage temperature range -55 to +150 °C SO-24 42.7 °C/W TSSOP24 55 °C/W 37.5 °C/W 55 °C/W IGND GND terminal current fCLK Clock frequency TJ Junction temperature range (1) 1. Such absolute value is based on the thermal shutdown protection. 3.2 Thermal data Table 6. Symbol TA TJ-OPR TSTG RthJA Thermal data Parameter Thermal resistance junctionambient (1) TSSOP24(2) Exposed pad QFN-24 1. According to Jedec standard 51-7B 2. The exposed pad should be soldered directly to the PCB to realize the thermal benefits. Doc ID 15819 Rev 4 7/35 Electrical ratings 3.3 STP1612PW05 Recommended operating conditions Table 7. Symbol Recommended operating conditions at 25 °C, VDD = 5 V Parameter Test conditions Min. Typ. Max. Unit 3.0 - 5.5 V - 20 V - 60 mA VDD Supply voltage VO Output voltage IO Output current OUTn IOH Output current SERIAL-OUT - +1 mA IOL Output current SERIAL-OUT - -1 mA VIH Input voltage 0.7 VDD - VDD V VIL Input voltage GND - 0.3 VDD V 3 twLAT LE pulse width 20 - ns twCLK CLK pulse width 10 - ns twEN PWCLK pulse width 20 - ns 5 - ns 5 - ns 5 - ns tSETUP(D) Setup time for DATA VDD = 3.3 V to 5.0 V tHOLD(D) Hold time for DATA tSETUP(L) Setup time for LATCH fCLK Clock frequency Cascade operation (1) - 30 MHz 1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please considered the timings carefully. 8/35 Doc ID 15819 Rev 4 STP1612PW05 4 Electrical characteristics Electrical characteristics TA = 25 °C (Unless otherwise specified) Table 8. Symbol Electrical characteristics (VDD = 5.0 V) Characteristics VDD Supply voltage VO Maximum output voltage Min. Typ. Max. Unit 4.5 5.0 5.5 V 20 V 60 mA SDO, TA = - 40 ~ 125 °C -8 mA SDO, TA = - 40 ~ 125 °C 8 mA OUT0 ~ OUT15 VO = 1.2V IOUT IOH Test conditions Output current IOL 5 VIH Input voltage “H” level TA = - 40 ~ 125 °C 0.7 * VDD VDD V VIL Input voltage “L” level TA = - 40 ~ 125 °C GND 0.3 * VDD V IOH Output leakage current VO = 20 V 10 μA IOL = + 1.0 mA, TA = - 40 ~ 125 °C 0.4 V VOL Output voltage SDO VOH IOH = -1.0 mA TA = - 40 ~ 125 °C VDD 0.4 V dIOUT1 Current skew (Channel) IOUT = 10 mA VO = 1.0 V, Rext = 69 kΩ ± 1.5 ± 3.0 % dIOUT2 Current skew (IC) IOUT = 10 mA VO = 1.0 V, Rext = 69 kΩ ± 3.0 ± 6.0 % %/dVO Output current vs. output voltage regulation VO within 1.0 V and 3.0 V, Rext = 34.7 kΩ @ 20 mA ± 0.1 ± 0.5 %/V %/dVDD Output current vs. supply voltage regulation VDD within 4.5 V and 5.5 V ± 1.0 ± 5.0 %/V 0.15 0.20 V 150 200 250 kΩ 7 10 13 IO = 20 mA, OUT0 ~ OUT15 = Off 6.6 9.5 12 IDD(off) 3 IO = 60 mA, OUT0 ~ OUT15 = Off 9 12.7 16.5 IDD(on) 1 IO = 20 mA, OUT0 ~ OUT15 = On 6.6 9.4 12.2 IO = 60 mA, OUT0 ~ OUT15 = On 8 11.5 14.9 VO,TH RIN(down) Pull-down resistor Rext = Open, IDD(off) 1 IDD(off) 2 IDD(on) 2 LE OUT0 ~ OUT15 = Off Supply current “Off” Supply current “On” Doc ID 15819 Rev 4 mA 9/35 Electrical characteristics Table 9. Symbol STP1612PW05 Electrical characteristics (VDD = 3.3 V) Characteristics VDD Supply voltage VO Sustaining voltage at OUT Ports Test conditions Typ. Max. Unit 3.0 3.3 3.6 V 20 V 60 mA SDO, TA = -40 ~ 125 °C -1.0 mA SDO TA = -40 ~ 125 °C 1.0 mA OUT0 ~ OUT15 IOUT IOH Min. VO = 1.2 V Output current IOL 5 VIH Input voltage “H” level TA = - 40 ~ 125 °C 0.7 * VDD VDD V VIL Input voltage “L” level TA = - 40 ~ 125 °C GND 0.3 * VDD V IOH Output leakage current VO = 17.0 V 0.5 μA IOL = +1.0 mA, TA = -40 ~ 125 °C 0.4 V VOL Output voltage SDO IOH = -1.0 mA TA = -40 ~ 125 °C VOH 2.9 V dIOUT1 Current skew (channel) IOUT = 10.5 mA, VO = 1.0 V, Rext = 69 kΩ at 10 mA ± 1.5 ± 3.0 % dIOUT2 Current skew (IC) IOUT = 10.8 mA, VO = 1.0 V, Rext = 69 kΩ at 10 mA ± 3.0 ± 6.0 % %/dVO Output current vs. VO within 1.0 V and 3.0 V, output voltage regulation Rext = 34.7 kΩ at 20 mA ± 0.1 ± 0.5 %/V ± 1.0 ± 5.0 %/V 200 250 kΩ Output current vs. %/dVDD supply voltage regulation VDD within 3.0 V and 3.6 V RIN(down) Pull-down resistor LE 150 IDD(off) 1 Rext = Open, OUT0 ~ OUT15 = Off 7.2 9.3 IDD(off) 2 Supply current “OFF” IO = 20 mA, OUT0 ~ OUT15 = Off 8.6 11 IDD(off) 3 IO = 60 mA, OUT0 ~ OUT15 = Off 11.7 15.2 IDD(on) 1 IO = 20 mA, OUT0 ~ OUT15 = On 29 37.7 IO = 60 mA, OUT0 ~ OUT15 = On 31.2 40 Supply current “ON” IDD(on) 2 10/35 Doc ID 15819 Rev 4 mA STP1612PW05 Electrical characteristics Figure 3. Test circuit for electrical characteristics IDD VDD IOUT V DD VIH,VIL .. . OUT0 SDI CLK Function Generator LE OUT15 IOL PWCLK SDO R - EXT GND I OH Logic input waveform VIH=VDD R ext V IL=GND Table 10. Symbol Switching characteristics (VDD = 5.0 V) TA = -40 ~ 125 °C Characteristics tSU0 tSU1 Setup time tSU2 tH0 Hold time tH1 Propagation delay time tPD2 tDL2 tDL3 tw( CLK) 1 ns LE ↓ – DCLK ↑ 5 ns CLK ↑ - SDI 3 ns CLK ↑ - LE ↓ 7 ns PWCLK-OUTn4 (1) SDO(2) OUTn4 + 2 (1) (1) LE Pulse width tw(PWCLK) Unit LE ↑ – DCLK ↑ OUTn4 +3 tw(L) Max. ns OUTn4 + 1 (1) Stagger delay time Typ. 1 LE – tDL1 Min. SDI - CLK ↑ CLK - SDO tPD0 tPD1 Conditions VDD = 5.0 V VIH = VDD VIL = GND Rext = 460 Ω VLED = 4.5 V RL = 152 Ω CL = 10 pF C1 = 100 nF C2 = 10 μF IO = 20 mA 30 40 100 30 ns ns 40 ns 40 ns 80 ns 120 ns 5 ns CLK 20 ns PWCLK 20 ns tON Output rise time of output ports 10 ns tOFF Output fall time of output ports 6 ns tEDD Error detection minimum duration (3) 1 µs 1. Refer to the timing waveform, where n = 0, 1, 2, 3. 2. In timing of “read configuration” and “read error status code”, the next CLK rising edge should be tPD2 after the falling edge of LE. 3. Refer to Figure 5 on page 13. Doc ID 15819 Rev 4 11/35 Electrical characteristics Table 11. Symbol STP1612PW05 Switching characteristics (VDD = 3.3 V) Characteristics Conditions Setup time tSU2 tH0 tPD1 tPD2 tDL1 tDL2 tDL3 tw(L) tw(CLK) Max. Unit 1 ns LE ↑ – DCLK ↑ 1 ns LE ↓ – DCLK ↑ 5 ns CLK ↑ - SDI 3 ns CLK ↑ - LE ↓ 7 ns Hold time tH1 tPD0 Typ. SDI - DCLK ↑ tSU0 tSU1 Min. CLK - SDO VDD = 3.3 V Propagation delay PWCLK-OUTn4(1) VIH = VDD time VIL = GND LE – SDO(2) Rext = 460 Ω VLED = 4.5 V OUTn4 + 1 (1) RL = 152 Ω Stagger delay OUTn4 + 2 (1) time CL = 10 pF OUTn4 +3 (1) C1 = 100 nF C2 = 10 μF LE 5 ns Pulse width CLK 20 ns PWCLK 20 ns tw(PWCLK) 45 40 120 45 ns ns 40 ns 40 ns 80 ns 120 ns tON Output rise time of output ports 11.6 ns tOFF Output fall time of output ports 7 ns tDEC Error detection duration 0.5 1 μs 1. Refer to the timing waveform Figure 4, where n = 0, 1, 2, 3. 2. In timing of “read configuration” and “read error status code”, the next CLK rising edge should be tPD2 after the falling edge of LE. Figure 4. Test circuit for switching characteristics V DD IDD C1 I OUT VIH,VIL Function Generator VDD .. . O UT0 SDI CLK LE RL CL O UT 15 RL P W CLK R - E XT GND SDO CL Logic input VL ED waveform VIH=VDD Rext VIL=G ND 12/35 Doc ID 15819 Rev 4 CL C2 STP1612PW05 5 Timing waveform Timing waveform Figure 5. Timing waveform PWCLK PWCLK PWCLK Doc ID 15819 Rev 4 13/35 Principle of operation 6 STP1612PW05 Principle of operation Table 12. Control command Signals combination 14/35 Description Command name LE Number of CLK rising edge when LE is asserted Data latch High 1 Global latch High 2 or 3 Buffer data are transferred to the comparators Read configuration High 4 or 5 Move out “configuration register” to the shift register Enable “error detection” High 6 or 7 Detect the status of each output’s LED Read “error status code” High 8 or 9 Move out “error status code” of 16 outputs to the shift registers Write configuration High 10 or 11 Serial data are transferred to the “configuration register” Reset to 16-bit shift register length High 12 or 13 Set to 16-bit the shift register length Doc ID 15819 Rev 4 The action after a falling edge of LE Serial data are transferred to the buffers STP1612PW05 Figure 6. Principle of operation Timing diagram $ATA,ATCH #,+ ,% -3" $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ 3$) 0REVIOUS$ATA 3$/ 'LOBAL,ATCH #,+ ,% -3" $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ 3$) 0REVIOUS$ATA 3$/ 2EAD#ONFIGURATION #,+ . . . . . . . . ,% & $ # ! % " 0REVIOUS$ATA 3$/ 7RITE#ONFIGURATION #,+ ,% 3$) & % # $ " ! 0REVIOUS$ATA 3$/ Doc ID 15819 Rev 4 . . . .EXT$ATA $ . $ . $ . .EXT$ATA $ $ $ . . . . .EXT$ATA & % $ 15/35 Definition of configuration register 7 STP1612PW05 Definition of configuration register Configuration register MSB F LSB E D C B A 9 8 7 6 5 4 3 2 1 0 Default value MSB LSB F E D X 0 1 Table 13. C B A 11 8 7 1 6 5 4 3 2 8’b10101011 1 0 0 0 Configuration register Bit Attribute Definition F Read/Write Shift register length E Read Thermal error flag D 9 Read/Write PWM counter: 16-bit or 12-bit Value Function 0 (default) Shift register length 0 = 16-bit,1 = 256-bit 0 (default) Safe (OK) 1 0 (default) Over temperature (>150 °C typ.) To set the gray scale mode (PWM): 0 = 12-bit 1 = 16-bit 00 64 times of MSB(1) 6-bit PWM counting plus once of LSB(1) 6-bit PWM counting 01 16 times of MSB 6-bit PWM counting by 1/4 PWCLK plus once of LSB 6-bit PWM counting 10 4 times of MSB 6-bit PWM counting by 1/16 PWCLK plus once of LSB 6-bit PWM counting C Read/Write PWM counting mode selection B 11 (default) PWM counting A Read/Write 9~2 Read/Write PWM data synchronization mode Current gain adjustment 0 Auto-synchronization 1 (default) Manual synchronization 00000000 ~ 8’b10101011 (default) 11111111 0 (default) Disable 1 0 Read/Write TSD thermal shutdown Time-out alert of Read/Write PWCLK disconnection 1 Enable (2) the output channel turn OFF if TTF > 150 °C 0 (default) Enable (3) 1 Disable 1. Please refer to “setting the PWM counting mode” section. 2. Please refer to “TSD” thermal error flag and thermal shutdown “section. 3. Please refer to “time-out alert of PWCLK disconnection” section. 16/35 Doc ID 15819 Rev 4 STP1612PW05 8 Grey scales data loading Grey scales data loading The STP1612PW05 is able to manage a gray-scale depth of 12 or 16 bits for each output, exploiting an e-PWM algorithm. The bit D of the configuration register is used to select the grey-scale loading. Its value can be set to “0” for 12 bits or “1” for 16 bits. By default, D is set to “0”. Loading of the data is performed through the serial input on a dedicated buffer and two different methods can be used. With both methods, the first incoming data packet is relative to the output 15; the following packet is relative to the output 14 and so on up to the output 0. If F=”0”, when a data packet has been loaded, the latch signal (LE) must become active for one CLK cycle (data latch). When the last data packet, relative to the output 0, has been loaded, the latch signal must be active for two CLK cycles (global latch) and all the data will be transferred to the e-PWM registers starting from the MSB. If F=”1” all data packets (12 or 16 bits x16) are loaded and then the global latch signal must be active and all the data will be transferred to the e-PWM registers starting from the MSB. Figure 7. Full timing for data loading Doc ID 15819 Rev 4 17/35 Setting the PWM gray scale counter 9 STP1612PW05 Setting the PWM gray scale counter STP1612PW05 provides a 12-bit or 16-bit PWM color depth. Each serial data input will be implemented according to the e-PWM algorithm. 9.1 PWM data synchronization STP1612PW05 defines the different counting algorithms that support e-PWM, technology, (scrambled PWM). With e-PWM, the total PWM cycles can be broken down into MSB (most significant bits) and LSB (least significant bits) of gray scale cycles, and the MSB information can be dithered across many refresh cycles to achieve overall same high bit resolution. STP1612PW05 also allows changing different counting algorithms and provides the best output linearity when there are fewer transitions of output. Figure 8. 12-bit e-PWM operation example PWCLK PWCLK PWCLK PWCLK PWCLK 18/35 Doc ID 15819 Rev 4 STP1612PW05 9.2 Setting the PWM gray scale counter Synchronization for PWM counting The data synchronization between the incoming data flow and the output channels is managed through the bit A within the configuration register. If the bit A is set to “0” the device performs itself the data synchronization: when all the new data are loaded with a “global latch”, the device wait until all the PWM counter completes the counting cycle before updating them with the new data, at the next CLK rising edge. Conversely, if bit A is set to “1” (default), the data synchronization is not performed by the device and is managed by the microcontroller, which has to take care of the data and signals. If this is not done, there might be artefacts on the output image. Figure 9. Synchronization for PWM counting CLK PWCLK Figure 10. Without synchronization for PWM counting CLK PWCLK Doc ID 15819 Rev 4 19/35 Error detection conditions 10 STP1612PW05 Error detection conditions The STP1612PW05 can detect open channels (OD) and LED short-circuits (SD). The detection circuitry performs open- and short-circuit detection simultaneously and the image quality will not be impacted since the test duration is short (0.5 µs typ). To perform the open-circuit, short-circuit error detection a channel must be on, the command “enable error detection” starts the detection. After 0.5 µs (typ) the command “read error status code” allows to get the status from the serial output (SDO). Table 14. Note: Detection conditions (VDD = 3.3 to 5 V temp. range -40 to 125 °C) SW-1 or SW-3b Open line or output short to GND detected ==> IODEC ≤ 0.5 x IO SW-2 or SW-3a Short on LED or short to V-LED detected ==> VO ≥ 2.3 V Where: IO = the output current programmed by the REXT, IODEC = the detected output current in detection mode Figure 11. Detection circuit 16 STP1612PW05 20/35 Doc ID 15819 Rev 4 STP1612PW05 Setting output current The output current (IOUT) is set by an external resistor, Rext. It is calculated from the equation: VR-EXT = 1.24 x G; IOUT = (VR-EXT/Rext) x 560 Whereas Rext is the resistance of the external resistor connected to R-EXT terminal and VR-EXT is its voltage. G is the digital current gain, which is set by the bit9 – bit2 of the configuration register. The default value of G is 1. For your information, the output current is about 20 mA when Rext = 34.70 kΩ and 10 mA when Rext = 69.6 kΩ if G is set to default value 1. The formula and setting for G are described in next section. Figure 12. Rext vs output current Rext (kOhm) 11 Setting output current 275 250 225 200 175 150 125 100 75 50 25 0 3 5 10 20 30 50 60 80 Iout (mA) Table 15. Rext vs output current (1) Iout (mA) Rext (kΩ) 3 238.2 5 142.2 10 69.6 20 34.70 30 22.94 50 13.72 60 11.40 80 8.63 1. TA = 25 °C, Vdd = 3.3 V; 5.0 V, VLed = 3.0 V, Vdrop = 1.5 V, HC = 0101011 (default) Doc ID 15819 Rev 4 21/35 Current gain adjustment 12 STP1612PW05 Current gain adjustment Figure 13. Gain vs DA6 - DA0 The bit 9 to bit 2 of the configuration register set the gain of output current, i.e., G. Being 8bit in total, ranging from 8’b00000000 to 8’b11111111, these bits allow the user to set the output current gain up to 256 levels. These bits can be further defined in the configuration register as follows: Configuration register MSB LSB F E D C B A 9 8 7 6 5 4 3 2 1 0 - - - - - - HC DA6 DA5 DA4 DA3 DA2 DA1 DA0 - - 1. Bit 9 is HC bit. The setting is in the low current range when HC=0, and in the high current range when HC=1. 2. Bit 8 to bit 2 are DA6 ~ DA0. The relationship between these bits and current gain G is: HC = 1, D = (256G-128)/3 HC = 0, D = (1024G-128)/3 and D in the above decimal numeration can be converted to its equivalent in binary form by the following equation: D = DA6x26 + DA5x25 + DA4x24 + DA3x23 + DA2x22 + DA1x21 + DA0x20 In other words, these bits can be looked as a floating number with 1-bit exponent HC and 7bit mantissa DA6~DA0. 22/35 Doc ID 15819 Rev 4 STP1612PW05 Delay time of staggered output For example, HC = 1, G = 1.25, D = (256x1.25-128)/3 = 64 the D in binary form would be: D = 64 = 1x26+0x25+0x24+0x23+0x22+0x21+0x20 The bit 9 to bit 2 of the configuration register are set to 8’b1100,0000. 13 Delay time of staggered output This feature prevents large inrush current from the power line and reduces the bypass capacitors. The outputs are organized in four groups OUT4n, OUT4n+1, OUTn4+2, OUT4n+3 and each group has 40 ns delay between the previous one. E.g.: OUT4n has no delay, OUTn4+1 has 40ns delay, OUTn4+2 has 80ns delay, OUTn4+3 has 120 ns delay. 14 Thermal protection Thermal flag provides an indication about the status of the junction temperature. When the junction temperature reaches 150 °C the bit E of the configuration register is set to “1”, signaling dangerous operating condition. This flag is useful when thermal shutdown function is disabled. The thermal shutdown function, if activated by configuration register, turns-off all output channels if the junction exceeds 150 °C. As soon as the junction temperature is below 140 °C the outputs channels will be turned ON. In thermal shutdown mode, the digital core is active and data flow is guaranteed. Doc ID 15819 Rev 4 23/35 Time-out alert of GCLK disconnection 15 STP1612PW05 Time-out alert of GCLK disconnection When the PWCLK signal is disconnected for around 1 second, all output ports will be turned off automatically. This function will protect the LED display system from staying ON indefinitely and prevent excessive current from damaging the power system. The default is set to ‘enable” when bit “0” is 0. When the PWCLK is active again and new serial data are moved in, the driver resumes to work after resetting the internal counters and comparators. Figure 14. Time-out alert application scheme PWCLK 500K STP1612PW05 24/35 STP1612PW05 Doc ID 15819 Rev 4 STP1612PW05 STP1612PW05 STP1612PW05 16 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 16. TSSOP24 mechanical data mm. inch Dim. Min. Typ A A1 Max. Min. Typ. 1.1 0.05 A2 0.15 Max. 0.043 0.002 0.9 0.006 0.035 b 0.19 0.30 0.0075 0.0118 c 0.09 0.20 0.0035 0.0079 D 7.7 7.9 0.303 0.311 E 4.3 4.5 0.169 0.177 e 0.65 BSC 0.0256 BSC H 6.25 6.5 0.246 0.256 K 0° 8° 0° 8° L 0.50 0.70 0.020 0.028 Figure 15. TSSOP24 package dimensions Doc ID 15819 Rev 4 25/35 Package mechanical data Table 17. STP1612PW05 TSSOP24 tape and reel mm. inch Dim. Min. A Typ Max. - 330 13.2 Typ. Max. - 12.992 0.504 - 0.519 C 12.8 - D 20.2 - 0.795 - N 60 - 2.362 - T - 22.4 - 0.882 Ao 6.8 - 7 0.268 - 0.276 Bo 8.2 - 8.4 0.323 - 0.331 Ko 1.7 - 1.9 0.067 - 0.075 Po 3.9 - 4.1 0.153 - 0.161 P 11.9 - 12.1 0.468 - 0.476 Figure 16. TSSOP24 reel dimensions 26/35 Min. Doc ID 15819 Rev 4 STP1612PW05 Package mechanical data Table 18. SO-24 mechanical data mm. inch Dim. Min. Typ A a1 Max. Min. Typ. 2.65 0.1 0.104 0.2 a2 Max. 0.004 0.008 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 C 0.5 0.020 c1 45°(typ.) D 15.20 15.60 0.598 0.614 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 13.97 0.550 F 7.40 7.60 0.291 0.300 L 0.50 1.27 0.020 0.050 S °(max.) 8 Doc ID 15819 Rev 4 27/35 Package mechanical data STP1612PW05 Figure 17. SO-24 package dimensions 28/35 Doc ID 15819 Rev 4 STP1612PW05 Package mechanical data Table 19. SO-24 tape and reel mm. inch Dim. Min. A Typ Max. - 330 13.2 Min. Typ. Max. - 12.992 0.504 - 0.519 C 12.8 - D 20.2 - 0.795 - N 60 - 2.362 - T - 30.4 - 1.197 Ao 10.8 - 11.0 0.425 - 0.433 Bo 15.7 - 15.9 0.618 - 0.626 Ko 2.9 - 3.1 0.114 - 0.122 Po 3.9 - 4.1 0.153 - 0.161 P 11.9 - 12.1 0.468 - 0.476 Figure 18. SO-24 reel dimensions Doc ID 15819 Rev 4 29/35 Package mechanical data Table 20. STP1612PW05 TSSOP24 exposed pad mm inch Dim. Min. Typ. Max. A 1.2 A1 0.15 A2 0.8 b Max. 0.047 0.004 0.006 0.039 0.041 0.031 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 7.7 7.8 7.9 0.303 0.307 0.311 D1 4.7 5.0 5.3 0.185 0.197 0.209 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.5 0.169 0.173 0.177 E2 2.9 3.2 3.5 0.114 0.126 0.138 0.65 K 0° L 0.45 0.60 0.0256 8° 0° 0.75 0.018 Figure 19. TSSOP24 package dimensions 30/35 Typ. 1.05 e 1 Min. Doc ID 15819 Rev 4 8° 0.024 0.030 STP1612PW05 Package mechanical data Table 21. QFN24 (4x4) mechanical data mm. mils Dim. Min. Typ A Max. Min. Typ. 1.00 Max. 39.4 A1 0.00 0.05 0.0 2.0 b 0.18 0.30 7.1 11.8 D 3.9 4.1 153.5 161.4 D2 2.6 2.8 76.8 88.6 E 3.9 4.1 153.5 161.4 E2 2.6 2.8 76.8 88.6 e L 0.50 0.40 19.7 0.60 Doc ID 15819 Rev 4 15.7 23.6 31/35 Package mechanical data STP1612PW05 Figure 20. QFN24 (4x4) mechanical drawing 32/35 Doc ID 15819 Rev 4 STP1612PW05 Package mechanical data Tape & Reel QFNxx/DFNxx (4x4) MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. 330 C 12.8 D 20.2 N 99 13.2 MAX. 12.992 0.504 0.519 0.795 101 T 3.898 3.976 14.4 0.567 Ao 4.35 0.171 Bo 4.35 0.171 Ko 1.1 0.043 Po 4 0.157 P 8 0.315 Doc ID 15819 Rev 4 33/35 Revision history 17 STP1612PW05 Revision history Table 22. 34/35 Document revision history Date Revision Changes 17-Jun-2009 1 Initial release. 10-Aug-2009 2 Updated Section 9.2 on page 19 and Table 12 on page 14 29-Oct-2009 3 Updated: Figure 2 on page 6 and Table 21 on page 31 Added: Figure 14 on page 24 18-Dec-2009 4 Updated Section 11 on page 21 Doc ID 15819 Rev 4 STP1612PW05 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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