STMICROELECTRONICS STP24DP05BTR

STP24DP05
24-bit constant current
LED sink driver with output error detection
Features
■
Low voltage power supply down to 3 V
■
8 x 3 constant current output channels
■
Adjustable output current through external
resistors
■
Short and open output error detection
■
Serial data IN/Parallel data OUT
■
Shift register data flow registers control
■
Accepts 3.3 V and 5 V micro driver
■
Output current: 5-80 mA
■
25 MHz clock frequency
■
High thermal efficiency package
Description
The STP24DP05 is a monolithic, low voltage, low
current power 24-bit shift register designed for
LED panel displays. The device contains a
8 x 3-bit serial-in, parallel-out shift register that
feeds a 8 x 3-bit D-type storage register. In the
output stage, twenty-four regulated current
sources were designed to provide 5-80 mA
constant current to drive the LEDs.
The 8x3 shift registers data flow sequence order
can be managed with two dedicated pins.
TQFP48
The data detection results are loaded in the shift
registers and shifted out via the serial line output.
The detection functionality is activated with a
dedicated pin or as alternative, through a logic
sequence that allows the user to enter or exit from
detection mode.
Through three external resistors, users can adjust
the output current for each 8-channel group,
controlling in this way the light intensity of LEDs.
The STP24DP05 guarantees a 20 V output
driving capability, allowing users to connect more
LEDs in series.
The high clock frequency, 25 MHz, makes the
device suitable for high data rate transmission.
The 3.3 V of voltage supply is useful for
applications that interface any micro from 3.3 V.
The STP24DP05 has a dedicated pin to activate
the outputs with a sequential delay, that will
prevent inrush current during outputs turn-ON.
The device detection circuit checks 3 different
conditions that can occur on the output line: short
to GND, short to VO or open line.
Table 1.
May 2008
Device summary
Order code
Package
Packaging
STP24DP05BTR
TQFP48
Tape and reel
Rev 1
1/26
www.st.com
26
Contents
STP24DP05
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
2
Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7
Feature description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1
DG: gradual outputs delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.2
Error detection condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.3
Phase one: “entering in detection mode” . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.4
Phase two: “error detection” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.5
Phase three: “resuming to normal mode” . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.6
Shift registers data flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.7
EFLAG/TFLAG - output detection and overtemperature monitoring . . . . 19
8
Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/26
STP24DP05
1
Summary description
Summary description
Table 2.
Current accuracy
Typical current accuracy
Output voltage
Output current
Between bits
1.1
VDD
Temperature
3.3 V to 5 V
25 °C
Between ICs
≥ 1.0 V
±3%
±6%
≥ 15 to 80 mA
≥ 0.2 V
±6%
±6%
5 to 15 mA
Pin connection and description
Figure 1.
Pin connection
TQFP48 exposed pad
3/26
Summary description
Table 3.
4/26
STP24DP05
Pin description
Pin N°
Symbol
Name and function
1, 7, 12, 25, 30, 36
GND
Ground terminal
2
SDI
Serial data input
35
SDO
Serial data output
4
CLK
Clock for serial data
3
LE\DM
5
DM
13, 16, 19, 22,
39, 42, 45, 48
R1 - 8
8
TF
Thermal flag (open drain)
29
EF
Error detection flag (open drain)
9
DG
Gradual delay
15, 17, 20, 23,
37, 40, 43, 46
B1 - 8
8 channel LED driver outputs
32
OE-B
Output enable for B1 - 8
33
OE-G
Output enable for G1 - 8
34
OE-R\DM
Output enable for R1 - 8
28
REXTR
Control outputs R1 - 8
27
REXTG
Control outputs G1 - 8
26
REXTB
Control outputs B1 - 8
14, 18, 21, 24,
38, 41, 44, 48
G1 - 8
8 channel LED driver outputs
10
DF0
Data banks flow bit 0
11
DF1
Data banks flow bit 1
31
VDD
Supply voltage terminal
Data latch in both SH register
Detection mode pin
8 channel LED driver outputs
STP24DP05
Electrical ratings
2
Electrical ratings
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
program and other relevant quality documents.
Table 4.
Absolute maximum ratings
Symbol
2.2
Parameter
Value
Unit
0 to 7
V
VDD
Supply voltage - digital
VO
Output voltage - LED driver
-0.5 to 20
V
VTF and
VER
Open drain absolute voltage
0 to 7
V
IO
Output current - LED driver
80
mA
VI
Input voltage - digital
-0.4 to VDD+0.4
V
IGND
GND terminal current
2000
mA
fCLK
Clock frequency
30
MHz
Value
Unit
Thermal data
Table 5.
Symbol
Thermal data
Parameter
TOPR
Operating temperature range
-40 to 125
°C
TSTG
Storage temperature range
-40 to 150
°C
RthJC
Thermal resistance junction-case
25
°C/W
5/26
Electrical ratings
2.3
STP24DP05
Recommended operating conditions
Table 6.
Symbol
Recommended operating conditions
Parameter
Test conditions
Min
Typ
3.0
Max
Unit
5.5
V
20
V
80
mA
VDD
Supply voltage
VO
Output voltage
IO
Output current
OUTn
IOH
Output current
SERIAL-OUT
+10
mA
IOL
Output current
SERIAL-OUT
-10
mA
VIH
Input voltage
0.7VDD
VDD+0.3
V
VIL
Input voltage
-0.3
0.3VDD
V
5
twLAT
LE pulse width
15
ns
twCLK
CLK pulse width
15
ns
twEN
OE pulse width
150
ns
15
ns
5
ns
10
ns
tSETUP(D) Setup time for DATA
VDD = 3.0 V to 5.0 V
tHOLD(D) Hold time for DATA
tSETUP(L) Setup time for LATCH
fCLK
Clock frequency
Cascade operation
(1)
25
MHz
1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please
consider the timings carefully.
6/26
STP24DP05
Electrical characteristics
3
Electrical characteristics
Table 7.
Electrical characteristics
(VDD = 3.3 V to 5 V, T = 25 °C, unless otherwise specified.)
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
VIH
Input voltage high level
0.7VDD
VDD
V
VIL
Input voltage low level
GND
0.3VDD
V
IOH
Output leakage current
VOH = 20 V
10
µA
VOL
Output voltage
(Serial-OUT)
IOL = 1 mA
0.4
V
VOH
Output voltage
(Serial-OUT)
IOH = -1 mA
VDD-0.4V
V
VO = 0.3 V, REXT = 2 kΩ,
IO = 10 mA
20
mA
VO = 0.3 V, REXT = 1 kΩ,
IO = 20 mA
80
mA
IOL3
VO = 0.3V, REXT = 250 Ω,
IO = 80 mA
80
mA
∆IOL1
VO = 0.3 V, REXT = 2 kΩ,
IO = 10 mA
±2
±3
%
±2
±3
%
±2
±3
%
IOL1
IOL2
∆IOL2
∆IOL3
RSIN(up)
Output current
Output current error among
VO = 0.3 V, REXT = 1 kΩ,
the channels
IO = 20 mA
(All outputs ON)
VO = 0.3V, REXT = 250 Ω,
IO = 80 mA
Pull-up resistor
300
600
800
kΩ
RSIN(down)
Pull-down resistor
300
400
500
kΩ
LE(up)
DG(up)
OE-R\
DM (up)
OE-G (up)
OE-B (up)
DF0
DF1
Pull-up resistor
300
400
500
kΩ
REXT = 1 kΩ
OUT 0 to 15 = OFF
9
12
IDD(OFF2)
REXT = 250 Ω
OUT 0 to 15 = OFF
32
40
IDD(ON1)
REXT = 1 kΩ
OUT 0 to 15 = ON
13
18
REXT = 250 Ω
OUT 0 to 15 = ON
35
40
IDD(OFF1)
Supply current (OFF)
mA
Supply current (ON)
IDD(ON2)
7/26
Electrical characteristics
Table 7.
Electrical characteristics
(VDD = 3.3 V to 5 V, T = 25 °C, unless otherwise specified.)
Symbol
Parameter
Thermal
Thermal protection
VTF
Output voltage
ITF
Output current
VEF
Output voltage
IEF
Output current
Table 8.
STP24DP05
Test conditions
Min
Typ
Max
170
°C
5
VTF @ 1 V
V
20
mA
5
VEF @ 1 V
V
20
mA
Switching characteristics (VDD = 5 V, T = 25 °C, unless otherwise specified.)
Symbol
Parameter
Typ
Max
tPLH1
Propagation delay time,
CLK-OUTn, LE = H, OE = L
VDD = 3.3 V
62
100
VDD = 5 V
38
60
tPLH2
Propagation delay time,
LE-OUTn, OE = L
VDD = 3.3 V
67
107
VDD = 5 V
44
60
tPLH3
Propagation delay time,
OE-OUTn, LE = H
VDD = 3.3 V
65
83
VDD = 5 V
38
45
Propagation delay time,
CLK-SDO
VDD = 3.3 V
14
22
36
tPLH
VDD = 5 V
9
14
23
Propagation delay time,
CLK-OUTn, LE = H,
OE = L
VDD = 3.3 V
46
70
tPHL1
VDD = 5 V
39
50
Propagation delay time,
LE-OUTn, OE = L
VDD = 3.3 V
51
76
tPHL2
VDD = 5 V
46
55
Propagation delay time,
OE-OUTn, LE = H
VDD = 3.3 V
41
45
tPHL3
VDD = 5 V
33
39
Propagation delay time,
CLK-SDO
VDD = 3.3 V
15
24
38
tPHL
VDD = 5 V
9
15
24
Output rise time
10~90% of voltage
waveform
VDD = 3.3 V
33
57
tON
VDD = 5 V
17
27
Output fall time
90~10% of voltage
waveform
VDD = 3.3 V
24
34
tOFF
VDD = 5 V
25
37
Test conditions
VDD = 3.3 V
VIL = GND
IO = 20 mA
REXT = 1 kΩ
VIH = VDD
CL = 10 pF
VL = 3.0 V
RL = 60 Ω
Min
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tr
CLK rise time (1)
5000
ns
tf
CLK fall time (1)
5000
ns
1. In order to achieve high cascade data transfer, please consider tr/tf timings carefully.
8/26
Unit
STP24DP05
Block diagram
4
Block diagram
Figure 2.
Block diagram
9/26
Equivalent circuit and outputs
5
10/26
Equivalent circuit and outputs
Figure 3.
OExx terminal
Figure 4.
LE\DM terminal
Figure 5.
CLK, SDI terminal
STP24DP05
STP24DP05
Equivalent circuit and outputs
Figure 6.
SDO terminal
Figure 7.
TF and EF
11/26
Timing diagrams
6
Timing diagrams
Figure 8.
Note:
12/26
STP24DP05
Timing diagram
The latches circuit holds data when the LE terminal is low.
1
When LE\DML terminal is at high level, latch circuit hold the data it passes from the input to
the output.
2
When either OE-R\DM, OE-G, OE-B terminals are at low level, output terminals R\G\B1 to
R\G\B8 respond to the data, either ON or OFF.
3
When either OE-R\DM, OE-G, OE-B terminals are at high level, it switches off all the data on
the output terminal R\G\B1 to R\G\B8.
STP24DP05
Timing diagrams
Figure 9.
Clock, serial-in, serial-out
13/26
Timing diagrams
Figure 10. Clock, serial-in, latch, enable, outputs
Figure 11. Outputs
14/26
STP24DP05
STP24DP05
Feature description
7
Feature description
7.1
DG: gradual outputs delay
This feature prevents large inrush current and reduces the bypass capacitors.
The fixed delay time can be activated with DG = LOW and the typical output delay is 20 ns
for each group of 8 outputs R, G, B. Eg: R1, G1, B1 has no delay, R2, G2, B2 has 20 ns
delay and R3, G3, B3, has 40 ns delay, etc.
Table 9.
Typical gradual delay time table
Delay time (ns) from ↓OExx
R1
G1
B1
R2
G2
B2
R3
G3
B3
R4
G4
B4
R5
G5
B5
R6
G6
B6
R7
G7
B7
R8
G8
B8
DG = 0
0
30
60
90
120
150
180
200
0
0
0
0
0
0
0
DG = 1
7.2
Error detection condition
Table 10.
Detection conditions (VDD = 3.3 to 5 V, IO = 20 mA, tA = 25 °C)
SW-1 Open Open line or output short
or SW-3b to GND detected
SW-2
Closed or
SW-3a
Note:
Short on LED or short to
V-LED detected
=> IODEC ≤ 0.4 x IO
No error
detected
=> IODEC ≥ 0.35 x IO
=> VO ≥ 2.6 V
No error
detected
=> VO ≤ 2.4 V
IO = the output current programmed by the REXT
IODEC = the detected output current in detection mode
Table 11.
Typical current threshold values to detect LED open line
Iset (mA)
Rext (Ω)
Typ. out current detection (mA)
5
3920
1.28
10
1960
2.45
20
980
7.4
50
386
17
80
241
27
15/26
Feature description
STP24DP05
Figure 12. Detection circuit
23
24
STP24DP05
16
7.3
Phase one: “entering in detection mode”
From the “normal mode” condition the device can switch to the “error detection mode“ by a
DM PIN set to LOW or a logic sequence on the OE-R/DM and LE/DM pins as showed in the
following table and diagram:
Figure 13. EDM timing diagram using DM pin
Table 12.
16/26
SPI sequence to enter in detection mode - truth table
CLK
1°
2°
3°
4°
5°
OE-R/DM
H
L
H
H
H
LE/DM
L
L
L
H
L
STP24DP05
Feature description
Figure 14. SPI sequence to enter in detection mode - time diagram
OE-R/DM
LE/DM
After these five CLK cycles the device goes into the “error detection mode“ and at the 6th
rise front of CLK the SDI data are ready for the sampling.
7.4
Phase two: “error detection”
The eight data bits must be set “1“ in order to set ON all the outputs during the detection.
The data are latched by LE/DM and after that the outputs are ready for the detection
process. When the micro controller switches the OE-R/DM to LOW, the device drives the
LEDs in order to analyze if an OPEN or SHORT condition has occurred.
Figure 15. Detection diagram
The LEDs status will be detected at least in 1 microsecond and after this time the
microcontroller sets OE-R/DM in HIGH state and the output data detection result will go to
the microprocessor via SDO.
Detection mode and normal mode use both the same format data. As soon as all the
detection data bits are available on the serial line, the device may go back to normal mode
of operation.
17/26
Feature description
7.5
STP24DP05
Phase three: “resuming to normal mode”
In order to re-enter in normal mode either the LE\DML pin or the sequence showed in the
following table and diagram can be used:
Table 13.
SPI sequence to resume in normal mode - truth table
CLK
1°
2°
3°
4°
5°
OE-R/DM
H
L
H
H
H
LE/DM
L
L
L
L
L
Note:
For proper device operation the "entering in detection" sequence must be followed by a
"resume mode" sequence, it is not possible to insert consecutive equal sequence.
7.6
Shift registers data flow control
The 8x3 shift registers have a default RGB sequence serial data flow as showed on block
diagram Figure 2.
The data can be redirected by DF0 and DF1 pins, these pins change the order of the data
flow according to the following table:
Table 14.
18/26
Shifter register data flow control
Sequence
DF0
DF1
BGR
1
1
BGR
0
1
RGB
1
0
GBR
0
0
STP24DP05
7.7
Feature description
EFLAG/TFLAG - output detection and overtemperature
monitoring
The open-drain output EFLAG and TFLAG are used to report the STP24DP05 error flags.
During normal operating conditions, the voltage on EFLAG/TFLAG is pulledup through an
external resistor. When an error is detected, the internal switch is turned on, to GND.
Figure 16. TF and EF test circuit
19/26
Typical application schematic
8
Typical application schematic
Figure 17. Typical application schematic
20/26
STP24DP05
STP24DP05
Typical characteristics
Figure 18. Typical external resistor values vs output current capabilities
4500
4000
External Resistance (Ohm)
9
Typical characteristics
3500
Temp. = 25°C
Vdd = 5.0V
Iset = 5mA; 10mA; 20mA; 50mA; 80mA
3000
2500
2000
1500
1000
500
0
0
10
20
30
40
50
60
70
80
90
Output Current (mA)
Table 15.
Typical external resistor values vs output current capabilities
Iset
5 mA
10 mA
20 mA
50 mA
80 mA
Rext (Ω)
4210
2050
1000
400
249
Figure 19. Typical dropout voltage vs output current
Table 16.
Typical dropout voltage vs output current
Iset
Rext (Ω)
Avg (mV) @ 3.3 V
Avg (mV) @ 5.0 V
5
4210
59
41
10
2050
130
90
20
1000
201
180
50
400
500
480
80
249
810
790
21/26
Package mechanical data
10
STP24DP05
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
22/26
STP24DP05
Package mechanical data
Figure 20. TQFP48 mechanical data
TQFP48 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
A
MAX.
MIN.
TYP.
1.6
0.15
0.063
A1
0.05
A2
1.35
1.40
1.45
0.053
0.055
B
0.17
0.22
0.27
0.007
0.009
C
0.09
0.20
0.0035
0.002
0.006
D
9.00
0.354
7.00
0.276
D3
5.50
0.216
e
0.50
0.020
E
9.00
0.354
E1
7.00
0.276
E3
5.50
0.216
L
0.45
K
0.60
0.75
0.018
1.00
0˚
3.5˚
0.057
0.011
0.0079
D1
L1
MAX.
0.024
0.030
0.039
7˚
0˚
3.5˚
7˚
0110596/C
23/26
Package mechanical data
STP24DP05
Figure 21. TQFP48 tape and reel
Tape & Reel TQFP48 MECHANICAL DATA
mm.
inch
DIM.
MIN.
A
MAX.
MIN.
330
13.2
TYP.
MAX.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
24/26
TYP
0.504
22.4
0.519
0.882
Ao
9.5
9.7
0.374
0.382
Bo
9.5
9.7
0.374
0.382
Ko
2.1
2.3
0.083
0.091
Po
3.9
4.1
0.153
0.161
P
11.9
12.1
0.468
0.476
STP24DP05
11
Revision history
Revision history
Table 17.
Document revision history
Date
Revision
19-Apr-2008
1
Changes
First release
25/26
STP24DP05
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