STP08CP05 Low voltage, low current power 8-bit shift register Features ■ Low voltage power supply down to 3 V ■ 8 constant current output channels ■ Adjustable output current through external resistor ■ Serial Data IN/Parallel data OUT ■ 3.3 V micro driver-able ■ Output current: 5-100 mA ■ 30MHz clock frequency ■ Available in high thermal efficiency TSSOP exposed pad ■ ESD protection 2.5 kV HBM, 200 V MM Dip-16 TSSOP16 (Exposed pad) TSSOP16 SO-16 Description The STP08CP05 is a monolithic, low voltage, low current, power 8-bit shift register designed for LED panel displays. The STP08CP05 contains an 8-bit serial-in, parallel-out shift register that feeds a 8-bit D-type storage register. In the output stage, eight regulated current sources were designed to provide 5-100 mA constant current to drive the LEDs, the output current setup time is 11 ns (typ), thus improving the system performance. The STP08CP05 is backward compatible in functionality and footprint with STP8C/L596. Through an external resistor, users can adjust the STP08CP05 output current, controlling in this way the light intensity of LEDs, in addition, user can adjust LED’s brightness intensity from 0% to 100% via OE pin. The STP08CP05 guarantees a 20 V output driving capability, allowing users to connect more LEDs in series. The high clock frequency, 30 MHz, also satisfies the system requirement of high volume data transmission. The 3.3 V of voltage supply is useful for applications that interface with any micro from 3.3 V. Compared with a standard TSSOP package, the TSSOP exposed pad increases heat dissipation capability by a 2.5 factor. Table 1. Device summary Order codes Package Packaging STP08CP05B1R DIP-16 25 parts per tube STP08CP05MTR SO-16 (Tape and reel) 2500 parts per reel STP08CP05TTR TSSOP16 (Tape and reel) 2500 parts per reel STP08CP05XTTR TSSOP16 exposed-pad (Tape and reel) 2500 parts per reel February 2008 Rev 3 1/27 www.st.com 27 Contents STP08CP05 Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Truth table and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.1 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.2 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/27 STP08CP05 1 Summary description Summary description Table 2. Typical current accuracy Current accuracy Output voltage Output current Between bits Between ICs ±1.5 % ±3 % ≥1.3 V 1.1 20 to 100 mA Pin connection and description Figure 1. Note: Connections diagram The Exposed-pad is electrically not connected Table 3. Pin description Pin N° Symbol Name and function 1 GND Ground terminal 2 SDI Serial data input terminal 3 CLK Clock input terminal 4 LE Latch input terminal 5-12 OUT 0-7 13 OE 14 SDO 15 R-EXT 16 VDD Output terminal Output enable input terminal (active low) Serial data out terminal Constant current programming 5 V supply voltage terminal 3/27 Block diagram 2 Block diagram Figure 2. Block diagram 4/27 STP08CP05 STP08CP05 3 Maximum rating Maximum rating Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol 3.2 Parameter Value Unit 0 to 7 V VDD Supply voltage IGND VO Output voltage -0.5 to 20 V IO Output current 100 mA IGND GND terminal current 800 mA fCLK Clock frequency 50 MHz TOPR Operating temperature range -40 to +125 °C TSTG Storage temperature range -55 to +150 °C Thermal data Table 5. Thermal data Symbol Parameter RthJA Thermal resistance junction-ambient DIP-16 SO-16 TSSOP-16 90 125 140 TSSOP-16 (1) (exposed pad) Unit 37.5 °C/W 1. The Exposed-Pad should be soldered to the PBC to realize the thermal benefits 5/27 Maximum rating 3.3 STP08CP05 Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Test conditions Min Typ Unit 5.5 V 20 V 100 mA VDD Supply voltage VO Output voltage IO Output current OUTn IOH Output current SERIAL-OUT +1 mA IOL Output current SERIAL-OUT -1 mA VIH Input voltage 0.7 VDD VDD+0.3 V VIL Input voltage -0.3 0.3 VDD V 3.0 5 twLAT LE pulse width 20 ns twCLK CLK pulse width 20 ns twEN OE pulse width 200 ns 7 ns tHOLD(D) Hold time for DATA 4 ns tSETUP(L) Setup time for LATCH 15 ns tSETUP(D) Setup time for DATA fCLK Clock frequency VDD = 3.0 to 5.0V Cascade operation (1) 1. In order to achieve high cascade data transfer,please consider tr/tf timings carefully. 6/27 Max 30 MHz STP08CP05 Electrical characteristics 4 Electrical characteristics Table 7. Electrical characteristics (VDD = 3.3 V to 5 V, T = 25 °C, unless otherwise specified.) Symbol Parameter Test conditions Min Typ Max Unit VIH Input voltage high level 0.7 VDD VDD V VIL Input voltage low level GND 0.3VDD V IOH Output leakage current VOH = 20 V 0.5 10 µA VOL Output voltage (Serial-OUT) IOL = 1 mA 0.03 0.4 V VOH Output voltage (Serial-OUT) IOH = -1 mA IOL1 VOH - VDD =- 0.4 V V VO = 0.3 V, Rext = 3.9 kΩ 4.25 5 5.75 VO = 0.3 V, Rext = 970 Ω 19.4 20 20.6 VO = 1.3 V, Rext = 190 Ω 97 100 103 VO = 0.3 VREXT = 3.9 kΩ ±5 ±8 VO = 0.3 VREXT = 970 Ω ± 1.5 ± 2.75 VO = 1.3 VREXT =190 Ω ± 1.2 ± 2.5 150 300 600 KΩ 100 200 400 KΩ REXT = 980 OUT 0 to 7 = OFF 4 5 IDD(OFF2) REXT = 250 OUT 0 to 7 = OFF 11.2 13.5 IDD(ON1) REXT = 980 OUT 0 to 7 = ON 4.5 5 REXT = 250 OUT 0 to 7 = ON 11.7 13.5 IOL2 Output current IOL3 ∆IOL1 ∆IOL2 ∆IOL3 RSIN(up) Output current error between bit (All Output ON) Pull-up resistor RSIN(down) Pull-down resistor IDD(OFF1) mA % Supply current (OFF) mA Supply current (ON) IDD(ON2) Thermal Thermal protection (1) 170 °C 1. Guaranteed by desing (not tested) The thermal protection switches OFF only the outputs 7/27 Switching characteristics 5 STP08CP05 Switching characteristics Table 8. Switching characteristics (VDD = 5 V, T = 25 °C, unless otherwise specified.) Symbol Parameter Test conditions Min Typ Max VDD = 3.3 V 35 50 VDD = 5 V 18 28 tPLH1 Propagation delay time, CLK-OUTn, LE = H, OE = L Propagation delay time, LE -OUTn, OE = L VDD = 3.3 V 48 74 tPLH2 VDD = 5 V 30 50 Propagation delay time, OE -OUTn, LE = H VDD = 3.3 V 55 82 tPLH3 VDD = 5 V 37 58 Propagation delay time, CLK-SDO VDD = 3.3 V 21 28 tPLH VDD = 5 V 17 22 Propagation delay time, CLK-OUTn, LE = H, OE = L VDD = 3.3 V 11 17 tPHL1 VDD = 5 V 7 11 Propagation delay time, LE -OUTn, OE = L VDD = 3.3 V 24 40 tPHL2 VDD = 5 V 21 31 Propagation delay time, OE -OUTn, LE = H VDD = 3.3 V 20 35 tPHL3 VDD = 5 V 18 28 Propagation delay time, CLK-SDO VDD = 3.3 V 24 32 tPHL VDD = 5 V 19 25 Output rise time 10~90% of voltage waveform VDD = 3.3 V 26 40 tON VDD = 5 V 11 17 Output fall time 90~10% of voltage waveform VDD = 3.3 V 5 10 tOFF VDD = 5 V 4 8 ns ns ns VDD = 3.3 V VIL = GND IO = 20 mA REXT = 1 KΩ VIH = VDD CL = 10 pF VL = 3.0 V RL = 60 Ω ns ns ns ns ns ns ns tr CLK rise time (1) 5000 ns tf CLK fall time (1) 5000 ns 1. In order to achieve high cascade data transfer, please consider tr/tf timings carefully. 8/27 Unit STP08CP05 6 Equivalent circuit and outputs Equivalent circuit and outputs Figure 3. OE terminal Figure 4. LE terminal Figure 5. CLK, SDI terminal 9/27 Equivalent circuit and outputs Figure 6. 10/27 SDO terminal STP08CP05 STP08CP05 Truth table and timing diagram 7 Truth table and timing diagram 7.1 Truth table Table 9. Truth table Clock Note: LE OE SDI OUT0 ........ OUT0 ........ OUT7 SDO H L Dn Dn ..... Dn -5 ..... Dn -7 Dn -7 L L Dn + 1 No Change Dn -7 H L Dn + 2 Dn +2 ..... Dn -3 ..... Dn -5 Dn -5 X L Dn + 3 Dn +2 ..... Dn -3 ..... Dn -5 Dn -5 X H Dn + 3 OFF Dn -5 OUT0 to OUT7 = ON when Dn = H; OUT0 to OUT7 = OFF when Dn = L. 11/27 Truth table and timing diagram 7.2 12/27 Timing diagram Figure 7. Timing diagram Figure 8. Clock, serial-in, serial-out STP08CP05 STP08CP05 Truth table and timing diagram Figure 9. Clock, serial-in, latch, enable, outputs Figure 10. Outputs 13/27 Typical characteristics 8 STP08CP05 Typical characteristics Figure 11. Output current-REXT resistor 8000 7000 Rext (Ohm) 6000 5000 4000 3000 2000 1000 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Ouput Current (mA) Table 10. Output current-REXT resistor 14/27 Output current (mA) 3 5 10 20 50 80 100 130 Rext (Ω) 6740 3930 1913 963 386 241 192 124 STP08CP05 Typical characteristics Figure 12. ISET vs drop out voltage (VDROP) 910 810 Vdrop (mV) 710 610 Vdd 5.0V Vdd 3.0V 510 410 310 210 110 10 0 10 20 30 40 50 60 70 80 90 100 110 Iset (mA) Table 11. ISET vs drop out voltage (VDROP) Vdd (V) I set (mA) Rext (Ω) 3 3 6470 30.6 31.2 30.93 5 3930 46.5 52.9 48.63 10 1910 80.9 100 82.26 20 963 150 161 157 50 386 392 396 394.3 80 241 636 646 640.3 100 192 846 850 848 3 6470 25.6 29 26.96 5 3930 40.8 41.7 41.16 10 1910 80.1 105 89.2 20 963 153 154 154 50 386 379 386 382 80 241 618 626 621 100 192 825 830 827 5 Vdrop Min (mV) Vdrop Max (mV) Vdrop AVG (mV) 15/27 Typical characteristics STP08CP05 Figure 13. Power dissipation vs temperature package Note: The Exposed-Pad should be soldered to the PBC to realize the thermal benefits. % Figure 14. Current precision between outputs vs output current 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 1 10 Iset (mA) 16/27 100 STP08CP05 Test circuit 9 Test circuit Figure 15. DC characteristics Figure 16. AC characteristics 17/27 Test circuit STP08CP05 Figure 17. Typical application schematic 18/27 STP08CP05 10 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 19/27 Package mechanical data STP08CP05 Figure 18. DIP-16 mechanical data Plastic DIP-16 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 0.77 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 P001C 20/27 STP08CP05 Package mechanical data Figure 19. TSSOP16 mechanical data TSSOP16 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 D 4.9 5 5.1 0.193 0.197 0.201 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0˚ L 0.45 A 0.60 0.0256 BSC 8˚ 0˚ 0.75 0.018 8˚ 0.024 0.030 A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080338D 21/27 Package mechanical data STP08CP05 Figure 20. TSSOP16 exposed pad mechanical data TSSOP16 EXPOSED PAD MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A 1.2 A1 0.15 A2 0.8 b TYP. MAX. 0.047 0.004 0.006 0.039 0.041 1.05 0.031 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 4.9 5.1 0.193 D1 1.7 E 6.2 6.4 6.6 E1 4.3 4.4 4.5 E2 1.5 e 1 MIN. 5 0.197 0.201 0.244 0.252 0.260 0.169 0.173 0.177 0.067 0.059 0.65 K 0° L 0.45 0.60 0.0256 8° 0° 0.75 0.018 8° 0.024 0.030 7419276A 22/27 STP08CP05 Package mechanical data Figure 21. TSSOP16 tape and reel Tape & Reel TSSOP16 MECHANICAL DATA mm. inch DIM. MIN. A TYP MAX. MIN. 330 MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 TYP. 0.504 22.4 0.519 0.882 Ao 6.7 6.9 0.264 0.272 Bo 5.3 5.5 0.209 0.217 Ko 1.6 1.8 0.063 0.071 Po 3.9 4.1 0.153 0.161 P 7.9 8.1 0.311 0.319 23/27 Package mechanical data STP08CP05 Figure 22. SO-16 mechanical data SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.25 b 0.35 b1 0.19 a2 0.068 0.004 0.010 0.46 0.013 0.018 0.25 0.007 1.64 C MAX. 0.063 0.5 0.010 0.019 c1 45° (typ.) D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 G L M S 4.0 0.149 0.157 4.6 5.3 0.181 0.208 0.5 1.27 0.019 0.050 0.62 0.024 8° (max.) 0016020D 24/27 STP08CP05 Package mechanical data Figure 23. SO-16 tape and reel Tape & Reel SO-16 MECHANICAL DATA mm. inch DIM. MIN. A TYP MAX. MIN. 330 MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 TYP. 0.504 22.4 0.519 0.882 Ao 6.45 6.65 0.254 0.262 Bo 10.3 10.5 0.406 0.414 Ko 2.1 2.3 0.082 0.090 Po 3.9 4.1 0.153 0.161 P 7.9 8.1 0.311 0.319 25/27 Revision history 11 STP08CP05 Revision history Table 12. Revision history 26/27 Date Revision Changes 23-May-2007 1 First release 28-Jun-2007 2 Updated Table 7 on page 7 14-Feb-2008 3 Updated Table 8 on page 8 and added Figure 11 and Figure 12 on page 15 STP08CP05 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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