STMICROELECTRONICS STR910FW32X6T

STR91xF
ARM966E-S™ 16/32-Bit Flash MCU with Ethernet, USB, CAN,
AC Motor Control, 4 Timers, ADC, RTC, DMA
PRELIMINARY DATA
■
16/32-bit 96 MHz ARM9E based MCU
– ARM966E-S RISC core: Harvard architecture, 5-stage pipeline, Tightly-Coupled
Memories (SRAM and Flash)
– STR91xF implementation of core adds highspeed burst Flash memory interface,
instruction prefetch queue, branch cache
– Up to 96 MIPS directly from Flash memory
– Single-cycle DSP instructions are supported
– Binary compatible with 16/32-bit ARM7 code
■ Dual burst Flash memories, 32-bits wide
– 256KB/512KB Main Flash, 32KB 2nd Flash
– Sequential Burst operation up to 96 MHz
– 100K min erase cycles, 20 yr min retention
■ SRAM, 32-bits wide
■
– 64K or 96K bytes, optional battery backup
9 programmable DMA channels
– One for Ethernet, eight programmable chnls
■ Clock, reset, and supply management
– Two supplies required. Core: 1.8V +/-10%,
I/O: 2.7 to 3.6V
– Internal osc operating with ext. 4-25MHz xtal
– Internal PLL up to 96MHz
– Real-time clock provides calendar functions,
tamper detection, and wake-up functions
– Reset Supervisor monitors voltage supplies,
watchdog timer, wake-up unit, ext. reset
– Brown-out monitor for early warning interrupt
– Run, Idle, and Sleep Mode as low as 50 uA
■ Operating temperature -40 to +85°C
■
Vectored interrupt controller (VIC)
– 32 IRQ vectors, 30 intr pins, any can be FIQ
– Branch cache minimizes interrupt latency
LQFP80 12 x12mm
■
LQFP128 14 x 14mm
8-channel, 10-bit A/D converter (ADC)
– 0 to 3.6V range, 2 usec conversion time
■ 11 Communication interfaces
– 10/100 Ethernet MAC with DMA and MII port
– USB Full-speed (12 Mbps) slave device
– CAN interface (2.0B Active)
– 3 16550-style UARTs with IrDA protocol
– 2 Fast I2C™, 400 kHz
– 2 channels for SPI™, SSI™, or Microwire™
– 8/16-bit EMI bus on 128 pin packages
■ Up to 80 I/O pins (muxed with interfaces)
– 5V tolerant, 16 have high sink current (8mA)
– Bit-wise manipulation of pins within a port
■ 16-bit standard timers (TIM)
– 4 timers each with 2 input capture, 2 output
compare, PWM and pulse count modes
■ 3-Phase induction motor controller (IMC)
– 3 pairs of PWM outputs, adjustable centers
– Emergency stop, dead-time gen, tach input
■ JTAG interface with boundary scan
– ARM EmbeddedICE® RT for debugging
– In-System Programming (ISP) of Flash
■ Embedded trace module (ARM ETM9)
– Hi-speed instruction tracing, 9-pin interface
Device summary
Features
STR910FM32X STR910FW32X STR911FM42X STR911FM44X STR912FW42X STR912FW44X
FLASH - Kbytes
256+32
RAM - Kbytes
64
Peripheral
CAN, 48 I/Os
functions
Packages
LQFP80
April 2006
256+32
64
CAN, EMI,
80 I/Os
LQFP128
256+32
96
512+32
96
USB, CAN, 48 I/Os
LQFP80
256+32
512+32
96
96
Ethernet, USB, CAN, EMI,
80 I/Os
LQFP128
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/72
72
STR91xF
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
System-in-a-Package (SiP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Package choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3
ARM966E-S CPU core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4
Burst Flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.5
2.4.1
Pre-Fetch Queue (PFQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4.2
Branch Cache (BC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4.3
Management of literals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRAM (64K or 96K Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5.1
Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5.2
Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6
DMA data movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7
Non-volatile memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7.1
Primary Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.7.2
Secondary Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.8
One-time-programmable (OTP) memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.9
Vectored interrupt controller (VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.10
2.9.1
FIQ handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.9.2
IRQ handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.9.3
Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock control unit (CCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.10.1 Master clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.10.2 Reference clock (RCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.10.3 AHB clock (HCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.10.4 APB clock (PCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.10.5 Flash memory interface clock (FMICLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.10.6 Baud rate clock (BRCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.10.7 External memory interface bus clock (BCLK) . . . . . . . . . . . . . . . . . . . . . . . . 16
2.10.8 USB interface clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.10.9 Ethernet MAC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.10.10 Operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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2.11
Flexible power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.11.1 Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.11.2 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.11.3 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.12
Voltage supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.12.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . . . . . 18
2.12.2 Battery supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.13
System supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.13.1 Supply voltage brownout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.13.2 Supply voltage dropout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.13.3 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.13.4 External RESET_INn pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.13.5 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.13.6 JTAG debug command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.13.7 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.14
Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.15
JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.15.1 In-system-programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.15.2 Boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.15.3 CPU debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.15.4 JTAG security bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.16
Embedded trace module (ARM ETM9, v. r2p2) . . . . . . . . . . . . . . . . . . . . . . 23
2.17
Ethernet MAC interface with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.18
USB 2.0 slave device interface with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.18.1 Packet buffer interface (PBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.18.2 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.18.3 Suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.19
CAN 2.0B interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.20
UART interfaces with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.20.1 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.21
I2C interfaces with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.21.1 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.22
SSP interfaces (SPI, SSI, and Microwire) with DMA . . . . . . . . . . . . . . . . . . . 27
2.22.1 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.23
General purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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2.24
A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.25
Standard timers (TIM) with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.25.1 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.26
Three-phase induction motor controller (IMC) . . . . . . . . . . . . . . . . . . . . . . . 30
2.27
External memory interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1
5
6
Default pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.1
Buffered and non-buffered writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.2
System (AHB) and peripheral (APB) buses . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.4
Two independent Flash memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.4.1
Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.4.2
Optional configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.2
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3
LVD electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.4
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.5
AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.6
RESET_INn and power-on-reset characteristics . . . . . . . . . . . . . . . . . . . . . 51
6.7
Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.8
RTC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.9
PLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.10
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.11
External memory bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.12
ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.13
Communication interface electrical characteristics . . . . . . . . . . . . . . . . . . . . 61
6.13.1 10/100 Ethernet MAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 61
6.13.2 USB electrical interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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6.13.3 CAN interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.13.4 I2C electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.13.5 SPI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.14
JTAG interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
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Introduction
1
STR91xF
Introduction
STR91xF is a series of ARM-powered microcontrollers which combines a 16/32-bit ARM966ES RISC processor core, dual-bank Flash memory, large SRAM for data or code, and a rich
peripheral set to form an ideal embedded controller for a wide variety of applications such as
point-of-sale terminals, industrial automation, security and surveillance, vending machines,
communication gateways, serial protocol conversion, and medical equipment. The ARM966E-S
core can perform single-cycle DSP instructions, good for speech processing, audio algorithms,
and low-end imaging.
This Preliminary Datasheet provides STR91xF ordering information, functional overview,
mechanical information, and electrical device characteristics.
For complete information on STR91xF memory, registers, and peripherals, please refer to the
STR91xF Reference Manual.
For information on programming the STR91xF Flash memory please refer to the STR9 Flash
Programming Reference Manual
For information on the ARM966E-S core, please refer to the ARM966E-S Rev. 2 Technical
Reference Manual.
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STR91xF
Functional overview
2
Functional overview
2.1
System-in-a-Package (SiP)
The STR91xF is a SiP device, comprised of two stacked die. One die is the ARM966E-S CPU
with peripheral interfaces and analog functions, and the other die is the burst Flash. The two die
are connected to each other by a custom high-speed 32-bit burst memory interface and a serial
JTAG test/programming interface.
2.2
Package choice
STR91xF devices are available in 128-pin (14 x 14 mm) and 80-pin (12 x 12 mm) LQFP
packages. Refer to the table on the first page and to Table 27 on page 69 for a list of available
peripherals for each of the package choices.
2.3
ARM966E-S CPU core
The ARM966E-S core inherently has separate instruction and data memory interfaces (Harvard
architecture), allowing the CPU to simultaneously fetch an instruction, and read or write a data
item through two Tightly-Coupled Memory (TCM) interfaces as shown in Figure 1. The result is
streamlined CPU Load and Store operations and a significant reduction in cycle count per
instruction. In addition to this, a 5-stage pipeline is used to increase the amount of operational
parallelism, giving the most performance out of each clock cycle.
Ten DSP-enhanced instruction extensions are supported by this core, including single-cycle
execution of 32x16 Multiply-Accumulate, saturating addition/subtraction, and count leadingzeros. As an example of efficient signal processing, a 512-point FFT takes just 29K CPU cycles
on the ARM966E-S core(a).
The ARM966E-S core is binary compatible with 32-bit ARM7 code and 16-bit Thumb® code.
2.4
Burst Flash memory interface
A Burst Flash memory interface (Figure 1) has been integrated into the Instruction TCM
(I-TCM) path of the ARM966E-S core. Also in this path is a 4-instruction Pre-Fetch Queue
(PFQ) and a 4-entry Branch Cache (BC), enabling the ARM966E-S core to perform up to 96
MIPS while executing code directly from Flash memory. This architecture provides high
performance levels without a costly instruction SRAM, instruction cache, or external SDRAM.
Eliminating the instruction cache also means interrupt latency is reduced and code execution
becomes more deterministic.
2.4.1
Pre-Fetch Queue (PFQ)
As the CPU core accesses sequential instructions through the I-TCM, the PFQ always looks
ahead and will pre-fetch instructions, taking advantage any idle bus cycles due to variable
a.
“ARM DSP-Enhanced Extensions”, page 3, White Paper from ARM Ltd., 2001
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Functional overview
STR91xF
length instructions. The PFQ will fetch 32-bits at a time from the Burst Flash memory at a rate
of up to 96 MHz.
2.4.2
Branch Cache (BC)
When instruction addresses are not sequential, such as a program branch situation, the PFQ
would have to flush and reload which would cause the CPU to stall if no BC were present.
Before reloading, the PFQ checks the BC to see if it contains the desired target branch
address. The BC contains up to four of the most recently taken branch addresses and the first
four instructions associated with each of these branches. This check is extremely fast, checking
all four BC entries simultaneously for a branch address match (cache hit). If there is a hit, the
the BC immediately supplies the instruction and prevents a CPU stall. This gives the PFQ time
to start pre-fetching again while the CPU consumes these four instructions from the BC. The
advantage here is that program loops (very common with embedded control applications) run
very fast if the address of the loops are contained in the BC.
In addition, there is a 5th branch cache entry that is dedicated to the Vectored Interrupt
Controller (VIC) to further reduce interrupt latency by eliminating the stall latency typically
imposed by fetching the instruction that reads the interrupt vector address from the VIC.
2.4.3
Management of literals
Typical ARM architecture and compilers do not place literals (data constants) sequentially in
Flash memory with the instructions that use them, but instead the literals are placed at some
other address which looks like a program branch from the PFQ’s point of view. The STR91xF
implementation of the ARM966E-S core has special circuitry to prevent flushing the PFQ when
literals are encountered in program flow to keep performance at a maximum.
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STR91xF
Functional overview
Figure 1.
STR91xF block diagram
Stacked Burst Flash Memory Die
STR91xF
JTAG ISP
1.8V
CORE SUPPLY, VDD
GND
CORE GND, VSS
3.0 or 3.3V
2nd Flash
Main Flash 256K,
Bytes
or 512K Bytes 32K
Burst Interface
I/O SUPPLY, VDDQ
GND
I/O GND, VSSQ
BACKUP
SUPPLY
VBATT
RTC
64K or 96K
Byte
SRAM
Burst Interface
Pre-Fetch Que
and Branch
Cache
Arbiter
Data TCM
Interface
Instruction
ARM966E-S
TCM
RISC CPU Core Interface
Control Logic / BIU and Write Buffer
JTAG
JTAG
Debug
and
ETM
ETM
AMBA / AHBA Interface
32K Hz
XTAL
Real Time Clock
Wake Up
PLL, Power Management,
and Supervisory Reset
EMI bus*** or
16 GPIO
EMI Ctrl
External Memory
Interface (EMI)***,
Muxed Address/Data
Programmable DMA
Controller (8 ch.)
Ethernet**
or 16 GPIO
Ethernet**
MAC, 10/100
Motor Control,
3-ph Induction
(3) UART w/ IrDA
(2) I2C
32
USB* Full Speed, 10
Endpoints with FIFOs
USB Bus
To Ethernet
PHY (MII) **
16
AHB
to
APB
(4) 16-bit Timers,
CAPCOM, PWM
Request
from
UART,
I2C,
SPI,
Timers,
Ext Req
Dedicated
DMA
(80) GPIO
48
MUX to 48 GPIO
4 MHz to
25
MHz XTAL
APB
AHB
Programmable Vectored
Programmable
Vectored
Interrupt Controllers
Interrupt Controller
(2) SPI
CAN 2.0B
8 Channel 10-bit
ADC
Watchdog Tmr
AVDD
AVREF*
AVSS
* USB not available on STR910
** Ethernet MAC not available on STR910F and STR911F
*** EMI not available on LQFP80
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Functional overview
2.5
STR91xF
SRAM (64K or 96K Bytes)
A 32-bit wide SRAM resides on the CPU’s Data TCM (D-TCM) interface, providing single-cycle
data accesses. As shown in Figure 1, the D-TCM shares SRAM access with the Advanced
High-performance Bus (AHB). Sharing is controlled by simple arbitration logic to allow the DMA
unit on the AHB to also access to the SRAM.
2.5.1
Arbitration
Zero-wait state access occurs for either the D-TCM or the AHB when only one of the two is
requesting SRAM. When both request SRAM simultaneously, access is granted on an
interleaved basis so neither requestor is starved, granting one 32-bit word transfer to each
requestor before relinquishing SRAM to the other. When neither the D-TCM or the AHB are
requesting SRAM, the arbiter leaves access granted to the most recent user (if D-TCM was last
to use SRAM then the D-TCM will not have to arbitrate to get access next time).
The CPU may execute code from SRAM through the AHB. There are no wait states as long as
the D-TCM is not contending for SRAM access. The ARM966E-S CPU core has a small prefetch queue built into this instruction path through the AHB to look ahead and fetch instructions
during idle bus cycles.
2.5.2
Battery backup
When a battery is connected to the designated battery backup pin (VBATT), SRAM contents
are automatically preserved when the normal operating voltage on VDD pins is lost or sags
below threshold. Automatic switchover to SRAM can be disabled by firmware if it is desired that
the battery will power only the RTC and not the SRAM during standby.
2.6
DMA data movement
DMA channels on the Advanced High-performance Bus (AHB) take full advantage of the
separate data path provided by the Harvard architecture, moving data rapidly and largely
independent of the instruction path. There are two DMA units, one is dedicated to move data
between the Ethernet interface and SRAM, the other DMA unit has eight programmable
channels with 16 request signals to service other peripherals and interfaces (USB, SSP, I2C,
UART, Timers, EMI, and external request pins). Both single word and burst DMA transfers are
supported. Memory-to-memory transfers are supported in addition to memory-peripheral
transfers. DMA access to SRAM is shared with D-TCM accesses, and arbitration is described
in Section 2.5.1. Efficient DMA transfers are managed by firmware using linked list descriptor
tables.
2.7
Non-volatile memories
There are two independent 32-bit wide Burst Flash memories enabling true read-while-write
operation. The Flash memories are single-voltage erase/program with 20 year minimum data
retention and 100K minimum erase cycles. The primary Flash memory is much larger than the
secondary Flash.
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STR91xF
2.7.1
Functional overview
Primary Flash memory
Using the STR91xF device configuration software tool, it is possible to specify that the primary
Flash memory is the default memory from which the CPU boots at reset, or otherwise specify
that the secondary Flash memory is the default boot memory. This choice of boot memory is
non-volatile and stored in a location that can be programmed and changed only by JTAG InSystem Programming. See Section 5: Memory mapping, for more detail.
The primary Flash memory has equal length 64K byte sectors. Devices with 256 Kbytes of
primary Flash have four sectors and 512K devices have eight sectors.
2.7.2
Secondary Flash memory
The smaller of the two Flash memories can be used to implement a bootloader, capable of
storing code to perform robust In-Application Programming (IAP) of the primary Flash memory.
The CPU executes code from the secondary Flash, while updating code in the primary Flash
memory. New code for the primary Flash memory can be downloaded over any of the
interfaces on the STR91xF (USB, Ethernet, CAN, UART, etc.)
Additionally, the Secondary Flash memory may also be used to store small data sets by
emulating EEPROM though firmware, eliminating the need for external EEPROM memories.
This raises the data security level because passcodes and other sensitive information can be
securely locked inside the STR91xF device.
The secondary Flash memory has four equal length sectors of 8 Kbytes each.
Both the primary Flash memory and the secondary Flash memory can be programmed with
code and/or data using the JTAG In-System Programming (ISP) channel, totally independent of
the CPU. This is excellent for iterative code development and for manufacturing.
2.8
One-time-programmable (OTP) memory
There are 32 bytes of OTP memory ideally suited for serial numbers, security keys, factory
calibration constants, or other permanent data constants. These OTP data bytes can be
programmed only one time through either the JTAG interface or by the CPU, and these bytes
can never be altered afterwards. As an option, a “lock bit” can be set by the JTAG interface or
the CPU which will block any further writing to the this OTP area. The “lock bit” itself is also
OTP. If the OTP array is unlocked, it is always possible to go back and write to an OTP byte
location that has not been previously written, but it is never possible to change an OTP byte
location if any one bit of that particular byte has been written before. The last two OTP bytes are
reserved for the STR91xF product ID and revision level.
2.9
Vectored interrupt controller (VIC)
Interrupt management in the STR91xF is implemented from daisy-chaining two standard ARM
VIC units. This combined VIC has 32 prioritized interrupt request channels and generates two
interrupt output signals to the CPU. The output signals are FIQ and IRQ, with FIQ having higher
priority.
2.9.1
FIQ handling
FIQ (Fast Interrupt reQuest) is the only non-vectored interrupt and the CPU can execute an
Interrupt Service Routine (ISR) directly without having to determine/prioritize the interrupt
11/72
Functional overview
STR91xF
source, minimizing ISR latency. Typically only one interrupt source is assigned to FIQ. An FIQ
interrupt has its own set of banked registers to minimize the time to make a context switch. Any
of the 32 interrupt request input signals coming into the VIC can be assigned to FIQ.
2.9.2
IRQ handling
IRQ is a vectored interrupt and is the logical OR of all 32 interrupt request signals coming into
the 32 IRQ channels. Priority of individual vectored interrupt requests is determined by
hardware (IRQ channel Intr 0 is highest priority, IRQ channel Intr 31 is lowest). However, CPU
firmware may re-assign individual interrupt sources to individual hardware IRQ channels,
meaning that firmware can effectively change interrupt priority levels as needed.
When the IRQ signal is activated by an interrupt request, VIC hardware will resolve the IRQ
interrupt priority, then the ISR reads the VIC to determine both the interrupt source and the
vector address to jump to the service code.
The STR91xF has a feature to reduce ISR response time for IRQ interrupts. Typically, it
requires two memory accesses to read the interrupt vector address from the VIC, but the
STR91xF reduces this to a single access by adding a 5th entry in the instruction branch cache,
dedicated for interrupts. This 5th cache entry always holds the instruction that reads the
interrupt vector address from the VIC, eliminating one of the memory accesses typically
required in traditional ARM implementations.
2.9.3
Interrupt sources
The 32 interrupt request signals coming into the VIC on 32 IRQ channels are from various
sources; 5 from a wake-up unit and the remaining 27 come from internal sources on the
STR91xF such as on-chip peripherals, see Table 1. Optionally, firmware may force an interrupt
on any IRQ channel.
One of the 5 interrupt requests generated by the wake-up unit (IRQ25 in Table 1) is derived
from the logical OR of all 32 inputs to the wake-up unit. Any of these 32 inputs may be used to
wake up the CPU and/or cause an interrupt. These 32 inputs consist of 30 external interrupts
on selected and enabled GPIO pins, plus the RTC interrupt, and the USB Resume interrupt.
Each of 4 remaining interrupt requests generated by the wake-up unit (IRQ26 in Table 1) are
derived from groupings of 8 interrupt sources. One group is from GPIO pins P3.2 to P3.7 plus
the RTC interrupt and the USB Resume interrupt; the next group is from pins P5.0 to P5.7; the
next group is from pins P6.0 to P6.7; and last the group is from pins P7.0 to P7.7. This allows
individual pins to be assigned directly to vectored IRQ interrupts or one pin assigned directly to
the non-vectored FIQ interrupt.
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STR91xF
Functional overview
See Table 1 for recommended interrupt source assignments to physical IRQ interrupt channels.
Interrupt source assignments are made by CPU firmware during initialization, thus establishing
interrupt priorities.
Table 1.
Recommended IRQ Channel assignments (set by CPU firmware)
VIC IRQ Channel
Logic Block
Interrupt Source
0 (high priority)
1
2
3
4
5
6
7
8
9
10
WatchDog
CPU Firmware
CPU Core
CPU Core
TIM Timer 0
TIM Timer 1
TIM Timer 2
TIM Timer 3
USB
USB
CCU
11
Ethernet MAC
12
DMA
13
14
15
16
17
18
CAN
IMC
ADC
UART0
UART1
UART2
19
I2C0
20
I2C1
21
22
23
24
SSP0
SSP1
BROWNOUT
RTC
25
Wake-Up (all)
26
Wake-up Group 0
27
28
29
30
Wake-up Group 1
Wake-up Group 2
Wake-up Group 3
USB
31 (low priority)
PFQ-BC
Timeout in WDT mode, Terminal Count in Counter Mode
Firmware generated interrupt
Debug Receive Command
Debug Transmit Command
Logic OR of ICI0_0, ICI0_1, OCI0_0, OCI0_1, Timer overflow
Logic OR of ICI1_0, ICI1_1, OCI1_0, OCI1_1, Timer overflow
Logic OR of ICI2_0, ICI2_1, OCI2_0, OCI2_1, Timer overflow
Logic OR of ICI3_0, ICI3_1, OCI3_0, OCI3_1, Timer overflow
Logic OR of high priority USB interrupts
Logic OR of low priority USB interrupts
Logic OR of all interrupts from Clock Control Unit
Logic OR of Ethernet MAC interrupts via its own dedicated
DMA channel.
Logic OR of interrupts from each of the 8 individual DMA
channels
Logic OR of all CAN interface interrupt sources
Logic OR of 8 Induction Motor Control Unit interrupts
End of AtoD conversion interrupt
Logic OR of 5 interrupts from UART channel 0
Logic OR of 5 interrupts from UART channel 1
Logic OR of 5 interrupts from UART channel 2
Logic OR of transmit, receive, and error interrupts of I2C
channel 0
Logic OR of transmit, receive, and error interrupts of I2C
channel 1
Logic OR of all interrupts from SSP channel 0
Logic OR of all interrupts from SSP channel 1
LVD warning interrupt
Logic OR of Alarm, Tamper, or Periodic Timer interrupts
Logic OR of all 32 inputs of Wake-Up unit (30 pins, RTC, and
USB Resume)
Logic OR of 8 interrupt sources: RTC, USB Resume, pins
P3.2 to P3.7
Logic OR of 8 interrupts from pins P5.0 to P5.7
Logic OR of 8 interrupts from pins P6.0 to P6.7
Logic OR of 8 interrupts from pins P7.0 to P7.7
USB Bus Resume Wake-up (also input to wake-up unit)
Special use of interrupts from Prefetch Queue and Branch
Cache
13/72
Functional overview
2.10
STR91xF
Clock control unit (CCU)
The CCU generates a master clock of frequency fMSTR. From this master clock the CCU also
generates individually scaled and gated clock sources to each of the following functional blocks
within the STR91xF.
●
CPU, fCPUCLK
●
Advanced High-performance Bus (AHB), fHCLK
●
Advanced Peripheral Bus (APB), fPCLK
●
Flash Memory Interface (FMI), fFMICLK
●
External Memory Interface (EMI), fBCLK
●
UART Baud Rate Generators, fBAUD
●
USB, fUSB
2.10.1 Master clock sources
The master clock in the CCU (fMSTR) is derived from one of three clock input sources. Under
firmware control, the CPU can switch between the three CCU inputs without introducing any
glitches on the master clock output. Inputs to the CCU are:
●
Main Oscillator (fOSC). The source for the main oscillator input is a 4 to 25 MHz external
crystal connected to STR91xF pins X1_CPU and X2_CPU, or an external oscillator device
connected to pin X1_CPU.
●
PLL (fPLL). The PLL takes the 4 to 25 MHz oscillator clock as input and generates a master
clock output up to 96 MHz (programmable). By default, at power-up the master clock is
sourced from the main oscillator until the PLL is ready (locked) and then the CPU may
switch to the PLL source under firmware control. The CPU can switch back to the main
oscillator source at any time and turn off the PLL for low-power operation. The PLL is
always turned off in Sleep mode.
●
RTC (fRTC). A 32.768 kHz external crystal can be connected to pins X1_RTC and
X2_RTC, or an external oscillator connected to pin X1_RTC to constantly run the real-time
clock unit. This 32.768 kHz clock source can also be used as an input to the CCU to run
the CPU in slow clock mode for reduced power.
As an option, there are a number of peripherals that do not have to receive a clock sourced
from the CCU. The USB interface can receive an external clock on pin P2.7, TIM timers TIM0/
TIM1 can receive an external clock on pin P2.4, and timers TIM2/TIM3 on pin P2.5.
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STR91xF
Functional overview
Figure 2.
Clock control
25MHz
PHYSEL
MII_PHYCLK
RCLK
X1_CPU
4-25MHz
X1_CPU
Main
OSC
PLL
fMSTR
fPLL
fOSC
RCLK
DIV
(1,2,4,8,16,1024)
X1_RTC
RTC
OSC
X2_RTC
32.768kHz
(1,2,4)
APB DIV)
fRTC
EXTCLK_TOT1
16-bit prescaler
EXTCLK_T2T3
16-bit prescaler
PCLK
(1,2,4,8)
Master CLK
FMICLK
BRCLK
TIM01CLK
1/2
48MHz
1/2
To UART
TIM23CLK
USB_CLK48M
HCLK
AHB DIV
CPUCLK
USBCLK
1/2
To USB
2.10.2 Reference clock (RCLK)
The main clock (fMSTR) can be divided to operate at a slower frequency reference clock (RCLK)
for the ARM core and all the peripherals. The RCLK provides the divided clock for the ARM
core, and feeds the dividers for the AHB, APB, External Memory Interface, and FMI units.
2.10.3 AHB clock (HCLK)
The RCLK can be divided by 1, 2 or 4 to generate the AHB clock. The AHB clock is the bus
clock for the AHB bus and all bus transfers are synchronized to this clock. The maximum HCLK
frequency is 96MHz.
2.10.4 APB clock (PCLK)
The RCLK can be divided by 1, 2, 4 or 8 to generate the APB clock. The APB clock is the bus
clock for the APB bus and all bus transfers are synchronized to this clock. Many of the
peripherals that are connected to the AHB bus also use the PCLK as the source for external
bus data transfers. The maximum PCLK frequency is 48MHz.
2.10.5 Flash memory interface clock (FMICLK)
The FMICLK clock is an internal clock derived from RCLK, defaulting to RCLK frequency at
power up. The clock can be optionally divided by 2. The FMICLK determines the bus bandwidth
between the ARM core and the Flash memory. Typically, codes in the Flash memory can be
fetched one word per FMICLK clock in burst mode. The maximum FMICLK frequency is
96MHz.
2.10.6 Baud rate clock (BRCLK)
The baud rate clock is an internal clock derived from fMSTR that is used by the three on-chip
UART peripherals for baudrate generation. The frequency can be optionally divided by 2.
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Functional overview
STR91xF
2.10.7 External memory interface bus clock (BCLK)
The BCLK is an internal clock that controls the EMI bus. All EMI bus signals are synchronized
to the BCLK. The BCLK is derived from the HCLK and the frequency can be configured to be
the same or half that of the HCLK. The maximum BCLK frequency is 66MHz.
2.10.8 USB interface clock
Special consideration regarding the USB interface: The clock to the USB interface must operate
at 48 MHz and comes from one of three sources, selected under firmware control:
●
CCU master clock output of 48 MHz.
●
CCU master clock output of 96 MHz. An optional divided-by-two circuit is available to
produce 48 MHz for the USB while the CPU system runs at 96MHz.
●
STR91xF pin P2.7. An external 48 MHz oscillator connected to pin P2.7 can directly
source the USB while the CCU master clock can run at some frequency other than 48 or
96 MHz.
2.10.9 Ethernet MAC clock
Special consideration regarding the Ethernet MAC: The external Ethernet PHY interface device
requires it’s own 25 MHz clock source. This clock can come from one of two sources:
●
A 25 MHz clock signal coming from a dedicated output pin (P5.2) of the STR91xF. In this
case, the STR91xF must use a 25 MHz signal on its main oscillator input in order to pass
this 25 MHz clock back out to the PHY device through pin P5.2. The advantage here is that
an inexpensive 25 MHz crystal may be used to source a clock to both the STR91xF and
the external PHY device.
●
An external 25 MHz oscillator connected directly to the external PHY interface device. In
this case, the STR91xF can operate independent of 25 MHz.
2.10.10 Operation example
As an example of CCU operation, a 25 MHz crystal can be connected to the main oscillator
input on pins X1_CPU and X2_CPU, a 32.768 kHz crystal connected to pins X1_RTC and
X2_RTC, and the clock input of an external Ethernet PHY device is connected to STR91xF
output pin P5.2. In this case, the CCU can run the CPU at 96 MHz from PLL, the USB interface
at 48 MHz, and the Ethernet interface at 25 MHz. The RTC is always running in the background
at 32.768 kHz, and the CPU can go to very low power mode dynamically by running from
32.768 kHz and shutting off peripheral clocks and the PLL as needed.
2.11
Flexible power management
The STR91xF offers configurable and flexible power management control that allows the user
to choose the best power option to fit the application. Power consumption can be dynamically
managed by firmware and hardware to match the system’s requirements. Power management
is provided via clock control to the CPU and individual peripherals.
Clocks to the CPU and peripherals can be individually divided and gated off as needed. In
addition to individual clock divisors, the CCU master clock source going to the CPU, AHB, APB,
EMI, and FMI can be divided dynamically by as much as 1024 for low power operation.
Additionally, the CCU may switch its input to the 32 kHz RTC clock at any time for low power.
16/72
STR91xF
Functional overview
The STR91xF supports the following three global power control modes:
●
Run Mode: All clocks are on with option to gate individual clocks off via clock mask
registers.
●
Idle Mode: CPU and FMI clocks are off until an interrupt, reset, or wake-up occurs. Preconfigured clock mask registers selectively allow individual peripheral clocks to continue
run during Idle Mode.
●
Sleep Mode: All clocks off except optional RTC clock. Wake up unit remains powered,
PLL is forced off.
A special mode is used when JTAG debug is active which never gates off any clocks even if the
CPU enters Idle or Sleep mode.
2.11.1 Run mode
This is the default mode after any reset occurs. Firmware can gate off or scale any individual
clock. Also available is a special Interrupt Mode which allows the CPU to automatically run full
speed during an interrupt service and return back to the selected CPU clock divisor rate when
the interrupt has been serviced. The advantage here is that the CPU can run at a very low
frequency to conserve power until a periodic wake-up event or an asynchronous interrupt
occurs at which time the CPU runs full speed immediately.
2.11.2 Idle mode
In this mode the CPU suspends code execution and the CPU and FMI clocks are turned off
immediately after firmware sets the Idle Bit. Various peripherals continue to run based on the
settings of the mask registers that exist just prior to entering Idle Mode. There are 3 ways to exit
Idle Mode and return to Run Mode:
Note:
●
Any reset (external reset pin, watchdog, low-voltage, power-up, JTAG debug command)
●
Any interrupt (external, internal peripheral, RTC alarm or interval)
●
Input from wake-up unit on GPIO pins (optionally does not cause interrupt)
It is possible to remain in Idle Mode for the majority of the time and the RTC can be
programmed to periodically wake up to perform a brief task or check status.
2.11.3 Sleep mode
In this mode all clock circuits except the RTC are turned off and main oscillator input pins
X1_CPU and X2_CPU are disabled. The entire chip is quiescent (except for RTC and wake-up
circuitry). There are three means to exit Sleep Mode and re-start the system:
2.12
●
Some resets (external reset pin, low-voltage, power-up, JTAG debug command)
●
RTC alarm
●
Input from wake-up unit
Voltage supplies
The STR91xF requires two separate operating voltage supplies. The CPU and memories
operate from a 1.65V to 2.0V on the VDD pins, and the I/O ring operates at 2.7V to 3.6V on the
VDDQ pins.
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Functional overview
STR91xF
2.12.1 Independent A/D converter supply and reference voltage
The ADC unit on 128-pin packages has an isolated analog voltage supply input at pin AVDD to
accept a very clean voltage source, independent of the digital voltage supplies. The analog
voltage supply range on pin AVDD is the same range as the digital voltage supply on pin
VDDQ. Additionally, an isolated analog supply ground connection is provided on pin AVSS only
on 128-pin packages for further ADC supply isolation. On 80-pin packages, the analog voltage
supply is shared with the ADC reference voltage pin (as described next), and the analog ground
is shared with the digital ground at a single point in the STR91xF device on pin AVSS_VSSQ.
A separate external analog reference voltage input for the ADC unit is available on 128-pin
packages at the AVREF pin for better accuracy on low voltage inputs, and the voltage on
AVREF can range from 1.0V to VDDQ. For 80-pin packages, the ADC reference voltage is tied
internally to the ADC unit supply voltage at pin AVCC_AVREF, meaning the ADC reference
voltage is fixed to the ADC unit supply voltage.
2.12.2 Battery supply
An optional stand-by voltage from a battery or other source may be connected to pin VBATT to
retain the contents of SRAM in the event of a loss of the VDD supply. The SRAM will
automatically switch its supply from the internal VDD source to the VBATT pin when the voltage
of VDD drops below that of VBATT.
The VBATT pin also supplies power to the RTC unit, allowing the RTC to function even when
the main digital supplies (VDD and VDDQ) are switched off. Using the STR91xF device
configuration software tool, it is possible to select whether or not to power from VBATT only the
RTC unit, or power the RTC unit and the SRAM when the STR91xF device is powered off.
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STR91xF
2.13
Functional overview
System supervisor
The STR91xF monitors several system and environmental inputs and will generate a global
reset, a system reset, or an interrupt based on the nature of the input and configurable settings.
A global reset clears all functions on the STR91xF, a system reset will clear all but the Clock
Control Unit (CCU) settings and the system status register. At any time, firmware may reset
individual on-chip peripherals. System supervisor inputs include:
Note:
●
GR: CPU voltage supply (VDD) drop out or brown out
●
GR: I/O voltage supply (VDDQ) drop out or brown out
●
GR: Power-Up condition
●
SR: Watchdog timer timeout
●
SR: External reset pin (RESET_INn)
●
SR: JTAG debug reset command
GR: means the input causes Global Reset, SR: means the input causes System Reset
The CPU may read a status register after a reset event to determine if the reset was caused by
a watchdog timer timeout or a voltage supply drop out. This status register is cleared only by a
power up reset.
2.13.1 Supply voltage brownout
Each operating voltage source (VDD and VDDQ) is monitored separately by the Low Voltage
Detect (LVD) circuitry. The LVD will generate an early warning interrupt to the CPU when
voltage sags on either VDD or VDDQ voltage inputs. This is an advantage for battery powered
applications because the system can perform an orderly shutdown before the batteries become
too weak. The voltage trip point to cause a brown out interrupt is typically 0.25V above the LVD
dropout thresholds that cause a reset.
CPU firmware may prevent all brown-out interrupts by writing to interrupt mask registers at runtime.
2.13.2 Supply voltage dropout
LVD circuitry will always cause a global reset if the CPU’s VDD source drops below it’s fixed
threshold of 1.4V.
However, the LVD trigger threshold to cause a global reset for the I/O ring’s VDDQ source is set
to one of two different levels, depending if VDDQ will be operated in the range of 2.7V to 3.3V, or
3.0V to 3.6V. If VDDQ operation is at 2.7V to 3.3V, the LVD dropout trigger threshold is 2.4V. If
VDDQ operation is 3.0V and 3.6V, the LVD threshold is 2.7V. The choice of trigger level is made
by STR91xF device configuration software from STMicroelectronics, and is programmed into
the STR91xF device along with other configurable items through the JTAG interface when the
Flash memory is programmed.
CPU firmware may prevent some LVD resets if desired by writing a control register at run-time.
Firmware may also disable the LVD completely for lowest-power operation when an external
LVD device is being used.
2.13.3 Watchdog timer
The STR91xF has a 16-bit down-counter (not one of the four TIM timers) that can be used as a
watchdog timer or as a general purpose free-running timer/counter. The clock source is the
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Functional overview
STR91xF
peripheral clock from the APB, and an 8-bit clock pre-scaler is available. When enabled by
firmware as a watchdog, this timer will cause a system reset if firmware fails to periodically
reload this timer before the terminal count of 0x0000 occurs, ensuring firmware sanity. The
watchdog function is off by default after a reset and must be enabled by firmware.
2.13.4 External RESET_INn pin
This input signal is active-low with hystereses (VRHYS). Other open-drain, active-low system
reset signals on the circuit board (such as closure to ground from a push-button) may be
connected directly to the RESET_INn pin, but an external pull-up resistor to VDDQ must be
present as there is no internal pullup on the RESET_INn pin.
A valid active-low input signal of tRINMIN duration on the RESET_INn pin will cause a system
reset within the STR91xF. There is also a RESET_OUTn pin on the STR91xF that can drive
other system components on the circuit board. RESET_OUTn is active-low and has the same
timing of the Power-On-Reset (POR) shown next, tPOR.
2.13.5 Power-up
The LVD circuitry will always generate a global reset when the STR91xF powers up, meaning
internal reset is active until VDDQ and VDD are both above the LVD thresholds. This POR
condition has a duration of tPOR, after which the CPU will fetch its first instruction from address
0x0000.0000.
2.13.6 JTAG debug command
When the STR91xF is in JTAG debug mode, an external device which controls the JTAG
interface can command a system reset to the STR91xF over the JTAG channel.
2.13.7 Tamper detection
On 128-pin STR91xF devices only, there is a tamper detect input pin, TAMPER_IN, used to
detect and record the time of a tamper event on the end product such as malicious opening of
an enclosure, unwanted opening of a panel, etc. The activation mode of the tamper pin is
programmable to one of two modes. One is Normally Closed/Tamper Open, the other mode will
detect when a signal on the tamper input pin is driven from low-to-high, or high-to-low
depending on firmware configuration. Once a tamper event occurs, the RTC time (millisecond
resolution) and the date are recorded in the RTC unit. Simultaneously, the SRAM standby
voltage source will be cut off to invalidate all SRAM contents. Tamper detection control and
status logic are part of the RTC unit.
2.14
Real-time clock (RTC)
The RTC combines the functions of a complete time-of-day clock (millisecond resolution) with
an alarm programmable up to one month, a 9999-year calender with leap-year support,
periodic interrupt generation from 1 to 512 Hz, tamper detection (described in Section 2.13.7),
and an optional clock calibration output on the JRTCK pin. The time is in 24 hour mode, and
time/calendar values are stored in binary-coded decimal format.
The RTC also provides a self-isolation mode that is automatically activated during power down.
This feature allows the RTC to continue operation when VDDQ and VDD are absent, as long as
an alternate power source, such as a battery, is connected to the VBATT input pin. The current
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STR91xF
Functional overview
drawn by the RTC unit on the VBATT pin is very low in this standby mode, IRTC_STBY (this
assumes SRAM battery backup is not enabled).
2.15
JTAG interface
An IEEE-1149.1 JTAG interface on the STR91xF provides In-System-Programming (ISP) of all
memory, boundary scan testing of pins, and the capability to debug the CPU.
Six pins are used on this JTAG serial interface. The five signals JTDI, JTDO, JTMS, JTCK, and
JTRSTn are all standard JTAG signals complying with the IEEE-1149.1 specification. The sixth
signal, JRTCK (Return TCK), is an output from the STR91xF and it is used to pace the JTCK
clock signal coming in from the external JTAG test equipment for debugging. The frequency of
the JTCK clock signal coming from the JTAG test equipment must be at least 10 times less than
the ARM966E-S CPU core operating frequency (fCPUCLK). To ensure this, the signal JRTCK is
output from the STR91xF and is input to the external JTAG test equipment to hold off transitions
of JTCK until the CPU core is ready, meaning that the JTAG equipment cannot send the next
rising edge of JTCK until the equipment receives a rising edge of JRTCK from the STR91xF.
The JTAG test equipment must be able to interpret the signal JRTCK and perform this adaptive
clocking function. If it is known that the CPU clock will always be at least ten times faster than
the incoming JTCK clock signal, then the JRTCK signal is not needed.
The two die inside the STR91xF (CPU die and Flash memory die) are internally daisy-chained
on the JTAG bus, see Figure 3 on page 22. The CPU die has two JTAG Test Access Ports
(TAPs), one for boundary scan functions and one for ARM CPU debug. The Flash memory die
has one TAP for program/erase of non-volatile memory. Because these three TAPs are daisychained, only one TAP will converse on the JTAG bus at any given time while the other two
TAPs are in BYPASS mode. The TAP positioning order within this JTAG chain is the boundary
scan TAP first, followed by the ARM debug TAP, followed by the Flash TAP. All three TAP
controllers are reset simultaneously by one of two methods:
●
A chip-level global reset, caused only by a Power-On-Reset (POR) or a Low Voltage
Detect (LVD).
●
A reset command issued by the external JTAG test equipment. This can be the assertion
of the JTAG JTRSTn input pin on the STR91xF or a JTAG reset command shifted into the
STR91xF serially.
This means that chip-level system resets from watchdog time-out or the assertion of
RESET_INn pin do not affect the operation of any JTAG TAP controller. Only global resets
effect the TAPs.
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STR91xF
Functional overview
Figure 3.
JTAG chaining inside the STR91xF
STR91xx
MAIN FLASH
SECONDARY FLASH
JTAG TAP CONTROLLER #3
TDO
TMS
TCK TRST
TDI
BURST FLASH
MEMORY DIE
JTAG
Instruction
register length
is 8 bits
JTDO
JTRSTn
JTCK
JTMS
JTDI
ARM966ES DIE
JRTCK
TDI
TMS
TCK TRST
JTAG TAP CONTROLLER #1
BOUNDARY SCAN
TDO
TDI
TRST
TCK
TMS
JTAG TAP CONTROLLER #2
TDO
JTAG
Instruction
register length:
5 bits for TAP #1
4 bits for TAP #2
CPU DEBUG
2.15.1 In-system-programming
The JTAG interface is used to program or erase all memory areas of the STR91xF device. The
pin RESET_INn must be asserted during ISP to prevent the CPU from fetching invalid
instructions while the Flash memories are being programmed.
Note that the 32 bytes of OTP memory locations cannot be erased by any means once
programmed by JTAG ISP or the CPU.
2.15.2 Boundary scan
Standard JTAG boundary scan testing compliant with IEEE-1149.1 is available on the majority
of pins of the STR91xF for circuit board test during manufacture of the end product. STR91xF
pins that are not serviced by boundary scan are the following:
●
JTAG pins JTCK, JTMS, JTDI, JTDO, JTRSTn, JRTCK
●
Oscillator input pins X1_CPU, X2_CPU, X1_RTC, X2_RTC
●
Tamper detect input pin TAMPER_IN (128-pin package only)
2.15.3 CPU debug
The ARM966E-S CPU core has standard ARM EmbeddedICE-RT logic, allowing the STR91xF
to be debugged through the JTAG interface. This provides advanced debugging features
making it easier to develop application firmware, operating systems, and the hardware itself.
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STR91xF
Functional overview
Debugging requires that an external host computer, running debug software, is connected to
the STR91xF target system via hardware which converts the stream of debug data and
commands from the host system’s protocol (USB, Ethernet, etc.) to the JTAG EmbeddedICERT protocol on the STR91xF. These protocol converters are commercially available and
operate with debugging software tools.
The CPU may be forced into a Debug State by a breakpoint (code fetch), a watchpoint (data
access), or an external debug request over the JTAG channel, at which time the CPU core and
memory system are effectively stopped and isolated from the rest of the system. This is known
as Halt Mode and allows the internal state of the CPU core, memory, and peripherals to be
examined and manipulated. Typical debug functions are supported such as run, halt, and
single-step. The EmbeddedICE-RT logic supports two hardware compare units. Each can be
configured to be either a watchpoint or a breakpoint. Breakpoints can also be data-dependent.
Debugging (with some limitations) may also occur through the JTAG interface while the CPU is
running full speed, known as Monitor Mode. In this case, a breakpoint or watchpoint will not
force a Debug State and halt the CPU, but instead will cause an exception which can be tracked
by the external host computer running monitor software. Data can be sent and received over
the JTAG channel without affecting normal instruction execution. Time critical code, such as
Interrupt Service Routines may be debugged real-time using Monitor Mode.
2.15.4 JTAG security bit
This is a non-volatile bit (Flash memory based), which when set will not allow any further JTAG
commands to be accepted by the STR91xF except the “Full Chip Erase” command. No JTAG
debug commands are accepted while the security bit is set.
Using JTAG ISP, this bit is typically programmed during manufacture of the end product to
prevent unwanted future access to firmware intellectual property. The JTAG Security Bit can be
cleared only by a JTAG “Full Chip Erase” command, making the STR91xF device blank and
ready for programming again. The CPU can read the status of the JTAG Security Bit, but it may
not change the bit value.
2.16
Embedded trace module (ARM ETM9, v. r2p2)
The ETM9 interface provides greater visibility of instruction and data flow happening inside the
CPU core by streaming compressed data at a very high rate from the STR91xF though a small
number of ETM9 pins to an external Trace Port Analyzer (TPA) device. The TPA is connected to
a host computer using USB, Ethernet, or other high-speed channel. Real-time instruction flow
and data activity can be recorded and later formatted and displayed on the host computer
running debugger software, and this software is typically integrated with the debug software
used for EmbeddedICE-RT functions such as single-step, breakpoints, etc. Tracing may be
triggered and filtered by many sources, such as instruction address comparators, data
watchpoints, context ID comparators, and counters. State sequencing of up to three triggers is
also provided. TPA hardware is commercially available and operates with debugging software
tools.
The ETM9 interface is nine pins total, four of which are data lines, and all pins can be used for
GPIO after tracing is no longer needed. The ETM9 interface is used in conjunction with the
JTAG interface for trace configuration. When tracing begins, the ETM9 engine compresses the
data by various means before broadcasting data at high speed to the TPA over the four data
lines. The most common ETM9 compression technique is to only output address information
when the CPU branches to a location that cannot be inferred from the source code. This means
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Functional overview
STR91xF
the host computer must have a static image of the code being executed for decompressing the
ETM9 data. Because of this, self-modified code cannot be traced.
2.17
Ethernet MAC interface with DMA
STR91xF devices in the 128-pin package provide an IEEE-802.3-2002 compliant Media
Access Controller (MAC) for Ethernet LAN communications through an industry standard
Medium Independent Interface (MII). The STR91xF requires an external Ethernet physical
interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is
connected to the STR91xF MII port using as many as 18 signals (see pins which have signal
names MII_* in Table 2).
The MAC corresponds to the OSI Data Link layer and the PHY corresponds to the OSI Physical
layer. The STR91xF MAC is responsible for:
●
Data encapsulation, including frame assembly before transmission, and frame parsing/
error detection during and after reception.
●
Media access control, including initiation of frame transmission and recover from
transmission failure.
The STR91xF MAC includes the following features:
●
Supports 10 and 100 Mbps rates
●
Tagged MAC frame support (VLAN support)
●
Half duplex (CSMA/CD) and full duplex operation
●
MAC control sublayer (control frames) support
●
32-bit CRC generation and removal
●
Several address filtering modes for physical and multicast address (multicast and group
addresses)
●
32-bit status code for each transmitted or received frame
●
Internal FIFOs to buffer transmit and receive frames. Transmit FIFO depth is 4 words (32
bits each), and the receive FIFO is 16 words deep.
A 32-bit burst DMA channel residing on the AHB is dedicated to the Ethernet MAC for highspeed data transfers, side-stepping the CPU for minimal CPU impact during transfers. This
DMA channel includes the following features:
2.18
●
Direct SRAM to MAC transfers of transmit frames with the related status, by descriptor
chain
●
Direct MAC to SRAM transfers of receive frames with the related status, by descriptor
chain
●
Open and Closed descriptor chain management
USB 2.0 slave device interface with DMA
The STR91xF provides a USB slave controller that implements both the OSI Physical and Data
Link layers for direct bus connection by an external USB host on pins USBDP and USBPN. The
USB interface detects token packets, handles data transmission and reception, and processes
handshake packets as required by the USB 2.0 standard.
The USB slave interface includes the following features:
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STR91xF
Functional overview
●
Supports USB low and full-speed transfers (12 Mbps), certified to comply with the USB 2.0
specification
●
Supports isochronous, bulk, control, and interrupt endpoints
●
Configurable number of endpoints allowing a mixture of up to 20 single-buffered
monodirectional endpoints or up to 10 double-buffered bidirectional endpoints
●
Dedicated, dual-port 2 Kbyte USB Packet Buffer SRAM. One port of the SRAM is
connected by a Packet Buffer Interface (PBI) on the USB side, and the CPU connects to
the other SRAM port.
●
CRC generation and checking
●
NRZI encoding-decoding and bit stuffing
●
USB suspend resume operations
2.18.1 Packet buffer interface (PBI)
The PBI manages a set of buffers inside the 2 Kbyte Packet Buffer, both for transmission and
reception. The PBI will choose the proper buffer according to requests coming from the USB
Serial Interface Engine (SIE) and locate it in the Packet SRAM according to addresses pointed
by endpoint registers. The PBI will also auto-increment the address after each exchanged byte
until the end of packet, keeping track of the number of exchanged bytes and preventing buffer
overrun. Special support is provided by the PBI for isochronous and bulk transfers,
implementing double-buffer usage which ensures there is always an available buffer for a USB
packet while the CPU uses a different buffer.
2.18.2 DMA
A programmable DMA channel may be assigned by CPU firmware to service the USB interface
for fast and direct transfers between the USB bus and SRAM with little CPU involvement. This
DMA channel includes the following features:
●
Direct USB Packet Buffer SRAM to system SRAM transfers of receive packets, by
descriptor chain for bulk or isochronous endpoints.
●
Direct system SRAM to USB Packet Buffer SRAM transfers of transmit packets, by
descriptor chain for bulk or isochronous endpoints.
●
Linked-list descriptor chain support for multiple USB packets
2.18.3 Suspend mode
CPU firmware may place the USB interface in a low-power suspend mode when required, and
the USB interface will automatically wake up asynchronously upon detecting activity on the
USB pins.
2.19
CAN 2.0B interface
The STR91xF provides a CAN interface complying with CAN protocol version 2.0 parts A and
B. An external CAN transceiver device connected to pins CAN_RX and CAN_TX is required for
connection to the physical CAN bus.
The CAN interface manages up to 32 Message Objects and Identifier Masks using a Message
SRAM and a Message Handler. The Message Handler takes care of low-level CAN bus activity
such as acceptance filtering, transfer of messages between the CAN bus and the Message
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Functional overview
STR91xF
SRAM, handling of transmission requests, and interrupt generation. The CPU has access to
the Message SRAM via the Message Handler using a set of 38 control registers.
The follow features are supported by the CAN interface:
●
Bitrates up to 1 Mbps
●
Disable Automatic Retransmission mode for Time Triggered CAN applications
●
32 Message Objects
●
Each Message Object has its own Identifier Mask
●
Programmable FIFO mode
●
Programmable loopback mode for self-test operation
The CAN interface is not supported by DMA.
2.20
UART interfaces with DMA
The STR91xF supports three independent UART serial interfaces, designated UART0, UART1,
and UART2. Each interface is very similar to the industry-standard 16C550 UART device. All
three UART channels support IrDA encoding/decoding, requiring only an external LED
transceiver to pins UARTx_RX and UARTx_Tx for communication. One UART channel
(UART0) supports full modem control signals.
UART interfaces include the following features:
●
Maximum baud rate of 460.8 Kbps
●
Separate FIFOs for transmit and receive, each 16 deep, each FIFO can be disabled by
firmware if desired
●
Programmable FIFO trigger levels between 1/8 and 7/8
●
Programmable baud rate generator based on CCU master clock, or CCU master clock
divided by two
●
Programmable serial data lengths of 5, 6, 7, or 8 bits with start bit and 1 or 2 stop bits
●
Programmable selection of even, odd, or no-parity bit generation and detection
●
False start-bit detection
●
Line break generation and detection
●
Support of IrDA SIR ENDEC functions for data rates of up to 115.2K bps
●
IrDA bit duration selection of 3/16 or low-power (1.14 to 2.23 µsec)
●
Channel UART0 supports modem control functions CTS, DCD, DSR, RTS, DTR, and RI
For your reference, only two standard 16550 UART features are not supported, 1.5 stop bits
and independent receive clock.
2.20.1 DMA
A programmable DMA channel may be assigned by CPU firmware to service channels UART0
and UART1 for fast and direct transfers between the UART bus and SRAM with little CPU
involvement. Both DMA single-transfers and DMA burst-transfers are supported for transmit
and receive. Burst transfers require that UART FIFOs are enabled.
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STR91xF
2.21
Functional overview
I2C interfaces with DMA
The STR91xF supports two independent I2C serial interfaces, designated I2C0, and I2C1.
Each interface allows direct connection to an I2C bus as either a bus master or bus slave
device (firmware configurable). I2C is a two-wire communication channel, having a bidirectional data signal and a single-directional clock signal based on open-drain line drivers,
requiring external pull-up resistors.
Byte-wide data is transferred between a Master device and a Slave device on two wires. More
than one bus Master is allowed, but only one Master may control the bus at any given time.
Data is not lost when another Master requests the use of a busy bus because I2C supports
collision detection and arbitration. More than one Slave device may be present on the bus, each
having a unique address. The bus Master initiates all data movement and generates the clock
that permits the transfer. Once a transfer is initiated by the Master, any device that is addressed
is considered a Slave. Automatic clock synchronization allows I2C devices with different bit
rates to communicate on the same physical bus. A single device can play the role of Master or
Slave, or a single device can be a Slave only. A Master or Slave device has the ability to
suspend data transfers if the device needs more time to transmit or receive data.
Each I2C interface on the STR91xF has the following features:
●
Programmable clock supports various rates up to I2C Standard rate (100 KHz) or Fast rate
(400 KHz).
●
Serial I/O Engine (SIOE) takes care of serial/parallel conversion; bus arbitration; clock
generation and synchronization; and handshaking
●
Multi-master capability
●
7-bit or 10-bit addressing
2.21.1 DMA
A programmable DMA channel may be assigned by CPU firmware to service each I2C channel
for fast and direct transfers between the I2C bus and SRAM with little CPU involvement. Both
DMA single-transfers and DMA burst-transfers are supported for transmit and receive.
2.22
SSP interfaces (SPI, SSI, and Microwire) with DMA
The STR91xF supports two independent Synchronous Serial Port (SSP) interfaces, designated
SSP0, and SSP1. Primary use of each interface is for supporting the industry standard Serial
Peripheral Interface (SPI) protocol, but also supporting the similar Synchronous Serial Interface
(SSI) and Microwire communication protocols.
SPI is a three or four wire synchronous serial communication channel, capable of full-duplex
operation. In three-wire configuration, there is a clock signal, and two data signals (one data
signal from Master to Slave, the other from Slave to Master). In four-wire configuration, an
additional Slave Select signal is output from Master and received by Slave.
The SPI clock signal is a gated clock generated from the Master and regulates the flow of data
bits. The Master may transmit at a variety of baud rates, up to 24 MHz
In multi-Slave operation, no more than one Slave device can transmit data at any given time.
Slave selection is accomplished when a Slave’s “Slave Select” input is permanently grounded
or asserted active-low by a Master device. Slave devices that are not selected do not interfere
with SPI activities. Slave devices ignore the clock signals and keep their data output pins in
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STR91xF
Functional overview
high-impedance state when not selected. The STR91xF supports SPI multi-Master operation
because it provides collision detection.
Each SSP interface on the STR91xF has the following features:
●
Full-duplex, three or four-wire synchronous transfers
●
Master or Slave operation
●
Programmable clock bit rate with prescaler, up to 24MHz for Master and 4MHz for Slave
●
Separate transmit and receive FIFOs, each 16-bits wide and 8 locations deep
●
Programmable data frame size from 4 to 16 bits
●
Programmable clock and phase polarity
●
Specifically for Microwire protocol:
–
●
Half-duplex transfers using 8-bit control message
Specifically for SSI protocol:
–
Full-duplex four-wire synchronous transfer
–
Transmit data pin tri-stateable when not transmitting
2.22.1 DMA
A programmable DMA channel may be assigned by CPU firmware to service each SSP
channel for fast and direct transfers between the SSP bus and SRAM with little CPU
involvement. Both DMA single-transfers and DMA burst-transfers are supported for transmit
and receive. Burst transfers require that FIFOs are enabled.
2.23
General purpose I/O
There are up to 80 GPIO pins available on 10 I/O ports for 128-pin devices, and up to 48 GPIO
pins on 6 I/O ports for 80-pin devices. Each and every GPIO pin by default (during and just after
a reset condition) is in high-impedance input mode, and some GPIO pins are additionally
routed to certain peripheral function inputs. CPU firmware may initialize GPIO pins to have
alternate input or output functions as listed in Table 2. At any time, the logic state of any GPIO
pin may be read by firmware as a GPIO input, regardless of its reassigned input or output
function.
Bit masking is available on each port, meaning firmware may selectively read or write individual
port pins, without disturbing other pins on the same port during a write.
Firmware may designate each GPIO pin to have open-drain or push-pull characteristics.
All GPIO pins are 5V tolerant, meaning in they can drive a voltage level up to VDDQ, and can be
safely driven by a voltage up to 5.5V.
There are no internal pull-up or pull-down resistors on GPIO pins. As such, it is recommended
to ground all unused GPIO pins to minimize power consumption and noise generation.
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STR91xF
2.24
Functional overview
A/D converter (ADC)
The STR91xF provides an eight-channel, 10-bit successive approximation analog-to-digital
converter. The ADC input pins are multiplexed with other functions on Port 4 as shown in
Table 2. Following are the major ADC features:
2.25
●
Fast conversion time, as low as 2 usec
●
Accuracy. Integral and differential non-linearity are both +/- 2 LSB (4 conversion counts).
●
0 to 3.6V input range. External reference voltage input pin (AVREF) available on 128-pin
packages for better accuracy on low-voltage inputs. The voltage on AVREF can range
from 1.0V to VDDQ.
●
CPU Firmware may convert one ADC input channel at a time, or it has the option to set the
ADC to automatically scan and convert all eight ADC input channels sequentially before
signalling an end-of-conversion
●
Automatic continuous conversion mode is available for any number of designated ADC
input channels
●
Analog watchdog mode provides automatic monitoring of any ADC input, comparing it
against two programmable voltage threshold values. The ADC unit will set a flag or it will
interrupt the CPU if the input voltage rises above the higher threshold, or drops below the
lower threshold.
●
The ADC unit goes to stand-by mode (very low-current consumption) after any reset event.
CPU firmware may also command the ADC unit to stand-by mode at any time.
Standard timers (TIM) with DMA
The STR91xF has four independent, free-running 16-bit timer/counter modules designated
TIM0, TIM1, TIM2, and TIM3. Each general purpose timer/counter can be configured by
firmware for a variety of tasks including; pulse width and frequency measurement (input
capture), generation of waveforms (output compare and PWM), event counting, delay timing,
and up/down counting.
Each of the four timer units have the following features:
●
16-bit free running timer/counter
●
Internal timer/counter clock source from a programmable 8-bit prescale of the CCU PCLK
clock output
●
Optional external timer/counter clock source from pin P2.4 shared by TIM0/TIM1, and pin
P2.5 shared by TIM2/TIM3. Frequency of these external clocks must be at least 4 times
less the frequency of the internal CCU PCLK clock output
●
Two dedicated 16-bit Input Capture registers for measuring up to two input signals. Input
Capture has programmable selection of input signal edge detection
●
Two dedicated 16-bit Output Compare registers for generation up to two output signals
●
PWM output generation with 16-bit resolution of both pulse width and frequency
●
One pulse generation in response to an external event
●
A dedicated interrupt to the CPU with five interrupt flags
2.25.1 DMA
A programmable DMA channel may be assigned by CPU firmware to service each timer/
counter module TIM0 and TIM1 for fast and direct transfers.
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Functional overview
2.26
STR91xF
Three-phase induction motor controller (IMC)
The STR91xF provides an integrated controller for variable speed motor control applications.
Six PWM outputs are generated on high current drive pins P6.0 to P6.5 for controlling a threephase AC induction motor drive circuit assembly. Rotor speed feedback is provided by
capturing a tachometer input signal on pin P6.6, and an asynchronous hardware emergency
stop input is available on pin P6.7 to stop the motor immediately if needed, independently of
firmware.
The IMC unit has the following features:
2.27
●
Three PWM outputs generated using a 10-bit PWM counter, one for each phase U, V, W.
Complimentary PWM outputs are also generated for each phase.
●
Choice of classic or zero-centered PWM generation modes
●
10-bit PWM counter clock is supplied through a programmable 8-bit prescaler of the APB
clock.
●
Programmable 6-bit dead-time generator to add delay to each of the three complimentary
PWM outputs
●
8-bit repetition counter
●
Automatic rotor speed measurement with 16-bit resolution. Schmitt trigger tachometer
input with programmable edge detection
●
Hardware asynchronous emergency stop input
●
A dedicated interrupt to CPU with eight flags
External memory interface (EMI)
STR91xF devices in 128-pin packages offer an external memory bus for connecting external
parallel peripherals and memories. The EMI bus resides on ports 7, 8, and 9 and operates with
either an 8 or 16-bit data path. The configuration of 8 or 16 bit mode is specified by CPU
firmware writing to configuration registers at run-time. If the application does not use the EMI
bus, then these port pins may be used for general purpose I/O as shown in Table 2.
The EMI has the following features:
30/72
●
Supports static asynchronous memory access cycles, including page mode for non-mux
operation
●
Four configurable memory regions, each with a chip select output (EMI_CS0n ...
EMI_CS3n)
●
Programmable wait states per memory region for both write and read operations
●
16-bit multiplexed data mode (Figure 4): 16 bits of data and 16 bits of low-order address
are multiplexed together on ports 8 and 9, while port 7 contains eight more high-order
address signals. The output signal on pin EMI_ALE is used to demultiplex the signals on
ports 8 and 9, and the polarity of EMI_ALE is programmable. The output signals on pins
EMI_BWR_WRLn and EMI_WRHn are the write strobes for the low and high data bytes
respectively. The output signal EMI_RDn is the read strobe for both the low and high data
bytes.
●
8-bit multiplexed data mode: This is a variant of the 16-bit multiplexed mode. Although
this mode can provide 24 bits of address and 8 bits of data, it does require an external
latch device on Port 8. However, this mode is most efficient when connecting devices that
STR91xF
Functional overview
only require 8 bits of address on an 8-bit multiplexed address/data bus, and have simple
read, write, and latch inputs as shown in Figure 5
To use all 24 address bits, the following applies: 8 bits of lowest-order data and 8 bits of
lowest-order address are multiplexed on port 8. On port 9, 8-bits of mid-order address are
multiplexed with 8 bits of data, but these 8 data values are always at logic zero on this port
during a write operation, and these 8 data bits are ignored during a read operation. An
external latch device (such as a ‘373 latch) is needed to de-multiplex the mid-order 8
address bits that are generated on port 8. Port 7 outputs the 8 highest-order address
signals directly (not multiplexed). The output signal on pin EMI_ALE is used to demultiplex
the signals on ports 8 and 9, and the polarity of EMI_ALE is programmable. The output
signal on pin EMI_BWR_WRLn is the data write strobe, and the output on pin EMI_RDn is
the data read strobe.
●
8-bit non-multiplexed data mode (Figure 6): Eight bits of data are on port 8, while 16 bits
of address are output on ports 7 and 9. The output signal on pin EMI_BWR_BWLn is the
data write strobe and the output on pin EMI_RDn is the data read strobe.
Figure 4.
EMI 16-bit multiplexed connection example
STR91xx
16-BIT
DEVICE
EMI_CS3n
EMI_CS2n
EMI_CS1n
EMI_CS0n
CHIP_SELECT
EMI_WRHn
EMI_BWR_WRLn
WRITE_HIGH_BYTE
WRITE_LOW_BYTE
EMI_RDn
EMI_ALE
(1)
EMI_A23
EMI_A22
EMI_A21
EMI_A20
EMI_A19
EMI_A18
EMI_A17
EMI_A16
EMI_AD15
EMI_AD14
EMI_AD13
EMI_AD12
EMI_AD11
EMI_AD10
READ
ADDR_LATCH
P7.7
P7.6
P7.5
P7.4
P7.3
P7.2
P7.1
P7.0
P9.7
P9.6
P9.5
P9.4
P9.3
P9.2
P9.1
EMI_AD9
P9.0
EMI_AD8
EMI_AD7
P8.7
P8.6
EMI_AD6
P8.5
EMI_AD5
P8.4
EMI_AD4
P8.3
EMI_AD3
P8.2
EMI_AD2
P8.1
EMI_AD1
P8.0
EMI_AD0
A23
A22
A21
A20
A19
A18
A17
A16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
31/72
STR91xF
Functional overview
Figure 5.
EMI 8-bit multiplexed connection example
ST R91xx EMI_CS3n
EMI_CS2n
EMI_CS1n
EMI_CS0n
8-BIT
DEVICE
CHIP_SELECT
EMI_BWR_WRLn
EMI_RDn
EMI_ALE
EMI_AD7
EMI_AD6
EMI_AD5
EMI_AD4
EMI_AD3
EMI_AD2
EMI_AD1
EMI_AD0
Figure 6.
P8.7
P8.6
P8.5
P8.4
P8.3
P8.2
P8.1
P8.0
AD 7
AD 6
AD 5
AD 4
AD 3
AD 2
AD 1
AD 0
EMI 8-bit non-multiplexed connection example
STR91xx
8-BIT
DEVICE
EMI_CS3n
EMI_CS2n
EMI_CS1n
EMI_CS0n
CHIP_SELECT
EMI_BWR_WRLn
EMI_RDn
EMI_A15
EMI_A14
EMI_A13
EMI_A12
EMI_A11
EMI_A10
EMI_A9
EMI_A8
EMI_A7
EMI_A6
EMI_A5
EMI_A4
EMI_A3
EMI_A2
EMI_A1
EMI_A0
EMI_D7
EMI_D6
EMI_D5
EMI_D4
EMI_D3
EMI_D2
EMI_D1
EMI_D0
32/72
WRIT E
READ
ADDR_LAT CH
WRITE
READ
P9.7
P9.6
P9.5
P9.4
P9.3
P9.2
P9.1
P9.0
P7.7
P7.6
P7.5
P7.4
P7.3
P7.2
P7.1
P7.0
P8.7
P8.6
P8.5
P8.4
P8.3
P8.2
P8.1
P8.0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
STR91xF
3
Related documentation
Related documentation
Available from www.arm.com:
ARM966E-S Rev 2 Technical Reference Manual
Available from www.st.com:
STR91xF Reference Manual
STR9 Flash Programming Manual (PM0020)
The above is a selected list only, a full list STR91xF application notes can be viewed at
http://www.st.com.
33/72
STR91xF
Pin description
4
Pin description
STR91xFM 80-pin package pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P4.4
P4.5
P4.6
P4.7
AVREF_AVDD
VSSQ
VDDQ
JTDO
JTDI
VSS
VDD
JTMS
JTCK
JTRSTn
VSSQ
X1_CPU
X2_CPU
VDDQ
RESET_OUTn
JRTCK
Figure 7.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
STR91xFM
80-pin LQFP
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
USBDP (1)
USBDN (1)
P6.7
P6.6
RESET_INn
VSSQ
VDDQ
P6.5
P6.4
VSS
VDD
P5.7
P5.6
P5.5
VDDQ
VSSQ
P5.4
P3.7
P3.6
P3.5
P2.2
P2.3
P2.4
VBATT
VSSQ
X2_RTC
X1_RTC
VDDQ
P2.5
VSS
VDD
P2.6
(2) USBCLK_P.27
P3.0
VSSQ
VDDQ
P3.1
P3.2
P3.3
P3.4
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P4.3
P4.2
P4.1
P4.0
VSS_VSSQ
VDDQ
P2.0
P2.1
P5.0
VSS
VDD
P5.1
P6.2
P6.3
VDDQ
VSSQ
P5.2
P5.3
P6.0
P6.1
1)NU (Not Used) on STR910FM devices. Pin 59 is not connected, pin 60 must be pulled up by a 1.5Kohm resistor to VDDQ.
2) No USBCLK function on STR910FM devices.
34/72
STR91xF
Pin description
STR91xFW 128-pin package pinout
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
P4.3
P4.4
P4.5
P4.6
P4.7
AVREF
AVDD
VSSQ
VDDQ
P7.7
P7.6
JTDO
P1.7
JTDI
P1.6
VSS
VDD
JTMS
P1.5
P1.4
JTCK
JTRSTn
P1.3
VSSQ
X1_CPU
X2_CPU
VDDQ
P1.2
RESET_OUTn
P1.1
P1.0
JRTCK
Figure 8.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
STR91xFW
128-pin LQFP
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
USBDP (1)
USBDN (1)
MII_MDIO (1)
P6.7
P6.6
TAMPER_IN
P0.7
RESET_INn
P0.6
VSSQ
VDDQ
P0.5
P6.5
P6.4
VSS
VDD
P5.7
P5.6
P0.4
P5.5
P0.3
EMI_RDn
EMI_ALE
VDDQ
VSSQ
P0.2
P5.4
P0.1
P3.7
P0.0
P3.6
P3.5
P2.2
P8.4
P2.3
P8.5
P2.4
P8.6
VBATT
VSSQ
X2_RTC
X1_RTC
VDDQ
P8.7
P2.5
P9.0
P9.1
VSS
VDD
P9.2
P9.3
P9.4
P2.6
(2) USBCLK_P2.7
P3.0
VSSQ
VDDQ
P9.5
P3.1
P3.2
P3.3
P9.6
P3.4
P9.7
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P4.2
P4.1
P4.0
AVSS
P7.0
P7.1
P7.2
VSSQ
VDDQ
P2.0
P2.1
P5.0
P7.3
P7.4
P7.5
VSS
VDD
P5.1
P6.2
P6.3
EMI_BWR_WRLn
EMI_WRHn
VDDQ
VSSQ
(3) PHYCLK_P5.2
P8.0
P5.3
P8.1
P6.0
P8.2
P6.1
P8.3
1)NU (Not Used) on STR910FW devices. Pin 95 is not connected, pin 96 must be pulled up by a 1.5Kohm resistor to VDDQ.
2) No USBCLK function on STR910FW devices.
3) No PHYCLK function on STR910FW devices.
35/72
STR91xF
Pin description
4.1
Default pin functions
During and just after reset, all pins on ports 0-9 default to high-impedance input mode until
CPU firmware assigns other functions to the pins. This initial input mode routes all pins on ports
0-9 to be read as GPIO inputs as shown in the “Default Pin Function” column of Table 2.
Simultaneously, certain port pin signals are also routed to other functional inputs as shown in
the “Default Input Function” column of Table 2, and these pin input functions will remain until
CPU firmware makes other assignments. At any time, even after the CPU assigns pins to
alternate functions, the CPU may always read the state of any pin on ports 0-9 as a GPIO input.
CPU firmware may assign alternate functions to port pins as shown in columns “Alternate Input
1” or “Alternate Output 1, 2, 3” of Table 2 by writing to control registers at run-time.
Notes for Table 2:
Notes: 1 STMicroelectronics advises to ground all unused pins on port 0 - 9 to reduce noise
susceptibility, noise generation, and minimize power consumption. There are no internal or
programmable pull-up resistors on ports 0-9.
2 All pins on ports 0 - 9 are 5V tolerant
3 Pins on ports 0,1,2,4,5,7,8,9 have 4 mA drive and 4mA sink. Ports 3 and 6 have 8 mA drive and
8 mA sink.
4 For 8-bit non-muxed EMI operation: Port 8 is eight bits of data, ports 7 and 9 are 16 bits of
address.
5 For 16-bit muxed EMI operation: Ports 8 and 9 are 16 bits of muxed address and data bits, port
7 is up to eight additional bits of high-order address
6 Signal polarity is programmable for interrupt request inputs, EMI_ALE, timer input capture
inputs and output compare/PWM outputs, motor control tach and emergency stop inputs, and
motor control phase outputs.
7 HiZ = High Impedance, V = Voltage Source, G = Ground, I/O = Input/Output
8 STR910F devices do not support USB. On these devices USBDP and USBDN signals are "Not
Used" (USBDN is not connected, USBDP must be pulled up by a 1.5K ohm resistor to VDDQ),
and all functions named “USB" are not available.
9 STR910F 128-pin devices do not support Ethernet. On these devices PHYCLK and all
functions named “MII*" are not available.
Device pin description
80 pin
128 pin
Pkg
Signal Type
Table 2.
Pin Name
-
67
P0.0
I/O
-
69
P0.1
I/O
-
71
P0.2
I/O
-
76
P0.3
I/O
-
78
P0.4
I/O
36/72
Alternate functions
Default Pin Default Input
Function
Function
GPIO_0.0,
MII_TX_CLK,
GP Input, HiZ PHY Xmit clock
GPIO_0.1,
GP Input, HiZ
-
GPIO_0.2,
MII_RXD0,
GP Input, HiZ
PHY Rx data0
Alternate
Input 1
Alternate
Output 1
Alternate
Output 2
Alternate
Output 3
I2C0_CLKIN,
I2C clock in
GPIO_0.0,
GP Output
I2C0_CLKOUT,
I2C clock out
ETM_PCK0,
ETM Packet
I2C0_DIN,
GPIO_0.1,
I2C0_DOUT,
I2C data in
GP Output
I2C data out
ETM_PCK1,
ETM Packet
I2C1_CLKIN,
I2C clock in
GPIO_0.2,
GP Output
I2C1_CLKOUT,
I2C clock out
ETM_PCK2,
ETM Packet
GPIO_0.3,
MII_RXD1,
I2C1_DIN,
GPIO_0.3,
I2C1_DOUT,
GP Input, HiZ
PHY Rx data
I2C data in
GP Output
I2C data out
ETM_PCK3,
ETM Packet
GPIO_0.4,
MII_RXD2,
TIM0_ICAP1,
GPIO_0.4,
EMI_CS0n,
ETM_PSTAT0,
GP Input, HiZ
PHY Rx data
Input Capture
GP Output
EMI Chip Select ETM pipe status
STR91xF
80 pin
128 pin
Pkg
Signal Type
Pin description
Pin Name
-
85
P0.5
I/O
-
88
P0.6
I/O
-
90
P0.7
I/O
-
98
P1.0
I/O
-
99
P1.1
I/O
-
101
P1.2
I/O
-
106
P1.3
I/O
-
109
P1.4
I/O
-
110
P1.5
I/O
-
114
P1.6
I/O
Alternate functions
Default Pin Default Input
Function
Function
Alternate
Input 1
Alternate
Output 1
GPIO_0.5,
MII_RXD3,
TIM0_ICAP2,
GPIO_0.5,
GP Input, HiZ
PHY Rx data
Input Capture
GP Output
Alternate
Output 2
Alternate
Output 3
EMI_CS1n,
ETM_PSTAT1,
EMI Chip Select ETM pipe status
GPIO_0.6,
MII_RX_CLK,
TIM2_ICAP1,
GPIO_0.6,
GP Input, HiZ
PHY Rx clock
Input Capture
GP Output
GPIO_0.7,
MII_RX_DV,
TIM2_ICAP2,
GPIO_0.7,
EMI_CS3n,
ETM_TRSYNC,
GP Input, HiZ
PHY data valid
Input Capture
GP Output
EMI Chip Select
ETM trace sync
UART1_TX,
SSP1_SCLK,
GPIO_1.0,
MII_RX_ER,
ETM_EXTRIG,
GPIO_1.0,
GP Input, HiZ
PHY rcv error
ETM ext. trigger
GP Output
GPIO_1.1,
GP Input, HiZ
GPIO_1.2,
GP Input, HiZ
GPIO_1.3,
GP Input, HiZ
GPIO_1.4,
GP Input, HiZ
-
EMI_CS2n,
ETM_PSTAT2,
EMI Chip Select ETM pipe status
UART xmit data SSP mstr clk out
UART1_RX,
GPIO_1.1,
MII_TXD0,
SSP1_MOSI,
UART rcv data
GP Output
MAC Tx data
SSP mstr dat out
SSP1_MISO,
GPIO_1.2,
MII_TXD1,
UART0_TX,
SSP mstr data in
GP Output
MAC Tx data
UART xmit data
UART2_RX,
GPIO_1.3,
MII_TXD2,
SSP1_NSS,
UART rcv data
GP Output
MAC Tx data
SSP mstr sel out
I2C0_CLKIN,
I2C clock in
GPIO_1.4,
MII_TXD3,
GP Output
MAC Tx data
I2C0_CLKOUT,
I2C clock out
GPIO_1.5,
MII_COL,
CAN_RX,
GPIO_1.5,
UART2_TX,
ETM_TRCLK,
GP Input, HiZ
PHY collision
CAN rcv data
GP Output
UART xmit data
ETM trace clock
GPIO_1.6,
MII_CRS,
I2C0_DOUT,
GP Input, HiZ PHY carrier sns
GPIO_1.7,
I2C0_DIN,
GPIO_1.6,
CAN_TX,
I2C data in
GP Output
CAN Tx data
I2C data out
ETM_EXTRIG,
GPIO_1.7,
MII_MDC,
ETM_TRCLK,
ETM ext. trigger
GP Output
MAC mgt dat ck
ETM trace clock
I2C0_CLKIN,
I2C clock in
GPIO_2.0,
GP Output
I2C0_CLKOUT,
I2C clock out
ETM_PCK0,
ETM Packet
-
116
P1.7
I/O
7
10
P2.0
I/O
8
11
P2.1
I/O
21
33
P2.2
I/O
22
35
P2.3
I/O
23
37
P2.4
I/O
GPIO_2.4,
EXTCLK_T0T1
GP Input, HiZ Ext clk timer0/1
SSP0_SCLK,
GPIO_2.4,
SSP slv clk in
GP Output
29
45
P2.5
I/O
GPIO_2.5,
EXTCLK_T2T3
GP Input, HiZ Ext clk timer2/3
SSP0_MOSI,
GPIO_2.5,
SSP slv dat in
GP Output
32
53
P2.6
I/O
33
54
USBCLK
_P2.7
I/O
34
55
P3.0
I/O
37
59
P3.1
I/O
GP Input, HiZ
-
GPIO_2.0,
UART0_CTS,
GP Input, HiZ
Clear To Send
GPIO_2.1,
UART0_DSR,
GP Input, HiZ Data Set Ready
I2C0_DIN,
GPIO_2.1,
I2C0_DOUT,
I2C data in
GP Output
I2C data out
ETM_PCK1,
ETM Packet
GPIO_2.2,
UART0_DCD,
Dat Carrier Det
I2C1_CLKIN,
I2C clock in
GPIO_2.2,
GP Input, HiZ
GP Output
I2C1_CLKOUT,
I2C clock out
ETM_PCK2,
ETM Packet
GPIO_2.3,
UART0_RI,
I2C1_DIN,
GPIO_2.3,
I2C1_DOUT,
GP Input, HiZ
Ring Indicator
I2C data in
GP Output
I2C data out
ETM_PCK3,
ETM Packet
SSP0_SCLK,
ETM_PSTAT0,
GPIO_2.6,
GP Input, HiZ
GPIO_2.7,
-
GP Input, HiZ
USB_CLK48M,
48MHz to USB
GPIO_3.0,
DMA_RQST0,
GP Input, HiZ Ext DMA requst
GPIO_3.1,
DMA_RQST1,
GP Input, HiZ Ext DMA requst
SSP0_MISO,
GPIO_2.6,
SSP mstr data in
GP Output
SSP0_NSS,
GPIO_2.7,
SSP slv sel in
GP Output
SSP mstr clk out ETM pipe status
SSP0_MOSI,
ETM_PSTAT1,
SSP mstr dat out ETM pipe status
SSP0_MISO,
ETM_PSTAT2,
SSP slv data out ETM pipe status
SSP0_NSS,
ETM_TRSYNC,
SSP mstr sel out ETM trace sync
UART0_RxD,
GPIO_3.0,
UART2_TX,
UART rcv data
GP Output
UART xmit data
UART2_RxD,
GPIO_3.1,
UART0_TX,
UART rcv data
GP Output
UART xmit data
TIM0_OCMP1,
Out comp/PWM
TIM1_OCMP1,
Out comp/PWM
37/72
STR91xF
80 pin
128 pin
Pkg
Signal Type
Pin description
Pin Name
38
60
P3.2
I/O
39
61
P3.3
I/O
40
63
P3.4
I/O
41
65
P3.5
I/O
42
66
P3.6
I/O
43
68
P3.7
I/O
4
3
P4.0
I/O
3
2
P4.1
I/O
2
1
P4.2
I/O
1
128
P4.3
I/O
80 127
P4.4
I/O
79 126
P4.5
I/O
78 125
P4.6
I/O
77 124
P4.7
I/O
9
P5.0
I/0
12
12
18
P5.1
I/0
17
25
PHYCLK
_P5.2
I/O
18
27
P5.3
I/O
44
70
P5.4
I/O
47
77
P5.5
I/O
48
79
P5.6
I/O
49
80
P5.7
I/O
38/72
Alternate functions
Default Pin Default Input
Function
Function
Alternate
Input 1
Alternate
Output 1
Alternate
Output 2
Alternate
Output 3
GPIO_3.2,
EXINT2,
UART1_RxD,
GPIO_3.2,
CAN_TX,
UART0_DTR,
GP Input, HiZ
External Intr
UART rcv data
GP Output
CAN Tx data
Data Trmnl Rdy
GPIO_3.3,
EXINT3,
CAN_RX,
GPIO_3.3,
UART1_TX,
UART0_RTS,
GP Input, HiZ
External Intr
CAN rcv data
GP Output
UART xmit data
Ready To Send
GPIO_3.4,
EXINT4,
SSP1_SCLK,
GPIO_3.4,
SSP1_SCLK,
UART0_TX,
GP Input, HiZ
External Intr
SSP slv clk in
GP Output
GPIO_3.5,
EXINT5,
SSP1_MISO,
GPIO_3.5,
GP Input, HiZ
External Intr
SSP mstr data in
GP Output
SSP mstr clk out UART xmit data
SSP1_MISO,
UART2_TX,
SSP slv data out UART xmit data
GPIO_3.6,
EXINT6,
SSP1_MOSI,
GPIO_3.6,
SSP1_MOSI,
CAN_TX,
GP Input, HiZ
External Intr
SSP slv dat in
GP Output
SSP mstr dat out
CAN Tx data
SSP1_NSS,
TIM1_OCMP1,
SSP mstr sel out Out comp/PWM
GPIO_3.7,
EXINT7,
SSP1_NSS,
GPIO_3.7,
GP Input, HiZ
External Intr
SSP slv select in
GP Output
GPIO_4.0,
ADC0,
TIM0_ICAP1,
GPIO_4.0,
GP Input, HiZ
ADC input chnl
Input Capture
GP Output
GPIO_4.1,
ADC1,
TIM0_ICAP2,
GPIO_4.1,
GP Input, HiZ
ADC input chnl
Input Capture
GP Output
GPIO_4.2,
ADC2,
TIM1_ICAP1,
GPIO_4.2,
GP Input, HiZ
ADC input chnl
Input Capture
GP Output
GPIO_4.3,
ADC3,
TIM1_ICAP2,
GPIO_4.3,
GP Input, HiZ
ADC input chnl
Input Capture
GP Output
GPIO_4.4,
ADC4,
TIM2_ICAP1,
GPIO_4.4,
GP Input, HiZ
ADC input chnl
Input Capture
GP Output
GPIO_4.5,
ADC5,
TIM2_ICAP2,
GPIO_4.5,
GP Input, HiZ
ADC input chnl
Input Capture
GP Output
GPIO_4.6,
ADC6,
TIM3_ICAP1,
GPIO_4.6,
GP Input, HiZ
ADC input chnl
Input Capture
GP Output
TIM0_OCMP1,
Out comp/PWM
ETM_PCK0,
ETM Packet
TIM0_OCMP2,
Out comp
ETM_PCK1,
ETM Packet
TIM1_OCMP1,
Out comp/PWM
ETM_PCK2,
ETM Packet
TIM1_OCMP2,
Out comp
ETM_PCK3,
ETM Packet
ETM_PSTAT0,
TIM2_OCMP1,
Out comp/PWM ETM pipe status
TIM2_OCMP2,
Out comp
ETM_PSTAT1,
ETM pipe status
ETM_PSTAT2,
TIM3_OCMP1,
Out comp/PWM ETM pipe status
GPIO_4.7,
ADC7,
TIM3_ICAP2,
GPIO_4.7,
ADC input chnl
Input Capture
GP Output
TIM3_OCMP2,
Out comp
ETM_TRSYNC,
GP Input, HiZ
GPIO_5.0,
EXINT8,
CAN_RX,
GPIO_5.0,
ETM_TRCLK,
UART0_TX,
GP Input, HiZ
External Intr
CAN rcv data
GP Output
ETM trace clock
UART xmit data
GPIO_5.1,
EXINT9,
UART0_RxD,
GPIO_5.1,
CAN_TX,
UART2_TX,
GP Input, HiZ
External Intr
UART rcv data
GP Output
CAN Tx data
UART xmit data
MII_PHYCLK,
25Mhz to PHY
TIM3_OCMP1,
Out comp/PWM
GPIO_5.2,
EXINT10,
UART2_RxD,
GPIO_5.2,
GP Input, HiZ
External Intr
UART rcv data
GP Output
ETM trace sync
GPIO_5.3,
EXINT11,
ETM_EXTRIG,
GPIO_5.3,
MII_TX_EN,
GP Input, HiZ
External Intr
ETM ext. trigger
GP Output
MAC xmit enbl
TIM2_OCMP1,
Out comp/PWM
GPIO_5.4,
EXINT12,
SSP0_SCLK,
GPIO_5.4,
SSP0_SCLK,
EMI_CS0n,
GP Input, HiZ
External Intr
SSP slv clk in
GP Output
GPIO_5.5,
EXINT13,
SSP0_MOSI,
GPIO_5.5,
GP Input, HiZ
External Intr
SSP slv dat in
GP Output
GPIO_5.6,
EXINT14,
SSP0_MISO,
GPIO_5.6,
GP Input, HiZ
External Intr
SSP mstr dat in
GP Output
GPIO_5.7,
EXINT15,
SSP0_NSS,
GPIO_5.7,
GP Input, HiZ
External Intr
SSP slv select in
GP Output
SSP mstr clk out EMI Chip Select
SSP0_MOSI,
EMI_CS1n,
SSP mstr dat out EMI Chip Select
SSP0_MISO,
EMI_CS2n,
SSP slv data out EMI Chip Select
SSP0_NSS,
EMI_CS3n,
SSP mstr sel out EMI Chip Select
STR91xF
80 pin
128 pin
Pkg
Signal Type
Pin description
Pin Name
19
29
P6.0
I/O
20
31
P6.1
I/O
13
19
P6.2
I/O
14
20
P6.3
I/O
52
83
P6.4
I/O
53
84
P6.5
I/O
57
92
P6.6
I/O
58
93
P6.7
I/O
-
5
P7.0
I/O
-
6
P7.1
I/O
-
7
P7.2
I/O
-
13
P7.3
I/O
-
14
P7.4
I/O
-
15
P7.5
I/O
-
118
P7.6
I/O
-
119
P7.7
I/O
-
26
P8.0
I/O
-
28
P8.1
I/O
-
30
P8.2
I/O
-
32
P8.3
I/O
-
34
P8.4
I/O
Alternate functions
Default Pin Default Input
Function
Function
Alternate
Input 1
Alternate
Output 1
Alternate
Output 2
Alternate
Output 3
TIM0_OCMP1,
Out comp/PWM
IMC phase U hi
TIM0_OCMP2,
Out comp
IMC phase U lo
GPIO_6.0,
EXINT16,
TIM0_ICAP1,
GPIO_6.0,
GP Input, HiZ
External Intr
Input Capture
GP Output
GPIO_6.1,
EXINT17,
TIM0_ICAP2,
GPIO_6.1,
GP Input, HiZ
External Intr
Input Capture
GP Output
GPIO_6.2,
EXINT18,
TIM1_ICAP1,
GPIO_6.2,
GP Input, HiZ
External Intr
Input Capture
GP Output
GPIO_6.3,
EXINT19,
TIM1_ICAP2,
GPIO_6.3,
GP Input, HiZ
External Intr
Input Capture
GP Output
GPIO_6.4,
EXINT20,
TIM2_ICAP1,
GPIO_6.4,
GP Input, HiZ
External Intr
Input Capture
GP Output
GPIO_6.5,
EXINT21,
TIM2_ICAP2,
GPIO_6.5,
GP Input, HiZ
External Intr
Input Capture
GP Output
GPIO_6.6,
EXINT22_TRIG,
UART0_RxD,
GPIO_6.6,
Ext Intr & Tach
GP Input, HiZ
UART rcv data
GP Output
EXINT23_STOP, ETM_EXTRIG,
GPIO_6.7,
GP Input, HiZ Ext Intr & Estop ETM ext. trigger
GP Output
GPIO_6.7,
MC_UH,
MC_UL,
MC_VH,
TIM1_OCMP1,
Out comp/PWM
IMC phase V hi
TIM1_OCMP2,
Out comp
IMC phase V lo
TIM2_OCMP1,
Out comp/PWM
IMC phase W hi
TIM2_OCMP2,
Out comp
IMC phase W lo
MC_VL,
MC_WH,
MC_WL,
ETM_TRCLK,
TIM3_OCMP1,
Out comp/PWM
ETM trace clock
TIM3_OCMP2,
Out comp
UART xmit data
GPIO_7.0,
EXINT24,
TIM0_ICAP1,
GPIO_7.0,
8b) EMI_A0,
GP Input, HiZ
External Intr
Input Capture
GP Output
16b) EMI_A16
GPIO_7.1,
EXINT25,
TIM0_ICAP2,
GPIO_7.1,
8b) EMI_A1,
GP Input, HiZ
External Intr
Input Capture
GP Output
16b) EMI_A17
GPIO_7.2,
EXINT26,
TIM2_ICAP1,
GPIO_7.2,
8b) EMI_A2,
GP Input, HiZ
External Intr
Input Capture
GP Output
16b) EMI_A18
GPIO_7.3,
EXINT27,
TIM2_ICAP2,
GPIO_7.3,
8b) EMI_A3,
GP Input, HiZ
External Intr
Input Capture
GP Output
16b) EMI_A19
UART0_TX,
ETM_PCK0,
ETM Packet
ETM_PCK1,
ETM Packet
ETM_PCK2,
ETM Packet
ETM_PCK3,
ETM Packet
GPIO_7.4,
EXINT28,
UART0_RxD,
GPIO_7.4,
8b) EMI_A4,
EMI_CS3n,
GP Input, HiZ
External Intr
UART rcv data
GP Output
16b) EMI_A20
EMI Chip Select
GPIO_7.5,
EXINT29,
ETM_EXTRIG,
GPIO_7.5,
8b) EMI_A5,
EMI_CS2n,
GP Input, HiZ
External Intr
ETM ext. trigger
GP Output
16b) EMI_A21
EMI Chip Select
GPIO_7.6,
EXINT30,
TIM3_ICAP1,
GPIO_7.6,
8b) EMI_A6,
EMI_CS1n,
GP Input, HiZ
External Intr
Input Capture
GP Output
16b) EMI_A22
EMI Chip Select
GPIO_7.7,
EXINT31,
TIM3_ICAP2,
GPIO_7.7,
EMI_CS0n,
16b) EMI_A23,
GP Input, HiZ
External Intr
Input Capture
GP Output
EMI chip select
8b) EMI_A7
-
-
-
-
-
-
-
-
-
-
GPIO_8.0,
GP Input, HiZ
GPIO_8.1,
GP Input, HiZ
GPIO_8.2,
GP Input, HiZ
GPIO_8.3,
GP Input, HiZ
GPIO_8.4,
GP Input, HiZ
GPIO_8.0,
8b) EMI_D0,
GP Output
16b) EMI_AD0
GPIO_8.1,
8b) EMI_D1,
GP Output
16b) EMI_AD1
GPIO_8.2,
8b) EMI_D2,
GP Output
16b) EMI_AD2
GPIO_8.3,
8b) EMI_D3,
GP Output
16b) EMI_AD3
GPIO_8.4,
8b) EMI_D4,
GP Output
16b) EMI_AD4
-
39/72
STR91xF
80 pin
128 pin
Pkg
Signal Type
Pin description
Pin Name
-
36
P8.5
I/O
-
38
P8.6
I/O
-
44
P8.7
I/O
-
46
P9.0
I/O
-
47
P9.1
I/O
-
50
P9.2
I/O
-
51
P9.3
I/O
-
52
P9.4
I/O
-
58
P9.5
I/O
-
62
P9.6
I/O
-
64
P9.7
I/O
Alternate functions
Default Pin Default Input
Function
Function
GPIO_8.5,
GP Input, HiZ
GPIO_8.6,
GP Input, HiZ
GPIO_8.7,
GP Input, HiZ
GPIO_9.0,
GP Input, HiZ
GPIO_9.1,
GP Input, HiZ
GPIO_9.2,
GP Input, HiZ
GPIO_9.3,
GP Input, HiZ
GPIO_9.4,
GP Input, HiZ
GPIO_9.5,
GP Input, HiZ
GPIO_9.6,
GP Input, HiZ
GPIO_9.7,
GP Input, HiZ
Alternate
Input 1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Alternate
Output 1
GPIO_8.5,
8b) EMI_D5,
GP Output
16b) EMI_AD5
GPIO_8.6,
8b) EMI_D6,
GP Output
16b) EMI_AD6
GPIO_8.7,
8b) EMI_D7,
GP Output
16b) EMI_AD7
GPIO_9.0,
8b) EMI_A8
GP Output
16b) EMI_AD8
GPIO_9.1,
8b) EMI_A9,
GP Output
16b) EMI_AD9
GPIO_9.2,
8b) EMI_A10,
GP Output
16b)EMI_AD10
GPIO_9.3,
8b) EMI_A11,
GP Output
16b)EMI_AD11
GPIO_9.4,
8b) EMI_A12,
GP Output
16b)EMI_AD12
GPIO_9.5,
8b) EMI_A13,
GP Output
16b)EMI_AD13
GPIO_9.6,
8b) EMI_A14,
GP Output
16b)EMI_AD14
GPIO_9.7,
8b) EMI_A15,
GP Output
16b)EMI_AD15
-
21
O
EMI byte write
strobe (8 bit
mode) or low
byte write
strobe (16 bit
mode)
-
22 EMI_WRHn O
EMI high byte
write strobe
(16-bit mode)
N/A
-
74
EMI_ALE
O
EMI address
latch enable
(mux mode)
N/A
-
75
EMI_RDn
O
EMI read
strobe
N/A
-
91
TAMPER
_IN
I
Tamper
detection input
N/A
-
94
MII_MDIO I/O
MAC/PHY
managment
data line
N/A
59
95
USBDN
I/O
USB data (-)
bus connect
N/A
60
96
USBDP
I/O
USB data (+)
bus connect
N/A
56
89
RESET
_INn
I
External reset
input
N/A
40/72
EMI_BWR
_WRLn
Alternate
Output 2
N/A
Alternate
Output 3
-
-
STR91xF
Pin Name
Signal Type
Pin description
Default Pin Default Input
Function
Function
62 100
RESET
_OUTn
O
Global or
System reset
output
N/A
65 104
X1_CPU
I
CPU oscillator
or crystal input
N/A
64 103
X2_CPU
O
CPU crystal
connection
N/A
27
42
X1_RTC
I
RTC oscillator
or crystal input
(32KHz)
N/A
26
41
X2_RTC
O
RTC crystal
connection
N/A
61
97
JRTCK
O
JTAG return
clock
67 107
JTRSTn
I
68 108
JTCK
I
JTAG clock
N/A
I
JTAG mode
select
N/A
128 pin
80 pin
Pkg
69 111
JTMS
Alternate functions
JTAG TAP
controller reset
Alternate
Input 1
Alternate
Output 1
RTC Oscillator
Calibration Out
JTDI
I
JTAG data in
N/A
JTDO
O
JTAG data out
N/A
-
122
AVDD
V
ADC analog
voltage sourc,
2.7V - 3.6V
N/A
-
4
AVSS
G
ADC analog
ground
N/A
5
-
AVSS
_VSSQ
Common
ground point
G
for digital I/O &
analog ADC
N/A
-
123
AVREF
V
ADC reference
voltage input
N/A
-
AVREF
_AVDD
N/A
N/A
73 117
76
Alternate
Output 3
RTC_CAL,
N/A
72 115
Combined
ADC ref
voltage and
V
ADC analog
voltage source,
Alternate
Output 2
N/A
2.7V - 3.6V
24
39
VBATT
V
Standby
voltage input
for RTC and
SRAM backup
N/A
41/72
STR91xF
Pin Name
6
9
VDDQ
V
15
23
VDDQ
V
36
57
VDDQ
V
46
73
VDDQ
V
54
86
VDDQ
V
28
43
VDDQ
V
63 102
VDDQ
V
74 120
VDDQ
V
80 pin
128 pin
Pkg
Signal Type
Pin description
-
8
VSSQ
G
16
24
VSSQ
G
35
56
VSSQ
G
45
72
VSSQ
G
55
87
VSSQ
G
25
40
VSSQ
G
66 105
VSSQ
G
75 121
VSSQ
G
11
17
VDD
V
31
49
VDD
V
50
81
VDD
V
70 112
VDD
V
10
16
VSS
G
30
48
VSS
G
51
82
VSS
G
71 113
VSS
G
42/72
Alternate functions
Default Pin Default Input
Function
Function
Alternate
Input 1
Alternate
Output 1
V Source for
I/O and USB.
N/A
2.7V to 3.6V
Digital Ground
for
!/O and USB
V Source for
CPU.
N/A
N/A
1.65V - 2.0V
Digital Ground
for CPU
N/A
Alternate
Output 2
Alternate
Output 3
STR91xF
5
Memory mapping
Memory mapping
The ARM966E-S CPU addresses a single linear address space of 4 giga-bytes (232) from
address 0x0000.0000 to 0xFFFF.FFFF as shown in Figure 9. Upon reset the CPU boots from
address 0x0000.0000, which is chip-select zero at address zero in the Flash Memory Interface
(FMI).
The Instruction TCM and Data TCM enable high-speed CPU operation without incurring any
performance or power penalties associated with accessing the system buses (AHB and APB).
I-TCM and D-TCM address ranges are shown at the bottom of the memory map in Figure 9.
5.1
Buffered and non-buffered writes
The CPU makes use of write buffers on the AHB and the D-TCM to decouple the CPU from any
wait states associated with a write operation. The user may choose to use write with buffers on
the AHB by setting bit 3 in control register CP15 and selecting the appropriate AHB address
range when writing. By default at reset, buffered writes are disabled (bit 3 of CP15 is clear) and
all AHB writes are non-buffered until enabled. Figure 9 shows that most addressable items on
the AHB are aliased at two address ranges, one for buffered writes and another for nonbuffered writes. A buffered write will allow the CPU to continue program execution while the
write-back is performed through a FIFO to the final destination on the AHB. If the FIFO is full,
the CPU is stalled until FIFO space is available. A non-buffered write will impose an immediate
delay to the CPU, but results in a direct write to the final AHB destination, ensuring data
coherency. Read operations from AHB locations are always direct and never buffered.
5.2
System (AHB) and peripheral (APB) buses
The CPU will access SRAM, higher-speed peripherals (USB, Ethernet, Programmable DMA),
and the external bus (EMI) on the AHB at their respective base addresses indicated in Figure 9.
Lower-speed peripherals reside on the APB and are accessed using two separate AHB-to-APB
bridge units (APB0 and APB1). These bridge units are essentially address windows connecting
the AHB to the APB. To access an individual APB peripheral, the CPU will place an address on
the AHB bus equal to the base address of the appropriate bridge unit APB0 or APB1, plus the
offset of the particular peripheral, plus the offset of the individual data location within the
peripheral. Figure 9 shows the base addresses of bridge units APB0 and APB1, and also the
base address of each APB peripheral. Please consult the STR91xx Reference manual for the
address of data locations within each individual peripheral.
5.3
SRAM
The SRAM is aliased at three separate address ranges as shown in Figure 9. When the CPU
accesses SRAM starting at 0x0400.0000, the SRAM appears on the D-TCM. When CPU
access starts at 0x4000.0000, SRAM appears in the buffered AHB range. Beginning at CPU
address 0x5000.0000, SRAM is in non-buffered AHB range. The SRAM size must be specified
by CPU intitialization firmware writing to a control register after any reset condition. Default
SRAM size is 32K bytes, with option to set to 64K bytes on STR91xFx32 devices, and to 96K
bytes on STR91xFx44 devices.
43/72
Memory mapping
STR91xF
When other AHB bus masters (such as a DMA controller) write to SRAM, their access is never
buffered. Only the CPU can make use of buffered AHB writes.
5.4
Two independent Flash memories
The STR91xF has two independent Flash memories, the larger primary Flash and the small
secondary Flash. It is possible for the CPU to erase/write to one of these Flash memories while
simultaneously reading from the other.
One or the other of these two Flash memories may reside at the “boot” address position of
0x0000.0000 at power-up or at reset as shown in Figure 9. The default configuration is that the
first sector of primary Flash memory is enabled and residing at the boot position, and the
secondary Flash memory is disabled. This default condition may be optionally changed as
described below.
5.4.1
Default configuration
When the primary Flash resides at boot position, typical CPU initialization firmware would set
the start address and size of the main Flash memory, and go on to enable the secondary Flash,
define it’s start address and size. Most commonly, firmware would place the secondary Flash
start address at the location just after the end of the primary Flash memory. In this case, the
primary Flash is used for code storage, and the smaller secondary flash can be used for data
storage (EEPROM emulation).
5.4.2
Optional configuration
Using the STR91xF device configuration software tool, one can specify that the smaller
secondary Flash memory is at the boot location at reset and the primary Flash is disabled. The
selection of which Flash memory is at the boot location is programmed in a non-volatile Flashbased configuration bit during JTAG ISP. The boot selection choice will remain as the default
until the bit is erased and re-written by the JTAG interface. The CPU cannot change this choice
for boot Flash, only the JTAG interface has access.
In this case where the secondary Flash defaults to the boot location upon reset, CPU firmware
would typically initialize the Flash memories the following way. The secondary Flash start
address and size is specified, then the primary Flash is enabled and its start address and size
is specified. The primary Flash start address would typically be located just after the final
address location of the secondary Flash. This configuration is particularly well-suited for InApplication-Programming (IAP). The CPU would boot from the secondary Flash memory,
initialize the system, then check the contents of the primary Flash memory (by checksum or
other means). If the contents of primary Flash is OK, then CPU execution continues from either
Flash memory. If the main Flash contents are incorrect, the CPU, while executing code from the
secondary Flash, can download new data from any STR91xx communication channel and
program into primary Flash memory. Application code then starts after the new contents of
primary Flash are verified.
44/72
STR91xF
Memory mapping
Notes for Figure 9: STR91xx memory map on page 46:
Notes: 1 Either of the two Flash memories may be placed at CPU boot address 0x0000.0000. By default,
the primary Flash memory is in boot position starting at CPU address 0x0000.0000 and the
secondary Flash memory may be placed at a higher address following the end of the primary
Flash memory. This default option may be changed using the STR91xx device configuration
software, placing the secondary Flash memory at CPU boot location 0x0000.0000, and then
the primary Flash memory may be placed at a higher address.
2 The local SRAM (64KB or 96KB) is aliased in three address windows. A) At 0x0400.0000 the
SRAM is accessible through the CPU’s D-TCM, at 0x4000.0000 the SRAM is accessible
through the CPU’s AHB in buffered accesses, and at 0x5000.0000 the SRAM is accessible
through the CPU’s AHB in non-buffered accesses. An AHB bus master other than the CPU can
access SRAM in all three aliased windows, but these accesses are always non-buffered. The
CPU is the only AHB master that can performed buffered writes.
3 APB peripherals reside in two AHB-to-APB peripheral bridge address windows, APB0 and
APB1. These peripherals are accessible with buffered AHB access if the CPU addresses them
in the address range of 0x4800.0000 to 0x4FFF.FFFF, and non-buffered access in the address
range of 0x5800.0000 to 0x5FFF.FFFF.
4 Individual peripherals on the APB are accessed at the listed address offset plus the base
address of the appropriate AHB-to-APB bridge.
45/72
STR91xF
Memory mapping
Figure 9.
STR91xx memory map
PERIPHERAL BUS
MEMORY SPACE (4)
APB BASE +
OFFSET
TOTAL 4 GB CPU
MEMORY SPACE
APB1+0x03FF.FFFF
RESERVED
APB1+0x0000.E000
0xFFFF.FFFF
0xFFFF.F000
0xFC01.0000
0xFC00.0000
VIC0
4 KB
RESERVED
VIC1
I2C1
APB1+0x0000.D000
AHB
NONBUFFERED
APB1+0x0000.C000
APB1+0x0000.B000
64 KB
APB1+0x0000.A000
APB1+0x0000.9000
APB1+0x0000.8000
RESERVED
APB1+0x0000.7000
APB1+0x0000.6000
0x8000.0000
0x7C00.0000
0x7800.0000
0x7400.0000
0x7000.0000
0x6C00.0000
0x6800.0000
0x6400.0000
0x6000.0000
0x5C00.0000
0x5800.0000
0x5400.0000
0x5000.0000
0x4C00.0000
0x4800.0000
0x4400.0000
0x4000.0000
0x3C00.0000
0x3800.0000
0x3400.0000
0x3000.0000
0x2C00.0000
0x2800.0000
0x2400.0000
0x2000.0000
ENET
8-CH DMA
64 MB
EMI
64 MB
USB
64 MB
ENET
64 MB
8-CH DMA
64 MB
EMI
64 MB
USB
64 MB
APB1
AHB
NONBUFFERED
64 MB
FMI
64 MB
SRAM, AHB (2)
64 MB
APB1
64 MB
APB0
64 MB
FMI
64 MB
SRAM, AHB (2)
64 MB
Ext. MEM, CS0
64 MB
Ext. MEM, CS1
64 MB
Ext. MEM, CS2
64 MB
Ext. MEM, CS3
64 MB
Ext. MEM, CS0
64 MB
Ext. MEM, CS1
64 MB
Ext. MEM, CS2
64 MB
APB1+0x0000.4000
APB1+0x0000.3000
APB1+0x0000.2000
APB1+0x0000.1000
APB1+0x0000.0000
AHB
BUFFERED
4 KB
WATCHDOG
4 KB
ADC
4 KB
CAN
4 KB
SSP1
4 KB
SSP0
4 KB
UART2
4 KB
UART1
4 KB
UART0
4 KB
IMC
4 KB
SCU
4 KB
RTC
4 KB
APB1 CONFIG
4 KB
PERIPHERAL BUS,
NON- BUFFERED
ACCESS (3)
RESERVED
GPIO PORT P9
APB0+0x0000.F000
AHB
NONBUFFERED
APB0+0x0000.E000
APB0+0x0000.D000
APB0+0x0000.C000
PERIPHERAL BUS,
BUFFERED ACCESS (3)
AHB
BUFFERED
APB0+0x0000.B000
APB0+0x0000.A000
APB0+0x0000.9000
APB0+0x0000.8000
APB0+0x0000.7000
AHB
NONBUFFERED
APB0+0x0000.6000
APB0+0x0000.5000
APB0+0x0000.4000
APB0+0x0000.3000
AHB
BUFFERED
APB0+0x0000.2000
APB0+0x0000.1000
64 MB
APB0+0x0000.0000
GPIO PORT P8
4 KB
4 KB
GPIO PORT P6
4 KB
GPIO PORT P5
4 KB
GPIO PORT P4
4 KB
GPIO PORT P3
4 KB
GPIO PORT P2
4 KB
GPIO PORT P1
4 KB
GPIO PORT P0
4 KB
TIM3
4 KB
TIM2
4 KB
TIM1
4 KB
TIM0
4 KB
WAKE-UP UNIT
4 KB
APB0 CONFIG
4 KB
(1)
SECONDARY
FLASH (BANK 1),
32KB
RESERVED
MAIN FLASH
(BANK 0),
256KB or 512KB
0x0800.0000
0x0400.0000
0x0000.0000
FLASH, I-TCM (1)
Using 64 KB or 96
KB
Using 288 KB or 544
KB
0x0000.0000
DEFAULT ORDER
46/72
4 KB
GPIO PORT P7
Order of the two Flash memories is user defined.
SRAM, D-TCM (2)
APB1,
AHBto-APB
Bridge
APB0+0x03FF.FFFF
APB0+0x0001.0000
64 MB
APB0
Ext. MEM, CS3
APB1+0x0000.5000
64 MB
4 KB
I2C0
MAIN FLASH
(BANK 0),
256KB or 512KB
SECONDARY
FLASH (BANK 1),
32KB
OPTIONAL ORDER
APB0,
AHBto-APB
Bridge
STR91xF
Electrical characteristics
6
Electrical characteristics
6.1
Absolute maximum ratings
This product contains devices to protect the inputs against damage due to high static voltages.
However, it is advisable to take normal precautions to avoid application of any voltage higher
than the specified maximum rated voltages. It is also recommended to ground any unused input
pin to reduce power consumption and minimize noise.
Table 3.
Absolute maximum ratings
Value
Symbol
Note:
Parameter
Unit
Min
Max
VDD
Voltage on VDD pin with respect to ground VSS
-0.3
2.4
V
VDDQ
Voltage on VDDQ pin with respect to ground VSS
-0.3
4.0
V
VBATT
Voltage on VBATT pin with respect to ground VSS
-0.3
4.0
V
AVDD
Voltage on AVDD pin with respect to ground VSS
(128-pin package)
-0.3
4.0
V
AVREF
Voltage on AVREF pin with respect to ground VSS
(128-pin package)
-0.3
4.0
V
AVREF_AVDD
Voltage on AVREF_AVDD pin with respect to
Ground VSS (80-pin package)
-0.3
4.0
V
VIN
Voltage on any other pin with respect to ground
VSS
-0.3
4.0
V
IOV
Input current on any pin during overload condition
-10
+10
mA
ITDV
Absolute sum of all input currents during overload
condition
|200|
mA
TST
Storage Temperature
+150
°C
ESD
ESD Susceptibility (Human Body Model)
-55
2000
V
Stresses exceeding above listed recommended "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. During overload conditions (VIN>VDDQ or VIN<VSSQ) the
voltage on pins with respect to ground (VSSQ) must not exceed the recommended values.
47/72
STR91xF
Electrical characteristics
6.2
Operating conditions
Table 4.
Operating conditions
Symbol
6.3
Test
Conditions
Parameter
Value
Unit
Min
Max
VDD
Digital CPU supply voltage
1.65
2.0
V
VDDQ
Digital I/O supply voltage
2.7
3.6
V
VBATT
SRAM backup and RTC supply
voltage
2.5
3.5
V
AVDD
Analog ADC supply voltage
(128-pin package)
2.7
3.6
V
AVREF
Analog ADC reference voltage
(128-pin package)
1.0
3.6
V
AVREF_AVDD
Combined analog ADC
reference and ADC supply
voltage (80-pin package)
2.7
3.6
V
TA
Ambient temperature under bias
-40
+85
C
LVD electrical characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 °C unless otherwise specified.
Table 5.
Symbol
LVD Electrical Characteristics
Parameter
VDD_LVD
VDD LVD Threshold
VDDQ_LVD
VDDQ LVD Threshold
VDD_BRN
VDD Brown Out Warning
Threshold
VDDQ_BRN
VDDQ Brown Out Warning
Threshold
Test
Conditions
Notes: 1 For VDDQ I/O voltage operating at 2.7 - 3.3V.
2 For VDDQ I/O voltage operating at 3.0 - 3.6V.
48/72
Value
Unit
Min
Typ
Max
1.35
1.4
1.45
V
(1)
2.35
2.4
2.45
V
(2)
2.65
2.7
2.75
1.6
1.65
1.7
V
(1)
2.6
2.65
2.7
V
(2)
2.9
2.95
3.0
STR91xF
6.4
Electrical characteristics
DC electrical characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 °C unless otherwise specified.
Table 6.
DC Electrical Characteristics
Value
Symbol
Parameter
Test Conditions
Unit
Min
VIH
General inputs
Input High Level
RESET and TCK inputs
Typ
Max
2.0
0.8VDDQ
General inputs
0.8
VIL
Input Low Level
VHYS
Input Hysteresis
Schmitt Trigger
General inputs
Output High Level
High current pins
I/O ports 3 and 6:
Push-Pull, IOH = 8mA
VDDQ-0.7
Output High Level
Standard current pins
I/O ports 0,1,2,4,5,7,8,9:
Push-Pull, IOH = 4mA
VDDQ-0.7
Output Low Level
High current pins
I/O ports 3 and 6:
Push-Pull, IOL = 8mA
0.4
Output Low Level
I/O ports 0,1,2,4,5,7,8,9:
Push-Pull, IOL = 4mA
0.4
VOH
VOL
Standard current pins
V
0.2VDDQ
RESET and TCK inputs
0.4
V
V
V
49/72
STR91xF
Electrical characteristics
6.5
AC electrical characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 °C unless otherwise specified.
Table 7.
AC electrical characteristics
Value
Symbol
Parameter
Test Conditions
Unit
Min
IDDRUN
Run Mode Current
IIDLE
Idle Mode Current
ISLEEP
Sleep Mode Current
IRTC_STBY
RTC Standby Current
ISRAM_STBY SRAM Standby Current
Typ
Max
CPU_CLK =
96MHz [1]
1.7
2.3
mA/MHz
All peripherals on
[2]
1.14
1.7
mA/MHz
All peripherals off
[3]
0.45
0.75
mA/MHz
LVD On [4]
55
825
µA
LVD Off [4]
50
820
µA
Measured on
VBATT pin
0.3
0.9
µA
Measured on
VBATT pin
5
85
µA
Notes: 1 ARM core and peripherals active with all clocks on. Power can be conserved by turning off
clocks to peripherals which are not required.
2 ARM core stopped and all peripheral clocks active.
3 ARM core stopped and all peripheral clocks stopped.
4 ARM core and all peripheral clocks stopped (with exception of RTC).
Figure 10. Sleep Mode current vs temperature
2000
1800
Max
1600
1400
Idd[µA]
1200
Typical
1000
800
600
400
200
0
-40
-20
0
20
40
60
TEMP [°C]
50/72
80
100
120
STR91xF
Electrical characteristics
Table 8.
AC electrical characteristics
Value
Symbol
Parameter
Test Conditions
Unit
Min
fMSTR
fCPUCLK
6.6
CCU Master Clk Output
CPU Core Frequency
Typ
32.768
Max
96,000
kHz
Executing from
SRAM
96
MHz
Executing from
Flash
96
MHz
fPCLK
Peripheral Clock for APB
48
MHz
fHCLK
Peripheral Clock for AHB
96
MHz
fOSC
Clock Input
25
MHz
fFMICLK
FMI Flash Bus clock (internal
clock)
96
MHz
fBCLK
External Memory Bus clock
(internal clock)
66
MHz
fRTC
RTC Clock
fEMAC
fUSB
4
32.768
kHz
EMAC PHY Clock
25
MHz
USB Clock
48
MHz
RESET_INn and power-on-reset characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 °C unless otherwise specified.
Table 9.
RESET_INn and Power-On-Reset Characteristics
Value
Symbol
Parameter
Test Conditions
Unit
Min
tRINMIN
RESET_INn Valid Active Low
tPOR
Power-On-Reset Condition
duration
tRSO
RESET_OUT Duration
(Watchdog reset)
Typ
100
VDDQ,VDD ramp
time is less than
10ms
Max
ns
10
ms
one
PCLK
ns
51/72
STR91xF
Electrical characteristics
6.7
Main oscillator electrical characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 °C unless otherwise specified.
Table 10.
Main oscillator electrical characteristics
Value
Symbol
Parameter
Test Conditions
Unit
Min
tSTUP(OSC) Oscillator Start-up Time
6.8
Typ
Max
Stable VDDQ
3
mS
RTC oscillator electrical characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 °C unless otherwise specified.
Table 11.
RTC oscillator electrical characteristics
Value
Symbol
Parameter
Test Conditions
Unit
Min
gM(RTC)
Max
LVD 1)
Oscillator Start _voltage
tSTUP(RTC) Oscillator Start-up Time
Typ
V
Stable VDDQ
1
S
Notes: 1 Min oscillator start voltage is the same as low voltage detect level (2.4V or 2.7V) for VDDQ
Table 12.
RTC crystal electrical characteristics
Value
Symbol
Parameter
Test Conditions
Unit
Min
52/72
fO
Resonant frequency
RS
Series resistance
CL
Load capacitance
Typ
Max
32.768
kHz
40
8
kΩ
pF
STR91xF
6.9
Electrical characteristics
PLL electrical characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 °C unless otherwise specified.
Table 13.
PLL Electrical Characteristics
Value
Symbol
Parameter
Test Conditions
Unit
Min
fPLL
PLL Output Clock
fOSC
Clock Input
tLOCK
PLL lock time
∆tJITTER
PLL Jitter (peak to peak)
Typ
Max
6.25
96
MHz
4
25
MHz
300
1500
µs
0.1
0.2
ns
53/72
STR91xF
Electrical characteristics
6.10
Flash memory characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 °C unless otherwise specified.
Table 14.
Flash memory program/erase characteristics
Value
Parameter
Bank erase
Sector erase
Bank program
Sector program
Test Conditions
Typ after
Typ2) 100K W/E
cycles2)
Unit
Max
Primary Bank
(512 Kbytes)1)
7
TBD
TBD
s
Primary Bank
(256 Kbytes)1)
4
TBD
TBD
s
Secondary Bank
(32 Kbytes)
700
TBD
TBD
ms
Of Primary Bank
(64 Kbytes)
1200
TBD
TBD
ms
Of Secondary Bank
(8 Kbytes)
300
TBD
TBD
ms
Primary Bank
(512 Kbytes)1)
3700
TBD
TBD
ms
Primary Bank
(256 Kbytes)1)
1900
TBD
TBD
ms
Secondary Bank
(32 Kbytes)
250
TBD
TBD
ms
Of Primary Bank
(64 Kbytes)
600
TBD
TBD
ms
Of Secondary Bank
(8 Kbytes)
60
TBD
TBD
ms
8
TBD
TBD
µs
TBD
µs
Word program
Sector erase
timeout
Notes: 1 STR91xFx44 devices have 512 Kbytes primary Flash, STR91xFx32 devices have 256 Kbytes
primary Flash
2 VDD = 1.8V, VDDQ = 3.3V, TA = 25°C.
Table 15.
Flash memory endurance
Value
Parameter
Test Conditions
Unit
Min
Program/erase cycles
Data retention
54/72
Per word
Typ
Max
100K
cycles
20
years
STR91xF
6.11
Electrical characteristics
External memory bus timings
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 °C unless otherwise specified.
Table 16.
EMI Bus Clock Period
Symbol
Parameter
tBCLK
Value
1 /(fHCLK x EMI_ratio)
EMI Bus Clock period
Notes: 1 EMI Bus clock is an internal clock only and is not available on the EMI bus pin
2 EMI_ratio =1/ 2 by default (can be programmed to be 1 by setting the proper bits in the
SCU_CLKCNTR register)
Table 17.
EMI read operation
Value
Symbol
Parameter
Unit
Min
tRCR
Read to CSn inactive
tRP
Read Pulse Width
tRDS
Typ
Max
0
ns
(WSTRD-WSTOEN+1)*
tBCLK
ns
Read Data Setup Time
4
ns
tRDH
Read Data Hold Time
0
ns
tRAS
Read Address Setup Time
(WSTOEN)* tBCLK
ns
tRAH
Read Address Hold Time
0
ns
tAW
ALE pulse width
(ALE_LENGTH)* tBCLK
ns
tAAH
Address to ALE hold time
tBCLK/2
ns
tAAS
Address to ALE setup time
(ALE_LENGTH)* tBCLK
ns
Notes: 1 ALE_LENGTH = 1 by default (can be programmed to be 2 by setting the bits In the SCU_SCR0
register)
2 WSTRD = 1Fh by default (RD wait state time = WSTRD x tBCLK, WSTRD can be programmed
in the EMI_RCRx Register)
3 WSTOEN = 1 by default (RD assertion delay from chip select. WSTOEN can be programmed in
the EMI_OECRx Register)
55/72
STR91xF
Electrical characteristics
Figure 11. Non-mux bus (8-bit) read timings
EMI_CSxn
tRCR
EMI_A [15:0]
A ddress
tRA H
EMI_D[7:0]
Data
tRA S
tRDS
tRDH
tRP
EMI_RDn
Figure 12. Mux bus (16-bit) read timings
EMI_CSxn
EMI_A LE
tA W
tRCR
EMI_A [23:16]
A ddress
tA A S
EMI_A D[15:0]
EMI_RDn
56/72
tA A H
tRA H
A ddress
Data
tRA S
tRDS
tRP
tRDH
STR91xF
Electrical characteristics
Table 18.
EMI write operation
Symbol
Parameter
tWCR
WRn to CSn inactive
tWP
Write Pulse Width
Value
Test
Conditions
Unit
Typ
tBCLK/2
ns
(WSTWR-WSTWEN+1) x tBCLK
ns
(WSTWEN+1/2) x tBCLK
ns
Write Data Setup Time
(non-mux mode)
tWDS
Write Data Setup Time
(mux mode )
tWDH
Write Data Hold Time
tWAS
ALE length=1
WSTWEN>2
(WSTWEN - 1.5) x tBCLK
ALE length=2
WSTWEN>3
(WSTWEN - 2.5) x tBCLK
tBCLK/2
ns
Write Address Setup Time
(WSTWEN+1/2) x tBCLK 4)
ns
tWAH
Write Address Hold Time
tBCLK/2
ns
tAW
ALE pulse width
(ALE_LENGTH) x tBCLK
ns
tAAH
Address to ALE hold time
tBCLK/2
ns
tAAS
Address to ALE setup time
(ALE_LENGTH) x tBCLK
ns
Notes: 1 ALE_LENGTH = 1 by default (can be programmed to be 2 by setting the bits In the SCU_SCR0
register)
2 WSTWR =1Fh by default (WR wait state time = WSTWR x tBCLK, WSTWR can be programmed
in the EMI_WCRx Register)
3 WSTWEN= 0 by default (WR assertion delay from chip select. WSTWEN can be programmed
in the EMI_WECRx Register)
4 When the CPU executes a 16-bit write to a x8 EMI bus, the second write cycle's address setup
time is defined as tWAS=(WSTWEN - ½) x tBCLK
Figure 13. Non-Mux Bus (8-bit) write timings
EMI_CSxn
tWCR
EMI_A[15:0]
Address
EMI_D[7:0]
Data
tWAH
tWAS
tWDS
tWP
tWDH
EMI_BWR_WRLn
57/72
STR91xF
Electrical characteristics
Figure 14. Mux Bus (16-bit) Write Timings
EMI_CSxn
EMI_A LE
tA W
tWCR
EMI_A [23:16]
A ddress
tA A S
EMI_A D[15:0]
tA A H
A ddress
tWDS
tWA H
Data
tWA S
EMI_WRLn
EMI_WRHn
58/72
tWDH
tWP
STR91xF
6.12
Electrical characteristics
ADC electrical characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 °C unless otherwise specified.
Table 19.
ADC Electrical Characteristics
Value
Symbol
Parameter
Test Conditions
Unit
Min
VAIN
Input Voltage Range
RES
Typ
Max
AVREF
V
Resolution
10
Bits
NCH
Number of Input Channels
8
N
fADC
ADC Clock Frequency
3.4
MHz
TBD
µs
TBD
ns
2
µs
212.5
ksps
Start Up Time
0
0.1
Return From Idle
Track and Hold Acquisition
Time
Conversion Time
fADC =
Throughput Rate
fADC =
6.25
CIN
Input Capacitance
TBD
pF
ZIN
Input Impedance
TBD
MW
ED
Differential Non-Linearity
[1] [2]
3.5
TBD
LSB[3]
EL
Integral Non-Linearity
[1]
5
TBD
LSB
EO
Offset Error
[1]
3
TBD
LSB
EG
Gain Error
[1]
1
TBD
LSB
ET
Absolute Error
[1]
4
TBD
LSB
IADC
Power Consumption
TBD
mA
ISTBY
Standby Power Consumption
TBD
µA
Notes: 1 Conditions: AVSS = 0 V, AVDD = 3.3 V.
2 The A/D is monotonic, there are no missing codes.
3 1 LSB = (VDDA - VSSA)/1024
59/72
STR91xF
Electrical characteristics
Figure 15. ADC conversion characteristics
Digital Result
EG
1023
1022
1LSB
1021
IDEAL
V
–V
DDA
SSA
= -----------------------------------------
1024
(2)
ET
(3)
7
(1)
6
5
EO
4
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
EL
3
ED
2
1 LSBIDEAL
1
ET=Total Unadjusted Error: maximum
deviation between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the
first actual transition and the first ideal
one.
EG=Gain Error: deviation between the
last ideal transition and the last actual
one.
ED=Differential Linearity Error: maximum
deviation between actual steps and the
ideal one.
EL=Integral Linearity Error: maximum
deviation between any actual transition
and the end point correlation line.
Vin (LSBIDEAL)
0
1
VSSA
60/72
2
3
4
5
6
7
1021 1022 1023 1024
VDDA
STR91xF
6.13
Electrical characteristics
Communication interface electrical characteristics
6.13.1 10/100 Ethernet MAC electrical characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 °C unless otherwise specified.
Ethernet MII Interface Timings
Figure 16. MII_RX_CLK and MII_TX_CLK timing diagram
3
MII_RX_TCLK, MII_TX_CLK
2
4
4
1
Table 20.
MII_RX_CLK and MII_TX_CLK timing table
Value
Symbol
Parameter
Symbol
Unit
Min
Max
1
Cycle time
tc(CLK)
2
Pulse duration HIGH
tHIGH(CLK)
40%
60%
3
Pulse duration LOW
tLOW(CLK)
40%
60%
4
Transition time
tt(CLK)
40
ns
1
ns
Figure 17. MDC timing diagram
3
MDC
2
4
4
1
Table 21.
MDC timing table
Value
Symbol
Parameter
Symbol
Unit
Min
Max
1
Cycle time
tc(MDC)
266
2
Pulse duration HIGH
tHIGH(MDC)
40%
60%
3
Pulse duration LOW
tLOW(MDC)
40%
60%
4
Transition time
tt(MDC)
ns
1
ns
Ethernet MII management timings
Figure 18. Ethernet MII management timing diagram
MDC
1
MDIO
output
2
3
MDIO
input
61/72
STR91xF
Electrical characteristics
Table 22.
Ethernet MII management timing table
Value
Symbol
Parameter
Symbol
Unit
Min
Max
1
MDIO delay from rising
edge of MDC
tc(MDIO)
2
MDIO setup time to rising
edge of MDC
Tsu (MDIO)
2.70
ns
3
MDIO hold time from rising
edge of MDC
Th (MDIO)
-2.03
ns
2.83
ns
Ethernet MII transmit timings
Figure 19. Ethernet MII transmit timing diagram
MII_TX_CLK
2
1
3
MII_TX_EN
4
5
MII_CRS
6
8
MII_COL
7
MII_TXD
Table 23.
Ethernet MII transmit timing table
Value
Symbol
Parameter
Symbol
Unit
Min
62/72
Max
1
MII_TX_CLK high to
MII_TX_EN valid
tVAL(MII_TX_EN)
4.20
ns
2
MII_TX_CLK high to
MII_TX_EN invalid
Tinval(MII_TX_EN)
4.86
ns
3
MII_CRS valid to
MII_TX_CLK high
Tsu(MII_CRS)
0.61
ns
4
MII_TX_CLK high to
MII_CRS invalid
Th(MII_CRS)
0.00
ns
5
MII_COL valid to
MII_TX_CLK high
Tsu(MII_COL)
0.81
ns
6
MII_TX_CLK high to
MII_COL invalid
Th(MII_COL)
0.00
ns
7
MII_TX_CLK high to
MII_TXD valid
tVAL(MII_TXD)
5.02
ns
8
MII_TXCLK high to
MII_TXD invalid
Tinval(MII_TXD
5.02
ns
STR91xF
Electrical characteristics
Ethernet MII Receive timings
Figure 20. Ethernet MII receive timing diagram
MII_RX_CLK
1
2
MII_RXD
MII_RX_DV
MII_RX_ER
Figure 21. Ethernet MII receive timing table
Value
Symbol
Parameter
Symbol
Unit
Min
Max
1
MII_RXD valid to
MII_RX_CLK high
Tsu(MII_RXD)
0.81
ns
2
MII_RX_CLK high to
MII_RXD invalid
Th(MII_RXD)
0.00
ns
6.13.2 USB electrical interface characteristics
USB 2.0 Compliant in Full Speed Mode
6.13.3 CAN interface electrical characteristics
Conforms to CAN 2.0B protocol specification
63/72
STR91xF
Electrical characteristics
6.13.4 I2C electrical characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 °C unless otherwise specified.
Table 24.
Symbol
I2C Electrical Characteristics
Parameter
Standard I2C
Min
Max
Fast I2C
Min
Unit
Max
tBUF
Bus free time between a STOP
and START condition
4.7
1.3
ms
tHD:STA
Hold time START condition.
After this period, the first clock
pulse is generated
4.0
0.6
µs
tLOW
LOW period of the SCL clock
4.7
1.3
µs
tHIGH
HIGH period of the SCL clock
4.0
0.6
µs
tSU:STA
Set-up time for a repeated
START condition
4.7
0.6
µs
tHD:DAT
Data hold time
0
0
ns
tSU:DAT
Data set-up time
250
100
ns
tR
Rise time of both SDA and SCL
signals
1000
20+0.1Cb
300
ns
tF
Fall time of both SDA and SCL
signals
300
20+0.1Cb
300
ns
tSU:STO
Set-up time for STOP condition
Cb
Capacitive load for each bus
line
4.0
0.6
400
µs
400
pF
Notes: 1 The device must internally provide a hold time of at least 300 ns for the SDA signal in order to
bridge the undefined region of the falling edge of SCL
2 The maximum hold time of the START condition has only to be met if the interface does not
stretch the low period of SCL signal
3 Cb = total capacitance of one bus line in pF
64/72
STR91xF
Electrical characteristics
6.13.5 SPI electrical characteristics
VDDQ = 2.7 - 3.6V, VDD = 1.65 - 2V, TA = -40 / 85 °C unless otherwise specified.
Table 25.
SPI electrical characteristics
Value
Symbol
Parameter
Test Conditions
Unit
Typ
fSCLK
1/tc(SCLK)
tr(SCLK)
SPI clock frequency
Max
Master
24
Slave
4
SPI clock rise and fall times
50pF load
tsu(SS)
SS setup time
Slave
1
th(SS)
SS hold time
Slave
1
tw(SCLKH)
tw(SCLKL)
SCLK high and low time
tsu(MI)
tsu(SI)
Data input setup time
th(MI)
th(SI)
Data input hold time
ta(SO)
Data output access time
Slave
6
tdis(SO)
Data output disable time
Slave
6
tv(SO)
Data output valid time
6
th(SO)
Data output hold time
Slave (after enable
edge)
tv(MO)
Data output valid time
th(MO)
Data output hold time
tf(SCLK)
0.1
Master
MHz
V/ns
1
Slave
Master
5
Slave
Master
6
Slave
tPCLK
0
Master (before capture
edge)
0.25
0.25
Figure 22. SPI slave timing diagram with CPHA=0 1)
NSS INPUT
SCLK INPUT
tsu(NSS)
tc(SCLK)
th(NSS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
MISO OUTPUT
tw(SCLKH)
tw(SCLKL)
MSB OUT
tsu(SI)
MOSI INPUT
tv(SO)
th(SO)
tdis(SO)
tr(SCLK)
tf(SCLK)
BIT6 OUT
LSB OUT
th(SI)
MSB IN
BIT1 IN
LSB IN
Notes: 1 Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
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STR91xF
Electrical characteristics
Figure 23. SPI slave timing diagram with CPHA=11)
NSS INPUT
tsu(NSS)
tc(SCLK)
th(NSS)
SCLK INPUT
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCLKH)
tw(SCLKL)
ta(SO)
MISO OUTPUT
tv(SO)
MSB OUT
HZ
tsu(SI)
th(SO)
BIT6 OUT
LSB OUT
th(SI)
MSB IN
MOSI INPUT
tdis(SO)
tr(SCLK)
tf(SCLK)
BIT1 IN
LSB IN
Figure 24. SPI master timing diagram 1)
NSS INPUT
tc(SCLK)
SCLK IOUTPUT
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCLKH)
tw(SCLKL)
tsu(MI)
MISO INPUT
MOSI OUTPUT
th(MI)
MSB IN
tv(MO)
tr(SCLK)
tf(SCLK)
BIT6 IN
MSB OUT
BIT6 OUT
Notes: 1 Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
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LSB IN
th(MO)
LSB OUT
STR91xF
6.14
Electrical characteristics
JTAG interface electrical characteristics
Table 26.
JTAG interface electrical characteristics
Value
Symbol
Parameter
Unit
Min
Max
tJTCKL
JTCK Low
3(1/fCPUCLK)
ns
tJTCKH
JTCK High
3(1/fCPUCLK)
ns
tJTCKP
JTCK Period
10(1/fCPUCLK)
ns
tJTSU
JTDI, JTMS Setup before JTCK High
4
ns
tJTHLD
JTDI Hold after JTCK High
4
ns
tJTMSHLD
JTMS Hold after JTCK High
3(1/fCPUCLK)
ns
tJDHLD
JTDO Hold Time
20
ns
tJDVAL
JTDO Low to JTDO Valid
20
ns
fJRTCK
JRTCK Frequency
fCPUCLK/ 10
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STR91xF
Package mechanical data
7
Package mechanical data
Figure 25. 80-Pin Low Profile Quad Flat Package
SEATING
PLANE
C
mm
inches
Dim.
A
A2
Min
Typ Max Min
b
c
A1
A
0.25 mm
GAGE PLANE
ccc
C
A1
D1
L
D3
60
L1
41
61
40
b
E3
0.063
0.006
0.05
A2
1.35 1.40 1.45 0.053 0.055 0.057
b
0.17 0.22 0.27 0.007 0.009 0.011
c
0.09
E1
E
0.551
D1
12.00
0.472
D2
9.50
0.374
E
14.00
0.551
E1
12.00
0.472
E2
9.50
0.374
0.50
0.020
e
k
21
0.008
14.00
0.45 0.60 0.75 0.018 0.024 0.030
L1
80
0.20 0.004
D
L
1.00
0d
0.039
7d
ddd
1
1.60
0.15 0.002
A1
k
D
Typ Max
0d
7d
0.08
0.003
20
Number of Pins
e
PIN 1
IDENTIFICATION
N
80
Figure 26. 128-Pin Low Profile Quad Flat Package
SEATING
PLANE
C
mm
inches
Dim.
A
A2
Min
Typ Max Min
0.25 mm
GAGE PLANE
b
c
A1
A
ccc
C
A1
D1
L
D3
96
0.063
0.15 0.002
0.006
A1
0.05
A2
1.35 1.40 1.45 0.053 0.055 0.057
b
0.13 0.18 0.23 0.005 0.007 0.009
k
D
Typ Max
1.60
L1
65
c
0.09
D
15.80 16.00 16.20 0.622 0.630 0.638
64
0.008
D1 13.80 14.00 14.20 0.543 0.551 0.559
D3
97
0.20 0.004
E
12.40
0.488
15.80 16.00 16.20 0.622 0.630 0.638
E1 13.80 14.00 14.20 0.543 0.551 0.559
b
E3
E1
E
E3
12.40
0.488
e
0.40
0.016
L
0.45 0.60 0.75 0.018 0.024 0.030
L1
128
33
k
ccc
1
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3.5d
0.039
7d
0d
3.5d
0.08
32
Number of Pins
e
PIN 1
IDENTIFICATION
1.00
0d
N
128
7d
0.003
STR91xF
8
Ordering information
Ordering information
Table 27.
Ordering information
Part Number
Flash KB RAM KB
Major Peripherals
Package
STR910FM32X6
256+32
64
CAN, 48 I/Os
LQFP80,
12x12mm
STR910FW32X6
256+32
64
CAN, EMI, 80 I/Os
LQFP128,
14x14mm
STR911FM42X6
256+32
96
USB, CAN, 48 I/Os
STR911FM44X6
512+32
96
LQFP80,
12x12mm
STR912FW42X6
256+32
96
Ethernet, USB, CAN, EMI, 80 I/Os
LQFP128,
14x14mm
STR912FW44X6
512+32
96
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STR91xF
Ordering information
Table 28.
Ordering information scheme
Example:
STR9
1
2
F
W
4
4
X
6
T
Family
ARM9 Microcontroller Family
Series
1 = STR9 Series 1
Feature set
0 = CAN, UART, IrDA, I2C, SSP
1 = USB, CAN, UART, IrDA, I2C, SSP
2 = USB, CAN, UART, IrDA, I2C, SSP, ETHERNET
Memory type
F = Flash
No. of pins
M = 80
W = 128
SRAM size
3 = 64K
4 = 96K
Program Memory Size
2 = 256K
4 = 512K
Package
X = plastic LQFP
Temperature Range
6 = -40 to 85°C
Shipping Option
T = Tape & Reel Packing
For a list of available options (e.g. speed, package) or for further information on any aspect of this
device, please contact the ST Sales Office nearest to you.
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STR91xF
9
Revision history
Revision history
Date
Revision
12-Apr-2006
1
Changes
Initial release
71/72
STR91xF
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