STD100N3LF3 STU100N3LF3 N-channel 30V - 0.0045Ω - 80A - DPAK - IPAK Planar STripFET™ II Power MOSFET General features RDS(on) ID Type VDSSS STD100N3LF3 30 V <0.0055 Ω 80 A(1) 110 W STU100N3LF3 30 V <0.0055 Ω 80 A(1) 110 W Pw 3 3 2 1 1 1. Current limited by package ■ 100% avalanche tested ■ Logic level threshold DPAK IPAK Description This Power MOSFET is the latest refinement of STMicroelectronics unique “Single Feature Size™” strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics, low gate charge and less critical alignment steps therefore a remarkable manufacturing reproducibility. This new improved device has been specifically designed for Automotive application and DC-DC converters. Internal schematic diagram Applications ■ Switching application Order codes Part number Marking Package Packaging STD100N3LF3 100N3LF3 DPAK Tape & reel STU100N3LF3 100N3LF3 IPAK Tube February 2007 Rev 1 1/15 www.st.com 15 Contents STD100N3LF3 - STU100N3LF3 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/15 ................................................ 9 STD100N3LF3 - STU100N3LF3 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Drain-source voltage (VGS = 0) 30 V Drain current (continuous) at TC = 25°C 80 A Drain current (continuous) at TC=100°C 70 A IDM (2) Drain current (pulsed) 320 A PTOT Total dissipation at TC = 25°C 110 W Derating factor 0.73 W/°C 3.9 V/ns -55 to 175 °C Value Unit VDS ID (1) ID Parameter dv/dt (3) Peak diode recovery voltage slope Tstg TJ Storage temperature Max. operating junction temperature 1. Current limited by package. 2. Pulse width limited by safe operating area 3. ISD ≤80A, di/dt ≤360 A/µs, VDS ≤V(BR)DSS, TJ ≤TJMAX Table 2. Symbol Thermal data Parameter RthJC Thermal resistance junction-case Max 1.36 °C/W RthJA Thermal resistance junction-ambient Max 100 °C/W Tl Maximum lead temperature for soldering purpose 275 °C Value Unit Table 3. Symbol Avalanche characteristics Parameter IAR Not-repetitive avalanche current (pulse width limited by TJ max) 40 A EAS Single pulsed avalanche energy (starting TJ = 25°C, ID = IAV, VDD = 24V 500 mJ 3/15 Electrical characteristics 2 STD100N3LF3 - STU100N3LF3 Electrical characteristics (TCASE=25°C unless otherwise specified) Table 4. Symbol V(BR)DSS On/off states Parameter Drain-source breakdown voltage Test conditions ID = 250µA, VGS = 0 Zero gate voltage drain current (VGS = 0) IGSS Gate body leakage current (VDS = 0) VGS = ±20V Gate threshold voltage VDS= VGS, ID = 250µA Table 5. Symbol gfs (1) Ciss Coss Crss Qg Static drain-source on resistance V VDS = Max rating @125°C 1 10 µA µA ±200 nA 1 V VGS = 5V, ID = 20A 0.0045 0.0055 0.008 0.01 Ω Ω VGS = 10 V, ID = 40 A @125°C 0.0068 Ω VGS = 5 V, ID = 20 A @125°C 0.0146 Ω Parameter Test conditions Min. Typ. Max. Unit Forward transconductance VDS = 10 V, ID = 15A 31 S Input capacitance Output capacitance Reverse transfer capacitance VDS = 25V, f = 1 MHz, VGS = 0 2060 728 67 pF pF pF Qgd RG Gate input resistance VDD = 24V, ID = 80A VGS = 5V Figure 15 on page 9 f = 1MHz gate DC Bias = 0 Test signal level = 20mV Open drain 1. Pulsed: pulse duration=300µs, duty cycle 1.5% 4/15 Unit Dynamic Total gate charge Gate-source charge Gate-drain charge Qgs Max. 30 VGS = 10V, ID = 40A RDS(on) Typ. VDS = Max rating, IDSS VGS(th) Min. 20 7 7.5 1.9 27 nC nC nC Ω STD100N3LF3 - STU100N3LF3 Table 6. Symbol td(on) tr td(off) tf Table 7. Symbol Electrical characteristics Switching times Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. 9 205 31 35 VDD= 15V, ID= 40A, RG=4.7Ω, VGS=10V Figure 14 on page 9 Unit ns ns ns ns Source drain diode Max Unit Source-drain current 80 A ISDM(1) Source-drain current (pulsed) 320 A VSD(2) Forward on voltage 1.3 V ISD trr Qrr IRRM Parameter Reverse recovery time Reverse recovery charge Reverse recovery current Test conditions Min Typ. ISD = 40A, VGS = 0 ISD = 80A, di/dt = 100A/µs, VDD = 25V, TJ = 150°C 40 40 2 ns µC A Figure 16 on page 9 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300µs, duty cycle 1.5% 5/15 Electrical characteristics STD100N3LF3 - STU100N3LF3 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characteristics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 6/15 STD100N3LF3 - STU100N3LF3 Electrical characteristics Figure 7. Gate charge vs gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs temperature Figure 11. Normalized on resistance vs temperature Capacitance variations Figure 10. Normalized BVDSS vs temperature Figure 12. Source-drain diode forward characteristics 7/15 Electrical characteristics STD100N3LF3 - STU100N3LF3 Figure 13. Allowable Iav vs time in avalanche The previous curve gives the single pulse safe operating area for unclamped inductive loads, under the following conditions: PD(AVE) = 0.5 * (1.3 * BVDSS *IAV) EAS(AR) = PD(AVE) * tAV Where: IAV is the allowable current in avalanche PD(AVE) is the average power dissipation in avalanche (single pulse) tAV is the time in avalanche 8/15 STD100N3LF3 - STU100N3LF3 3 Test circuit Test circuit Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit Figure 16. Test circuit for inductive load switching and diode recovery times 9/15 Package mechanical data 4 STD100N3LF3 - STU100N3LF3 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 10/15 STD100N3LF3 - STU100N3LF3 Package mechanical data TO-251 (IPAK) MECHANICAL DATA mm DIM. MIN. inch MAX. MIN. A 2.2 TYP. 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A3 0.7 1.3 0.027 0.051 B 0.64 0.9 0.025 0.031 B2 5.2 5.4 0.204 0.212 B3 TYP. MAX. 0.85 B5 0.033 0.3 0.012 B6 0.95 C 0.45 C2 0.48 D 6 E 6.4 6.6 0.037 0.6 0.017 0.023 0.6 0.019 0.023 6.2 0.236 0.244 0.252 0.260 G 4.4 4.6 0.173 0.181 H 15.9 16.3 0.626 0.641 L 9 9.4 0.354 0.370 L1 0.8 1.2 0.031 0.047 L2 0.8 1 0.031 0.039 A1 C2 A3 A C H B B6 = 1 = 2 G = = = E B2 = 3 B5 L D B3 L2 L1 0068771-E 11/15 Package mechanical data STD100N3LF3 - STU100N3LF3 DPAK MECHANICAL DATA mm. inch DIM. MIN. A A1 A2 B b4 C C2 D D1 E E1 e e1 H L (L1) L2 L4 R V2 TYP 2.2 0.9 0.03 0.64 5.2 0.45 0.48 6 MAX. MIN. 2.4 1.1 0.23 0.9 5.4 0.6 0.6 6.2 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 6.6 0.252 5.1 6.4 0.260 0.173 0.368 0.039 2.8 0.8 0.181 0.397 0.110 0.031 1 0.023 0.2 0° 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 0.185 0.090 4.6 10.1 0.6 MAX. 0.200 4.7 2.28 4.4 9.35 1 TYP. 0.039 0.008 8° 0° 8° 0068772-F 12/15 STD100N3LF3 - STU100N3LF3 5 Packaging mechanical data Packaging mechanical data DPAK FOOTPRINT All dimensions are in millimeters TAPE AND REEL SHIPMENT REEL MECHANICAL DATA DIM. mm MIN. A B DIM. mm inch MIN. MAX. A0 6.8 7 0.267 0.275 B0 10.4 10.6 0.409 0.417 B1 MIN. MAX. MIN. 330 1.5 C 12.8 D 20.2 G 16.4 N 50 T TAPE MECHANICAL DATA inch MAX. 12.992 0.059 13.2 0.504 0.520 18.4 0.645 0.724 0.795 1.968 22.4 0.881 BASE QTY BULK QTY 2500 2500 MAX. 12.1 0.476 1.6 0.059 0.063 D 1.5 D1 1.5 E 1.65 1.85 F 7.4 7.6 0.291 0.299 K0 2.55 2.75 0.100 0.108 P0 3.9 4.1 0.153 0.161 P1 7.9 8.1 0.311 0.319 P2 1.9 2.1 0.075 0.082 R 40 W 15.7 0.059 0.065 0.073 1.574 16.3 0.618 0.641 13/15 Revision history 6 STD100N3LF3 - STU100N3LF3 Revision history Table 8. 14/15 Revision history Date Revision 07-Feb-2006 1 Changes Initial release. STD100N3LF3 - STU100N3LF3 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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