USBUFxxW6 A. S. D. EMI filter and line termination for USB upstream ports Application EMI Filter and line termination for USB upstream ports on: ■ ■ USB Hubs PC peripherals SOTT323-6L Features ■ ■ ■ ■ Monolithic device with recommended line termination for USB upstream ports Integrated Rt series termination and Ct bypassing capacitors. Integrated ESD protection Small package size Description Table 1. Order Codes Part Number Marking USBUF01W6 UU1 USBUF02W6 UU2 Figure 1. Functional diagram 3.3 V The USB specification requires upstream ports to be terminated with pull-up resistors from the D+ and D- lines to Vbus. On the implementation of USB systems, the radiated and conducted EMI should be kept within the required levels as stated by the FCC regulations. In addition to the requirements of termination and EMC compatibility, the computing devices are required to be tested for ESD susceptibility. Rt Grd ■ ■ ■ EMI / RFI noise suppression Required line termination for USB upstream ports ESD protection exceeding IEC 61000-4-2 level 4 High flexibility in the design of high density boards Tailored to meet USB 1.1 standard February 2006 3.3 V Rt D2 D3 Ct Benefits ■ D4 Ct The USBUFxxW6 provides the recommended line termination while implementing a low pass filter to limit EMI levels and providing ESD protection which exceeds IEC 61000-4-2 level 4 standard. The device is packaged in a SOT323-6L which is the smallest available lead frame package (50% smaller than the standard SOT23). ■ Rp D1 Rt Rp Ct CODE 01 33 Ω 1.5 kΩ 47 pF CODE 02 22 Ω 1.5 kΩ 47 pF Tolerance ± 10% ± 10% ± 20% Complies with the following standards: IEC 61000-4-2, level 4 ± 15 kV (air discharge) ± 8 kV (contact discharge) MIL STD 883E, Method 3015-7 Class 3 C = 100 pF R = 1500 Ω 3 positive strikes and 3 negative strikes (F = 1 Hz) Rev 5 1/11 www.st.com 11 Characteristics 1 USBUFxxW6 Characteristics Table 2. Absolute ratings (Tamb = 25° C) Symbol Parameter VPP Tj Tstg Unit ESD discharge IEC 61000-4-2, air discharge ESD discharge IEC 61000-4-2, contact discharge ESD discharge - MIL STD 883E - Method 3015-7 ± 16 ±9 ± 25 kV Maximum junction temperature 150 °C - 55 to + 150 °C 260 °C -40 to 70 °C 100 mW Storage temperature range TL Lead solder temperature (10 second duration) Top Operating temperature range P 2 Value Power rating per resistor Technical information Figure 2. USB standard requirements 3.3V 1.5k Rt Full-speed or Low-speed USB Transceiver Ct Twisted pair shielded Rt DHost or Hub port Ct 15k Rt D+ D+ 15k Zo = 90ohms 5m max Ct Full-speed USB Transceiver Ct Hub 0 or Full-speed function Ct Low-speed USB Transceiver Ct Hub 0 or Low-speed function Rt D- FULL SPEED CONNECTION 3.3V 1.5k Full-speed or Low-speed USB Transceiver Ct Untwisted unshielded Rt DHost or Hub port Ct 15k D+ D+ Rt 3m max 15k LOW SPEED CONNECTION 2/11 Rt Rt D- USBUFxxW6 Application example Figure 3. Implementation of ST solutions for USB ports Host/Hub USB por transceivert Downstream port USBUF01W6 USBDF01W5 D2 Rt D+ D+ in Ct Rd D+ out D+ Gnd Ct Ct Rt 3.3 V Rt D- in Rt D+ D+ Gnd Ct Rd D1 CABLE Gnd D- Upstream port Peripheral transceiver 2.1 Technical information D- D- Rp D- out D3 3.3V D4 D- FULL SPEED CONNECTION USBUF01W6 USBDF01W5 D2 Rt D+ D+ in Ct Rd D+ out D+ Gnd D+ Ct Ct Rt 3.3 V Rt Gnd DD- in Rt D- D1 CABLE Gnd Ct Rd Upstream port D+ Peripheral transceiver Host/Hub USB por transceivert Downstream port D- D- out Rp D3 3.3V D4 D- LOW SPEED CONNECTION 2.2 EMI filtering Current FCC regulations requires that class B computing devices meet specified maximum levels for both radiated and conducted EMI. ● Radiated EMI covers the frequency range from 30 MHz to 1 GHz. ● Conducted EMI covers the 450 kHz to 30 MHz range. For the types of devices utilizing the USB, the most difficult test to pass is usually the radiated EMI test. For this reason the USBUFxxW6 device is aiming to minimize radiated EMI. The differential signal (D+ and D-) of the USB does not contribute significantly to radiated or conducted EMI because the magnetic field of both conductors cancels each other. The inside of the PC environment is very noisy and designers must minimize noise coupling from the different sources. D+ and D-must not be routed near high speed lines (clocks spikes). Induced common mode noise can be minimized by running pairs of USB signals parallel to each other and running grounded guard trace on each side of the signal pair from the USB controller to the USBUF device. If possible, locate the USBUF device physically near the 3/11 Technical information USBUFxxW6 USB connectors. Distance between the USB controller and the USB connector must be minimized. The 47 pF (Ct) capacitors are used to bypass high frequency energy to ground and for edge control, and are placed between the driver chip and the series termination resistors (Rt). Both Ct and Rt should be placed as close to the driver chip as is practicable. The USBUFxxW6 ensures a filtering protection against ElectroMagnetic and RadioFrequency Interferences thanks to its low-pass filter structure. This filter is characterized by the following parameters: ● cut-off frequency ● Insertion loss ● high frequency rejection. Figure 4. USBUFxxW6 typical attenuation Figure 5. Measurement configuration S21 (dB) 0 50Ω -10 TEST BOARD UUx Vg -20 50Ω -30 1 2.3 10 100 Frequency (MHz) 1,000 ESD PROTECTION In addition to the requirements of termination and EMC compatibility, computing devices are required to be tested for ESD susceptibility. This test is described in the IEC 61000-4-2 and is already in place in Europe. This test requires that a device tolerates ESD events and remains operational without user intervention. The USBUFxxW6 is particularly optimized to perform ESD protection. ESD protection is based on the use of device which clamps at: Vcl = VBR + Rd . IPP This protection function is splitted in 2 stages. As shown in figure 6, the ESD strikes are clamped by the first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor Rt. Such a configuration makes the output voltage very low at the output. 4/11 USBUFxxW6 Technical information Figure 6. USBUFxxW6 ESD clamping behavior Rg S1 Rd VPP VBR Rd Vinput Rload Voutput VBR USBUF01W6 ESD Surge Figure 7. S2 Rt Device to be protected Measurement board ESD SURGE Vin UUx 16kV Air Discharge TEST BOARD Vout To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical dynamical resistance value Rd. By taking into account these following hypothesis: Rt > Rd, Rg > Rd and Rload > Rd, it gives these formulas: R g ⋅ V BR + R d ⋅ V g Vinput = ---------------------------------------------Rg R t ⋅ V BR + R d ⋅ Vinput V ouput = -----------------------------------------------------Rt The results of the calculation done for Vg = 8 kV, Rg = 330 Ω (IEC 61000-4-2 standard), VBR = 7 V (typ.) and Rd = 1 Ω (typ.) give: Vinput = 31.2 V Voutput = 7.95 V This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at the Vinput side. This parasitic effect is not present at the Voutput side due the low current involved after the resistance Rt. The measurements done hereafter show very clearly (figure 8) the high efficiency of the ESD protection: ● no influence of the parasitic inductances on Voutput stage ● Voutput clamping voltage very close to VBR (breakdown voltage) in the positive way and - VF (forward voltage) in the negative way 5/11 Technical information Figure 8. USBUFxxW6 Remaining voltage at both stages S1 (Vinput) and S2 (Voutput) during ESD surge Vin Vin Vout Vout Positive surge Negative surge Please note that the USBUFxxW6 is not only acting for positive ESD surges but also for negative ones. For these kinds of disturbances it clamps close to ground voltage as shown in Figure 8. (negative surge. 2.4 Latch-up phenomena The early ageing and destruction of IC’s is often due to latch-up phenomenon which is mainly induced by dV/dt. Thanks to its structure, the USBUFxxW6 provides a high immunity to latch-up phenomenon by smoothing very fast edges. 2.5 Crosstalk behavior Figure 9. Crosstalk phenomenon. RG1 Line 1 VG1 RL1 RG2 VG2 RL2 DRIVERS α1 VG1 + β1 2VG2 Line 2 α2 VG2 + β2 1VG1 RECEIVERS The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor (β12 or β21) increases when the gap across lines decreases, particularly in silicon dice. In the example above the expected signal on load RL2 is α2VG2, in fact the real voltage at this point has got an extra value β21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few kΩ). 6/11 USBUFxxW6 Technical information Figure 10. Figure 10: Analog crosstalk measurements Figure 11. Typical analog crosstalk results Analog crosstalk (dB) 0 TEST BOARD -20 UUx -40 50Ω 50Ω Vg -60 -80 -100 1 10 100 Frequency (MHz) 1,000 Figure 10. gives the measurement circuit for the analog crosstalk application. In Figure 11., the curve shows the effect of the D+ cell on the D-cell. In usual frequency range of analog signals (up to 100 MHz) the effect on disturbed line is less than -37 db. Figure 12. Digital crosstalk measurements configuration +5V +5V 74HC04 74HC04 3.3 V Rt D+ D1 Square Pulse Generator Ct Rp D4 VG1 +5V Gnd D- 3.3 V Rt D2 Ct D3 β21 VG1 Figure 12. shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. Figure 13. Digital crosstalk results VG1 β21VG1 Figure 13. shows, with a signal from 0 to 5 V and rise time of few ns, the impact on the disturbed line is less than 250 mV peak to peak. No data disturbance was noted on the other line.The measurements performed with falling edges gives an impact within the same range. 7/11 Technical information 2.6 USBUFxxW6 Transition times This low pass filter has been designed in order to meet the USB 1.1 standard requirements that implies the signal edges are maintained within the 4 -20 ns stipulated USB specification limits. To verify this point, we have measured the rise time of VD+ voltage with and without the USBUFxxW6 device. Figure 14. Typical rise and fall times: measurement configuration +5V without +5V 74HC04 Figure 15. Typical rise times with and without protection device 74HC04 D+ USBDF 01W6 +5V Square Pulse Generator D- with Figure 14. shows the circuit used to perform measurements of the transition times. In Figure 15., we see the results of such measurements: trise = 3.8 ns driver alone trise = 7.8 ns with protection device The adding of the protection device causes the rise time increase of roughly 4ns. Note: 8/11 Rise time has been measured between 10% and 90% of the signal (resp. 90% and 10%) USBUFxxW6 3 Packaging information Packaging information Table 3. SOT323-6L Package Mechanical Data DIMENSIONS REF. Millimeters A E e b D Inches Min. Max. Min. Max. A 0.8 1.1 0.031 0.043 A1 0 0.1 0 0.004 A2 0.8 1 0.031 0.039 b 0.15 0.3 0.006 0.012 c 0.1 0.18 0.004 0.007 D 1.8 2.2 0.071 0.086 E 1.15 1.35 0.045 0.053 e A1 A2 Q1 e c L 0.65 Typ. 0.025 Typ. HE 1.8 2.4 0.071 0.094 L 0.1 0.4 0.004 0.016 Q1 0.1 0.4 0.004 0.016 HE Figure 16. Recommeneded footprint (dimensions in mm) 0.65 1.05 2.9 0.80 1.05 0.40 Table 4. Mechanical specifications Lead plating Tin-lead Lead plating thickness 5 m min 25 m max Lead material Sn / Pb (70% to 90%Sn) Lead coplanarity 10 m max Body material Molded epoxt Flammability UL94V-0 9/11 Ordering Information 4 5 10/11 USBUFxxW6 Ordering Information Ordering code Marking Package Weight Base qty Delivery mode USBUF01W6 UU1 SOT323-6L 5.4 mg 3000 Tape & reel USBUF02W6 UU2 SOT323-6L 5.4 mg 3000 Tape & reel Revision History Date Revision Description of Changes Mar-2002 3A Feb-2005 4 Layout update. No content change. 28-Feb-2006 5 Operating temperature range updated to -40 to 70° C. Layout updated to current standard. Last update. USBUFxxW6 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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