EMIF02-600FU7 Application Specific Discretes A.S.D.TM 10-BIT WIDE EMI FILTER INCUDING ESD PROTECTION MAIN APPLICATIONS Where EMI filtering in ESD sensitive equipment is required : Computers and printers Communication systems Mobile phones MCU Boards DESCRIPTION The EMIF02-600FU7 is a highly integrated array designed to suppress EMI / RFI noise in all systems subjected to electromagnetic interferences. Additionally, this filter includes an ESD protection circuitry which prevents the protected device from destruction when subjected to ESD surges up to 15 kV. The EMIF02-600FU7 provides best efficiency when using separated inputs and outputs, in the so-called 4-points structure. BENEFITS 10-bit EMI bi-directional low-pass-filter Enhanced ESD protection for the protected device, optimized by the four point structure High flexibility in the design of high density boards COMPLIESWITHTHE FOLLOWING STANDARDS : IEC 1000-4-2 15kV 8 kV SSOP24 FUNCTIONAL DIAGRAM . . . 10 C E L L S . . . (air discharge) (contact discharge) ESDresponseto IEC1000-4-2 (15 kVairdischarge) Filtering response (with 50Ω line) TM : ASD is trademark of STMicroelectronics. September 1998 - Ed: 2A 1/9 EMIF02-600FU7 ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C) Symbol Parameter and test conditions VPP Tj Value Unit ESD discharge IEC1000-4-2, air discharge ESD discharge IEC1000-4-2, contact discharge 16 9 kV Junction temperature 150 °C T op Operatingtemperature range -40 to + 85 °C Tstg Storage temperature range -55 to +150 °C TL Lead solder temperature (10 second duration) 260 °C ELECTRICAL CHARACTERISTICS (Tamb =25 °C) Symbol Parameter VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic impedance IPP Peak pulse current RI/O Serial resistance between Input and Output Symbol Test conditions VBR IR = 1 mA IRM VRM = 3V RI/O Serial resistance between Input and Output Rd Ipp = 10 A, t p = 2.5 µs (see note 1) Min. Typ. Max. Unit 6 7 8 V 1 µA 720 Ω 480 600 0.55 Note 1 : to calculate the ESD residual voltage, please refer to the paragraph ”ESD PROTECT ION” on pages 4 & 5 Fig.1 : Relative variation of leakage current versus reverse voltage(Typical values) IR[VR] / IR[VR=3V] 20.0 10.0 5.0 2.0 1.0 VR (V) 0.5 2.5 2/9 3.0 3.5 4.0 4.5 5.0 5.5 Ω EMIF02-600FU7 TECHNICAL INFORMATION FREQUENCY BEHAVIOR The EMIF02-600FU7 is firstly designed as an EMI/RFI filter. This low-pass filter is characterized by the following parameters: - Cut-off frequency - Insertion loss - High frequency rejection Fig A1 : EMIF02-600FU7frequencyresponse curve. Figure A1 gives these parameters, in particular the signal rejection at the GSM frequency is about -20dBm at 900MHz, while the attenuation for FM broadcast range (around 100MHz) is better than -32dBm Fig A2 : Measurement conditions SPECTRUM ANALYSER TG OUTPUT 50Ω RF INPUT EMIF02 Vg TEST BOARD Vin Vout 50Ω EMIF02 3/9 EMIF02-600FU7 ESD PROTECTION In addition to its filtering function, the EMIF02-600FU7 is particularly optimized to perform ESD protection. ESD protection is based on voltage clamping which can be calculated by : VCL = VBR + Rd.IPP This protection function is splitted in 2 stages. As shown in figure A3, the ESD strikes are clamped by the first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output voltage Vout very low. Fig A3 : ESD clamping behavior Rg ESD Surge Vg R Rd Rd Vbr Vbr Vout Vin Rload S2 S1 EMIF02-600FU7 Device to be protected To have a good approximation of the remaining voltages at both Vin and Vout stages, we provide the typical dynamical resistance value Rd. By taking into account these following hypothesis : R>>Rd, RG>>Rd and Rload>>Rd, it gives these formulas: Vin = Rg.Vbr+Rd.Vg Rg Vout = R.Vbr+Rd.Vin R The results of the calculation done for VG=8kV, RG=330Ω (IEC1000-4-2 standard) and VBR=7V (typ.) give: Vin = 20.33 V Vout = 7.01 V This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at the Vin side. This parasitic effect is not present at the Vout side due the low current involved after the resistance R. The measurements shown here after illustrate very clearly (Fig. A5a) the high efficiency of the ESD protection : - no influence of the parasitic inductances on Vout stage - Vout clamping voltage very close to VBR Fig A4 : Measurement conditions LOW-PASS FILTER Vin Vout GND 4/9 GND GND EMIF02-600FU7 Fig A5 : Remaining voltage at both stages S1 (Vin) and S2 (Vout) during ESD surge a) Positive surge b) Negative surge Please note that the EMIF02-600FU7 is not only acting for positive ESD surges but also for negative ones. For these kind of disturbances it clamps close to ground voltage as shown in Fig. A5b. NOTE: DYNAMIC RESISTANCE MEASUREMENT Fig A6 : Rd measurement current wave I As the value of the dynamic resistance remains stable for a surge duration lower than 20µs, the 2.5µs rectangular surge is well adapted. In addition both rise and fall times are optimized to avoid any parasitic phenomenon during the measurement of Rd. IPP t 2 µs 2.5 µs 2.5µs duration measurement wave CROSSTALK BEHAVIOR 1- Crosstalk phenomena Fig A7 : Crosstalk phenomena RG1 line 1 VG1 α VG1 β VG2 RL1 RG2 VG2 line 2 RL2 DRIVERS α VG2 β VG1 RECEIVERS The crosstalk phenomena are due to the coupling between 2 lines. The coupling factor ( β 12 or β21 ) increases when the gap across lines decreases, particularly in silicon dice. In the example above the expected signal on load RL2 is α2VG2, in fact the real voltage at this point has got an extra value β21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few kΩ). The following chapters give the value of both digital and analog crosstalk. 5/9 EMIF02-600FU7 2- Digital Crosstalk Fig A8 : Digital crosstalk measurement +5V +5V 74HC04 74HC04 Line 1 VG1 +5V Square Pulse Generator 5KHz Line 2 β21 VG1 Figure A8 shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. Figure A9 shows that in such a condition signal from 0 to 5V and rise time of 10 ns, the impact on the disturbed line is less than 20mV peak to peak. No data disturbance was noted on the concerned line. The same results were obtained with falling edges. Fig A9 : Digital crosstalk results 3- Analog Crosstalk Fig A10 : Analog crosstalk measurement Fig A11 : Typical analog crosstalk result 0 dB -10 -20 TG OUTPUT RF INPUT -30 -40 TEST BOARD -50 -60 EMIF02 -70 -80 F(MHz) 1 10 100 Figure A10 gives the measurement circuit for the analog application. In figure A11, the curve shows the effect of cell 1/24 on cell 2/23, no difference was found with other couples of adjacent cells. In usual frequency range of analog signals (up to 100MHz) the effect on disturbed line is less than -32 dBm. 6/9 EMIF02-600FU7 PSPICE MODEL Fig A12 : PSpice model of one EMIF02-600FU7cell 5nH 600 Ω 5nH Input Output Dzout Dzin 1Ω 1Ω 0.85nH GND Figure A12 shows the PSpice model of one cell of the EMIF02-600FU7. In this model, the clamping diodes (Dzin and Dzout) are defined by the following PSpice parameters : RS = 0.55 Cjo = 100p M = 0.3333 VJ = 0.6 BV = 7 IBV = 1u This model is available for frequency simulation and for ambient temperature of 27°C. The comparison between the PSpice simulation and the measured frequency response is given in figáA13. This shows that the PSpice model is very close to the product behavior. Fig A13 : Comparison between PSpice simulation and measured frequency response 0 dBm PSpice Model -10 Measured (smooth) -20 -30 F(MHz) -40 1 10 100 1000 7/9 EMIF02-600FU7 PACKAGE MECHANICAL DATA SSOP24 L A e b S a1 b1 E D 24 13 1 12 F Mechanical specifications Lead plating Tin-lead DIMENSIONS REF. Millimeters Inches Lead plating thickness 7µm min. 20 µm max. 0.068 0.073 0.079 Lead material Copper alloy 0.25 0.002 0.010 0.25 0.35 0.010 0.014 Lead coplanarity Body material 0.08mm max. Molded epoxy b1 0.10 0.35 0.0035 0.014 Flammability UL94V-0 D 8.07 E 7.60 Min. Typ. Max. Min. A 1.73 1.86 2.00 a1 0.05 b e 8.20 Max. 8.33 0.317 0.322 0.328 7.90 0.299 0.65 0.311 0.0256 F 5.20 5.38 0.2047 0.2118 L 0.25 0.88 0.0347 S 0.65mm 8.3mm 0.010 8°max RECOMMENDED FOOTPRINT 8/9 Typ. 5.3mm 0.45mm EMIF02-600FU7 ORDER CODE EMIF 02 ELECTRO MAGNETIC INTERFERENCE FILTER - 600 F U 7 RL RL : Tape & Reel RI/O value SSOP24 package Unidirectional transil diode NUMERICAL CODE Four point structure Order code Marking Package Weight Base qty Delivery mode EMIF02-600FU7 EMIF02-600 SSOP24 0.19g 59 tube EMIF02-600FU7RL EMIF02-600 SSOP24 0.19g 2000 tape & reel Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringementof patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1998 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com 9/9