TOSHIBA TMP1941AF

32-Bit TX System RISC
TX19 Family
TMP1941AF
MIPS16, application Specific Extensions and R3000A are a trademark of MIPS
Technologies, Inc.
The information contained herein is subject to change without notice.
The information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA for any infringements of patents or
other rights of the third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of TOSHIBA or others.
The products described in this document contain components made in the United States
and subject to export control of the U.S. authorities. Diversion contrary to the U.S. law
is prohibited.
TOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their
inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with
the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss
of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within
specified operating ranges as set forth in the most recent TOSHIBA products
specifications.
Also, please keep in mind the precautions and conditions set forth in the “Handling
Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
The Toshiba products listed in this document are intended for usage in general
electronics applications ( computer, personal equipment, office equipment, measuring
equipment, industrial robotics, domestic appliances, etc.).
These Toshiba products are neither intended nor warranted for usage in equipment that
requires extraordinarily high quality and/or reliability or a malfunction or failure of
which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended
Usage include atomic energy control instruments, airplane or spaceship instruments,
transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of Toshiba
products listed in this document shall be made at the customer’s own risk.
The products described in this document may include products subject to the foreign
exchange and foreign trade laws.
© 2003 TOSHIBA CORPORATION
All Rights Reserved
Preface
Toshiba offers a broad range of microcontrollers targeted for both commercial and industrial applications.
The TX System RISC TX19 Family manual contains the detailed specifications of the TX1941, including
the architecture, programming, capabilities, operation, electrical characteristics, packaging and so forth.
The TX1941 is a high-performance RISC processor based on the R3000A architecture and the MIPS16
Application Specific Extension pioneered by MIPS Technologies, Inc.
Recently, with the ever-growing market for lightweight portable devices, manufacturers of electronic
systems have been seeking cost-effective, single-chip solutions to processor-based applications. Toshiba
has designed the TX1941 to help customers achieve the best cost performance for their products.
TMP1941AF
Contents
Handling Precaution
TMP1941AF
1.
Features ................................................................................................................................................................... 1
2.
2.1
2.2
Signal Descriptions ................................................................................................................................................. 5
Pin Assignment .................................................................................................................................................. 5
Pin Usage Information ....................................................................................................................................... 6
3.1
Core Processor ........................................................................................................................................................ 9
Reset Operation ................................................................................................................................................. 9
3.
4.
Memory Map......................................................................................................................................................... 10
5.
Clock/Standby Control .......................................................................................................................................... 11
5.1
Clock Generation............................................................................................................................................. 12
5.1.1
Main System Clock ................................................................................................................................. 12
5.1.2
Subsystem Clock..................................................................................................................................... 12
5.1.3
Clock Source Block Diagrams ................................................................................................................ 13
5.2
Clock Generator (CG) Registers...................................................................................................................... 14
5.2.1
System Clock Control Registers.............................................................................................................. 14
5.2.2
ADC Conversion Clock .......................................................................................................................... 16
5.2.3
STOP/SLEEP Wake-up Interrupt Control Registers (INTCG Registers) ............................................... 16
5.2.4
Interrupt Request Clear Register ............................................................................................................. 18
5.3
System Clock Control Section ......................................................................................................................... 19
5.3.1
Oscillation Stabilization Time When Switching Between NORMAL and SLOW Modes...................... 19
5.3.2
System Clock Output .............................................................................................................................. 20
5.3.3
Reducing the Oscillator Clock Drive Capability..................................................................................... 20
5.4
Prescalar Clock Control Section ...................................................................................................................... 21
5.5
Clock Frequency Multiplication Section (PLL)............................................................................................... 21
5.6
Standby Control Section .................................................................................................................................. 22
5.6.1
TMP1941AF Operation in NORMAL and Standby Modes.................................................................... 23
5.6.2
CG Operation in NORMAL and Standby Modes ................................................................................... 23
5.6.3
Processor and Peripheral Block Operation in Standby Modes................................................................ 23
5.6.4
Wake-up Signaling.................................................................................................................................. 24
5.6.5
STOP Mode ............................................................................................................................................ 26
5.6.6
Returning from a Standby Mode............................................................................................................. 26
6.
Interrupts ............................................................................................................................................................... 29
6.1
Overview ......................................................................................................................................................... 29
6.2
Interrupt Sources.............................................................................................................................................. 31
6.3
Interrupt Detection........................................................................................................................................... 33
6.4
Resolving Interrupt Priority ............................................................................................................................. 33
6.5
Register Description ........................................................................................................................................ 34
6.5.1
Interrupt Vector Register (IVR) .............................................................................................................. 34
6.5.2
Interrupt Mode Control Registers (IMCF–IMC0) .................................................................................. 35
6.5.3
Interrupt Request Clear Register (INTCLR) ........................................................................................... 35
7.
7.1
7.2
7.3
7.4
7.5
7.6
I/O Ports ................................................................................................................................................................ 36
Address/Data Bus Bits 0–7 (AD0–AD7)......................................................................................................... 40
Address/Data Bus Bits 8–15 (AD8–AD15) / Address Bus Bits 8–15 (A8–A15) ............................................ 40
Address Bus Bits 16–23 (A16–A23) ............................................................................................................... 41
RD , WR , HWR , WAIT , BUSRQ , BUSAK , R / W ..................................................................................... 41
Port 37 ............................................................................................................................................................. 43
Port 4 (P40–P44) ............................................................................................................................................. 44
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TMP1941AF
7.7
7.8
7.9
7.10
7.11
7.12
Port 5 (P50–P57) ............................................................................................................................................. 47
Port 7 (P70–P77) ............................................................................................................................................. 48
Port 8 (P80–P87) ............................................................................................................................................. 52
Port 9 (P90–P97) ............................................................................................................................................. 55
Port A (PA0–PA7) ........................................................................................................................................... 60
Open-Drain Output Control ............................................................................................................................. 65
8.
External Bus Interface........................................................................................................................................... 66
8.1
Address and Data Buses .................................................................................................................................. 67
8.1.1
Supported Configurations ....................................................................................................................... 67
8.1.2
States of the Address Bus During On-Chip Address Accesses ............................................................... 67
8.2
External Bus Operation.................................................................................................................................... 68
8.2.1
Basic Bus Operation ............................................................................................................................... 68
8.2.2
Wait Timing............................................................................................................................................ 69
8.2.3
ALE Pulse Width .................................................................................................................................... 71
8.2.4
Read Recovery Time............................................................................................................................... 72
8.3
Bus Arbitration ................................................................................................................................................ 73
8.3.1
Bus Access Control................................................................................................................................. 73
8.3.2
Bus Arbitration Flow .............................................................................................................................. 73
8.3.3
Relinquishing the bus.............................................................................................................................. 74
9.
Chip Select/Wait Controller .................................................................................................................................. 75
9.1
Programming Chip Select Ranges ................................................................................................................... 75
9.1.1
Base/Mask Address Registers (BMA0–BMA3) ..................................................................................... 75
9.1.2
Base Address and Address Mask Value Calculations ............................................................................. 78
9.2
Chip Select/Wait Control Registers ................................................................................................................. 81
9.3
Application Example ....................................................................................................................................... 83
10. DMA Controller (DMAC)..................................................................................................................................... 84
10.1 Features............................................................................................................................................................ 84
10.2 Implementation ................................................................................................................................................ 85
10.2.1 On-Chip DMAC Interface....................................................................................................................... 85
10.2.2 DMAC Block.......................................................................................................................................... 86
10.2.3 Bus Snooping.......................................................................................................................................... 86
10.3 Register Description ........................................................................................................................................ 87
10.3.1 DMA Control Register (DCR) ................................................................................................................ 88
10.3.2 Channel Control Registers (CCRn)......................................................................................................... 89
10.3.3 Channel Status Registers (CSRn)............................................................................................................ 91
10.3.4 Source Address Registers (SARn) .......................................................................................................... 92
10.3.5 Destination Address Registers (DARn) .................................................................................................. 93
10.3.6 Byte Count Registers (BCRn) ................................................................................................................. 94
10.3.7 DMA Transfer Control Registers (DTCRn)............................................................................................ 95
10.3.8 Data Holding Register (DHR)................................................................................................................. 96
10.4 Operation ......................................................................................................................................................... 97
10.4.1 Overview................................................................................................................................................. 97
10.4.2 Transfer Request Generation ................................................................................................................ 100
10.4.3 DMA Address Modes ........................................................................................................................... 101
10.4.4 DMA Channel Operation ...................................................................................................................... 102
10.4.5 DMA Channel Priority.......................................................................................................................... 104
10.4.6 Interrupts............................................................................................................................................... 104
10.4.7 Data Packing and Unpacking ................................................................................................................ 105
10.5 DMA Transfer Timing................................................................................................................................... 106
10.5.1 Dual-Address Mode .............................................................................................................................. 106
10.6 Programming Example .................................................................................................................................. 108
11. 8-Bit Timers (TMRAs)........................................................................................................................................ 109
11.1 Block Diagrams ............................................................................................................................................. 110
11.2 Timer Components ........................................................................................................................................ 112
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TMP1941AF
11.2.1 Prescaler................................................................................................................................................ 112
11.2.2 Up-Counters (UC0 and UC1) ............................................................................................................... 113
11.2.3 Timer Registers (TA0REG and TA1REG) ........................................................................................... 113
11.2.4 Comparators (CP0 and CP1)................................................................................................................. 114
11.2.5 Timer Flip-Flop (TA1FF) ..................................................................................................................... 114
11.3 Register Description ...................................................................................................................................... 115
11.4 Operating Modes ........................................................................................................................................... 120
11.4.1 8-Bit Interval Timer Mode.................................................................................................................... 120
11.4.2 16-Bit Interval Timer Mode.................................................................................................................. 122
11.4.3 8-Bit Programmable Pulse Generation (PPG) Mode ............................................................................ 123
11.4.4 8-Bit PWM Generation Mode............................................................................................................... 125
11.4.5 Operating Mode Summary.................................................................................................................... 128
12. 16-Bit Timer/Event Counters (TMRBs).............................................................................................................. 129
12.1 Block Diagrams ............................................................................................................................................. 130
12.2 Timer Components ........................................................................................................................................ 134
12.2.1 Prescaler................................................................................................................................................ 134
12.2.2 Up-Counter (UC0) ................................................................................................................................ 135
12.2.3 Timer Registers (TB0RG0H/L and TB0RG1H/L)................................................................................ 135
12.2.4 Capture Registers (TB0CP0H/L and TB0CP1H/L) .............................................................................. 136
12.2.5 Capture Control Logic .......................................................................................................................... 137
12.2.6 Comparators (CP0 and CP1)................................................................................................................. 138
12.2.7 Timer Flip-Flop (TB0FF0).................................................................................................................... 138
12.3 Register Description ...................................................................................................................................... 139
12.4 Operating Modes ........................................................................................................................................... 149
12.4.1 16-Bit Interval Timer Mode .................................................................................................................. 149
12.4.2 16-Bit Event Counter Mode.................................................................................................................. 149
12.4.3 16-Bit Programmable Pulse Generation (PPG) Mode .......................................................................... 150
12.4.4 Timing and Measurement Functions Using the Capture Capability...................................................... 152
13. Serial I/O (SIO) ................................................................................................................................................... 157
13.1 Block Diagrams ............................................................................................................................................. 159
13.2 SIO Components............................................................................................................................................ 163
13.2.1 Prescaler................................................................................................................................................ 163
13.2.2 Baud Rate Generator............................................................................................................................. 164
13.2.3 Serial Clock Generator.......................................................................................................................... 167
13.2.4 Receive Counter.................................................................................................................................... 167
13.2.5 Receive Controller ................................................................................................................................ 167
13.2.6 Receive Buffer ...................................................................................................................................... 167
13.2.7 Transmit Counter .................................................................................................................................. 168
13.2.8 Transmit Controller............................................................................................................................... 168
13.2.9 Transmit Buffer..................................................................................................................................... 170
13.2.10 Parity Controller ................................................................................................................................... 170
13.2.11 Error Flags (UART mode only) ............................................................................................................ 170
13.2.12 Signal Generation Timing ..................................................................................................................... 171
13.3 Register Description ...................................................................................................................................... 172
13.4 Operating Modes ........................................................................................................................................... 186
13.4.1 Mode 0 (I/O Interface Mode)................................................................................................................ 186
13.4.2 Mode 1 (7-Bit UART Mode) ................................................................................................................ 189
13.4.3 Mode 2 (8-Bit UART Mode) ................................................................................................................ 190
13.4.4 Mode 3 (9-Bit UART Mode) ................................................................................................................ 190
14. Serial Bus Interface (SBI) ................................................................................................................................... 193
14.1 Block Diagram............................................................................................................................................... 193
14.2 Registers ........................................................................................................................................................ 194
14.3 I2C Bus Mode Data Formats.......................................................................................................................... 194
14.4 Description of the Registers Used in I2C Bus Mode...................................................................................... 195
14.5 I2C Bus Mode Configuration ......................................................................................................................... 199
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TMP1941AF
14.5.1 Acknowledgment Mode ........................................................................................................................ 199
14.5.2 Number of Bits Per Transfer................................................................................................................. 199
14.5.3 Serial Clock........................................................................................................................................... 199
14.5.4 Slave Addressing and Address Recognition Mode ............................................................................... 200
14.5.5 Configuring the SBI as a Master or a Slave .......................................................................................... 200
14.5.6 Configuring the SBI as a Transmitter or a Receiver ............................................................................. 201
14.5.7 Generating START and STOP Conditions ........................................................................................... 201
14.5.8 Asserting and Deasserting Interrupt Requests....................................................................................... 202
14.5.9 SBI Operating Modes ........................................................................................................................... 202
14.5.10 Lost-Arbitration Detection Monitor ...................................................................................................... 202
14.5.11 Slave Address Match Monitor .............................................................................................................. 203
14.5.12 General-Call Detection Monitor ........................................................................................................... 203
14.5.13 Last Received Bit Monitor.................................................................................................................... 203
14.5.14 Software Reset ...................................................................................................................................... 204
14.5.15 Serial Bus Interface Data Buffer Register (SBI0DBR)......................................................................... 204
14.5.16 I2C Bus Address Register (I2C0AR)..................................................................................................... 204
14.5.17 Baud Rate Register 1 (SBI0DBR1) ...................................................................................................... 204
14.5.18 Baud Rate Register 0 (SBI0BR0) ......................................................................................................... 204
14.6 Programming Sequences in I2C Bus Mode.................................................................................................... 205
14.6.1 SBI Initialization................................................................................................................................... 205
14.6.2 Generating a START Condition and a Slave Address .......................................................................... 205
14.6.3 Transferring a Data Word ..................................................................................................................... 206
14.6.4 Generating a STOP Condition .............................................................................................................. 210
14.6.5 Repeated START Condition ................................................................................................................. 211
14.7 Description of Registers Used in Clock-Synchronous 8-Bit SIO Mode ........................................................ 212
14.8 Clock-Synchronous 8-Bit SIO Mode Operation ............................................................................................ 214
14.8.1 Serial Clock........................................................................................................................................... 214
14.8.2 SIO Transfer Modes.............................................................................................................................. 216
15. Analog-to-Digital Converter (ADC).................................................................................................................... 221
15.1 Register Description ...................................................................................................................................... 222
15.2 Operation ....................................................................................................................................................... 227
15.2.1 Analog Reference Voltages................................................................................................................... 227
15.2.2 Selecting an Analog Input Channel (s).................................................................................................. 227
15.2.3 Starting an A/D Conversion .................................................................................................................. 227
15.2.4 Conversion Modes and Conversion-Done Interrupts ............................................................................ 228
15.2.5 Conversion Time................................................................................................................................... 229
15.2.6 Storing and Reading the A/D Conversion Result.................................................................................. 229
15.3 Programming Examples................................................................................................................................. 231
16. Watchdog Timer (WDT) ..................................................................................................................................... 232
16.1 Implementation .............................................................................................................................................. 232
16.2 Register Description ...................................................................................................................................... 234
16.2.1 Watchdog Timer Mode Register (WDMOD) ....................................................................................... 234
16.2.2 Watchdog Timer Control Register (WDCR) ........................................................................................ 234
16.3 Operation ....................................................................................................................................................... 236
17. Real-Time Clock (RTC) ...................................................................................................................................... 237
17.1 Implemention................................................................................................................................................. 237
18. Electrical Characteristics..................................................................................................................................... 239
18.1 Maximum Ratings.......................................................................................................................................... 239
18.2 DC Electrical Characteristics (1/2) ................................................................................................................ 240
18.3 DC Electrical Characteristics (2/2) ................................................................................................................ 241
18.4 AC Electrical Characteristics......................................................................................................................... 242
18.5 ADC Electrical Characteristics ...................................................................................................................... 248
18.6 SIO Timing .................................................................................................................................................... 249
18.6.1 I/O Interface Mode................................................................................................................................ 249
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TMP1941AF
18.7 SBI Timing .................................................................................................................................................... 250
18.7.1 I2C Mode............................................................................................................................................... 250
18.7.2 Clock-Synchronous 8-Bit SIO Mode .................................................................................................... 251
18.8 Event Counters (TA0IN, TA2IN, TB0IN0, TB0IN1, TB2IN0)..................................................................... 252
18.9 Timer Capture (TB0IN0, TB0IN1, TB1IN0, TB1IN1, TB2IN0, TB2IN1) .................................................. 252
18.10 General Interrupts .......................................................................................................................................... 252
18.11 NMI and STOP/SLEEP Wake-up Interrupts ................................................................................................ 252
18.12 SCOUT Pin.................................................................................................................................................... 252
18.13 Bus Request and Bus Acknowledge Signals.................................................................................................. 253
19. I/O Register Summary......................................................................................................................................... 254
19.1 I/O Ports ........................................................................................................................................................ 260
19.2 Interrupt Controller........................................................................................................................................ 262
19.3 Chip Select/Wait Controller .......................................................................................................................... 274
19.4 Clock Generator (CG) ................................................................................................................................... 278
19.5 DMA Controller (DMAC) ............................................................................................................................. 280
19.6 8-Bit Timers (TMRAs) .................................................................................................................................. 296
19.7 16-Bit Timer/Event Counters (TMRBs) ........................................................................................................ 297
19.8 Serial I/O (SIO) ............................................................................................................................................. 299
19.9 Serial Bus Interface (SBI).............................................................................................................................. 302
19.10 A/D Converter (ADC) ................................................................................................................................... 303
19.11 Watchdog Timer (WDT) ............................................................................................................................... 304
19.12 Real-Time Clock (RTC) ................................................................................................................................ 304
20.
I/O Port Equivalent-Circuit Diagrams................................................................................................................. 305
21. Notations, Precautions and Restrictions .............................................................................................................. 308
21.1 Notations and Terms...................................................................................................................................... 308
21.2 Precautions and Restrictions.......................................................................................................................... 308
v
TMP1941AF
vi
Handling Precautions
1 Using Toshiba Semiconductors Safely
1.
Using Toshiba Semiconductors Safely
TOSHIBA are continually working to improve the quality and the reliability of their products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in
which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily
injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind
the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
1
2 Safety Precautions
2.
Safety Precautions
This section lists important precautions which users of semiconductor devices (and anyone else)
should observe in order to avoid injury and damage to property, and to ensure safe and correct
use of devices.
Please be sure that you understand the meanings of the labels and the graphic symbol described
below before you move on to the detailed descriptions of the precautions.
[Explanation of labels]
Indicates an imminently hazardous situation which will result in death or
serious injury if you do not follow instructions.
Indicates a potentially hazardous situation which could result in death or
serious injury if you do not follow instructions.
Indicates a potentially hazardous situation which if not avoided, may
result in minor injury or moderate injury.
[Explanation of graphic symbol]
Graphic symbol
Meaning
Indicates that caution is required (laser beam is dangerous to eyes).
2
2 Safety Precautions
2.1
General Precautions regarding Semiconductor Devices
Do not use devices under conditions exceeding their absolute maximum ratings (e.g. current, voltage, power dissipation or
temperature).
This may cause the device to break down, degrade its performance, or cause it to catch fire or explode resulting in injury.
Do not insert devices in the wrong orientation.
Make sure that the positive and negative terminals of power supplies are connected correctly. Otherwise the rated maximum
current or power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it
to catch fire or explode and resulting in injury.
When power to a device is on, do not touch the device’s heat sink.
Heat sinks become hot, so you may burn your hand.
Do not touch the tips of device leads.
Because some types of device have leads with pointed tips, you may prick your finger.
When conducting any kind of evaluation, inspection or testing, be sure to connect the testing equipment’s electrodes or probes to
the pins of the device under test before powering it on.
Otherwise, you may receive an electric shock causing injury.
Before grounding an item of measuring equipment or a soldering iron, check that there is no electrical leakage from it.
Electrical leakage may cause the device which you are testing or soldering to break down, or could give you an electric shock.
Always wear protective glasses when cutting the leads of a device with clippers or a similar tool.
If you do not, small bits of metal flying off the cut ends may damage your eyes.
3
2 Safety Precautions
2.2
2.2.1
Precautions Specific to Each Product Group
Optical semiconductor devices
When a visible semiconductor laser is operating, do not look directly into the laser beam or look through the optical system.
This is highly likely to impair vision, and in the worst case may cause blindness.
If it is necessary to examine the laser apparatus, for example to inspect its optical characteristics, always wear the appropriate
type of laser protective glasses as stipulated by IEC standard IEC825-1.
Ensure that the current flowing in an LED device does not exceed the device’s maximum rated current.
This is particularly important for resin-packaged LED devices, as excessive current may cause the package resin to blow up,
scattering resin fragments and causing injury.
When testing the dielectric strength of a photocoupler, use testing equipment which can shut off the supply voltage to the
photocoupler. If you detect a leakage current of more than 100 µA, use the testing equipment to shut off the photocoupler’s
supply voltage; otherwise a large short-circuit current will flow continuously, and the device may break down or burst into
flames, resulting in fire or injury.
When incorporating a visible semiconductor laser into a design, use the device’s internal photodetector or a separate
photodetector to stabilize the laser’s radiant power so as to ensure that laser beams exceeding the laser’s rated radiant power
cannot be emitted.
If this stabilizing mechanism does not work and the rated radiant power is exceeded, the device may break down or the
excessively powerful laser beams may cause injury.
2.2.2
Power devices
Never touch a power device while it is powered on. Also, after turning off a power device, do not touch it until it has thoroughly
discharged all remaining electrical charge.
Touching a power device while it is powered on or still charged could cause a severe electric shock, resulting in death or serious
injury.
When conducting any kind of evaluation, inspection or testing, be sure to connect the testing equipment’s electrodes or probes to
the device under test before powering it on.
When you have finished, discharge any electrical charge remaining in the device.
Connecting the electrodes or probes of testing equipment to a device while it is powered on may result in electric shock, causing
injury.
4
2 Safety Precautions
Do not use devices under conditions which exceed their absolute maximum ratings (current, voltage, power dissipation,
temperature etc.).
This may cause the device to break down, causing a large short-circuit current to flow, which may in turn cause it to catch fire or
explode, resulting in fire or injury.
Use a unit which can detect short-circuit currents and which will shut off the power supply if a short-circuit occurs.
If the power supply is not shut off, a large short-circuit current will flow continuously, which may in turn cause the device to catch
fire or explode, resulting in fire or injury.
When designing a case for enclosing your system, consider how best to protect the user from shrapnel in the event of the device
catching fire or exploding.
Flying shrapnel can cause injury.
When conducting any kind of evaluation, inspection or testing, always use protective safety tools such as a cover for the device.
Otherwise you may sustain injury caused by the device catching fire or exploding.
Make sure that all metal casings in your design are grounded to earth.
Even in modules where a device’s electrodes and metal casing are insulated, capacitance in the module may cause the
electrostatic potential in the casing to rise.
Dielectric breakdown may cause a high voltage to be applied to the casing, causing electric shock and injury to anyone touching
it.
When designing the heat radiation and safety features of a system incorporating high-speed rectifiers, remember to take the
device’s forward and reverse losses into account.
The leakage current in these devices is greater than that in ordinary rectifiers; as a result, if a high-speed rectifier is used in an
extreme environment (e.g. at high temperature or high voltage), its reverse loss may increase, causing thermal runaway to occur.
This may in turn cause the device to explode and scatter shrapnel, resulting in injury to the user.
A design should ensure that, except when the main circuit of the device is active, reverse bias is applied to the device gate while
electricity is conducted to control circuits, so that the main circuit will become inactive.
Malfunction of the device may cause serious accidents or injuries.
When conducting any kind of evaluation, inspection or testing, either wear protective gloves or wait until the device has cooled
properly before handling it.
Devices become hot when they are operated. Even after the power has been turned off, the device will retain residual heat which
may cause a burn to anyone touching it.
2.2.3
Bipolar ICs (for use in automobiles)
If your design includes an inductive load such as a motor coil, incorporate diodes or similar devices into the design to prevent
negative current from flowing in.
The load current generated by powering the device on and off may cause it to function erratically or to break down, which could in
turn cause injury.
Ensure that the power supply to any device which incorporates protective functions is stable.
If the power supply is unstable, the device may operate erratically, preventing the protective functions from working correctly. If
protective functions fail, the device may break down causing injury to the user.
5
3 General Safety Precautions and Usage Considerations
3.
General Safety Precautions and Usage Considerations
This section is designed to help you gain a better understanding of semiconductor devices, so as
to ensure the safety, quality and reliability of the devices which you incorporate into your
designs.
3.1
3.1.1
From Incoming to Shipping
Electrostatic discharge (ESD)
When handling individual devices (which are not yet mounted on a printed
circuit board), be sure that the environment is protected against
electrostatic electricity. Operators should wear anti-static clothing, and
containers and other objects which come into direct contact with devices
should be made of anti-static materials and should be grounded to earth via
an 0.5- to 1.0-MΩ protective resistor.
Please follow the precautions described below; this is particularly important for devices which are
marked “Be careful of static.”.
(1) Work environment
• When humidity in the working environment decreases, the human body and other insulators
can easily become charged with static electricity due to friction. Maintain the recommended
humidity of 40% to 60% in the work environment, while also taking into account the fact that
moisture-proof-packed products may absorb moisture after unpacking.
• Be sure that all equipment, jigs and tools in the working area are grounded to earth.
• Place a conductive mat over the floor of the work area, or take other appropriate measures, so
that the floor surface is protected against static electricity and is grounded to earth. The
surface resistivity should be 104 to 108 Ω/sq and the resistance between surface and ground, 7.5
× 105 to 108 Ω
• Cover the workbench surface also with a conductive mat (with a surface resistivity of 104 to
108 Ω/sq, for a resistance between surface and ground of 7.5 × 105 to 108 Ω) . The purpose of this
is to disperse static electricity on the surface (through resistive components) and ground it to
earth. Workbench surfaces must not be constructed of low-resistance metallic materials that
allow rapid static discharge when a charged device touches them directly.
• Pay attention to the following points when using automatic equipment in your workplace:
(a) When picking up ICs with a vacuum unit, use a conductive rubber fitting on the end of the
pick-up wand to protect against electrostatic charge.
(b) Minimize friction on IC package surfaces. If some rubbing is unavoidable due to the
device’s mechanical structure, minimize the friction plane or use material with a small
friction coefficient and low electrical resistance. Also, consider the use of an ionizer.
(c) In sections which come into contact with device lead terminals, use a material which
dissipates static electricity.
(d) Ensure that no statically charged bodies (such as work clothes or the human body) touch
the devices.
6
3 General Safety Precautions and Usage Considerations
(e) Make sure that sections of the tape carrier which come into contact with installation
devices or other electrical machinery are made of a low-resistance material.
(f)
Make sure that jigs and tools used in the assembly process do not touch devices.
(g) In processes in which packages may retain an electrostatic charge, use an ionizer to
neutralize the ions.
• Make sure that CRT displays in the working area are protected against static charge, for
example by a VDT filter. As much as possible, avoid turning displays on and off. Doing so can
cause electrostatic induction in devices.
• Keep track of charged potential in the working area by taking periodic measurements.
• Ensure that work chairs are protected by an anti-static textile cover and are grounded to the
floor surface by a grounding chain. (Suggested resistance between the seat surface and
grounding chain is 7.5 × 105 to 1012Ω.)
• Install anti-static mats on storage shelf surfaces. (Suggested surface resistivity is 104 to 108
Ω/sq; suggested resistance between surface and ground is 7.5 × 105 to 108 Ω.)
• For transport and temporary storage of devices, use containers (boxes, jigs or bags) that are
made of anti-static materials or materials which dissipate electrostatic charge.
• Make sure that cart surfaces which come into contact with device packaging are made of
materials which will conduct static electricity, and verify that they are grounded to the floor
surface via a grounding chain.
• In any location where the level of static electricity is to be closely controlled, the ground
resistance level should be Class 3 or above. Use different ground wires for all items of
equipment which may come into physical contact with devices.
(2) Operating environment
• Operators must wear anti-static clothing and conductive shoes
(or a leg or heel strap).
• Operators must wear a wrist strap grounded to earth via a
resistor of about 1 MΩ.
• Soldering irons must be grounded from iron tip to earth, and must be used only at low voltages
(6 V to 24 V).
• If the tweezers you use are likely to touch the device terminals, use anti-static tweezers and in
particular avoid metallic tweezers. If a charged device touches a low-resistance tool, rapid
discharge can occur. When using vacuum tweezers, attach a conductive chucking pat to the tip,
and connect it to a dedicated ground used especially for anti-static purposes (suggested
resistance value: 104 to 108 Ω).
• Do not place devices or their containers near sources of strong electrical fields (such as above a
CRT).
7
3 General Safety Precautions and Usage Considerations
• When storing printed circuit boards which have devices mounted on them, use a board
container or bag that is protected against static charge. To avoid the occurrence of static charge
or discharge due to friction, keep the boards separate from one other and do not stack them
directly on top of one another.
• Ensure, if possible, that any articles (such as clipboards) which are brought to any location
where the level of static electricity must be closely controlled are constructed of anti-static
materials.
• In cases where the human body comes into direct contact with a device, be sure to wear antistatic finger covers or gloves (suggested resistance value: 108 Ω or less).
• Equipment safety covers installed near devices should have resistance ratings of 109 Ω or less.
• If a wrist strap cannot be used for some reason, and there is a possibility of imparting friction
to devices, use an ionizer.
• The transport film used in TCP products is manufactured from materials in which static
charges tend to build up. When using these products, install an ionizer to prevent the film from
being charged with static electricity. Also, ensure that no static electricity will be applied to the
product’s copper foils by taking measures to prevent static occuring in the peripheral
equipment.
3.1.2
Vibration, impact and stress
Handle devices and packaging materials with care. To avoid damage
to devices, do not toss or drop packages. Ensure that devices are not
subjected to mechanical vibration or shock during transportation.
Ceramic package devices and devices in canister-type packages which
have empty space inside them are subject to damage from vibration
and shock because the bonding wires are secured only at their ends.
Vibration
Plastic molded devices, on the other hand, have a relatively high level of resistance to vibration
and mechanical shock because their bonding wires are enveloped and fixed in resin. However,
when any device or package type is installed in target equipment, it is to some extent susceptible
to wiring disconnections and other damage from vibration, shock and stressed solder junctions.
Therefore when devices are incorporated into the design of equipment which will be subject to
vibration, the structural design of the equipment must be thought out carefully.
If a device is subjected to especially strong vibration, mechanical shock or stress, the package or
the chip itself may crack. In products such as CCDs which incorporate window glass, this could
cause surface flaws in the glass or cause the connection between the glass and the ceramic to
separate.
Furthermore, it is known that stress applied to a semiconductor device through the package
changes the resistance characteristics of the chip because of piezoelectric effects. In analog circuit
design attention must be paid to the problem of package stress as well as to the dangers of
vibration and shock as described above.
8
3 General Safety Precautions and Usage Considerations
3.2
3.2.1
Storage
General storage
• Avoid storage locations where devices will be exposed to moisture or direct sunlight.
• Follow the instructions printed on the device cartons regarding
transportation and storage.
• The storage area temperature should be kept within a
Humidity:
Temperature:
temperature range of 5°C to 35°C, and relative humidity
should be maintained at between 45% and 75%.
• Do not store devices in the presence of harmful (especially
corrosive) gases, or in dusty conditions.
@@
• Use storage areas where there is minimal temperature fluctuation. Rapid temperature changes
can cause moisture to form on stored devices, resulting in lead oxidation or corrosion. As a
result, the solderability of the leads will be degraded.
• When repacking devices, use anti-static containers.
• Do not allow external forces or loads to be applied to devices while they are in storage.
• If devices have been stored for more than two years, their electrical characteristics should be
tested and their leads should be tested for ease of soldering before they are used.
3.2.2
Moisture-proof packing
Moisture-proof packing should be handled with care. The handling
procedure specified for each packing type should be followed scrupulously.
If the proper procedures are not followed, the quality and reliability of
devices may be degraded. This section describes general precautions for
handling moisture-proof packing. Since the details may differ from device
to device, refer also to the relevant individual datasheets or databook.
(1) General precautions
Follow the instructions printed on the device cartons regarding transportation and storage.
• Do not drop or toss device packing. The laminated aluminum material in it can be rendered
ineffective by rough handling.
• The storage area temperature should be kept within a temperature range of 5°C to 30°C, and
relative humidity should be maintained at 90% (max). Use devices within 12 months of the
date marked on the package seal.
9
3 General Safety Precautions and Usage Considerations
• If the 12-month storage period has expired, or if the 30% humidity indicator shown in Figure 1
is pink when the packing is opened, it may be advisable, depending on the device and packing
type, to back the devices at high temperature to remove any moisture. Please refer to the table
below. After the pack has been opened, use the devices in a 5°C to 30°C. 60% RH environment
and within the effective usage period listed on the moisture-proof package. If the effective
usage period has expired, or if the packing has been stored in a high-humidity environment,
bake the devices at high temperature.
Packing
Moisture removal
Tray
If the packing bears the “Heatproof” marking or indicates the maximum temperature which it can
withstand, bake at 125°C for 20 hours. (Some devices require a different procedure.)
Tube
Transfer devices to trays bearing the “Heatproof” marking or indicating the temperature which
they can withstand, or to aluminum tubes before baking at 125°C for 20 hours.
Tape
Deviced packed on tape cannot be baked and must be used within the effective usage period
after unpacking, as specified on the packing.
• When baking devices, protect the devices from static electricity.
• Moisture indicators can detect the approximate humidity level at a standard temperature of
25°C. 6-point indicators and 3-point indicators are currently in use, but eventually all
indicators will be 3-point indicators.
HUMIDITY INDICATOR
60%
50%
30%
20%
10%
HUMIDITY INDICATOR
40
30
DANGER IF PINK
DANGER IF PINK
CHANGE DESICCANT
40%
20
READ AT LAVENDER
BETWEEN PINK & BLUE
READ AT LAVENDER
BETWEEN PINK & BLUE
(a) 6-point indicator
(b) 3-point indicator
Figure 1 Humidity indicator
10
3 General Safety Precautions and Usage Considerations
3.3
Design
Care must be exercised in the design of electronic equipment to achieve the desired reliability. It
is important not only to adhere to specifications concerning absolute maximum ratings and
recommended operating conditions, it is also important to consider the overall environment in
which equipment will be used, including factors such as the ambient temperature, transient
noise and voltage and current surges, as well as mounting conditions which affect device
reliability. This section describes some general precautions which you should observe when
designing circuits and when mounting devices on printed circuit boards.
For more detailed information about each product family, refer to the relevant individual
technical datasheets available from Toshiba.
3.3.1
Absolute maximum ratings
Do not use devices under conditions in which their absolute maximum
ratings (e.g. current, voltage, power dissipation or temperature) will be
exceeded. A device may break down or its performance may be degraded,
causing it to catch fire or explode resulting in injury to the user.
The absolute maximum ratings are rated values which must not be
exceeded during operation, even for an instant. Although absolute
maximum ratings differ from product to product, they essentially
concern the voltage and current at each pin, the allowable power
dissipation, and the junction and storage temperatures.
If the voltage or current on any pin exceeds the absolute maximum
rating, the device’s internal circuitry can become degraded. In the worst case, heat generated in
internal circuitry can fuse wiring or cause the semiconductor chip to break down.
If storage or operating temperatures exceed rated values, the package seal can deteriorate or the
wires can become disconnected due to the differences between the thermal expansion coefficients
of the materials from which the device is constructed.
3.3.2
Recommended operating conditions
The recommended operating conditions for each device are those necessary to guarantee that the
device will operate as specified in the datasheet.
If greater reliability is required, derate the device’s absolute maximum ratings for voltage,
current, power and temperature before using it.
3.3.3
Derating
When incorporating a device into your design, reduce its rated absolute maximum voltage,
current, power dissipation and operating temperature in order to ensure high reliability.
Since derating differs from application to application, refer to the technical datasheets available
for the various devices used in your design.
3.3.4
Unused pins
If unused pins are left open, some devices can exhibit input instability problems, resulting in
malfunctions such as abrupt increase in current flow. Similarly, if the unused output pins on a
device are connected to the power supply pin, the ground pin or to other output pins, the IC may
malfunction or break down.
Since the details regarding the handling of unused pins differ from device to device and from pin
11
3 General Safety Precautions and Usage Considerations
to pin, please follow the instructions given in the relevant individual datasheets or databook.
CMOS logic IC inputs, for example, have extremely high impedance. If an input pin is left open,
it can easily pick up extraneous noise and become unstable. In this case, if the input voltage level
reaches an intermediate level, it is possible that both the P-channel and N-channel transistors
will be turned on, allowing unwanted supply current to flow. Therefore, ensure that the unused
input pins of a device are connected to the power supply (Vcc) pin or ground (GND) pin of the
same device. For details of what to do with the pins of heat sinks, refer to the relevant technical
datasheet and databook.
3.3.5
Latch-up
Latch-up is an abnormal condition inherent in CMOS devices, in which Vcc gets shorted to
ground. This happens when a parasitic PN-PN junction (thyristor structure) internal to the
CMOS chip is turned on, causing a large current of the order of several hundred mA or more to
flow between Vcc and GND, eventually causing the device to break down.
Latch-up occurs when the input or output voltage exceeds the rated value, causing a large
current to flow in the internal chip, or when the voltage on the Vcc (Vdd) pin exceeds its rated
value, forcing the internal chip into a breakdown condition. Once the chip falls into the latch-up
state, even though the excess voltage may have been applied only for an instant, the large
current continues to flow between Vcc (Vdd) and GND (Vss). This causes the device to heat up
and, in extreme cases, to emit gas fumes as well. To avoid this problem, observe the following
precautions:
(1) Do not allow voltage levels on the input and output pins either to rise above Vcc (Vdd) or to
fall below GND (Vss). Also, follow any prescribed power-on sequence, so that power is applied
gradually or in steps rather than abruptly.
(2) Do not allow any abnormal noise signals to be applied to the device.
(3) Set the voltage levels of unused input pins to Vcc (Vdd) or GND (Vss).
(4) Do not connect output pins to one another.
3.3.6
Input/Output protection
Wired-AND configurations, in which outputs are connected together, cannot be used, since this
short-circuits the outputs. Outputs should, of course, never be connected to Vcc (Vdd) or GND
(Vss).
Furthermore, ICs with tri-state outputs can undergo performance degradation if a shorted output
current is allowed to flow for an extended period of time. Therefore, when designing circuits,
make sure that tri-state outputs will not be enabled simultaneously.
3.3.7
Load capacitance
Some devices display increased delay times if the load capacitance is large. Also, large charging
and discharging currents will flow in the device, causing noise. Furthermore, since outputs are
shorted for a relatively long time, wiring can become fused.
Consult the technical information for the device being used to determine the recommended load
capacitance.
12
3 General Safety Precautions and Usage Considerations
3.3.8
Thermal design
The failure rate of semiconductor devices is greatly increased as operating temperatures
increase. As shown in Figure 2, the internal thermal stress on a device is the sum of the ambient
temperature and the temperature rise due to power dissipation in the device. Therefore, to
achieve optimum reliability, observe the following precautions concerning thermal design:
(1) Keep the ambient temperature (Ta) as low as possible.
(2) If the device’s dynamic power dissipation is relatively large, select the most appropriate
circuit board material, and consider the use of heat sinks or of forced air cooling. Such
measures will help lower the thermal resistance of the package.
(3) Derate the device’s absolute maximum ratings to minimize thermal stress from power
dissipation.
θja = θjc + θca
θja = (Tj–Ta) / P
θjc = (Tj–Tc) / P
θca = (Tc–Ta) / P
in which θja = thermal resistance between junction and surrounding air (°C/W)
θjc = thermal resistance between junction and package surface, or internal thermal
resistance (°C/W)
θca = thermal resistance between package surface and surrounding air, or external
thermal resistance (°C/W)
Tj = junction temperature or chip temperature (°C)
Tc = package surface temperature or case temperature (°C)
Ta = ambient temperature (°C)
P = power dissipation (W)
Ta
θca
Tc
θjc
Tj
Figure 2 Thermal resistance of package
3.3.9
Interfacing
When connecting inputs and outputs between devices, make sure input voltage (VIL/VIH) and
output voltage (VOL/VOH) levels are matched. Otherwise, the devices may malfunction. When
connecting devices operating at different supply voltages, such as in a dual-power-supply system,
be aware that erroneous power-on and power-off sequences can result in device breakdown. For
details of how to interface particular devices, consult the relevant technical datasheets and
databooks. If you have any questions or doubts about interfacing, contact your nearest Toshiba
office or distributor.
13
3 General Safety Precautions and Usage Considerations
3.3.10
Decoupling
Spike currents generated during switching can cause Vcc (Vdd) and GND (Vss) voltage levels to
fluctuate, causing ringing in the output waveform or a delay in response speed. (The power
supply and GND wiring impedance is normally 50 Ω to 100 Ω.) For this reason, the impedance of
power supply lines with respect to high frequencies must be kept low. This can be accomplished
by using thick and short wiring for the Vcc (Vdd) and GND (Vss) lines and by installing
decoupling capacitors (of approximately 0.01 µF to 1 µF capacitance) as high-frequency filters
between Vcc (Vdd) and GND (Vss) at strategic locations on the printed circuit board.
For low-frequency filtering, it is a good idea to install a 10- to 100-µF capacitor on the printed
circuit board (one capacitor will suffice). If the capacitance is excessively large, however, (e.g.
several thousand µF) latch-up can be a problem. Be sure to choose an appropriate capacitance
value.
An important point about wiring is that, in the case of high-speed logic ICs, noise is caused
mainly by reflection and crosstalk, or by the power supply impedance. Reflections cause
increased signal delay, ringing, overshoot and undershoot, thereby reducing the device’s safety
margins with respect to noise. To prevent reflections, reduce the wiring length by increasing the
device mounting density so as to lower the inductance (L) and capacitance (C) in the wiring.
Extreme care must be taken, however, when taking this corrective measure, since it tends to
cause crosstalk between the wires. In practice, there must be a trade-off between these two
factors.
3.3.11
External noise
Printed circuit boards with long I/O or signal pattern lines
are vulnerable to induced noise or surges from outside
sources. Consequently, malfunctions or breakdowns can
result from overcurrent or overvoltage, depending on the
types of device used. To protect against noise, lower the
impedance of the pattern line or insert a noise-canceling
circuit. Protective measures must also be taken against
surges.
Input/Output
Signals
For details of the appropriate protective measures for a particular device, consult the relevant
databook.
3.3.12
Electromagnetic interference
Widespread use of electrical and electronic equipment in recent years has brought with it radio
and TV reception problems due to electromagnetic interference. To use the radio spectrum
effectively and to maintain radio communications quality, each country has formulated
regulations limiting the amount of electromagnetic interference which can be generated by
individual products.
Electromagnetic interference includes conduction noise propagated through power supply and
telephone lines, and noise from direct electromagnetic waves radiated by equipment. Different
measurement methods and corrective measures are used to assess and counteract each specific
type of noise.
Difficulties in controlling electromagnetic interference derive from the fact that there is no
method available which allows designers to calculate, at the design stage, the strength of the
electromagnetic waves which will emanate from each component in a piece of equipment. For this
reason, it is only after the prototype equipment has been completed that the designer can take
measurements using a dedicated instrument to determine the strength of electromagnetic
interference waves. Yet it is possible during system design to incorporate some measures for the
14
3 General Safety Precautions and Usage Considerations
prevention of electromagnetic interference, which can facilitate taking corrective measures once
the design has been completed. These include installing shields and noise filters, and increasing
the thickness of the power supply wiring patterns on the printed circuit board. One effective
method, for example, is to devise several shielding options during design, and then select the
most suitable shielding method based on the results of measurements taken after the prototype
has been completed.
3.3.13
Peripheral circuits
In most cases semiconductor devices are used with peripheral circuits and components. The input
and output signal voltages and currents in these circuits must be chosen to match the
semiconductor device’s specifications. The following factors must be taken into account.
(1) Inappropriate voltages or currents applied to a device’s input pins may cause it to operate
erratically. Some devices contain pull-up or pull-down resistors. When designing your
system, remember to take the effect of this on the voltage and current levels into account.
(2) The output pins on a device have a predetermined external circuit drive capability. If this
drive capability is greater than that required, either incorporate a compensating circuit into
your design or carefully select suitable components for use in external circuits.
3.3.14
Safety standards
Each country has safety standards which must be observed. These safety standards include
requirements for quality assurance systems and design of device insulation. Such requirements
must be fully taken into account to ensure that your design conforms to the applicable safety
standards.
3.3.15
Other precautions
(1) When designing a system, be sure to incorporate fail-safe and other appropriate measures
according to the intended purpose of your system. Also, be sure to debug your system under
actual board-mounted conditions.
(2) If a plastic-package device is placed in a strong electric field, surface leakage may occur due
to the charge-up phenomenon, resulting in device malfunction. In such cases take
appropriate measures to prevent this problem, for example by protecting the package surface
with a conductive shield.
(3) With some microcomputers and MOS memory devices, caution is required when powering on
or resetting the device. To ensure that your design does not violate device specifications,
consult the relevant databook for each constituent device.
(4) Ensure that no conductive material or object (such as a metal pin) can drop onto and short
the leads of a device mounted on a printed circuit board.
3.4
3.4.1
Inspection, Testing and Evaluation
Grounding
Ground all measuring instruments, jigs, tools and soldering irons to earth.
Electrical leakage may cause a device to break down or may result in electric
shock.
15
3 General Safety Precautions and Usage Considerations
3.4.2
Inspection Sequence
c Do not insert devices in the wrong orientation. Make sure that the positive
and negative electrodes of the power supply are correctly connected.
Otherwise, the rated maximum current or maximum power dissipation
may be exceeded and the device may break down or undergo performance
degradation, causing it to catch fire or explode, resulting in injury to the
user.
d When conducting any kind of evaluation, inspection or testing using AC
power with a peak voltage of 42.4 V or DC power exceeding 60 V, be sure
to connect the electrodes or probes of the testing equipment to the device
under test before powering it on. Connecting the electrodes or probes of
testing equipment to a device while it is powered on may result in electric
shock, causing injury.
(1) Apply voltage to the test jig only after inserting the device securely into it. When applying or
removing power, observe the relevant precautions, if any.
(2) Make sure that the voltage applied to the device is off before removing the device from the
test jig. Otherwise, the device may undergo performance degradation or be destroyed.
(3) Make sure that no surge voltages from the measuring equipment are applied to the device.
(4) The chips housed in tape carrier packages (TCPs) are bare chips and are therefore exposed.
During inspection take care not to crack the chip or cause any flaws in it.
Electrical contact may also cause a chip to become faulty. Therefore make sure that nothing
comes into electrical contact with the chip.
3.5
Mounting
There are essentially two main types of semiconductor device package: lead insertion and surface
mount. During mounting on printed circuit boards, devices can become contaminated by flux or
damaged by thermal stress from the soldering process. With surface-mount devices in particular,
the most significant problem is thermal stress from solder reflow, when the entire package is
subjected to heat. This section describes a recommended temperature profile for each mounting
method, as well as general precautions which you should take when mounting devices on printed
circuit boards. Note, however, that even for devices with the same package type, the appropriate
mounting method varies according to the size of the chip and the size and shape of the lead
frame. Therefore, please consult the relevant technical datasheet and databook.
3.5.1
Lead forming
c Always wear protective glasses when cutting the leads of a device with
clippers or a similar tool. If you do not, small bits of metal flying off the cut
ends may damage your eyes.
d Do not touch the tips of device leads. Because some types of device have
leads with pointed tips, you may prick your finger.
Semiconductor devices must undergo a process in which the leads are cut and formed before the
devices can be mounted on a printed circuit board. If undue stress is applied to the interior of a
device during this process, mechanical breakdown or performance degradation can result. This is
attributable primarily to differences between the stress on the device’s external leads and the
stress on the internal leads. If the relative difference is great enough, the device’s internal leads,
adhesive properties or sealant can be damaged. Observe these precautions during the leadforming process (this does not apply to surface-mount devices):
16
3 General Safety Precautions and Usage Considerations
(1) Lead insertion hole intervals on the printed circuit board should match the lead pitch of the
device precisely.
(2) If lead insertion hole intervals on the printed circuit board do not precisely match the lead
pitch of the device, do not attempt to forcibly insert devices by pressing on them or by pulling
on their leads.
(3) For the minimum clearance specification between a device and a
printed circuit board, refer to the relevant device’s datasheet and
databook. If necessary, achieve the required clearance by forming
the device’s leads appropriately. Do not use the spacers which are
used to raise devices above the surface of the printed circuit board
during soldering to achieve clearance. These spacers normally
continue to expand due to heat, even after the solder has begun to solidify; this applies
severe stress to the device.
(4) Observe the following precautions when forming the leads of a device prior to mounting.
• Use a tool or jig to secure the lead at its base (where the lead meets the device package) while
bending so as to avoid mechanical stress to the device. Also avoid bending or stretching device
leads repeatedly.
• Be careful not to damage the lead during lead forming.
• Follow any other precautions described in the individual datasheets and databooks for each
device and package type.
3.5.2
Socket mounting
(1) When socket mounting devices on a printed circuit board, use sockets which match the
inserted device’s package.
(2) Use sockets whose contacts have the appropriate contact pressure. If the contact pressure is
insufficient, the socket may not make a perfect contact when the device is repeatedly
inserted and removed; if the pressure is excessively high, the device leads may be bent or
damaged when they are inserted into or removed from the socket.
(3) When soldering sockets to the printed circuit board, use sockets whose construction prevents
flux from penetrating into the contacts or which allows flux to be completely cleaned off.
(4) Make sure the coating agent applied to the printed circuit board for moisture-proofing
purposes does not stick to the socket contacts.
(5) If the device leads are severely bent by a socket as it is inserted or removed and you wish to
repair the leads so as to continue using the device, make sure that this lead correction is only
performed once. Do not use devices whose leads have been corrected more than once.
(6) If the printed circuit board with the devices mounted on it will be subjected to vibration from
external sources, use sockets which have a strong contact pressure so as to prevent the
sockets and devices from vibrating relative to one another.
3.5.3
Soldering temperature profile
The soldering temperature and heating time vary from device to device. Therefore, when
specifying the mounting conditions, refer to the individual datasheets and databooks for the
devices used.
17
3 General Safety Precautions and Usage Considerations
(1) Using a soldering iron
Complete soldering within ten seconds for lead temperatures of up to 260°C, or within three
seconds for lead temperatures of up to 350°C.
(2) Using medium infrared ray reflow
• Heating top and bottom with long or medium infrared rays is recommended (see Figure 3).
Medium infrared ray heater
(reflow)
Product flow
Long infrared ray heater (preheating)
Figure 3 Heating top and bottom with long or medium infrared rays
• Complete the infrared ray reflow process within 30 seconds at a package surface temperature
of between 210°C and 240°C.
• Refer to Figure 4 for an example of a good temperature profile for infrared or hot air reflow.
Package surface temperature
(°C)
240
210
160
140
60-120
seconds
30
seconds
or less
Time (in seconds)
Figure 4 Sample temperature profile for infrared or hot air reflow
(3) Using hot air reflow
• Complete hot air reflow within 30 seconds at a package surface temperature of between 210°C
and 240°C.
• For an example of a recommended temperature profile, refer to Figure 4 above.
(4) Using solder flow
• Apply preheating for 60 to 120 seconds at a temperature of 150°C.
• For lead insertion-type packages, complete solder flow within 10 seconds with the
temperature at the stopper (or, if there is no stopper, at a location more than 1.5 mm from
the body) which does not exceed 260°C.
• For surface-mount packages, complete soldering within 5 seconds at a temperature of 250°C or
18
3 General Safety Precautions and Usage Considerations
less in order to prevent thermal stress in the device.
• Figure 5 shows an example of a recommended temperature profile for surface-mount packages
using solder flow.
Package surface temperature
(°C)
250
160
140
60-120 seconds
5 seconds
or less
Time (in seconds)
Figure 5 Sample temperature profile for solder flow
3.5.4
Flux cleaning and ultrasonic cleaning
(1) When cleaning circuit boards to remove flux, make sure that no residual reactive ions such
as Na or Cl remain. Note that organic solvents react with water to generate hydrogen
chloride and other corrosive gases which can degrade device performance.
(2) Washing devices with water will not cause any problems. However, make sure that no
reactive ions such as sodium and chlorine are left as a residue. Also, be sure to dry devices
sufficiently after washing.
(3) Do not rub device markings with a brush or with your hand during cleaning or while the
devices are still wet from the cleaning agent. Doing so can rub off the markings.
(4) The dip cleaning, shower cleaning and steam cleaning processes all involve the chemical
action of a solvent. Use only recommended solvents for these cleaning methods. When
immersing devices in a solvent or steam bath, make sure that the temperature of the liquid
is 50°C or below, and that the circuit board is removed from the bath within one minute.
(5) Ultrasonic cleaning should not be used with hermetically-sealed ceramic packages such as a
leadless chip carrier (LCC), pin grid array (PGA) or charge-coupled device (CCD), because
the bonding wires can become disconnected due to resonance during the cleaning process.
Even if a device package allows ultrasonic cleaning, limit the duration of ultrasonic cleaning
to as short a time as possible, since long hours of ultrasonic cleaning degrade the adhesion
between the mold resin and the frame material. The following ultrasonic cleaning conditions
are recommended:
Frequency: 27 kHz ∼ 29 kHz
Ultrasonic output power: 300 W or less (0.25 W/cm2 or less)
Cleaning time: 30 seconds or less
Suspend the circuit board in the solvent bath during ultrasonic cleaning in such a way that
the ultrasonic vibrator does not come into direct contact with the circuit board or the device.
19
3 General Safety Precautions and Usage Considerations
3.5.5
No cleaning
If analog devices or high-speed devices are used without being cleaned, flux residues may cause
minute amounts of leakage between pins. Similarly, dew condensation, which occurs in
environments containing residual chlorine when power to the device is on, may cause betweenlead leakage or migration. Therefore, Toshiba recommends that these devices be cleaned.
However, if the flux used contains only a small amount of halogen (0.05W% or less), the devices
may be used without cleaning without any problems.
3.5.6
Mounting tape carrier packages (TCPs)
(1) When tape carrier packages (TCPs) are mounted, measures must be taken to prevent
electrostatic breakdown of the devices.
(2) If devices are being picked up from tape, or outer lead bonding (OLB) mounting is being
carried out, consult the manufacturer of the insertion machine which is being used, in order
to establish the optimum mounting conditions in advance and to avoid any possible hazards.
(3) The base film, which is made of polyimide, is hard and thin. Be careful not to cut or scratch
your hands or any objects while handling the tape.
(4) When punching tape, try not to scatter broken pieces of tape too much.
(5) Treat the extra film, reels and spacers left after punching as industrial waste, taking care
not to destroy or pollute the environment.
(6) Chips housed in tape carrier packages (TCPs) are bare chips and therefore have their reverse
side exposed. To ensure that the chip will not be cracked during mounting, ensure that no
mechanical shock is applied to the reverse side of the chip. Electrical contact may also cause
a chip to fail. Therefore, when mounting devices, make sure that nothing comes into
electrical contact with the reverse side of the chip.
If your design requires connecting the reverse side of the chip to the circuit board, please
consult Toshiba or a Toshiba distributor beforehand.
3.5.7
Mounting chips
Devices delivered in chip form tend to degrade or break under external forces much more easily
than plastic-packaged devices. Therefore, caution is required when handling this type of device.
(1) Mount devices in a properly prepared environment so that chip surfaces will not be exposed
to polluted ambient air or other polluted substances.
(2) When handling chips, be careful not to expose them to static electricity.
In particular, measures must be taken to prevent static damage during the mounting of
chips. With this in mind, Toshiba recommend mounting all peripheral parts first and then
mounting chips last (after all other components have been mounted).
(3) Make sure that PCBs (or any other kind of circuit board) on which chips are being mounted
do not have any chemical residues on them (such as the chemicals which were used for
etching the PCBs).
(4) When mounting chips on a board, use the method of assembly that is most suitable for
maintaining the appropriate electrical, thermal and mechanical properties of the
semiconductor devices used.
* For details of devices in chip form, refer to the relevant device’s individual datasheets.
20
3 General Safety Precautions and Usage Considerations
3.5.8
Circuit board coating
When devices are to be used in equipment requiring a high degree of reliability or in extreme
environments (where moisture, corrosive gas or dust is present), circuit boards may be coated for
protection. However, before doing so, you must carefully consider the possible stress and
contamination effects that may result and then choose the coating resin which results in the
minimum level of stress to the device.
3.5.9
Heat sinks
(1) When attaching a heat sink to a device, be careful not to apply excessive force to the device in
the process.
(2) When attaching a device to a heat sink by fixing it at two or more locations, evenly tighten
all the screws in stages (i.e. do not fully tighten one screw while the rest are still only loosely
tightened). Finally, fully tighten all the screws up to the specified torque.
(3) Drill holes for screws in the heat sink exactly as specified. Smooth the
surface by removing burrs and protrusions or indentations which might
interfere with the installation of any part of the device.
(4) A coating of silicone compound can be applied between the heat sink and
the device to improve heat conductivity. Be sure to apply the coating
thinly and evenly; do not use too much. Also, be sure to use a non-volatile
compound, as volatile compounds can crack after a time, causing the
heat radiation properties of the heat sink to deteriorate.
(5) If the device is housed in a plastic package, use caution when selecting the type of silicone
compound to be applied between the heat sink and the device. With some types, the base oil
separates and penetrates the plastic package, significantly reducing the useful life of the
device.
Two recommended silicone compounds in which base oil separation is not a problem are
YG6260 from Toshiba Silicone.
(6) Heat-sink-equipped devices can become very hot during operation. Do not touch them, or you
may sustain a burn.
3.5.10
Tightening torque
(1) Make sure the screws are tightened with fastening torques not exceeding the torque values
stipulated in individual datasheets and databooks for the devices used.
(2) Do not allow a power screwdriver (electrical or air-driven) to touch devices.
3.5.11
Repeated device mounting and usage
Do not remount or re-use devices which fall into the categories listed below; these devices may
cause significant problems relating to performance and reliability.
(1) Devices which have been removed from the board after soldering
(2) Devices which have been inserted in the wrong orientation or which have had reverse
current applied
(3) Devices which have undergone lead forming more than once
21
3 General Safety Precautions and Usage Considerations
3.6
3.6.1
Protecting Devices in the Field
Temperature
Semiconductor devices are generally more sensitive to temperature than are other electronic
components. The various electrical characteristics of a semiconductor device are dependent on the
ambient temperature at which the device is used. It is therefore necessary to understand the
temperature characteristics of a device and to incorporate device derating into circuit design.
Note also that if a device is used above its maximum temperature rating, device deterioration is
more rapid and it will reach the end of its usable life sooner than expected.
3.6.2
Humidity
Resin-molded devices are sometimes improperly sealed. When these devices are used for an
extended period of time in a high-humidity environment, moisture can penetrate into the device
and cause chip degradation or malfunction. Furthermore, when devices are mounted on a regular
printed circuit board, the impedance between wiring components can decrease under highhumidity conditions. In systems which require a high signal-source impedance, circuit board
leakage or leakage between device lead pins can cause malfunctions. The application of a
moisture-proof treatment to the device surface should be considered in this case. On the other
hand, operation under low-humidity conditions can damage a device due to the occurrence of
electrostatic discharge. Unless damp-proofing measures have been specifically taken, use devices
only in environments with appropriate ambient moisture levels (i.e. within a relative humidity
range of 40% to 60%).
3.6.3
Corrosive gases
Corrosive gases can cause chemical reactions in devices, degrading device characteristics.
For example, sulphur-bearing corrosive gases emanating from rubber placed near a device
(accompanied by condensation under high-humidity conditions) can corrode a device’s leads. The
resulting chemical reaction between leads forms foreign particles which can cause electrical
leakage.
3.6.4
Radioactive and cosmic rays
Most industrial and consumer semiconductor devices are not designed with protection against
radioactive and cosmic rays. Devices used in aerospace equipment or in radioactive environments
must therefore be shielded.
3.6.5
Strong electrical and magnetic fields
Devices exposed to strong magnetic fields can undergo a polarization phenomenon in their plastic
material, or within the chip, which gives rise to abnormal symptoms such as impedance changes
or increased leakage current. Failures have been reported in LSIs mounted near malfunctioning
deflection yokes in TV sets. In such cases the device’s installation location must be changed or
the device must be shielded against the electrical or magnetic field. Shielding against magnetism
is especially necessary for devices used in an alternating magnetic field because of the
electromotive forces generated in this type of environment.
22
3 General Safety Precautions and Usage Considerations
3.6.6
Interference from light (ultraviolet rays, sunlight, fluorescent lamps and
incandescent lamps)
Light striking a semiconductor device generates electromotive force due to photoelectric effects.
In some cases the device can malfunction. This is especially true for devices in which the internal
chip is exposed. When designing circuits, make sure that devices are protected against incident
light from external sources. This problem is not limited to optical semiconductors and EPROMs.
All types of device can be affected by light.
3.6.7
Dust and oil
Just like corrosive gases, dust and oil can cause chemical reactions in devices, which will
adversely affect a device’s electrical characteristics. To avoid this problem, do not use devices in
dusty or oily environments. This is especially important for optical devices because dust and oil
can affect a device’s optical characteristics as well as its physical integrity and the electrical
performance factors mentioned above.
3.6.8
Fire
Semiconductor devices are combustible; they can emit smoke and catch fire if heated sufficiently.
When this happens, some devices may generate poisonous gases. Devices should therefore never
be used in close proximity to an open flame or a heat-generating body, or near flammable or
combustible materials.
3.7
Disposal of Devices and Packing Materials
When discarding unused devices and packing materials, follow all procedures specified by local
regulations in order to protect the environment against contamination.
23
4 Precautions and Usage Considerations Specific to Each Product Group
4.
Precautions and Usage Considerations Specific to Each
Product Group
This section describes matters specific to each product group which need to be taken into
consideration when using devices. If the same item is described in Sections 3 and 4, the
description in Section 4 takes precedence.
4.1
4.1.1
Microcontrollers
Design
(1) Using resonators which are not specifically recommended for use
Resonators recommended for use with Toshiba products in microcontroller oscillator applications
are listed in Toshiba databooks along with information about oscillation conditions. If you use a
resonator not included in this list, please consult Toshiba or the resonator manufacturer
concerning the suitability of the device for your application.
(2) Undefined functions
In some microcontrollers certain instruction code values do not constitute valid processor
instructions. Also, it is possible that the values of bits in registers will become undefined. Take
care in your applications not to use invalid instructions or to let register bit values become
undefined.
(3) Scratch and puncture wounds by the point of a probe
The tips of probes and adaptors used in development tools are individually designed to be
compatible with particular devices. Probes for some devices have sharp points. When you handle
them bare-handed, take care not to suffer a scratch or puncture wound.
24
4 Precautions and Usage Considerations Specific to Each Product Group
4.1.2
Reliability predictions for microcontroller devices
For microcontroller devices, the following junction temperature range is used for reliability
predictions:
Tj = 0°C ∼ 85°C
An estimation of the chip junction temperature, Tj, can be obtained from the equation:
Tj = Ta + Q ×➨ja
where:
Ta =
ambient temperature (°C)
The assumption is that the ambient temperature is not affected by any heat
transfers from the device.
Q = chip’s average power dissipation (W)
➨ja = package thermal resistance (°C/W)
Note 1: If you use a microcontroller device outside the 0 to 85°C range for long periods of time, contact
your nearest Toshiba office or authorized Toshiba dealer.
Note 2: For the ➨ja value, contact your nearest Toshiba office or authorized Toshiba dealer.
25
4 Precautions and Usage Considerations Specific to Each Product Group
26
TMP1941AF
TMP1941AF
32-Bit RISC Microprocessor TX19 Family
TMP1941AF
1.
Features
The TX19 is a family of high-performance 32-bit microprocessors that offers the speed of a 32-bit RISC
solution with the added advantage of a significantly reduced code size of a 16-bit architecture. The instruction
set of the TX19 includes as a subset the 32-bit instructions of the TX39, which is based on the MIPS R3000ATM
architecture. Additionally, the TX19 supports the MIPS16 Application-Specific Extensions (ASE) for improved
code density.
The TMP1941 is built on a TX19 core processor and a selection of intelligent peripherals. The TMP1941 is
suitable for low-voltage, low-power applications.
Features of the TMP1941 include the following:
(1) TX19 core processor
1)
2)
Two instruction set architecture (ISA) modes: 16-bit ISA for code density and 32-bit ISA for speed
•
The 16-bit ISA is object-code compatible with the code-efficient MIPS16 ASE.
•
The 32-bit ISA is object-code compatible with the high-performance TX39 family.
Combines high performance with low power consumption.
— High performance
•
Single clock cycle execution for most instructions
•
3-operand computational instructions for high instruction throughput
•
5-stage pipeline
•
On-chip high-speed memory
•
DSP function: Executes 32-bit x 32-bit multiplier operations with a 64-bit accumulation in a single
clock cycle.
— Low power consumption
3)
•
Optimized design using a low-power cell library
•
Programmable standby modes in which processor clocks are stopped
Fast interrupt response suitable for real-time control
•
Distinct starting locations for each interrupt service routine
•
Automatically generated vectors for each interrupt source
•
Automatic updates of the interrupt mask level
980508EBA1
• TOSHIBA continually is working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in
general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility
of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or
failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs,
please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products
specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability
Handbook.
• The products described in this document are subject to foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed
by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result
from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA
CORPORATION or others.
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined
by Philips.
TMP1941AF-1
2003-03-27
TMP1941AF
(2) 10-Kbyte on-chip RAM
No on-chip ROM
(3) External memory expansion
•
16-Mbyte off-chip address space for code and data
•
External bus interface with dynamic bus sizing for 8-bit and 16-bit data ports
(4) 4-channel DMA controller
•
Interrupt- or software-triggered
(5) 4-channel 8-bit timer
(6) 4-channel 16-bit timer
(7) 1-channel real-time counter (RTC)
(8) 4-channel general-purpose serial interface
Two channels support both UART and synchronous transfer modes and the other two channels are solely
for UART.
(9) 1-channel serial bus interface
Either I2C bus mode or clock-synchronous mode can be selected.
(10) 8-channel 10-bit A/D converter (with internal sample/hold)
Conversion time: 8.6 µs @40 MHz
(11) Watchdog timer
(12) 4-channel chip select/wait controller
(13) Interrupt sources
•
4 CPU interrupts:
software interrupt instruction
•
32 internal interrupts:
7 priority levels, with the exception of the watchdog timer interrupt
•
11 external interrupts:
7 priority levels, with the exception of the NMI interrupt
(14) 46-pin input/output ports
(15) Four standby modes
•
IDLE (HALT, DOZE), SLEEP, STOP
(16) Dual clocks
•
Clock for low-power operation: Low-speed clock (32.768 kHz)
•
RTC clock: Low-speed clock (32.768 kHz)
(17) Clock generator
•
On-chip PLL (x4)
•
Clock gear: Divides the operating speed of the CPU by 1/2, 1/4 or 1/8
(18) Little-endian
Higher address 31
Lower address
24 23
16 15
8 7
0
Word address
11
10
9
8
7
6
5
4
8
4
3
2
1
0
0
•
Byte 0 is the lowest-order byte (bits 7-0).
•
The address of a word data item is the address of its lowest-order byte (byte 0).
TMP1941AF-2
2003-03-27
TMP1941AF
(19) Operating voltage range: 2.7 to 3.6 V
(20) Operating frequency
•
40 MHz (Vcc ≥ 3.0 V)
•
28 MHz (Vcc ≥ 2.7 V)
(21) Package
•
100-pin QFP (14 x 14 x 1.4 (t) mm, 0.5-mm pitch)
TMP1941AF-3
2003-03-27
TMP1941AF
TX19 Processor Core
TX19 CPU
MAC
( ): Initial pin function
after reset
10-Kbyte RAM
X1
DMAC (4ch)
INT1-4 (PA0-3)
X2
G-Bus
NMI
INT0 (P77)
INTC
XT1 (P96)
CG
XT2 (P97)
INT5-A,
(P74-5, P80-1, P83-4)
SCOUT (P44)
PLLOFF
ADTRG (P53)
(P50−P57)
AN0−AN7
AVCC, AVSS
RESET
I/O Bus I/F
10-Bit
ADC
AD0-AD7
VREFH, VREFL
AD8/A8-AD15/A15
TXD0 (P90)
RXD0 (P91)
(P92)
SCLK0/ CTS0
SIO0
A0/A16-A7/A23
EBIF
TXD1 (P93)
RXD1 (P94)
(P95)
SCLK1/ CTS1
SCK (PA5)
SO/SDA (PA6)
SI/SCL (PA7)
RD
WR
HWR
SIO1
WAIT
BUSRQ
BUSAK
R/ W
Serial
Bus I/F
(SBI)
TA0IN (P70)
TA1OUT (P71)
TA2IN (P72)
TA3OUT (P73)
8-Bit TMRA0/1
8-Bit TMRA2/3
PORT3
P37
PORT4
(P40-P43)
CS0 - CS3
AM0/1
TB0IN0/INT5 (P74)
TB0IN1/INT6 (P75)
TB0OUT (P76)
16-Bit TMRB0
WDT
TB1IN0/INT7 (P80)
TB1IN1/INT8 (P81)
TB1OUT (P82)
TB2IN0/INT9 (P83)
TB2IN1/INTA (P84)
Real-Time
Counter (RTC)
16-Bit TMRB1
TXD3 (P70)
SIO3
16-Bit TMRB2
RXD3 (P71)
TB2OUT (P85)
TB3OUT (P86)
SIO4
16-Bit TMRB3
TXD4 (P72)
RXD4 (P73)
Figure 1.1 TMP1941AF Block Diagram
TMP1941AF-4
2003-03-27
TMP1941AF
2.
Signal Descriptions
This section contains pin assignments for the TMP1941AF as well as brief descriptions of the TMP1941AF
input and output signals.
2.1
Pin Assignment
The following illustrates the TMP1941AF pin assignment.
88 P44/SCOUT
DVSS
89
87 DVCC
P50/AN0
90
86 P43/CS3
P51/AN1
91
85 P42/CS2
P52/AN2
92
84 P41/CS1
P53/AN3/ADTRG
P54/AN4
93
94
83 P40/CS0
82 P37/DSU
P55/AN5
95
81 R/W
P56/AN6
96
80 BUSAK
P57/AN7
97
79 BUSRQ
VREFH
98
78 WAIT
VREFL
99
77 HWR
76 WR
AVSS
100
AVCC
1
75 RD
P70/TA0IN/TXD3
2
74 A7/A23
P71/TA1OUT/RXD3
3
73 A6/A22
P72/TA2IN/TXD4
4
72 A5/A21
P73/TA3OUT/RXD4
5
71 A4/A20
P74/TB0IN0/INT5
6
P75/TB0IN1/INT6
7
70 A3/A19
69 A2/A18
P76/TB0OUT
8
68 A1/A17
P77/INT0
9
67 A0/A16
P80/TB1IN0/INT7
10
P81/TB1IN1/INT8
11
66 AD15/A15
65 AD14/A14
P82/TB1OUT
12
64 DVCC
P83/TB2IN0/INT9
13
63 NMI
P84/TB2IN1/INTA
14
62 DVSS
P85/TB2OUT
P86/TB3OUT/INTLV
15
16
61 AD13/A13
60 AD12/A12
P87
17
59 AD11/A11
P90/TXD0
18
58 AD10/A10
P91/RXD0
19
57 AD9/A9
P92/SCLK0/CTS0
P93/TXD1
20
21
56 AD8/A8
P94/RXD1
22
54 AD6
P95/SCLK1/CTS1
23
AM0
24
53 AD5
52 AD4
CVCC
25
51 AD3
X2
26
50 AD2
CVSS
27
49 AD1
X1
28
48 AD0
AM1
29
47 DVCC
RESET
P96/XT1
30
31
46 ALE
P97/XT2
32
44 PA7/SI/SCL
PLLOFF
33
43 PA6/SO/SDA
FVCC
34
TEST
35
42 PA5/SCK
41 PA4/SDAO
FVSS
36
40 PA3/INT4
PA0/INT1
37
39 PA2/INT3
55 AD7
45 DVSS
38 PA1/INT2
Figure 2.1 100-Pin LQFP Pin Assignment
TMP1941AF-5
2003-03-27
TMP1941AF
2.2
Pin Usage Information
Table 2.1 lists the input and output pins of the TMP1941AF, including alternate pin names and functions
for multi-function pins.
Table 2.1 Pin Names and Functions
Pin Name
# of Pins
Type
Function
AD0–AD7
8
Input/output
Address (Lower): Bits 0-7 of the address/data bus
AD8–AD15
A8–A15
8
Input/output
Output
Address/Data (Upper): Bits 8-15 of the address/data bus
Address: Bits 8-15 of the address bus
A0–A7
A16–A23
8
Output
Output
Address: Bits 0-7 of the address bus
Address: Bits 16-23 of the address bus
RD
1
Output
Read Strobe: Asserted during a read operation from an external memory device
WR
1
Output
Write Strobe: Asserted during a write operation on D0-D7
HWR
1
Output
Higher Write Strobe: Asserted during a write operation on D8-D15
WAIT
1
Input
Wait: Causes the CPU to suspend external bus activity
BUSRQ
1
Input
Bus Request: Asserted by an external bus master to request bus mastership
BUSAK
1
Output
Bus Acknowledge: Indicates that the CPU has relinquished the bus in response to
BUSRQ .
R/W
1
Output
Read/Write: Indicates the direction of data transfer on the bus: 1 = read or dummy
cycle, 0 = write cycle
P37
1
Input/output
Input
Port 37: Programmable as input or output (with internal pull-up resister)
DSU
P40
DSU Enable: If this pin is sampled low at the rising edge of RESET , the TMP1941AF
enters DSU mode for software debugging using an external real-time debug system. If
this pin is sampled as high at the rising edge of RESET , the TMP1941AF enters
NORMAL mode.
1
Input/output
Output
Port 40: Programmable as input or output (with internal pull-up resister)
Chip Select 0: Asserted low to enable external devices at programmed addresses
1
Input/output
Output
Port 41: Programmable as input or output (with internal pull-up resister)
Chip Select 1: Asserted low to enable external devices at programmed addresses
1
Input/output
Output
Port 42: Programmable as input or output (with internal pull-up resister)
Chip Select 2: Asserted low to enable external devices at programmed addresses
1
Input/output
Output
Port 43: Programmable as input or output (with internal pull-up resister)
Chip Select 3: Asserted low to enable external devices at programmed addresses
P44
SCOUT
1
Input/output
Output
Port 44: Programmable as input or output
System Clock Output: Drives out a clock signal at the same frequency as the CPU
clock (high-speed or low-speed)
P50–P57
AN0–AN7
ADTRG
8
Input
Input
Input
Port 5: Input-only
Analog Input: Input to the on-chip A/D Converter
A/D Trigger: Starts an A/D conversion (multiplexed with P53)
P70
TA0IN
TXD3
1
Input/output
Input
Output
Port 70: Programmable as input or output
8-Bit Timer 0 Input: Input to Timer 0
Serial Transmit Data 3: Programmable as a push-pull or open-drain output
P71
TA1OUT
RXD3
1
Input/output
Output
Input
Port 71: Programmable as input or output
8-Bit Timer 1 Output: Output from either Timer 0 or Timer 1
Serial Receive Data 3
P72
TA2IN
TXD4
1
Input/output
Input
Output
Port 72: Programmable as input or output
8-Bit Timer 2 Input: Input to Timer 2
Serial Transmit Data 4: Programmable as a push-pull or open-drain output
P73
TA3OUT
RXD4
1
Input/output
Output
Input
Port 73: Programmable as input or output
8-Bit Timer 3 Output: Output from either Timer 2 or Timer 3
Serial Receive Data 4
P74
TB0IN0
INT5
1
Input/output
Input
Input
Port 74: Programmable as input or output
16-Bit Timer 0 Input 0: Count/capture trigger input to 16-bit Timer 0
Interrupt Request 5: Programmable to be high-level, low-level, rising-edge or fallingedge sensitive
CS0
P41
CS1
P42
CS2
P43
CS3
TMP1941AF-6
2003-03-27
TMP1941AF
Pin Name
# of Pins
Type
P75
TB0IN1
INT6
1
Input/output
Input
Input
P76
TB0OUT
P77
INT0
1
Input/output
Output
Input/output
Input
P80
TB1IN0
INT7
1
Input/output
Input
Input
P81
TB1IN1
INT8
1
Input/output
Input
Input
P82
TB1OUT
P83
TB2IN0
INT9
1
Input/output
Output
Input/output
Input
Input
P84
TB2IN1
INTA
1
Input/output
Input
Input
P85
TB2OUT
P86
TB3OUT
P87
1
Input/output
Output
Input/output
Output
Input/output
1
1
1
1
P90
TXD0
P91
RXD0
P92
SCLK0
CTS0
P93
TXD1
P94
RXD1
P95
SCLK1
CTS1
P96
XT1
P97
XT2
PA0–PA3
INT1–INT4
1
PA4
PA5
SCK
1
1
1
1
1
1
1
1
1
4
Input/output
Output
Input/output
Input
Input/output
Input/output
Input
Input/output
Output
Input/output
Input
Input/output
Input/output
Input
Input/output
Input
Input/output
Output
Input/output
Input
Input/output
Input/output
Input/output
Function
Port 75: Programmable as input or output
16-Bit Timer 0 Input 1: Capture trigger input to 16-bit Timer 0
Interrupt Request 6: Programmable to be high-level, low-level, rising-edge or fallingedge sensitive
Port 76: Programmable as input or output
16-Bit Timer 0 Output: Output from 16-bit Timer 0
Port 77: Programmable as input or output
Interrupt Request 0: Programmable to be high-level, low-level, rising-edge or fallingedge sensitive
Port 80: Programmable as input or output
16-Bit Timer 1 Input 0: Count/capture trigger input to 16-bit Timer 1
Interrupt Request 7: Programmable to be high-level, low-level, rising-edge or fallingedge sensitive
Port 81: Programmable as input or output
16-Bit Timer 1 Input 1: Capture trigger input to 16-bit Timer 1
Interrupt Request 8: Programmable to be high-level, low-level, rising-edge or fallingedge sensitive
Port 82: Programmable as input or output
16-Bit Timer 1 Output: Output from 16-bit Timer 1
Port 83: Programmable as input or output
16-Bit Timer 2 Input 0: Count/capture trigger input to 16-bit Timer 2
Interrupt Request 9: Programmable to be high-level, low-level, rising-edge or fallingedge sensitive
Port 84: Programmable as input or output
16-Bit Timer 2 Input 1: Capture trigger input to 16-bit Timer 2
Interrupt Request A: Programmable to be high-level, low-level, rising-edge or fallingedge sensitive
Port 85: Programmable as input or output
16-Bit Timer 2 Output: Output from 16-bit Timer 2
Port 86: Programmable as input or output
16-Bit Timer 3 Output: Output from 16-bit Timer 3
Port 87: Programmable as input or output
This pin is used to select the operating mode during reset. This pin should be pulled
down to a logic 0 during a reset sequence.
Port 90: Programmable as input or output
Serial Transmit Data 0: Programmable as a push-pull or open-drain output
Port 91: Programmable as input or output
Serial Receive Data 0
Port 92: Programmable as input or output
Serial Clock Input/Output 0
Serial Clear-to-Send 0
Port 93: Programmable as input or output
Start Serial Transmit Data 1: Programmable as a push-pull or open-drain output
Port 94: Programmable as input or output
Serial Receive Data 1
Port 95: Programmable as input or output
Serial Clock Input/Output 1
Serial Clear-to-Send 1
Port 96: Programmable as input or open-drain output
Connection pin for a low-speed crystal
Port 97: Programmable as input or open-drain output
Connection pin for a low-speed crystal
Ports A0–A3: Individually programmable as input or output
Interrupt Request 1–4: Individually programmable to be high-level, low-level, risingedge or falling-edge sensitive
Port A4: Programmable as input or output
Port A5: Programmable as input or output
Clock input/output pin when the Serial Bus Interface is in SIO mode
TMP1941AF-7
2003-03-27
TMP1941AF
Pin Name
# of Pins
Type
Function
PA6
SO
SDA
1
Input/output
Output
Input/output
PA7
SI
SCL
1
Input/output
Input
Input/output
ALE
1
Output
NMI
AM1
AM0
1
1
1
Input
Input
Input
TEST
PLLOFF
1
1
Input
Input
RESET
VREFH
1
1
Input
Input
VREFL
1
Input
AVCC
1

AVSS
1

X1/X2
DVCC,
CVCC
DVSS,
CVSS
2
5
Input/output

Port A6: Programmable as input or output
Data transmit pin when the Serial Bus Interface is in SIO mode
Data transmit/receive pin when the Serial Bus Interface is in I2C mode; programmable
as a push-pull or open-drain output
Port A7: Programmable as input or output
Data receive pin when the Serial Bus Interface is in SIO mode
Clock input/output pin when the Serial Bus Interface is in I2C mode; as an output,
programmable as a push-pull or open-drain output
Address Latch Enable (This signal is driven out only when external memory is
accessed.)
Nonmaskable Interrupt Request: Causes an NMI interrupt on the falling edge
AM1 should be tied to logic 0.
AM0 should be tied to logic 0 when configuring a 16-bit or mixed 8-/16-bit bus.
AM0 should be tied to logic 1 when configuring a 8-bit bus.
Test pin: This pin should be left open or tied to ground.
This pin should be tied to logic 1 when the frequency multiplied clock from the PLL is
used; otherwise, it should be tied to logic 0.
Reset (with internal pull-up resister): Initializes the whole TMP1941AF.
Input pin for high reference voltage for the A/D Converter. This pin should be
connected to the AVCC pin when the A/D Converter is not used.
Input pin for low reference voltage for the A/D Converter. This pin should be connected
to the AVSS pin when the A/D Converter is not used.
Power supply pin for the A/D Converter. This pin should always be connected to power
supply even when the A/D Converter is not used.
Ground pin for the A/D Converter. This pin should always be connected to ground
even when the A/D Converter is not used.
Connection pins for a high-speed crystal
Power supply pins
5

Ground pins (0 V)
Note 1:
When a DSU ICE is used, P37 and A0-A7 function as debug interface signals.
Note 2:
P37 and P87 should be held at the prescribed logic states for one system clock cycle before and after the rising
edge of RESET , with the RESET signal being stable in either logic state.
The following shows the DSU interface signals.
Figure 2.2 DSU Interface Signals
DSU Debug Interface
If the DSU pin is sampled low at the rising edge of RESET , the Port A pins are configured as interface signals for an
external real-time debug system. The DSU pin has an internal pullup resistor.
DRESET
(PA7)
I
DCLK
(PA0)
O
DBGE
(PA5)
I
PCST[2]
(PA1)
O
PCST[1]
(PA2)
O
PCST[0]
(PA3)
O
SDI/ DINT
(PA6)
I
SDAO/TPC
(PA4)
O
Debug Reset
DRESET signal for an external real-time debug system
Debug Clock
DCLK signal for an external real-time debug system
Debugger Enable
DBGE signal for an external real-time debug system
PC Trace Status [2]
PCTS[2] signal for an external real-time debug system
PC Trace Status [1]
PCST[1] signal for an external real-time debug system
PC Trace Status [0]
PCTS[0] signal for an external real-time debug system
Serial Data Input / Debug Interrupt
SDI/ DINT signal for an external real-time debug system
Serial Data and Address Output / Target PC
SDAO/TPC signal for an external real-time debug system
TMP1941AF-8
2003-03-27
TMP1941AF
3.
Core Processor
The TMP1941AF contains a high-performance 32-bit core processor called the TX19. For a detailed
description of the core processor, refer to the 32-Bit TX System RISC TX19 Core Architecture manual.
Be sure to read Section 21, Notations, Precautions and Restrictions, before using this product.
Functions unique to the TMP1941AF, which are not covered in the architecture manual, are described below.
3.1
Reset Operation
To reset the TMP1941AF, RESET must be asserted for at least 12 system clock periods after the power
supply voltage and the internal high-frequency oscillator have stabilized. This time is typically 2.4 µs at 40
MHz when the on-chip PLL is utilized, and 4.8 µs otherwise. After a reset, either the PLL-multiplied clock
or an external clock is selected, depending on the logic state of the PLLOFF pin. By default, the selected
clock is geared down to 1/8 for internal operation.
The following occurs as a result of a reset:
•
The System Control Coprocessor (CP0) registers within the TX19 core processor are initialized.
For details, refer to the 32-Bit TX System RISC TX19 Core Architecture manual.
•
The Reset exception is taken. Program control is transferred to the exception handler at a
predefined address. This predefined location is called exception vector, which directly indicates the
start of the actual exception handler routine. The Reset exception is always vectored to virtual
address 0xBFC0_0000 (which is the same as for the Nonmaskable Interrupt exception).
•
All on-chip I/O peripheral registers are initialized.
•
All port pins, including those multiplexed with on-chip peripheral functions, are configured as
either general-purpose inputs or general-purpose outputs.
Note: A reset operation does not affect the contents of the on-chip RAM.
TMP1941AF-9
2003-03-27
TMP1941AF
4.
Memory Map
The mapping of virtual addresses to physical addresses is shown below.
0xFFFF_FFFF
Virtual Address
Physical Address
16 Mbytes Reserved
16 Mbytes Reserved
On-Chip Peripherals
(Reserved)
Kseg2
On-Chip RAM (10 KB)
1 Gbytes
0xC000_0000
Kseg1
(Reserved)
16 Mbytes Reserved
Reserved for
debugging (2 MB)
0xA000_0000
Kseg0
0x8000_0000
16 Mbytes Reserved
0xFFFF_FFFF
0xFFFF_E000
0xFFFF_BFFF
0xFFFF_9800
0xFFFF_8000
0xFF3F FFFF
0xFF20 FFFF
(Reserved)
2 Gbytes
0xFF00_0000
0x4000_0000
Kuseg
Inaccessible
0x2000_0000
512 Mbytes
0x0000_0000
0x0000_0000
Figure 4.1 Memory Map
Note 1: The on-chip RAM is mapped to the addresses from 0xFFFF_9800 through 0xFFFF_BFFF.
Note 2: The TMP1941AF has access to only 16 Mbytes of external physical address space. The 16-Mbyte physical
memory can be located anywhere within the CPU’s 3.5-Gbyte physical address space through use of
programmable chip select signals. However, any address references to the on-chip memory, on-chip
peripheral or reserved regions override external memory access.
Note 3: No instruction should be placed in the last four words of the physical memory available in the user’s system.
TMP1941AF-10
2003-03-27
TMP1941AF
Clock/Standby Control
The TMP1941AF has two clocking modes: Single-Clock mode which operates off of the high-speed clock
supplied from the X1/X2 pins, and Dual-Clock mode which operates off of the high-speed clock supplied from
the X1/X2 pins and the low-speed clock supplied from the XT1/XT2 pins.
Figure 5.1 shows the transitions between clocking modes in Single-Clock mode and Dual-Clock mode.
Reset
Reset released
Instruction
IDLE Mode
(CPU halted)
(Selectable peripheral operation)
Interrupt
Instruction
NORMAL Mode
(fc / gear_value)
STOP Mode
(Whole chip halted)
Interrupt
(a) Single-Clock Mode
Reset
Reset released
Instruction
IDLE Mode
(CPU halted)
(Selectable peripheral operation)
NORMAL Mode
(fc/gear_value)
Interrupt
Instruction
Interrupt
Instruction
SLEEP Mode
(fs only)
(Only RTC is active.)
Interrupt
Instruction
Interrupt
5.
Interrupt
Interrupt
SLOW Mode
(fs)
Instruction
STOP Mode
(Whole chip halted)
Note 1:
Before a transition to SLOW or SLEEP mode can occur, the low-speed oscillator (fs) must be oscillating
stably.
Note 2:
After SLEEP mode is exited, the TMP1941AF returns to the mode it was in before entering SLEEP mode.
Note 3:
After STOP mode is exited, the TMP1941AF returns to the mode specified by the System Control Register 0
(SYSCR0). See Section 5.2.
(b) Dual-Clock Mode
Figure 5.1 Standby Modes Flow Diagram
Reset
Reset
Reset released
PLLOFF = 0
PLL not used
Reset released
PLLOFF = 1
PLL used
NORMAL Mode
NORMAL Mode
fc = fpll = fosc × 4
fsys = fc / 8
∴fsys = fosc / 2
fperiph = fsys
fc = fosc / 2
fsys = fc / 8
∴fsys = fosc / 16
fperiph = fsys
A. When the PLL clock is used
fosc:
fs:
fpll:
fc:
fgear:
fsys:
fperiph:
B. When the PLL is not used
Clock frequency supplied via the X1 and X2 pins
Clock frequency supplied via the XT1 and XT2 pins
PLL multiplied clock frequency (x4)
Clock frequency selected by the PLLOFF pin
Clock frequency selected by the GEAR[1:0] bits in the SYSCR1
System clock frequency selected by the SYSCK bit in the SYSCR1
Clock source for the prescalers inside on-chip peripherals
Figure 5.2 Default Clock Frequencies in NORMAL Mode
TMP1941AF-11
2003-03-27
TMP1941AF
5.1
Clock Generation
5.1.1
Main System Clock
•
A crystal can be connected between X1 and X2, or X1 can be externally driven with a clock.
•
The on-chip PLL can be enabled or disabled (bypassed) during reset by using the PLLOFF pin.
When the PLL is enabled, the input clock frequency is multiplied by four.
•
The clock gear can be programmed to divide the clock by 2, 4 or 8. (The default is 1/8 on reset.)
•
Input clock frequency
Input Frequency Range
fmax
fmin
PLL
ON
(For both crystal and external clock)
4–10 MHz
40 MHz
2 MHz
Crystal
16–20 MHz
20 MHz
1 MHz
PLL OFF
External clock
16–20 MHz
20 MHz
1 MHz
20–40 MHz
20 MHz1
1.25 MHz
Note 1: The DFOSC bit in the SYSCR1 must be cleared to 0. The default is 0 on reset.
5.1.2
Subsystem Clock
•
A 32.768-kHz crystal is connected between XT1 and XT2 (or XT1 can be externally driven with a
clock.)
•
SLOW mode: The CPU operates off of the low-speed clock.
•
SLEEP mode: Only the Real-Time Counter (RTC) is operational.
TMP1941AF-12
2003-03-27
TMP1941AF
5.1.3
Clock Source Block Diagrams
SYSCR0.WUEF
SYSCR2.WUPT[1:0]
SYSCR3.LUPTM
fperiph
(To on-chip
peripherals)
fgear
Warm-up Timer
Lock (PLL) Timer
SYSCR0.
XTEN
XT1
XT2
SYSCR1.FPSEL
fc
fs
fs
LowSpeed
Oscillator
fpll = fosch × 4
fsys
MUX
X1
X2
SYSCR0.
XEN
PLL
HighSpeed
Oscillator fosc
÷2
÷2
÷4
÷8
SYSCR1.SYSCK
SYSCR1.GEAR[1:0]
The default is 1/8 on reset.
PLLOFF (Default setting pin)
SYSCR1.DFOSC
CPU
fsys
fadc
SYSCR0.
PRCK[1:0]
ROM
÷2
÷4
RAM
ADCCK[1:0]
DMAC
fperiph
÷2
÷4
INTC
On-chip peripherals:
ADC, TMRA/B, SIO,
SBI, PIO, WDT, RTC
÷2
φT0
On-chip peripherals:
TMRA/B, SIO, SBI
(prescaler input)
Real-Time Counter
(RTC)
fs
SYSCR3.SCOSEL
SCOUT
Note 1:
When the clock gear is used to reduce the system clock frequency (fsys), the prescalars within on-chip
peripherals must be programmed so that the prescaler output (φ
φTn) satisfies the following relationship:
φTn < fsys / 2
Descriptions of each peripheral on the following sections include tables showing legal programming alternatives.
Note 2:
When the low-speed clock (fs) is used as the system clock, all on-chip peripherals except the Watchdog Timer
(WDT) and the Real-Time Counter (RTC) must be disabled.
Note 3:
The presclar clock source (φ
φTn) must not be changed while any of the peripherals to which it is supplied are
running.
Figure 5.3 Clock Source Block Diagrams
TMP1941AF-13
2003-03-27
TMP1941AF
5.2
Clock Generator (CG) Registers
5.2.1
System Clock Control Registers
7
SYSCR0
(0xFFFF_EE00)
6
5
Name
XEN
XTEN
RXEN
Read/Write
Reset Value
1
0
1
Function
High-speed Low-speed High-speed
oscillator
oscillator
oscillator
after exiting
STOP
mode
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
4
3
RXTEN
RSYSCK
R/W
0
0
Low-speed Clock
select after
oscillator
after exiting exiting
STOP
STOP
mode
mode
0: Disable
1: Enable
0:
High-speed
1:
Low-speed
2
1
0
WUEF
PRCK1
PRCK0
0
Oscillator
warm-up
period
(WUP)
timer
0
0
Prescaler clock select
00: fperiph/4
01: fperiph/2
10: fperiph
11: Reserved
On writes:
0: Don’tcare
1: Start
WUP
On reads:
0: Expired
1: Not
expired
SYSCR1
(0xFFFF_EE01)
Name
Read/Write
Reset Value
Function
15
14
13
12
11
10
9
8






SYSCK
FPSEL
DFOSC

GEAR1
GEAR0
0
High-speed
oscillator
frequency
divide
factor

R/W
0
System
clock
(fsys)
select
0: Highspeed
(fgear)
1: Lowspeed (fs)
23
SYSCR2
(0xFFFF_EE02)
SYSCR3
(0xFFFF_EE03)
22
Name
DRVSOCH DRVOSCL
Read/Write
Reset Value
0
0
Function
High-speed Low-speed
oscillator
oscillator
drive
drive
capability capability
0: High
0: High
1: Low
1: Low
Name
Read/Write
Reset Value
Function
0
fperiph
select
0: fgear
1: fc
00: fc
01: fc/2
10: fc/4
11: fc/8
0:
Divide-by-2
1:
Divide-by-1
21
20
19
18
17
16
WUPT1
WUPT0
STBY1
STBY0



DRVE
R/W
0
1: Pins are
driven in
STOP
mode.
R/W
1
0
1
1
Oscillator warm-up time Standby mode select
00: Reserved
01: 28/input frequency
10: 214/input frequency
11: 216/input frequency
00: Reserved
01: STOP mode
10: SLEEP mode
11: IDLE mode
31
30
29
28
27
26



SCOSEL
R/W
0
SCOUT
output
select



ALESEL
R/W
1
ALE output
width
select






0: fs
1: fsys
R/W
1
1
High-speed clock (fc)
gear select
0: fsys × 0.5
1: fsys × 1.5
TMP1941AF-14
25
LUPFG
R
0
PLL lock
0: Locked
1:
Unlocked
24
LUPTM
R/W
0
PLL lock
time select
0: 216/input
frequency
1: 212/input
frequency
2003-03-27
TMP1941AF
Note 1:
The Config register in the CP0 has the Doze and Halt bits. Setting the Halt bit puts the TMP1941AF in one of the
standby modes, as specified by the STBY1-STBY0 bits in the SYSCR2. Setting the Doze bit puts the TMP1941AF
in IDLE mode, irrespective of the settings of the STBY1-STBY0 bits.
Note 2:
When the PLL is not used, the LUPTM bit in the SYSCR3 must be set to 1 (212/input frequency).
Note 3:
The WUPT1-WUPT0 bits in the SYSCR2 must not be changed during the oscillator warm-up period. The LUPTM
bit in the SYSCR3 must not be changed during the PLL lock period.
Note 4:
The following considerations relate to consecutive mode changes immediately after a warm-up event (e.g.,
SLEEP–NORMAL–SLEEP).
Hardware warm-up (with no software intervention)
(1)
After having transitioned from STOP or SLEEP mode to NORMAL mode
•
When the PLL is used
A transition to a next mode can not occur until the PLL locks (SYSCR3.LUPFG=0) and at least five
program instructions are executed (including the instruction to check the LUPFG flag).
•
When the PLL is not used
•
When the oscillator warm-up time (SYSCR2.WUPT[1:0]) is programmed to 01 (28/input frequency)
A transition to a next mode can not occur until the PLL locks (SYSCR3.LUPFG=0) and at least five
program instructions are executed.
•
When the oscillator warm-up time (SYSCR2.WUPT[1:0]) is programmed to either 10 (214/input
frequency) or 11 (216/input frequency)
A transition to a next mode can not occur until at least five program instructions are executed.
(2)
After having transitioned from STOP or SLEEP mode to SLOW mode
Once in SLOW mode, a transition to a next mode can occur immediately.
Software warm-up
(1)
After having transitioned from SLOW mode to NORMAL mode
•
When the PLL is used
The NORMAL mode can be entered after the oscillator warm-up period timer has expired (i.e., after the
SYSCR2.WUEF bit is cleared). A transition to a next mode can not occur until the PLL locks
(SYSCR3.LUPFG=0) and at least five program instructions are executed (including the instruction to
check the LUPFG flag).
•
When the PLL is not used
•
When the oscillator warm-up time (SYSCR2.WUPT[1:0]) is programmed to either 01 (28/input
frequency)
The NORMAL mode can be entered after the oscillator warm-up period timer has expired (i.e., after
the SYSCR2.WUEF bit is cleared). A transition to a next mode can not occur until the PLL locks
(SYSCR3.LUPFG=0) and at least five program instructions are executed.
•
When the oscillator warm-up time (SYSCR2.WUPT[1:0]) is programmed to either 10 (214/input
frequency) or 11 (216/input frequency)
The NORMAL mode can be entered after the oscillator warm-up timer has expired (i.e., after the
SYSCR2.WUEF bit is cleared). A transition to a next mode can not occur until at least five program
instructions are executed.
(2)
After having transitioned from NORMAL mode to SLOW mode
After the oscillator warm-up timer has expired (SYSCR2.WUEF=0), a transition to a next mode can not occur
until at least five program instructions are executed.
TMP1941AF-15
2003-03-27
TMP1941AF
5.2.2
ADCCLK
(0xFFFF_EE04)
ADC Conversion Clock
Name
Read/Write
Reset Value
Function
7
6
5
4
3
2
1
0


















ADCCK1
R/W
0
ADCCK0
R/W
0
ADC conversion clock
(fadc) select
00: fsys/2
01: fsys/4
10: fsys/8
11: Don’t use.
Note: A/D conversion is executed using the clock selected by this register. Reduced conversion
accuracy occurs unless the conversion time is set to 8.6 µs or more.
Relationships Between fsys Frequencies and A/D Conversion Times
Conversion Clock
fsys
fsys/2
fsys/4
fsys/8
32 MHz
Don’t use.
10.75 µs
21.5 µs
20 MHz
8.6 µs
17.2 µs
34.4 µs
16 MHz
10.75 µs
21.5 µs
43.0 µs
10 MHz
17.2 µs
34.4 µs
68.8 µs
8 MHz
21.5 µs
43.0 µs
86.0 µs
Note: The conversion clock must not be changed while A/D conversion is in progress.
5.2.3
IMCGA0
(0xFFFF_EE10)
IMCGA1
(0xFFFF_EE11)
IMCGA2
(0xFFFF_EE12)
STOP/SLEEP Wake-up Interrupt Control Registers (INTCG Registers)
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
7
6






15
14






23
22






5
4
EMCG01
EMCG00
R/W
1
0
Wake-up
INT0
sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
13
12
EMCG11
EMCG10
R/W
1
0
Wake-up
INT1
sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
21
20
EMCG21
EMCG20
R/W
1
0
Wake-up INT2 sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
TMP1941AF-16
3
2
1









0
INT0EN
R/W
0
INT0
enable
0: Disable
1: Enable
11
10
9









8
INT1EN
R/W
0
INT1
enable
0: Disable
1: Enable
19
18
17









16
INT2EN
R/W
0
INT2
enable
0: Disable
1: Enable
2003-03-27
TMP1941AF
IMCGA3
(0xFFFF_EE13)
IMCGB0
(0xFFFF_EE14)
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
IMCGB1
(0xFFFF_EE15)
Name
Read/Write
Reset Value
Function
IMCGB2
(0xFFFF_EE16)
Name
Read/Write
Reset Value
Function
IMCGB3
(0xFFFF_EE17)
Name
Read/Write
Reset Value
Function
31
30






7
6






15
14






23
22






31
30






29
28
EMCG31
EMCG30
R/W
1
0
Wake-up INT3 sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
5
4
EMCG41
EMCG40
R/W
1
0
Wake-up INT4 sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
13
27
26
25









24
INT3EN
R/W
0
INT3
enable
0: Disable
1: Enable
3
2
1









0
INT4EN
R/W
0
INT4
enable
0: Disable
1: Enable
12
11
10
9
8




1
0
Must be set to 10.











0
Must be set
to 0.
20
19
18
17
16




1
0
Must be set to 10.











0
Must be set
to 0.
27
26
25
24









INTRTCEN
R/W
0
INTRTC
enable
21
29
28
EMCG71
EMCG70
R/W
1
0
Wake-up INTRTC
sensitivity
00: Don’t use.
01: Don’t use.
10: Don’t use.
11: Rising edge
These bits must be set
to 11.
0:Disable
1: Enable
Note 1:
The edge/level sensitivity must be defined for an interrupt pin which is enabled as wake-up
signaling to exit STOP/SLEEP mode.
Note 2:
Interrupt programming must follow these steps:
1. Configure the pin as an interrupt input, if the pin is multiplexed with a general-purpose port.
2. Set the active state for the interrupt during initialization.
3. Clear any interrupt request.
4. Enable the interrupt.
Note 3:
The above steps must be performed with the relevant interrupt pin disabled.
Note 4:
The TMP1941AF has six interrupt sources which can be used for wake-up signaling to exit
STOP/SLEEP mode: INT0 to INT4 (external interrupts) and INTRTC (internal RTC interrupt).
Note 5:
When one of these interrupt sources is used for STOP/SLEEP wake-up signaling, its interrupt
sensitivity defined in the CG block overrides the setting in the INTC block. In the INTC block,
its senstivity must be set to the high level (which has no effect).
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TMP1941AF
Example: Enabling the INT0 interrupt
IMCGA0.EMCG[01:00] = 10
IMCGA0.INT0EN = 1
IMC0L.EIM[11:10] = 01
IMC0L.IL[12:10] = 101
CG block
(Set the INT0 sensitivity to the falling edge)
INTC block
(Set the interrupt sensitivity to the high level, and the interrupt
priority level to 5.)
All interrupt sources other than those used for STOP/SLEEP wake-up signaling are controlled by the
INTC block.
5.2.4
EICRCG
(0xFFFF_EE20)
Interrupt Request Clear Register
Name
Read/Write
Reset Value
Function
7
6
5
4
3
2















ICRCG2
1
0
ICRCG1
ICRCG0
W



Clear interrupt request
000: INT0 100: INT4
001: INT1 101: Reserved
010: INT2 110: Reserved
011: INT3 111: INTRTC
Note 1:
Clearing the INT0-INT4 and INTRTC interrupt requests, if programmed for STOP/SLEEP wakeup signaling, requires two register settings: first, the EICRCG register in the CG block, and
then the INTCLR register in the INTC block. The clearing of other interrupt sources is
controlled through the INTCLR register alone.
Note 2:
In cases where INT0-INT4 are not used for STOP/SLEEP wake-up signaling, they are controlled
by the INTC block in the same way as other interrupt sources. INTRTC is controlled by both
the CG and INTC blocks, regardless of whether it is used for wake-up signaling.
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5.3
System Clock Control Section
A system reset initializes the SYSCR0.XEN bit to 1, the SYSCR0.XTEN bit to 0 and the
SYSCR1.GEAR[1:0] bits to 00, putting the TMP1941AF in Single-Clock mode. If the on-chip PLL is
enabled, the PLL reference clock is always multiplied by four. By default, the system clock frequency (fsys)
is geared down to fc/8, where fc = fosc × 4 (fosc is the oscillator frequency). For example, if an 8-MHz
crystal is connected between the X1 and X2 pins, the fsys clock operates at 4 MHz (8 × 4 × 1/8).
The PLL output clock can be disabled by setting the PLLOFF pin low during reset. Regardless of the
logic state of the PLLOFF pin, the fsys frequency is, by default, geared down to fc/8. A reset clears the
SYSCR1.DFOSC bit to 0, setting fc to fosc/2. Therefore, for example, if a 20-MHz crystal is connected
between the X1 and X2 pins, fsys becomes 20 × 1/2 × 1/8 = 1.25 MHz.
Alternatively, the X1 pin can be driven with an external clock. Since the fsys clock must have a 50% duty
cycle, it is recommended to use the default DFOSC bit value of 0 (i.e., fc = fosc × 1/2). However, the divideby-2 clock generator may be bypassed by setting the DFOSC bit after reset. This causes fc to be equal to
fosc; i.e., fsys becomes double the rate available when a crystal is connected between X1 and X2.
5.3.1
Oscillation Stabilization Time When Switching Between NORMAL and SLOW Modes
When a crystal is connected between the X1 and X2 pins and/or the XT1 and XT2 pins, the
integrated warm-up period timer is used to assure oscillation stability. The warm-up period can be
selected through the WUPT1–WUPT0 bits of the SYSCR2 to suit the crystal used. The warm-up period
timer can be started by software writing a 1 to the WUEF bit in the SYSCR0. This bit is self-clearing; it
can be read to ascertain that the timer has expired.
Table 5.1 shows the warm-up periods required when the clocking is switched between NORMAL and
SLOW modes.
Note 1:
No warm-up is necessary when the TMP1941AF is driven by an external oscillator clock which is
already stable.
Note 2:
Because the warm-up period timer is clocked by the oscillator clock, any frequency fluctuations
will lead to small timer errors. Table 5.1 should be considered as approximate values.
Note 3:
Ensure that the PLL lock flag (SYSCR3.LUPFG) is cleared before starting the warm-up period
timer.
Note 4:
When a low-speed crystal is connected between XT1 (Port 96) and XT2 (Port 97), the following
register settings are required to reduce power consumption:
When a crystal is connected between XT1 and XT2:
P9CR.P96C–P97C = 11
P9.P96–P97 = 00
When XT1 is driven with an external clock:
P9CR.P96C–P97C = 11
P9.P96–P97 = 10
Table 5.1 Warm-up Periods
Warm-up Period Select
SYSCR2.WUPT[1:0]
High-Speed Clock
(fosc)
Low-Speed Clock
(fs)
01 (28/ oscillation frequency)
25.6 (µs)
7.8
(ms)
10 (214/ oscillation frequency)
1.638 (ms)
500
(ms)
11 (216/ oscillation frequency)
6.554 (ms)
2000 (ms)
Assumption: fosc = 10 MHz, fs = 32.768 kHz
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2003-03-27
TMP1941AF
Example: Switching from NORMAL mode to SLOW mode
SYSCR2.WUPT[1:0] = xx
SYSCR0.XTEN = 1
SYSCR0.WUEF = 1
Check SYSCR0.WUEF.
SYSCR1.SYSCK = 1
SYSCR0.XEN = 0
5.3.2
Select warm-up period.
Enable low-speed clock (fs) oscillation.
Start warm-up period (WUP) timer.
Wait until SYSCR0.WUEF is cleared (i.e., the WUP expires.)
Switch system clock speed to low speed (fs).
Disable high-speed clock (fosc) oscillation.
System Clock Output
Either the fsys or fs clock can be driven out from the P44/SCOUT pin. The P44/SCOUT pin is
configured as SCOUT (system clock output) by programming the Port 4 registers as follows:
P4CR.P44C=1 and P4FC.P44F=1. The output clock is selected through the SYSCR3.SCOSEL bit.
Table 5.2 shows the pin states in each clocking mode when the P44/SCOUT pin is configured as
SCOUT.
Table 5.2 SCOUT Output States
SCOUT Select
NORMAL/
SLOW
SCOSEL = 0
The fs clock is driven out.
SCOSEL = 1
The fsys clock is driven out.
Standby Modes
IDLE
SLEEP
STOP
Held at either 1 or 0.
NOTE: The phase difference between the system clock output signal (SCOUT) and the internal clock
signal can not be guaranteed.
5.3.3
Reducing the Oscillator Clock Drive Capability
When a crystal is connected between the X1 and X2 pins and/or between XT1 and XT2 pins,
oscillator noise and power consumption can be reduced through the programming of the SYSCR2.
Setting the SYSCR2.DRVOSCH bit reduces the drive capability of the high-speed oscillator. Setting
the SYSCR2.DRVOSCL bit reduces the drive capability of the low-speed oscillator clock.
A reset clears both the DRVOSCH and DRVOSCL bits to 0, providing a high drive capability at
power-up. Both the high-speed and low-speed oscillator clocks must have a high drive capability (i.e.,
DRVOSCH=0, DRVOSCL=0) when clocking modes are changed.
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2003-03-27
TMP1941AF
•
Drive capability of the high-speed oscillator
fOSC
X1 Pin
C1
Oscillation Enable
Crystal
SYSCR2.DRVOSCH
C2
X2 Pin
•
Drive capability of the low-speed oscillator
XT1 Pin
C1
Oscillation Enable
Crystal
SYSCR2.DRVOSCL
C2
fS
XT2 Pin
Figure 5.4 Oscillator Clock Drive Capabilities
5.4
Prescalar Clock Control Section
The TMRA01, TMRA23, TMRB0 to TMRB3, SIO0 to SIO4 (there is no SIO2), and SBI have a clock
prescalar. The prescalar clock source (φT0) can be selected from fperiph/4, fperiph/2 and fperiph/1 through
the PRCK[1:0] bits of the SYSCR0. fperiph can be selected from either fgear or fc through the FPSEL bit of
the SYSCR1. The default reset values select fgear as fperiph, and fperiph/4 as φT0.
5.5
Clock Frequency Multiplication Section (PLL)
The on-chip PLL multiplies the frequency of the high-speed oscillator clock (fosc) by four to generate the
fpll clock. At reset, the PLL is disabled. To use the PLL, the PLLOFF pin must be high when RESET is
released.
Note: If the PLLOFF pin is low when RESET is released, the PLL will be disabled and the oscillator clock
will be driven with no frequency multiplication.
Being an analog circuit, the PLL requires a certain duration of time (called lock time) to stabilize, like an
oscillator. The oscillator warm-up period (WUP) timer is also used as the PLL lock timer. The LUPTM bit in
the SYSCR3 must be programmed so that the following relationship is satisfied:
PLL lock time ≥ Oscillator warm-up time
At reset, the default lock-up time is 216 / input frequency.
Setting the WUP timer control bit (SYSCR0.WUEF) starts the PLL lock timer. The SYSCR3.LUPTM bit
remains set while the PLL is out of lock, and is cleared when the PLL locks.
In real-time applications whose software execution time is critical, once the PLL has gone out of lock in a
standby mode, software must determine before resuming operation whether the PLL has locked (after the
oscillator warm-up period timer has expired) in order to assure clock stability.
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TMP1941AF
There is one thing to remember when changing the clock gear value.
The clock gear can be changed by the programming of the GEAR[1:0] bits of the SYSCR1. The RF[1:0]
bits of the CPU’s Config register need not be altered. It takes a few clock cycles for a gear change to take
effect. Therefore, one or more instructions following the instruction that changed the clock gear value may
be executed using the old clock gear value. If subsequent instructions need be executed with a new clock
gear value, a dummy instruction (one that executes a write cycle) should be inserted after the instruction that
modifies the clock gear value.
When the clock gear is used, the prescalars within on-chip peripherals must be programmed so that the
prescaler output (φTn) satisfies the following relationship:
φTn < fsys / 2
5.6
Standby Control Section
The TMP1941AF provides support for several levels of power reduction. While in NORMAL mode,
setting the Halt bit of the Config register within the TX19 core processor causes the TMP1941AF to enter
one of the standby modes — IDLE, SLEEP or STOP — as specified by the SYSCR2.STBY[1:0] bits.
Setting the Doze bit of the Config register causes the TMP1941AF to enter IDLE (Doze) mode, irrespective
of the setting of SYSCR2.STBY[1:0].
Prior to a transition to any of the standby modes, all interrupts other than those used for wake-up signaling
must be disabled through the Interrupt Controller (INTC).
The characteristics of the IDLE, SLEEP and STOP modes are as follows:
IDLE:
The CPU stops.
On-chip peripherals can be selectively enabled and disabled through use of a register bit in a
given peripheral, as shown in Table 5.3.
Table 5.3 IDLE Mode Register Settings
Peripheral
IDLE Mode Bit
TMRA01
TA01RUN.I2TA01
TMRA23
TA23RUN.I2TA23
TMRB0
TB0RUN.I2TB0
TMRB1
TB1RUN.I2TB1
TMRB2
TB2RUN.I2TB2
TMRB3
TB3RUN.I2TB3
SIO0
SC0MOD1.I2S0
SIO1
SC1MOD1.I2S1
SIO3
SC3MOD1.I2S3
SIO4
SC4MOD1.I2S4
SBI
SBI0BR1.I2SBI0
ADC
ADMOD1.I2AD
WDT
WDMOD.I2WDT
Note 1:
In Halt mode (i.e., a standby mode entered by setting the Halt bit in the Config register), the
TMP1941AF freezes the TX19 core processor, preserving the pipeline state. In Halt mode,
the TMP1941AF ignores any external bus requests; so it continues to assume bus
mastership.
Note 2:
In Doze mode (i.e., a standby mode entered by setting the Doze bit in the Config register),
the TMP1941AF freezes the TX19 core processor, preserving the pipeline state. In Doze
mode, the TMP1941AF recognizes external bus requests.
SLEEP: Only the internal low-speed oscillator and the RTC are operational.
STOP:
The whole TMP1941AF stops.
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TMP1941AF
5.6.1
TMP1941AF Operation in NORMAL and Standby Modes
Table 5.4 TMP1941AF Operation in NORMAL and Standby Modes
Operation Mode
Operating States
NORMAL
The TX19 core processor and peripherals operate at frequencies specified in the CG
block.
IDLE (Halt)
The processor and DMAC operations stop; other on-chip peripherals can be
selectively disabled.
IDLE (Doze)
Processor operation stops; the DMAC is operational; other on-chip peripherals can be
selectively disabled.
SLEEP
Processor operation stops; of the on-chip peripherals, only the RTC is operational (at
fs).
STOP
All processor and peripheral operations stop completely.
5.6.2
CG Operation in NORMAL and Standby Modes
Table 5.5 CG States in NORMAL and Standby Modes
Clock Source
Crystal
External Clock
Mode
Oscillator
PLL
Clock Supply to Peripherals
Clock Supply to CPU
NORMAL
On
On
Yes
Yes
SLOW
On
Off
Partially supplied (See Note.)
Yes
IDLE
(Halt)
On
On
Selectable
No
IDLE
(Doze)
On
On
Selectable
No
SLEEP
fs only
Off
RTC only
No
STOP
Off
Off
No
No
NORMAL
Off
On
Yes
Yes
SLOW
Off
Off
Partially supplied (See Note.)
Yes
IDLE
(Halt)
Off
On
Selectable
No
IDLE
(Doze)
Off
On
Selectable
No
SLEEP
Off
Off
RTC only
No
STOP
Off
Off
No
No
Note: The INTC, External Bus Interface (EBIF), I/O ports, WDT and RTC can operate in SLOW mode.
5.6.3
Processor and Peripheral Block Operation in Standby Modes
Table 5.6 Processor and Peripheral Blocks in Standby Modes
Circuit Block
TX19 Core Processor
DMAC
INTC
EBIF
External Bus Mastership
I/O Ports
Clock Source
IDLE (Doze)
IDLE (Halt)
SLEEP
STOP
fsys
Off
On
On
On
On
On
Off
Off
On
On
On
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
ADC
SIO
I2C
Timer Counters
WDT
Selectable on a block-by-block basis
RTC
fs
On
On
On
Off
CG

On
On
On
Off
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TMP1941AF
5.6.4
Wake-up Signaling
There are two ways to exit a standby mode: an interrupt request or reset signal. Availability of wakeup signaling depends on the settings of the Interrupt Mask Level bits, CMask[15:13], of the CP0 Status
register and the current standby mode (see Table 5.7).
•
Wake-up via Interrupt Signaling
The operation upon return from a standby mode varies, depending on the interrupt priority level
programmed before entering a standby mode. If the interrupt priority level is greater than the
processor’s interrupt mask level, execution resumes with the interrupt service routine. Upon
completion of the interrupt service routine, program execution resumes with the instruction
immediately following the instruction that activated the standby mode (i.e., the instruction that set
the Halt or Doze bit in the Config register).
If the interrupt priority level is equal to or less than the processor’s interrupt mask level, program
execution resumes with the instruction that activated the standby mode. The interrupt is left
pending.
Nonmaskable interrupts are always serviced upon return from a standby mode, regardless of the
current interrupt mask level.
•
Wake-up via Reset Signaling
Reset signaling always brings the TMP1941AF out of any standby mode. A wake-up from STOP
mode must allow sufficient time for the oscillator to restart and stabilize (see Table 5.1).
A reset does not affect the contents of the on-chip RAM, but initializes everything else, whereas an
interrupt preserves all internal states that were in effect before the standby mode was entered.
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TMP1941AF
Table 5.7 Wake-up Signaling Sources and Wake-up Operations
Interrupt Masking
Interrupts
Wake-up Signaling Sources
Standby Mode
Unmasked Interrupt
(request_level > mask_level)
IDLE
SLEEP
(Programmable)
STOP
✓1
IDLE
SLEEP
(Programmable)
✓
✓
STOP
✓1
NMI
✓
INTWDT
✓
–
–
✓
–
–
INT0–4
✓
✓
✓1
✦
✦
✦1
INTRTC
✓
✓
–
✦
✦
–
INT5–A
✓
–
–
✦
–
–
INTTA0–3
✓
–
–
✦
–
–
INTTB00–31
INTTBOF0–3
✓
–
–
✦
–
–
INTRX0–4
INTTX0–4
✓
–
–
✦
–
–
INTS2
✓
–
–
✦
–
–
INTAD
✓
–
–
✦
–
–
INTDMA2
✓
–
–
✦
–
–
✓
✓
✓
✓
✓
✓
RESET
✓
Masked Interrupt
(request_level ≤ mask_level)
✓:
Execution resumes with the interrupt service routine. ( RESET initializes the whole TMP1941AF.)
✦:
Execution resumes with the instruction that activated the standby mode. The interrupt is left pending.
–:
Cannot be used to exit a standby mode.
Note 1:
The TMP1941AF exits the standby mode after the warm-up period timer expires.
Note 2:
INTDMA is accepted only in IDLE (Doze) mode.
Note 3:
If the interrupt request level is greater than the mask level, an interrupt signal which is programmed as levelsensitive must be held active until interrupt processing begins. Otherwise, the interrupt will not be serviced
successfully.
Note 4:
If interrupts are disabled in the CPU, all interrupts other than those used for wake-up signaling must also be
disabled in the Interrupt Controller (INTC) before a standby mode is entered. Otherwise, any interrupt could
take the TMP1941AF out of the standby mode.
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TMP1941AF
5.6.5
STOP Mode
The STOP mode stops the whole TMP1941AF, including the on-chip oscillator. Pin states in STOP
mode depend on the setting of the SYSCR2.DRVE bit, as shown in Table 5.8. Upon detection of wakeup signaling, the warm-up period timer should be activated to allow sufficient time for the oscillator to
restart and stabilize before exiting STOP mode. After that, the system clock output can restart. On
exiting STOP mode, the TMP1941AF enters either NORMAL or SLOW mode, as programmed by the
RXEN, RXTEN and RSYSCK bits of the SYSCR0.
These register bits must be programmed prior to the instruction that activates a standby mode. The
warm-up period is chosen through the SYSCR2.WUPT[1:0] bits.
5.6.6
Returning from a Standby Mode
(1) Mode transitions from NORMAL to STOP to NORMAL
fsys
(High-speed clock)
Mode
System clock stopped
NORMAL
STOP
CG
(High-speed clock)
NORMAL
High-speed clock
oscillator started
Warm-up (W-up)
Warm-up started
Warm-up completed
When fosc = 10 MHz
W-up Time Select
SYSCR2.WUPT[1:0]
01 (28/fosc)
10 (214/fosc)
11 (216/fosc)
W-up Time (fc)
25.6 µs
1.638 ms
6.554 ms
(2) Mode transitions from NORMAL to SLEEP to NORMAL
fsys
(High-speed clock)
Mode
System clock stopped
SLEEP
NORMAL
CG
(High-speed clock)
CG
(Low-speed clock)
NORMAL
High-speed clock
oscillator started
Low-speed clock (fs) continues oscillation.
Low-speed clock (fs) continues oscillation.
Warm-up (W-up)
Warm-up started
Warm-up completed
When fosc = 10 MHz
W-up Time Select
SYSCR2.WUPT[1:0]
01 (28/fosc)
10 (214/fosc)
11 (216/fosc)
W-up Time (fc)
25.6 µs
1.638 ms
6.554 ms
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(3) Mode transitions from SLOW to STOP to SLOW
fsys
(Low-speed clock)
Mode
System clock stopped
SLOW
STOP
CG
(Low-speed clock)
SLOW
Low-speed clock
oscillator started
Warm-up (W-up)
Warm-up started
When fosc = 32.768 kHz
W-up Time Select
SYSCR2.WUPT[1:0]
01 (28/fosc)
10 (214/fosc)
11 (216/fosc)
Warm-up completed
W-up Time (fc)
7.8 ms
500 ms
2000 ms
(4) Mode transitions from SLOW to SLEEP to SLOW
fsys
(Low-speed clock)
Mode
SLEEP
SLOW
CG
(Low-speed clock)
SLOW
Low-speed clock
continues oscillation.
Warm-up (W-up)
Warm-up started
Warm-up completed
When fosc = 32.768 kHz
W-up Time Select
SYSCR2.WUPT[1:0]
01 (28/fosc)
10 (214/fosc)
11 (216/fosc)
W-up Time (fc)
7.8 ms
500 ms
2000 ms
Note 1:
Although the fs clock continues oscillation, a warm-up time must be specified.
Note 2:
For the TMP1941AF with an on-chip flash, when the RESET signal is used for STOP/ SLEEP wake-up
signaling, it must be held active for at least 500 µs for the internal system to stabilize.
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TMP1941AF
Table 5.8 Pin States in STOP Mode, Depending on the Setting of the SYSCR2.DRVE Bit
Pin Name
Type
DRVE = 0
DRVE = 1

AD0~AD7
Input/Output

AD8~AD15
Input/Output


A0~A7/A16∼A23
Output

Output
RD , WR
Output

Output
WAIT , BUSRQ
Input
PU*
Input
PU*
Output
HWR , BUSAK , R / W
Output
P37
Output mode
P40–43
Input mode
Output mode
PU*
PU*
Input
Output
P44 (SCOUT)
Input mode
Output mode


Input
Output
P50–57
Input pin


P70–76
Input mode
Output mode


Input
Output
P77 (INT0)
Input mode
Output mode
Input mode (INT0)


Input
Input
Output
Input
P80–87
Input mode
Output mode


Input
Output
P90–95
Input mode
Output mode


Input
Output
P96 (XT1) – P97 (XT2)
Input mode
Output mode
XT1, XT2



Input
Output

PA0–PA3
Input mode
Output mode
Input mode (INT1–INT4)


Input
Input
Output
Input
PA4–PA7
Input mode
Output mode


Input
Output
NMI
Input pin
ALE
Output pin
Input
Input
Output Low
Output Low
RESET
Input pin
Input
Input
AM0, AM1
Input pin
Input
Input
X1
Input pin
X2
Output pin


Output High
Output High
:
Pins configured for input mode and input-only pins are disabled. Pins configured for output mode and output-only
pins assume the high-Impedance state.
Input:
The input gate is active; the input voltage must be held at either the high or low level to keep the input pin from
floating.
Output: Pin direction is output.
PU*:
Programmable pull-up. Because the input gate is always disabled, no overlap current flows while in high-impedance
state.
TMP1941AF-28
2003-03-27
TMP1941AF
6.
Interrupts
6.1
Overview
Interrupt processing is coordinated bewtween the CP0 Status register, the Interrupt Controller (INTC) and
the Clock Generator (CG). The Status register contains the Interrupt Mask Level field (CMask[15:13]) and
the Interrupt Enable bit (IEc). For interrupt processing, also refer to the 32-Bit TX System RISC TX19 Core
Architecture manual.
The TMP1941AF interrupt mechanism includes the following features:
•
4 CPU internal interrupts (software interrupts)
•
12 external interrupt pins ( NMI , INT0 through INTA)
•
32 on-chip peripheral interrupts
•
Vector generation for each interrupt source
•
Programmable priority for each interrupt source (7 levels)
•
DMA trigger on interrupt
INTC
TX19L
Core Processor
CG
Interrupt
Detection
Block
6
Interrupt Priority
Settings
INT0–INT4
INTRTC
Interrupt Request
3
Nonmaskable
Interrupt Request
Interrupt Vector
Generation
Interrupt Clear
Register
Priority Resolver
Interrupt Detection
Block
6
5
INT0–INT4 bypass the CG unless used for
STOP/SLEEP wake-up signaling
Interrupt Clear Register
Internal interrupt signals
(DMAC, Timers, SIO, SBI, ADC)
INT5–INTA
NMI, INTWDT
Note 1:
There are interrupt enable and polarity bits in these registers:
• Interrupt Mode Control registers (IMCxx) in the INTC
• IMCGxx registers in the CG
Note 2:
The TMP1941AF provides six interrupt sources, INT0–INT4 and INTRTC, that can be used for
STOP/SLEEP wake-up signaling. External interrupts INT5–INTA cannot function as wake-up signals.
Figure 6.1 General Interrupt Mechanism
The Interrupt Detection block monitors interrupt events. Each interrupt source can be individually
programmed for active polarity and either level or edge sensitivity. The TMP1941AF interrupts are broadly
grouped as follows:
•
External interrupts INT0–INT4 and INTRTC
•
When enabled for STOP/SLEEP wake-up signaling
The TMP1941AF awakens from STOP or SLEEP mode, if so programmed, when any of the
external interrupts INT0–INT4 or INTRTC is asserted. The EMCGxx field in the IMCGxx register
TMP1941AF-29
2003-03-27
TMP1941AF
defines the interrupt polarity. The INTxEN bit in the IMCGxx register controls whether these
interrupt sources are enabled as wake-up signal sources (1=enable). If enabled, the interrupt
polarity (EIMxx) field in the INTC’s IMCxx register has no effect, but must be set to 01, or high
level. The ILxx field in the IMCxx register determines the action taken after exiting STOP/SLEEP
mode; i.e., whether execution resumes with an interrupt service routine.
•
When disabled for STOP/SLEEP wake-up signaling
If INT0–INT4 are disabled for STOP/SLEEP wake-up signaling, the INTC alone determines the
polarity and enabling of these interrupt sources. INTRTC is programmed through both the CG and
INTC, regardless of whether it is used for wake-up signaling.
•
External interrupts INT5–INTA and internal interrupts except INTRTC
These interrupts are programmable through the INTC.
The INTC collects interrupt events, prioritizes them and presents the highest-priority request to the TX19
core processor. Hardware interrupts are summarized below.
Interrupt
Programming
Interrupt Sensing
INT0–INT4
IMCGxx reg. in CG
IMCx reg. in INTC
When enabled for STOP/SLEEP wake-up signaling, the polarity
field in the INTC has no effect, but must always be set to “highlevel.” The actual sensitivity is programmed in the CG. When
disabled for STOP/SLEEP wake-up signaling, interrupt sensitivity
is programmed in the INTC. In either case, each interrupt source
is individually configurable as negative or positive polarity, and
as edge-triggered or level-sensitive.
INTRTC
IMCGxx reg. in CG
IMCx reg. in INTC
In the INTC, the polarity must always be set to “high-level.” The
actual sensitivity must be configured as rising-edge triggered in
the CG.
INT0–INTA
IMCx reg. in INTC
Configurable as negative or positive polarity, and as edgetriggered or level-sensitive.
INTDMAn
IMCx reg. in INTC
Falling edge
Other
IMCx reg. in INTC
Rising edge
On-Chip
Peripherals
Here are example register settings required to enable and disable the INT0 interrupt as a source of the
STOP/SLEEP wake-up signal (negative-edge triggered).
•
Enabling the interrupt
IMCGA0.EMCG[01:00] = 10
: Configure INT0 as negative-edge triggered
EICRCG.ICRCG[2:0] = 000
: Clear INT0 request
IMCGA0.INT0EN = 1
: Enable INT0 for wake-up signaling
IMC0L.EIM[11:10] = 01
: Configure INT0 as high-level sensitive
INTCLR.EICLR[5:0] = 000001 : Clear INT0 request
IMC0L.IL[12:10] = 101
INTC block
: Set INT0 priority level to 5
Status.IEc = 1, Status.CMask = xxx
•
CG block
TX19 core processor
Disabling the interrupt
Status.IEc = 0
IMC0L.IL[12:10] = 000
TX19 core processor
: Disable INT0 interrupt
INTCLR.EICLR[5:0] = 000001 : Clear INT0 request
IMCGA0.INT0EN = 0
: Disable INT0 for wake-up signaling
EICRCG.ICRCG[2:0] = 000
: Clear INT0 request
TMP1941AF-30
2003-03-27
TMP1941AF
6.2
Interrupt Sources
The TMP1941AF provides a reset interrupt, nonmaskable interrupts, and maskable interrupts:
•
Reset and nonmaskable interrupts
The RESET pin causes a Reset interrupt. The NMI pin functions as a nonmaskable interrupt. The
on-chip Watchdog Timer (WDT) is also capable of being a source of a nonmaskable interrupt
(INTWDT). Reset and nonmaskable interrupts are always vectored to virtual address 0xBFC0_0000.
•
Maskable interrupts
The TMP1941AF supports two types of maskable interrupts: software and hardware interrupts.
Maskable interrupts are vectored to virtual addresses 0xBFC0_0210 through 0xBFC0_0260, as shown
below.
Interrupt Source
Virtual Vector Address
0xBFC0_0000
Reset
Nonmaskable
Maskable
Software
Hardware
Swi0
0xBFC0_0210
Swi1
0xBFC0_0220
Swi2
0xBFC0_0230
Swi3
0xBFC0_0240
0xBFC0_0260
Note 1:
The above table shows the vector addresses when the BEV bit in the CP0 Status
register is set to 1. When BEV=1, all exception vectors reside in the on-chip ROM
space.
Note 2:
Software interrupts are posted by setting one of the Sw[3:0] bits in the CP0 Cause
register. Software interrupts are distinct from the “Software Set” interrupt which is one
of the hardware interrupt sources. A Software Set interrupt is posted from the INTC to
the TX19 core processor when the IL0[2:0] field in the INTC’s IMC0 register is set to a
non-zero value.
TMP1941AF-31
2003-03-27
TMP1941AF
Table 6.1 Hardware Interrupt Sources
Interrupt
Number
IVR[9:0]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
000
010
020
030
040
050
060
070
080
090
0A0
0B0
0C0
0D0
0E0
0F0
100
110
120
130
140
150
160
170
180
190
1A0
1B0
1C0
1D0
1E0
1F0
200
210
220
230
240
250
260
270
280
290
2A0
2B0
2C0
2D0
2E0
2F0
300
310
320
330
340
350
Interrupt Source
Software Set
INT0 pin
INT1 pin
INT2 pin
INT3 pin
INT4 pin
Reserved
Reserved
Reserved
Reserved
INT5 pin
INT6 pin
INT7 pin
INT8 pin
INT9 pin
INTA pin
Reserved
Reserved
Reserved
Reserved
INTTA0: 8-Bit Timer 0
INTTA1: 8-Bit Timer 1
INTTA2: 8-Bit Timer 2
INTTA3: 8-Bit Timer 3
Reserved
Reserved
Reserved
Reserved
INTTB00: 16-Bit Timer 0 (TB0RG0)
INTTB01: 16-bit Timer 0 (TB0RG1)
INTTB10: 16-bit Timer 1 (TB1RG0)
INTTB11: 16-bit Timer 1 (TB1RG1)
INTTB20: 16-bit Timer 2 (TB2RG0)
INTTB21: 16-bit Timer 2 (TB2RG1)
INTTB30: 16-bit Timer 3 (TB3RG0)
INTTB31: 16-bit Timer 3 (TB3RG1)
Reserved
Reserved
Reserved
Reserved
INTTBOF0: 16-Bit Timer 0 (Overflow)
INTTBOF1: 16-Bit Timer 1 (Overflow)
INTTBOF2: 16-Bit Timer 2 (Overflow)
INTTBOF3: 16-Bit Timer 3 (Overflow)
Reserved
Reserved
Reserved
Reserved
INTRX0: SIO receive (Channel 0)
INTTX0: SIO transmit (Channel 0)
INTRX1: SIO receive (Channel 1)
INTTX1: SIO transmit (Channel 1)
INTS2: Serial Bus Interface (SBI)
Reserved
TMP1941AF-32
Interrupt Control
Register
Address
IMC0L
0xFFFF_E000
IMC0H
0xFFFF_E002
IMC1L
0xFFFF_E004
IMC1H
0xFFFF_E006
IMC2L
0xFFFF_E008
IMC2H
0xFFFF_E00A
IMC3L
0xFFFF_E00C
IMC3H
0xFFFF_E00E
IMC4L
0xFFFF_E010
IMC4H
0xFFFF_E012
IMC5L
0xFFFF_E014
IMC5H
0xFFFF_E016
IMC6L
0xFFFF_E018
IMC6H
0xFFFF_E01A
IMC7L
0xFFFF_E01C
IMC7H
0xFFFF_E01E
IMC8L
0xFFFF_E020
IMC8H
0xFFFF_E022
IMC9L
0xFFFF_E024
IMC9H
0xFFFF_E026
IMCAL
0xFFFF_E028
IMCAH
0xFFFF_E02A
IMCBL
0xFFFF_E02C
IMCBH
0xFFFF_E02E
IMCCL
0xFFFF_E030
IMCCH
0xFFFF_E032
IMCDL
0xFFFF_E034
2003-03-27
TMP1941AF
Interrupt
Number
IVR[9:0]
54
55
56
57
58
59
60
61
62
63
360
370
380
390
3A0
3B0
3C0
3D0
3E0
3F0
6.3
Interrupt Source
INTRX3: SIO receive (Channel 3)
INTTX3: SIO transmit (Channel 3)
INTRX4: SIO receive (Channel 4)
INTTX4: SIO transmit (Channel 4)
INTRTC: RTC
INTAD: A/D conversion complete
INTDMA0: DMA complete (Channel 0)
INTDMA1: DMA complete (Channel 1)
INTDMA2: DMA complete (Channel 2)
INTDMA3: DMA complete (Channel 3)
Interrupt Control
Register
Address
IMCDH
0xFFFF_E036
IMCEL
0xFFFF_E038
IMCEH
0xFFFF_E03A
IMCFL
0xFFFF_E03C
IMCFH
0xFFFF_E03E
Interrupt Detection
When enabled as a STOP/SLEEP wake-up signal, the polarities of INT0–INT4 are programmed in the
EMCGxx field of the IMCGxx register within the CG; in this case, the EIMxx field of the IMCx register
within the INTC has no effect; it must be set to “high-level sensitive,” though. When disabled as a wake-up
singnal, the polarities of INT0–INT4 are programmed in the EIMxx field in the INTC’s IMCx register. The
polarity of INTRTC is always programmed in both the CG and the INTC. All other interrupts are always
programmed in the INTC’s IMCx register.
Each interrupt source is individually configurable as negative or positive polarity, and as edge-triggered or
level-sensitive. When a selected transition is detected, an interrupt request is issued to the INTC (except for
the NMI and INTWDT interrupts, which are directly delivered to the TX19 core processor).
It is the responsibility of software (an interrupt handler routine) to determine the cause of an interrupt and
to clear the interrupt condition. INTRTC and INT0–INT4 used for STOP/SLEEP wake-up signaling require
software access to two registers: the EICRCG register in the CG and the INTCLR register in the INTC.
Other interrupts can be cleared by writing its IVR[9:4] value to the INTCLR register located within the
INTC. For an external interrupt configured as level-sensitive, software must explicitly address the device in
question and clear the interrupt condition. A level-sensitive interrupt signal must be held active until the
TX19 core processor reads its interrupt vector from the Interrupt Vector Register (IVR).
6.4
Resolving Interrupt Priority
(1) Seven Interrupt Priority Levels
The Interrupt Mode Control registers (IMCF–IMC0) contain a 3-bit interrupt priority level (ILx) field
for each interrupt source, which ranges from level 0 to level 7, with level 7 being the highest priority.
Level 0 indicates that the interrupt is disabled.
(2) Interrupt Level Notification
When an interrupt event occurs, the INTC sends its priority level to the TX19 core processor. The
processor can determine the priority level of an interrupt being requested by reading the IL field in the
CP0 Cause register.
(3) Interrupt Vector (Interrupt Source Notification)
Whenever an interrupt request is made, the INTC automatically sets its vector in the IVR. The TX19
core processor can determine the exact cause of an interrupt by reading the IVR. If multiple interrupt
requests occur at the same level, the interrupt with the smallest interrupt number is delivered (see Table
6.1). When no interrupt is pending, the IVR[9:4] field in the IVR contains a value of zero.
When the TX19 core processor responds to a request with an interrupt acknowledge cycle, the INTC
forwards the interrupt vector for that interrupt request. At this time, the TX19 core processor saves the
priority level value in the CMask field of the CP0 Status register.
TMP1941AF-33
2003-03-27
TMP1941AF
6.5
Register Description
Table 6.2 INTC Register Map
Address
Symbol
0xFFFF_E060
INTCLR
0xFFFF_E040
IVR
Corresponding
Interrupt Number
Register Name
Interrupt Request Clear Register
All (63 − 0)
Interrupt Vector Register
All (63 − 0)
0xFFFF_E03C
IMCF
Interrupt Mode Control Register F
63 − 60
0xFFFF_E038
IMCE
Interrupt Mode Control Register E
59 − 56
0xFFFF_E034
IMCD
Interrupt Mode Control Register D
55 − 52
0xFFFF_E030
IMCC
Interrupt Mode Control Register C
51 − 48
0xFFFF_E02C
IMCB
Interrupt Mode Control Register B
47 − 44
0xFFFF_E028
IMCA
Interrupt Mode Control Register A
43 − 40
0xFFFF_E024
IMC9
Interrupt Mode Control Register 9
39 − 36
0xFFFF_E020
IMC8
Interrupt Mode Control Register 8
35 − 32
0xFFFF_E01C
IMC7
Interrupt Mode Control Register 7
31 − 28
0xFFFF_E018
IMC6
Interrupt Mode Control Register 6
27 − 24
0xFFFF_E014
IMC5
Interrupt Mode Control Register 5
23 − 20
0xFFFF_E010
IMC4
Interrupt Mode Control Register 4
19 − 16
0xFFFF_E00C
IMC3
Interrupt Mode Control Register 3
15 − 12
0xFFFF_E008
IMC2
Interrupt Mode Control Register 2
11 − 8
0xFFFF_E004
IMC1
Interrupt Mode Control Register 1
7−4
0xFFFF_E000
IMC0
Interrupt Mode Control Register 0
3−0
6.5.1
Interrupt Vector Register (IVR)
This register indicates the vector for the interrupt source when there is an interrupt event.
7
IVR
(0xFFFF_E040)
4
3
2
1
0
Name
IVRL
Read/Write
Reset Value
0
0
0
0
Function
Interrupt vector for the source of the current
interrupt




0
0
0
0
10
9
15
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
6
14
5
13
R
12
11
IVRH
R/W
8
IVRL
R
0
0
0
0
23
22
21
20
0
19
0
18
0
0
Interrupt vector for the
source of the current
interrupt
17
16
0
0
25
24
0
0
IVRM
R/W
0
0
0
0
31
30
29
28
0
27
0
26
IVRM
R/W
0
0
0
0
TMP1941AF-34
0
0
2003-03-27
TMP1941AF
6.5.2
Interrupt Mode Control Registers (IMCF–IMC0)
These registers control the interrupt priority level, active polarity, either level or edge sensitivity, and
DMA triggering.
IMC0L
(0xFFFF_E000)
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
IMC0H
(0xFFFF_E002)
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
Note 1:
Note 2:
Note 3:
6.5.3
7
6
5
4
3
2
1
0


EIM01
EIM00
DM0
IL02
IL01
IL00




R/W
0
0
Interrupt sensitivity
00: Low level
Must be set to 00.
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM0 = 0
Interrupt Number 0 (Software Set)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM0 = 1
DMAC channel select
000–011: Channel number (0–3)
100–111: Don’t use.
15
14
13
12
11
10
9
8






EIM11
EIM10
DM1
IL12
IL11
IL10
R/W
0
0
Interrupt sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM0 = 0
Interrupt Number 1 (INT0 pin)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM0 = 1
DMAC channel select
000–011: Channel number (0–3)
100–111: Don’t use.
23
22
21
20
19
18
17
16






EIM21
EIM20
DM2
IL22
IL21
IL20
31
30
29
28
27
26
25
24






EIM31
EIM30
DM3
IL32
IL31
IL30
0
0
Same as above
(INT1)
0
0
Same as above
(INT2)
R/W
0
0
0
0
Same as
Interrupt Number 2 (INT1 pin)
above
Same as above
(INT1)
R/W
0
0
0
0
Same as
Interrupt Number 3 (INT2 pin)
above
Same as above
(INT2)
Interrupt sensitivity must be programmed when interrupts are enabled.
For a complete list of the Interrupt Mode Control registers, see Chapter 19.
When an interrupt is used to trigger a DMAC channel, that DMAC channel must be put in
Ready state after the programming of the INTC.
Interrupt Request Clear Register (INTCLR)
Loading the EICLR[5:0] field of this register with the IVRL[9:4] value of the IVR causes the
corresponding interrupt to be cleared.
INTCLR
0xFFFF_E060)
Name
Read/Write
Reset Value
Function
Note1:
Note2:
7
6
5
4
3
2
1
0






EICLR5
EICLR4
EICLR3
EICLR2
EICLR1
EICLR0

W




IVRL[9:4] value for an interrupt to be cleared

An interrupt request must not be cleared before the TX19 core processor reads the IVR value.
Follow the steps below to disable a particular interrupt with the Interrupt Controller (INTC).
1. Globally disable the acceptance of interrupts by the core processor by clearing the IEc bit of
the Status register.
2. Disable a desired interrupt with the INTC by clearing the ILx[2:0] field of the IMCxx register.
3. Execute the SYNC instruction.
4. Enable the acceptance of interrupts by the core processor by setting the IEc bit of the
Status register.
Example: mtc0
r0,
r31
; _DI ( ) ;
sb
r0,
IMC** ; IMC** = 0 ;
sync
; _SYNC ( ) ;
mtc0
$sp, r31
; _EI ( ) ;
TMP1941AF-35
2003-03-27
TMP1941AF
7.
I/O Ports
The TMP1941AF has 46 I/O port pins. All the port pins except a few share pins with alternate functions. They
can be individually programmed as general-purpose I/O or dedicated I/O for the on-chip CPU or peripherals.
Table 7.1 shows all the I/O port pins available on the TMP1941AF and their shared functions. (There is no Port
6.) Table 7.2 is a summary of register settings used to control the port pins.
Table 7.1 Programmable I/O Ports
Port
Pin Name # of Pins
Direction
Pull
Resistor
Direction
Programmability
Port 3
P37
P40
P41
P42
P43
P44
1
1
1
1
1
1
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Pullup
Pullup
Pullup
Pullup
Pullup

Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
P50–P57
8
Input

Fixed
P70
P71
P72
P73
P74
P75
P76
P77
P80
P81
P82
P83
P84
P85
P86
P87
P90
P91
P92
P93
P94
P95
P96
P97
PA0–PA3
PA4
PA5
PA6
PA7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
1
1
1
1
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output





























Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Bitwise
Port 4
Port 5
Port 7
Port 8
Port 9
Port A
TMP1941AF-36
Alternate Functions
CS0
CS1
CS2
CS3
SCOUT
AN0–AN7/ ADTRG (P53)
TA0IN/TXD3
TA1OUT/RXD3
TA2IN/TXD4
TA3OUT/RXD4
TB0IN0/INT5
TB0IN1/INT6
TB0OUT
INT0
TB1IN0/INT7
TB1IN1/INT8
TB1OUT
TB2IN0INT9
TB2IN1/INTA
TB2OUT (/ BOOT in TMP1940FDBF)
TB3OUT/INTLV
TXD0
RXD0
SCLK0/ CTS0
TXD1
RXD1
SCLK1/ CTS1
XT1
XT2
INT1–INT4
SCK
SO/SDA
SI/SCL
2003-03-27
TMP1941AF
Table 7.2 I/O Port Programmability (1/2)
Port

Pin Name
Pn
PnCR
PnFC
Input/output
N/A
N/A
N/A
AD8-AD15 bus
Input/output
N/A
N/A
N/A
A8-A15 bus
Output
N/A
N/A
N/A
A16-A23 bus
Output
N/A
N/A
N/A
RD
Output
N/A
N/A
N/A
WR
Output
N/A
N/A
N/A
HWR (Note 1)
Output
N/A
N/A
N/A
BUSRQ
Input (with pullup disabled)
0
N/A
N/A
Input (with pullup enabled)
1
N/A
N/A
Input (with pullup disabled)
0
N/A
N/A
Input (with pullup enabled)
1
N/A
N/A
BUSAK
Output
N/A
N/A
N/A
R / W (Note 1)
Output
N/A
N/A
N/A
Input port (with pullup disabled)
0
0
0
Input port (with pullup enabled)
1
0
0
Input port (with pullup disabled)
Input port (with pullup enabled)
Output port
CS0 output
CS1 output
CS2 output
CS3 output
SCOUT output
Input port
AN[0:7] inputs (Note 2)
ADTRG input (Note 3)
Input port
Output port
TA0IN input
TXD3 output
TA1OUT output
RXD3 input
TA2IN input
TXD4 output
TA3OUT output
RXD4 input
TB0IN0 input
INT5 input
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
TB0IN1 input
INT6 input
X
X
0
TB0OUT output
Wake-up INT0 input (Note 4)
INT0 input (no wake-up)
X
X
X
P37
P40–P43
(Note 1)
Port 4
I/O Register Settings
AD0-AD7 bus
WAIT
Port 3
Direction / Function
P40
P41
P42
P43
P44
P50–P57
Port 5
P53
P70–P77
P70
P71
P72
P73
Port 7
P74
P75
P76
P77
TMP1941AF-37
N/A
0
1
0
1
1
0
0
1
1
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
Setting
unneeded
1
Setting
unneeded
1
1
Setting
unneeded
2003-03-27
TMP1941AF
Table 7.2 I/O Port Programmability (2/2)
Port
Pin Name
P80–P87
P80
P81
Function / Direction
PnFC
X
0
0
X
1
0
TB1IN0 input
X
INT7 input
X
TB1IN1 input
X
X
0
1
0
Setting
unneeded
0
1
0
Setting
unneeded
1
P82
TB1OUT output
X
1
P83
TB2IN0 input
X
0
1
0
Setting
unneeded
P84
X
TB2IN1 input
X
INTA input
X
0
1
0
Setting
unneeded
1
P85
TB2OUT output
X
1
P86
TB3OUT output
X
1
1
P90–P95
Input port
X
0
0
Output port
X
1
0
P90
TXD0 output
X
1
1
P91
RXD0 input
X
0
N/A
P92
SCLK0 output
X
1
1
CTS0 /SCLK0 input
X
0
1
P93
TXD1 output
X
1
1
P94
RXD1 input
X
0
N/A
P95
SCLK1 output
X
1
1
CTS1 /SCLK1 input
X
0
1
Input port
X
0
Output port (Note 5)
X
1
P96–P97
PA0–PA7
PA0–PA3
Port A
PnCR
Input port
INT9 input
Port 9
Pn
Output port
INT8 input
Port 8
I/O Register Settings
PA5
PA6
PA7
N/A
XT1–XT2 (Note 6)
X
0
Input port
X
0
0
Output port
X
1
0
0
Setting
unneeded
Wake-up INT1–INT4 inputs (Note 4)
X
INT1–INT4 inputs (no wake-up)
X
0
SCK input
X
0
SCK output
X
1
1
SDA input
X
0
0
1
SDA output (Note 5)/SO output
X
1
1
SI input/SCL input
X
0
0
SCL output (Note 7)
X
1
1
X: Don’t care
Pn: Port n Register, PnCR: Port n Control Register, PnFC: Port n Function Register
TMP1941AF-38
2003-03-27
TMP1941AF
Note 1:
HWR , R / W and P40 to P43 have their internal pullup resistors enabled when the corresponding P4FC
register bit is set and when the bus is released.
Note 2:
When P50–P57 are configured as analog channels of the ADC, the ADCH[2:0] field in A/D Mode Control
Register 1 (ADMOD1) is used to select a channel(s). See Section 15.1.
Note 3:
When P53 is configured as ADTRG , the ADTRGE bit in the ADMOD1 register is used to enable and disable
the external trigger input to the ADC.
Note 4:
When INT0–INT4 are enabled for a wake-up from STOP mode with the SYSCR2.DRIVE bit cleared (undriven
pins), the corresponding bit in the PnFC must be set.
Note 5:
When P96–P97 are configured as output ports, they function as open-drain outputs.
Note 6:
When P96–P97 are configured as XT1–XT2, the SYSCR0 register must be programmed to enable oscillation,
etc.
Note 7:
When PA6 and PA7 are configured as SDA and SCL outputs for the SBI, the ODEA[7:6] field in the Open-Drain
Enable (ODE) register can be used to configure them as either push-pull or open-drain ouptuts. Upon reset,
the default is push-pull. See Section 7.11.
TMP1941AF-39
2003-03-27
TMP1941AF
7.1
Address/Data Bus Bits 0–7 (AD0–AD7)
AD0–AD7 function as bits 0–7 of the address/data bus. The address bits 0–7 (A0–A7) and the data bits 0–
7 (D0–D7) are multiplexed onto these pins.
Internal Data Bus
Address/Data Outputs
AD0–AD7
Data Inputs
Figure 7.1 Address/Data Bus Bits 0–7 (AD0–AD7)
Address/Data Bus Bits 8–15 (AD8–AD15) / Address Bus Bits 8–15 (A8–A15)
These pins function as either AD[8:15] bits of the address/data bus or the A[8:15] bits of the address bus,
depending on the logic state of the AM0 pin. When AM0 is at logic 0 (i.e., 16-bit data bus or mixed 8/16-bit
data bus), these pins always function as the AD[8:15] bits of the address/data bus. When AM0 is at logic 1
(i.e., 8-bit data bus), these pins always function as the A[8:15] bits of the address bus.
Address/Data Outputs
Address Outputs
Internal Data Bus
7.2
AD8–AD15/A8–A15
Data Inputs
Figure 7.2 Address/Data Bus Bits 8–15 (AD8–AD15) / Address Bus Bits 8–15 (A8–A15)
TMP1941AF-40
2003-03-27
TMP1941AF
7.3
Address Bus Bits 16–23 (A16–A23)
Internal Data Bus
These pins always function as A[16:23] bits of the address bus.
Address Outputs
A16–A23
Figure 7.3 Address Bus Bits 16–23 (A16–A23)
RD , WR , HWR , WAIT , BUSRQ , BUSAK , R/ W
Internal Data Bus
These pins always function as bus control signals. Upon reset, the internal pullup resistors of the WAIT
and BUSRQ pins are enabled; the pullup resistors can be disabled by clearing the corresponding bits in the
P3 register. HWR and R/ W are held at logic 1 while BUSAK =0.
Internal Data Bus
7.4
RD
,
WR
P-ch
HWR , BUSAK , R/ W
Figure 7.4 RD , WR , HWR , BUSAK , R/ W
TMP1941AF-41
2003-03-27
Internal Data Bus
TMP1941AF
Output Latch
P3 Write
P-ch
(Programmable Pullup Resistor)
WAIT Input
WAIT , BUSRQ
BUSRQ Input
Figure 7.5 WAIT / BUSRQ
Pullup Control Register
P3
Name
(0xFFFF_F018)
Read/Write
7
6
5
4



RQPUP
R/W
3
2
1
0
WTPUP



R/W
Reset Value
1
1
1
Function
1
1 (Pullup)
1 (Pullup)
0: Pullup disabled
1: Pullup enabled
Note: The Pullup Control and P3 registers are physically the same register. Bit 7 of this register controls the internal
pullup register of Port 37.
Figure 7.6 WAIT / BUSRQ Pullup Control Register
TMP1941AF-42
2003-03-27
TMP1941AF
7.5
Port 37
Port 37 functions as a general-purpose I/O pin. Port 37 can be configured as an input or an output by
programming the P3CR register. Upon reset, the Output Latch P37 is set to 1 and the P37C bit in the P3CR
register is cleared, configuring Port37 for input mode with pullup.
Reset
Direction Control
(bitwise)
P-ch
Internal Data Bus
P3CR Write
Programmable
Pullup Resistor
S
Output Latch
P37
Output Buffer
P3 Write
P3 Read
Figure 7.7 Port 37
Port 3 Register
7
6
5


4
3
2
1
0



P3
Name
P37


(0xFFFF_F018)
Read/Write
R/W
R/W
R/W
Reset Value
1
1
1
Functoin
0: Pullup
disabled
1: Pullup
enabled
Note: The P3 and WAIT / BUSRQ Pullup Control registers are physically the same register. Bits 3 and 4 control the
internal pullup resistors of WAIT and BUSRQ .
Port 3 Control Register
P3CR
Name
(0xFFFF_F01A)
Read/Write
7
6
5
P37


3
2
1
0





Must be
written as 0.
Must be
written as 0.
Must be
written as 1.
W
Reset Value
Function
4
0
0: IN
1: OUT
Must be
written as 1.
Must be
written as 1.
Figure 7.8 Port 37 Registers
TMP1941AF-43
2003-03-27
TMP1941AF
7.6
Port 4 (P40–P44)
P40–P43 can be individually programmed to function as either discrete general-purpose I/O pins or
programmable chip select ( CS0 – CS3 ) pins. P44 can be programmed to function as either a general-purpose
I/O pin or a system clock output (SCOUT) pin.
The P4CR and P4FC registers select the direction and function of the Port 4 pins. Upon reset, the P4CR
and P4FC register bits are cleared, configuring all the Port 4 pins as input port pins; P40–P43 have an
internal pullup resistor. Upon reset, the Output Latch (P4) is set to all 1s.
Reset
Direction Control
(bitwise)
P4CR Write
P-ch
P4FC Write
S
Output Latch
Programmable
Pullup Resistor
S
A
B
Selector
Internal Data Bus
Function Control
(bitwise)
Output Buffer
P40
( CS0 )
P41 ( CS1 )
P42
( CS2 )
P43 ( CS3 )
P4 Write
CS0 , CS1 , CS2 , CS3
P4 Read
Figure 7.9 Port 4 (P40–P43)
TMP1941AF-44
2003-03-27
TMP1941AF
Reset
Direction
Control (bitwise)
P4CR Write
Internal Data Bus
Function
Control (bitwise)
P4FC Write
S
A
Output Latch
S
Selector Y
B
P44 (SCOUT)
P4 Write
S
B
Y Selector
A
P4 Read
fsys Clock
A
Y
Selector
fs Clock
B
S
SYSCR3.SCOSEL
Figure 7.10 Port 4 (P44)
TMP1941AF-45
2003-03-27
TMP1941AF
7
6
Port 4 Register
5
4
P4
Name



(0xFFFF_F01E)
Read/Write



Reset Value






P44
P43
2
1
0
P42
P41
P40
1 (Pullup)
1 (Pullup)
R/W
Input mode
1
7
Port 4 Control Register
6
5
4
P4CR
Name



(0xFFFF_F020)
Read/Write



Reset Value






1 (Pullup)
1 (Pullup)
3
2
1
0
P44C
P43C
P42C
P41C
P40C
0
0
0
0
W
1
0: IN
7
Port 4 Function Register
6
5
4
P4FC
Name



(0xFFFF_F021)
Read/Write



Reset Value



Function
3
1: OUT
3
2
1
0
P44F
P43F
P42F
P41F
P40F
0
0
0
0
W
1
0: Port
0: Port
1: SCOUT
1: CS
0
Port (P40)
1
CS0
0
Port (P41)
1
CS1
0
Port (P42)
1
CS2
0
Port (P43)
1
CS3
Figure 7.11 Port 4 Registers
TMP1941AF-46
2003-03-27
TMP1941AF
7.7
Port 5 (P50–P57)
Eight Port 5 pins are input-only pins shared with the analog input pins of the A/D Converter (ADC). P53
is also shared with the A/D trigger input pin.
Internal Data Bus
Port 5
P50–P57
(AN0–AN7)
Port 5 Read
A/D
Conversion
Result
Register
A/D
Converter
Channel
Selector
AD Read
ADTRG
(Only P53)
Figure 7.12 Port 5 (P50–P57)
7
6
P57
P56
Port 5 Register
5
4
P55
P54
3
2
1
0
P53
P52
P51
P50
P5
Bit Symbol
(0xFFFF_F025)
Read/Write
R
After reset
Input mode
Figure 7.13 Port 5 Register
Note 1:
A/D Mode Control Register 1 (ADMOD1) is used to select an A/D converter input channel(s)
and to enable the A/D trigger input. See Section 15.1.
Note 2:
When P53 is used as the A/D trigger Input ( ADTRG ) pin, P53 (AN3) can not function as an
analog input.
TMP1941AF-47
2003-03-27
TMP1941AF
7.8
Port 7 (P70–P77)
Eight Port 7 pins can be individually programmed to function as discrete general-purpose or dedicated I/O
pins. Upon reset, all Port 7 pins are configured as input port pins. Alternatively, P70 and P72 can each be
programmed as either the TXD output from an SIO channel or the clock input (TA0IN or TA2IN) to an 8-bit
timer. P71 and P73 can each be programmed as either the RXD input to an SIO channel or the timer output
(TA1OUT or TA3OUT) from an 8-bit timer. P74 and P75 can each be programmed as either the clock input
(TB0IN0 or TB0IN1) to a 16-bit timer or an external interrupt request pin (INT5 or INT6). P76 can be
programmed as the timer flip-flop output (TB0OUT) from a 16-bit timer. P77 can be programmed as an
external interrupt request pin (INT0).
The P7CR and P7FC registers select the direction and function of the Port 7 pins. A reset sets the Output
Latch (P7) to all 1s, and clears the P7CR and P7FC register bits, configuring all Port 7 pins as input port
pins. When INT0 is used as a wake-up from STOP mode with the SYSCR2.DRVE bit cleared, the
P7FC.P77F bit must be set to 1.
Reset
Direction Control
(bitwise)
P7CR Write
Internal Data Bus
Function Control
(bitwise)
P7FC Write
S
Output Latch
A
S
P70 (TA0IN/TXD3)
P72 (TA2IN/TXD4)
Selector
P7 Write
TXD3, TXD4
Configurable as an
open-drain output
ODE.ODE70
ODE.ODE72
B
S
B
Selector
P7 Read
A
TA0IN
TA2IN
Figure 7.14 Port 7 (P70, P72)
TMP1941AF-48
2003-03-27
TMP1941AF
Reset
Direction Control
(bitwise)
P7CR Write
Internal Data Bus
Function Control
(bitwise)
P7FC Write
S
Output Latch
A
S
P71 (TA1OUT/RXD3)
P73 (TA3OUT/RXD4)
Selector
P7 Write
B
Timer Flip-Flop Output
TA1OUT: From TMRA01
TA3OUT: From TMRA23
S
B
Selector
A
P7 Read
RXD3
RXD4
Reset
Direction Control
(bitwise)
P7CR Write
Internal Data Bus
Function Control
(bitwise)
P7FC Write
S
Output Latch
P74 (TB0IN0/INT5)
P75 (TB0IN1/INT6)
P7 Write
S
B
Selector
P7 Read
A
TB0IN0
TB0IN1
INT5
INT6
Figure 7.15 Port 7 (P71, P73, P74, P75)
TMP1941AF-49
2003-03-27
TMP1941AF
Reset
Direction Control
(bitwise)
P7CR Write
Internal Data Bus
Function Control
(bitwise)
P7FC Write
S
Output Latch
A
S
P76 (TB0OUT)
Selector
P7 Write
B
Timer Flip-Flop Output
TB0OUT: From TMRB0
S
B
Selector
A
P7 Read
Reset
Direction Control
(bitwise)
P7CR Write
Internal Data Bus
Function Control
(bitwise)
P7FC Write
S
Output Latch
P77 (INT0)
P7 Write
S
B
Selector
P7 Read
A
(Note)
INT0
Level/Edge Sensitivity
Positive/Negative Polarity
IMCGA0.EMCG[01:00], IMCGA0.INT0EN
IMC0L.EIM1
Figure 7.16 Port 7 (P76, P77)
TMP1941AF-50
2003-03-27
TMP1941AF
P7
(0xFFFF_F02B)
P7CR
(0xFFFF_F02E)
Name
Read/Write
Reset Value
Name
Read/Write
Reset Value
Function
Port 7 Register
5
4
7
6
P77
P76
P75
P74
3
2
1
0
P73
P72
P71
P70
1
1
R/W
Input mode (The Output Latch is set to 1.)
1
1
1
1
1
1
7
6
P77C
P76C
0
0
Port 7 Control Register
5
4
P75C
P74C
3
2
1
0
P73C
P72C
P71C
P70C
0
0
0
0
W
0
0: IN
0
1: OUT
Port 7 Direction Settings
0
Input
1
Output
Port 7 Function Register
6
5
4
7
P7FC
(0xFFFF_F02F)
Name
P77F
P76F
P75F
Read/Write
Reset Value
0
0
0
Function
0: Port
0: Port
0: Port
1: Wake-up 1: TB0OUT 1: TB0IN1
INT0
INT0 Settings
P7FC.P77F
P7CR.P77C
P74F
3
2
1
0
P73F
P72F
P71F
P70F
W
0
0: Port
1: TB0IN0
0
0
0: Port
0: Port
1: TA3OUT 1: TA2IN
1: RXD4
1: TXD4
0
0
0: Port
0: Port
1: TA1OUT 1: TA0IN
1: RXD3
1: TXD3
1
0
Note: Required to exit STOP mode,
with SYSCR2.DRVE cleared.
Otherwise, unneeded.
TB0OUT Settings
P7FC.P76F
P7CR.P76C
1
1
TB0IN1 Settings
P7FC.P75F
P7CR.P75C
1
0
TB0IN0 Settings
P7FC.P74F
P7CR.P74C
1
0
RXD4 Settings
P7FC.P73F
P7CR.P73C
1
0
TA3OUT Settings
P7FC.P73F
P7CR.P73C
1
1
TA2IN Settings
P7FC.P72F
P7CR.P72C
1
0
TXD4 Settings
P7FC.P72F
P7CR.P72C
1
1
RXD3 Settings
P7FC.P71F
P7CR.P71C
1
0
TA1OUT Settings
P7FC.P71F
P7CR.P71C
1
1
TA0IN Settings
P7FC.P70F
P7CR.P70C
1
0
TXD3 Settings
P7FC.P70F
P7CR.P70C
1
1
Figure 7.17 Port 7 Registers
TMP1941AF-51
2003-03-27
TMP1941AF
7.9
Port 8 (P80–P87)
Eight Port 8 pins can be individually programmed to function as discrete general-purpose or dedicated I/O
pins. Upon reset, all Port 8 pins are configured as input port pins, and the Output Latch (P8) is set to all 1s.
Port 8 pins (except P87) can be programmed as clock inputs to 16-bit timers, timer flip-flop outputs from 16bit timers, or external interrupt request pins (INT7 through INTA).
Setting the P8FC register bits configures the Port 8 pins for dedicated functions. A reset clears all the
P8CR and P8FC register bits, configuring all Port 8 pins as input port pins.
TMP1941AF-52
2003-03-27
TMP1941AF
Reset
Direction Control
(bitwise)
P8CR Write
Function Control
(bitwise)
Internal Data Bus
P8FC Write
S
Output Latch
P8 Write
S
B
P80 (TB1IN0/INT7)
P81 (TB1IN1/INT8)
P83 (TB2IN0/INT9)
P84 (TB2IN1/INTA)
Selector
A
P8 Read
TB1IN0
TB1IN1
TB2IN0
TB2IN1
INT7
INT8
INT9
INTA
Reset
Direction Control
(bitwise)
P8CR Write
Internal Data Bus
Function Control
(bitwise)
P8FC Write
S
Output Latch
A
P82 (TB1OUT)
P85 (TB2OUT)
P86 (TB3OUT)
P87
Selector
P8 Write
Timer Flip-Flop Output
S
B
TB1OUT: From TMRB1
TB2OUT: From TMRB2
TB3OUT: From TMRB3
S
B
Selector
P8 Read
A
Figure 7.18 Port 8 (P80~P87)
TMP1941AF-53
2003-03-27
TMP1941AF
7
6
P87
P86
Port 8 Register
5
4
1
0
P83
P82
P81
P80
Name
(0xFFFF_F030)
Read/Write
R/W
Reset Value
Input mode (The Output Latch is set to 1.)
7
Name
(0xFFFF_F032)
Read/Write
P87C
P84
2
P8
P8CR
P85
3
Port 8 Control Register
6
5
4
P86C
P85C
P84C
3
2
1
0
P83C
P82C
P81C
P80C
0
0
0
0
W
Reset Value
0
0
0
Function
0
0: IN
1: OUT
Port 8 Direction Settings
0
Input
1
Output
Port 8 Function Register
P8FC
Name
(0xFFFF_F033)
Read/Write
6
5
4
3
2
1
0
P86F
P85F
P84F
P83F
P82F
P81F
P80F

0
0
0
0
0
W
Reset Value
Function
7

Must be
written as
0.
0: Port
0: Port
0: Port
1: TB3OUT 1: TB2OUT 1: TB2IN1
0
0: Port
1: TB2IN0
0: Port
0: Port
1: TB1OUT 1: TB1IN1
0
0: Port
1: TB1IN0
TB1OUT Settings
TB3OUT Settings
P8FC.P82F
1
P8CR.P82C
1
TB2OUT Settings
P8FC.P86F
1
P8FC.P85F
1
P8CR.P86C
1
P8CR.P85C
1
Figure 7.19 Port 8 Registers
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7.10 Port 9 (P90–P97)
•
P90–P95
P90–P95 can be individually programmed to function as discrete general-purpose or dedicated I/O
pins. Upon reset, P90–P95 are configured as input port pins, and the corresponding Output Latch (P9)
bits are set to 1.
Setting the bits in the P9FC register configures the corresponding pin for SIO input or output pins. A
reset clears the relevant P9CR and P9FC bits, configuring P90–P95 as input port pins.
•
P96–P97
P96 and P97 function as general-purpose I/O pins. As output ports, P96 and P97 are configured as
open-drain outputs.
Upon reset, the relevant Output Latch (P9) bits are set to 1, and the P9CR register bits are set, causing
P96 and P97 to assume the high-impedance state.
P96 and P97 can also be used as the XT1 and XT2 pins; in this case, a low-frequency crystal is
connected between XT1 and XT2 to provide for Dual-Clock mode, which is controlled through System
Clock Control Registers 0 and 1 (SYSCR0 and SYSCR1).
(1) P90 (TXD0) and P93 (TXD1)
P90 and P93 can be programmed to function as either general-purpose I/O pins or TXD output pins for
SIO channels. P90 and P93 are configurable as open-drain outputs.
Reset
Direction Control
(bitwise)
P9CR Write
Internal Data Bus
Function Control
(bitwise)
P9FC Write
S
Output Latch
A
S
Selector
TXD0, TXD1
P9 Write
P90 (TXD0)
P93 (TXD1)
B
S
B
Configurable as
open-drain outputs
ODE.ODE90
ODE.ODE93
Selector
P9 Read
A
Figure 7.20 Port 9 (P90, P93)
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(2) P91 (RXD0) and P94 (RXD1)
P91 and P94 can be programmed to function as either general-purpose I/O pins or RXD input pins for
SIO channels.
Reset
Direction Control
(bitwise)
Internal Data Bus
P9CR Write
S
P91 (RXD0)
P94 (RXD1)
Output Latch
S
B
P9 Write
Selector
A
P9 Read
RXD0, RXD1
Figure 7.21 Port 9 (P91, P94)
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(3) P92 (SCLK0/ CTS0 ) and P95 (SCLK1/ CTS1 )
P92 and P95 can be programmed to function as general-purpose I/O pins, or SCLK clock input or output
pins or CTS input pins for SIO channels.
Reset
Direction Control
(bitwise)
P9CR Write
Function Control
(bitwise)
Internal Data Bus
P9FC Write
S
Output Latch
A
P92 (SCLK0/ CTS0 )
P95 (SCLK1/ CTS1 )
Selector
P9 Write
SCLK0 and
SCLK1 outputs
S
B
S
B
Selector
P9 Read
A
CTS0 , CTS1
SCLK0, SCLK1
Figure 7.22 Port 9 (P92, P95)
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(4) P96 (XT1) and P97 (XT2)
P96 and P97 function as general-purpose I/O pins. Alternatively, P96 and P97 can be used as the XT1
and XT2 pins for connecting a low-frequency crystal.
Reset
S
Direction Control
(bitwise)
Low-Frequency Oscillator Enable
P9CR Write
S
P96 (XT1)
Output Latch
Output Buffer
(Open-drain)
P9 Write
S
B
Internal Data Bus
Y Selector
A
P9 Read
(Enabled when 1)
S
Direction Control
(bitwise)
P9CR Write
S
P97 (XT2)
Output Latch
Output Buffer
(Open-Drain)
P9 Write
Low-Frequency Clock
S
B
Y Selector
A
P9 Read
Figure 7.23 Port 9 (P96, P97)
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P9
(0xFFFF_F031)
P9CR
(0xFFFF_F034)
Name
Read/Write
Reset Value
Name
Read/Write
Reset Value
Function
Port 9 Register
5
4
7
6
P97
P96
P95
P94
3
2
1
0
P93
P92
P91
P90
1
1
R/W
Output mode
1
1
1
Input mode
1
1
1
Port 9 Control Register
5
4
7
6
P97C
P96C
1
1
P95C
0
0: IN
P94C
W
0
1: OUT
3
2
1
0
P93C
P92C
P91C
P90C
0
0
0
0
Port 9 Direction Settings
0
Input
1
Output
P9FC
(0xFFFF_F035)
Name
Read/Write
Reset Value
Function
CTS1 /SCLK1 Input Settings
P9FC.P95F
1
P9CR.P95C
0
7
Port 9 Function Register
6
5
4


P95F



0
0: Port
1: SCLK1
output or
CTS1 /
SCLK1
input

3
2
1
0
P93F
P92F

P90F
0
0: Port
1: SCLK0
output or
CTS0 /
SCLK0
input

0
0: Port
1: TXD0
W
0
0: Port
1: TXD1
SCLK1 Output Settings
P9FC.P95F
1
P9CR.P95C
1
TXD1 Output Settings
P9FC.P93F
P9CR.P93C
1
1
TXD0 Output Settings
P9FC.P90F
P9CR.P90C
CTS1 /SCLK0 Input Settings
P9FC.P92F
1
P9CR.P92C
0
1
1
SCLK0 Output Settings
P9FC.P92F
1
P9CR.P92C
1
Note 1:
Setting bit 0 of the Open-Drain Enable (ODE) register configures theTXD0 pin as an open-drain
output. Setting bit 1 of the ODE register configures the TXD1 pin as an open-drain output. See
Section 7.11.
The P91/RXD0 and P94/RXD1 pins do not have bits for selecting pin functions. These pins can
be continuously used as shared input port and serial data input pins.
Note 2:
Low-speed oscillator consideration
When a low-frequency crystal is connected between XT1 (P96) and XT2 (P97), the following
register settings are required to reduce power consumption:
When a crystal is connected between XT1 and XT2:
P9CR.P96C–P97C = 11
P9.P96–P97 = 00
When XT1 is driven with an external clock:
P9CR.P96C–P97C = 11
P9.P96–P97 = 10
Figure 7.24 Port 9 Registers
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7.11 Port A (PA0–PA7)
Eight Port A pins can be individually programmed to function as discrete general-purpose or dedicated I/O
pins. Upon reset, all Port A pins are configured as input port pins.
Alternatively, PA0–PA3 can be programmed as external interrupt request pins (INT1–INT4), and PA5–
PA7 as the Serial Bus Interface (SBI) pins.
Setting the PAFC register bits configures the corresponding Port 8 pins for dedicated functions. A reset
clears all the PACR and PAFC register bits, configuring all Port A pins as input port pins.
When INT1–INT4 are used as a wake-up from STOP mode with the SYSCR2.DRVE bit cleared, the
corresponding bits in the PAFC register must be set to 1.
Port A can act as an interface to the DSU ICE.
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Reset
Direction Control
(bitwise)
PACR Write
Internal Data Bus
Function Control
(bitwise)
PAFC Write
S
PA0–PA3
(INT1–INT4)
Output Latch
B
S
PA Write
Selector
A
PA Read
(Note)
Level/Edge Sensitivity
Positive/Negative Polarity
INT1–INT4
IMCGAx.EMCGx[1:0], IMCGAx.INTxEN
IMCxx.EIMx
Reset
Direction Control
(bitwise)
Internal Data Bus
PACR Write
S
PA4
Output Latch
S
B
PA Write
Selector
PA Read
A
Figure 7.25 Port A (PA0–PA4)
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Reset
Direction Control
(bitwise)
PACR Write
Internal Data Bus
Function Control
(bitwise)
PAFC Write
S
Output Latch
A
S
PA5 (SCK)
Selector
PA Write
B
SCK Output
S
B
Selector
A
PA Read
SCK Input
Reset
Direction Control
(bitwise)
PACR Write
Internal Data Bus
Function Control
(bitwise)
PAFC Write
S
Output Latch
A
S
PA6 (SO/SDA)
Selector
PA Write
Configurable as an
open-drain output
ODE.ODEA6
B
SO Output
S
B
Selector
PA Read
A
SDA Input
Figure 7.26 Port A (PA5–PA6)
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Reset
Direction Control
(bitwise)
PACR Write
Internal Data Bus
Function Control
(bitwise)
PAFC Write
S
Output Latch
A
PA7 (SI/SCL)
Selector
PA Write
SCL Output
S
Configurable as an
open-drain output
ODE.ODEA7
B
S
B
Selector
PA Read
A
SI Input
SCL Input
Figure 7.27 Port A (PA7)
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7
6
PA7
PA6
Port A Register
5
4
1
0
PA3
PA2
PA1
PA0
Name
(0xFFFF_F036)
Read/Write
R/W
Reset Value
Input mode (The Output Latch set to 1.)
7
Name
(0xFFFF_F038)
Read/Write
Reset Value
PA7C
PA4
2
PA
PACR
PA5
3
Port A Control Register
6
5
4
PA6C
PA5C
PA4C
3
2
1
0
PA3C
PA2C
PA1C
PA0C
0
0
0
0
W
0
0
Function
0
0
0: IN
1: OUT
Port A Direction Settings
0
Input
1
Output
Port A Function Register
PAFC
Name
(0xFFFF_F039)
Read/Write
Reset Value
Function
7
6
5
4
3
2
1
0
PA7F
PA6F
PA5F
PA4F
PA3F
PA2F
PA1F
PA0F
0
0
0
W
0: Port
1: SCL
output
0: Port
0: Port
1: SDA/SO 1: SCK
output
output
Must be
written as
0.
0: Port
0: Port
0: Port
0: Port
1: Wake-up 1: Wake-up 1: Wake-up 1: Wakeup INT1
INT2
INT3
INT4
input
input
input
input
Wake-up INT1–INT4 Input Settings
PAFC.PAxF
1
PACR.PAxC
0
Note: Required to exit STOP
mode, with SYSCR2.DRVE
cleared. Otherwise,
unneeded.
SCK Output Settings
PAFC.PA5F
1
PACR.PA5C
1
SDA/SO Output Settings
SCL Output Settings
PAFC.PA7F
1
PACR.PA7C
1
PAFC.PA6F
1
PACR.PA6C
1
Figure 7.28 Port A Registers
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7.12 Open-Drain Output Control
The TXD output pins (P70, P72, P90 and P93) of the SIO, and the SO/SDA (PA6) and SI/SCL (PA7) pins
of the Serial Bus Interface (SBI) can be configured as either push-pull or open-drain outputs.
7
Open-Drain Enable Register
6
5
4
ODE
Name


(0xFFFF_F050)
Read/Write


Reset Value


Function
3
2
1
0
ODE72
ODE70
ODEA7
ODEA6
ODE93
ODE90
0
0
0
R/W
P72
0: Pushpull
1: Opendrain
P70
0: Pushpull
1: Opendrain
PA7
0: Pushpull
1: Opendrain
0
PA6
0: Pushpull
1: Opendrain
0
P93
0: Pushpull
1: Opendrain
0
P90
0: Pushpull
1: Opendrain
Figure 7.29 Open-Drain Enable Register
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8.
External Bus Interface
The TMP1941AF contains external bus interface logic that handles the transfer of information between the
internal busses and the memory or peripherals in the external address space. It consists of the External Bus
Interface (EBIF) logic and the Chip Select/Wait Controller.
The CS/Wait Controller provides four programmable chip select signals, with variable block sizes. The chip
select function supports automatic wait-state generation and data bus sizing (8-bit or 16-bit) for each of the four
address blocks and the rest of the external address locations.
The EBIF logic controls the timing of the external bus, based on the settings of the CS/Wait Controller. The
EBIF logic also performs dynamic bus sizing and bus arbitration.
(1) Wait-state generation
Individually programmable for each address block
•
Automatic insertion of up to seven wait cycles
•
WAIT pin
(2) Data bus width
Individually programmable (8-bit or 16-bit) for each address block
(3) Read recovery cycles
Individually programmable (to up to 2 cycles) for each address block. Read recovery cycles are dummy
cycles inserted between two consecutive external bus cycles.
(4) ALE pulse width
Selectable ALE pulse width (0.5 or 1.5 cycles). This setting applies to all the address blocks.
(5) Bus arbitration
•
When AM0 = 0
The TMP1941AF has either a mixed 8/16-bit data bus or the 16-bit data bus. The program memory
accessed after reset must be connected with the TMP1941AF with a 16-bit data bus.
•
When AM1 = 1
The TMP1941AF has a 8-bit data bus. When AM1 is at logic 1, the data bus width settings in the Chip
Select/Wait Control registers are ignored.
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8.1
Address and Data Buses
8.1.1
Supported Configurations
For external memory interface, Port 0 (AD0–AD7), Port 1 (AD8–AD15/A8–A15) and Port 2 (A16–
A23/A0–A7) pins can be configured as the address and data buses. The TMP1941AF supports the
following four bus configurations.
When AM1 = 0 and AM0 = 1, the address and data buses are configured as shown in (1) below.
When AM1 = 0 and AM0 = 0, the address and data buses are configured as shown in (2) below.
Address Lines
(1)
(2)
24 Max (16 Mbytes)
24 Max (16 Mbytes)
Data Lines
8
16
Multiplexed
Address/Data Lines
8
16
Pin
Functions
Port 0
AD0–AD7
AD0–AD7
Port 1
A8–A15
AD8–AD15
Port 2
A16–A23
A16–A23
A23-8
AD7-0
A23-8
A7-0
D7-0
A23-16
AD15-0
A23-8
A15-0
D15-0
Timing Diagram
ALE
ALE
RD
RD
Note 1:
Because the data bus is multiplxed with the address bus, even in the C and D configurations, address bits
also appear on the AD bus prior to the data being accepted or provided.
Note 2:
Upon reset, all of Ports 0–2 are configured as general-purpose input ports; programming is required to use
them as address or data bus pins.
Note 3:
Address and data bus configurations are selectable through the programming of the P1CR, P1FC, P2CR
and P2FC registers.
8.1.2
States of the Address Bus During On-Chip Address Accesses
While an on-chip address is being accessed, the address bus maintains the previous address externally
presented. During this time, the address/data bus assumes the high-impedance state.
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8.2
External Bus Operation
This section describes external bus operations. In the timing diagrams which follow, A23–A16 is the
address bus, and AD15–AD0 is the address/data bus.
This section only provides a functional description of the bus; refer to Section 18, AC Electrical
Characteristics, for detailed timing specifications.
8.2.1
Basic Bus Operation
While the TMP1941AF provides a total of three clock cycles to perform a read or write, it also allows
the bus cycle to be extended by inserting wait states.
Figure 8.1 shows external bus read timing. Figure 8.2 shows external bus write timing. While an onchip address is being accessed, the external address bus maintains the previous value with the ALE pin
kept inactive. During this time, the address/data bus assumes the high-impedance state, and bus control
signals such as RD and WR remain inactive.
tsys
A[23:16]
No change
Hi-Z
AD[15:0]
ADR
DATA
ALE
Inactive
Inactive
RD
External access
Internal access
Figure 8.1 Read Cycle Timing
tsys
A[23:16]
AD[15:0]
No change
ADR
Hi-Z
DATA
ALE
Inactive
Inactive
WR
External access
Internal access
Figure 8.2 Write Cycle Timing
Note: tsys is the system clock period.
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8.2.2
Wait Timing
The CS/Wait Controller provides two ways to insert wait states in a bus cycle.
Each address block can be programmed either:
•
to insert required number of wait state cycles (up to seven cycles), or
•
to use the WAIT pin to insert wait states dynamically on a cycle basis
Following are bus cycle timing diagrams with wait states.
Wait State
tsys
Upper Address
A[23:16]
AD[15:0]
ADR
DATA
Upper Address
ADR
DATA
ALE
RD
0 Wait State
1 Wait State
Figure 8.3 Read Cycle Timing (with Zero and One Wait State Cycle)
Wait States
tsys
A[23:16]
AD[15:0]
Upper Address
ADR
DATA
Upper Address
ADR
DATA
ALE
RD
WAIT
0 Wait State
(1 + N Wait States; N = 1)
Figure 8.4 Read Cycle Timing (with 1 + N Wait States; N=1)
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Wait State
tsys
Upper Address
A[23:16]
AD[15:0]
ADR
Upper Address
DATA
ADR
DATA
ALE
WR
0 Wait State
1 Wait State
Figure 8.5 Write Cycle Timing (with Zero and One Wait State Cycle)
Wait States
tsys
Upper Address
A[23:16]
AD[15:0]
ADR
DATA
Upper Address
ADR
DATA
ALE
WR
WAIT
0 Wait State
1 + N Wait States; N=1
Figure 8.6 Write Cycle Timing (with 1 + N Wait State Cycles; N=1)
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8.2.3
ALE Pulse Width
The ALE pulse width is programmed to 0.5 or 1.5 clock cycles through the ALESEL bit of the
SYSCR3 register within the CG. The default is 1.5 cycles. This setting applies to the whole external
address space.
tsys
ALE (ALESEL = 0)
0.5 Clock Cycles
AD[15:0]
ALE (ALESEL = 1)
1.5 Clock Cycles
AD[15:0]
Figure 8.7 ALE Pulse Width
Figure 8.8 shows read cycle timing, with the ALE width programmed to 0.5 and 1.5 clock cycles.
tsys
A[23:16]
AD[15:0]
Upper Address
ADR
DATA
Upper Address
ADR
DATA
ALE
RD
ALE = 0. 5 Clock Cycles
ALE = 1. 5 Clock Cycles
Figure 8.8 Read Cycle Timing (ALE = 0.5 and 1.5 Clock Cycles)
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8.2.4
Read Recovery Time
Following an external bus read cycle, a certain recovery time may be required before initiating the
next external bus cycle. To allow for a read recovery time, one or two dummy cycles can be inserted
between back-to-back bus cycles. (Dummy cycles can only be inserted immediately after a read.)
•
Between an external read and an external read:
Programmable
•
Between an external read and an external write:
Programmable
•
After an external write:
No dummy cycle
Dummy cycle insertion is programmable in the CS/Wait Controller.
tsys
RD
AD[15:0]
Read Data
Next ADR
ALE
AD[15:0]
Read Data
Next ADR
ALE
Two Dummy Cycles
Figure 8.9 Read Recovery Time
Dummy cycles insert idle cycles between transfers to enable slow off-chip peripherals to remove data
from the data bus before the next transfer begins. This provides a sufficient time after the RD strobe
for the previous read is deasserted until the address for the next read or write is placed on the address
bus. Figure 8.10 shows bus cycle timing with one and two dummy cycles inserted into bus cycles.
Dummy
Dummy
tsys
Upper Address
A[23:16]
AD[15:0]
DATA
DATA
ADR
ADR
ALE
RD
1 Dummy Cycle
2 Dummy Cycles
Figure 8.10 Read Cycle Timing (with Dummy Cycles Inserted)
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8.3
Bus Arbitration
The TMP1941AF provides support for an external bus master to take control of the external bus. Two bus
arbitration control signals, BUSRQ and BUSAK , are used to determine the bus master. One or more of the
external devices on the bus can have the capability of becoming bus master for the external bus, but not the
TMP1941AF internal bus.
8.3.1
Bus Access Control
External bus masters can gain control of the external bus, but not the TMP1941AF internal bus (GBus). Thus, external bus masters cannot access the TMP1941AF’s on-chip memory and peripherals.
The External Bus Interface (EBIF) logic in the TMP1941AF manages the arbitration of the external
bus; the CPU and on-chip DMAC do not participate in any way in this bus arbitration. During external
bus mastership, the CPU and the on-chip DMAC can access the internal memory (RAM and ROM) and
registers.
Once an external device assumes bus mastership, the CPU or the on-chip DMAC has no way to
regain the bus until the external bus master releases the bus. If the CPU or the on-chip DMAC issues an
external memory access request, it is forced to wait until the TMP1941AF regains the bus. Therefore,
should BUSRQ be left asserted for a long time, the TMP1941AF might suffer system lockups.
8.3.2
Bus Arbitration Flow
External devices capable of becoming bus masters assert BUSRQ to request the bus. The
TMP1941AF samples BUSRQ at the end of each external bus cycle, as seen on its internal bus (GBus). When the TMP1941AF has made an internal decision to grant the bus, it asserts BUSAK to
indicate to the requesting device that the bus is available. At the same time, the TMP1941AF puts the
address bus, the data bus and bus control signals in the high-impedance state.
A load or store may require multiple bus cycles, depending on the port size of the addressed device
(dynamic bus sizing). In that case, the TMP1941AF does not grant the bus until the entire transfer is
complete.
The TMP1941AF, if so programmed, automatically inserts dummy cycles between back-to-back bus
cycles to allow for sufficient read recovery time. In dummy cycles, the TMP1941AF has already
internally initiated a bus cycle on the G-Bus for the next external access. The TMP1941AF can only
accept an external bus request at the boundary of an internal G-Bus bus cycle. Therefore, if BUSRQ is
asserted during a dummy cycle, the TMP1941AF grants the bus after it completes the next external bus
cycle.
An external bus master must keep BUSRQ asserted until it is granted the bus.
A timing diagram of the bus arbitration sequence is shown in Figure 8.11.
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1
2
3
Internal clock
Internal address
External address
TMP1941AF external access
TMP1941AF
TMP1941AF external access
External bus master
TMP1941AF
BUSRQ
BUSAK
Figure 8.11 Bus Arbitration Timing Diagram
1. BUSRQ is sampled high.
2. The TMP1941AF recognizes the assertion of BUSRQ .
3. The TMP1941AF asserts BUSAK at the completion of the current bus cycle. The external bus
master recognizes BUSAK and assumes bus mastership to start a bus transfer.
8.3.3
Relinquishing the bus
When the external bus master has completed its bus transactions, it deasserts BUSRQ to relinquish
the bus to the TMP1941AF. Figure 8.12 shows the timing for an external bus master to relinquish the
bus.
1
2 3
Internal clock
Internal address
External address
TMP1941AF external access
TMP1941AF
TMP1941AF external
‡ @‡ A‡ access
B
External bus masters
TMP1941AF
BUSRQ
BUSAK
Figure 8.12 External Bus Master Relinquishing the Bus
1. The external bus master has control of the bus.
2. When the external bus master no longer needs the bus, it deasserts BUSRQ .
3. In response to the deassertion of BUSRQ , the TMP1941AF deasserts BUSAK .
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9.
Chip Select/Wait Controller
The TMP1941AF supports direct connections to ROM and SRAM devices.
The TMP1941AF provides four programmable chip select signals. Programmable features include variable
block sizes, data bus width, wait state insertion, and dummy cycle insertion for back-to-back bus cycles.
CS0 – CS3 (multiplexed with P40–P43) are the chip select output pins for the CS0–CS3 address ranges.
These chip select signals are generated when the CPU or on-chip DMAC issues an address within the
programmed ranges. The P40–P43 pins must be configured as CS0 – CS3 by programming the Port A Control
(P4CR) register and the Port 4 Function (P4FC) register.
Chip select address ranges are defined in terms of a base address and an address mask. There is a Base/Mask
Address (BMAn) register for each of the four chip select signals, where n is a number from 0 to 3.
There is also a set of three Chip Select/Wait Control registers, B01CS, B23CS and BEXCS, each of which
consists of a master enable bit, a data bus width bit, a wait state field and a dummy cycle field.
External memory devices can also use the WAIT pin to insert wait states and consequently prolong read and
write bus cycles.
9.1
Programming Chip Select Ranges
Each of the four chip select address ranges is defined in the BMAn register. The basic chip select model
allows one of the chip select output signals ( CS0 – CS3 ) to assert when an address on the address bus falls
within a particular programmed range. The B01CS register defines specific operations for CS0 and CS1 ,
and the B23CS register defines specific operations for CS2 and CS3 (see Section 9.2).
9.1.1
Base/Mask Address Registers (BMA0–BMA3)
The organizations of the BMAn registers are shown in Figure 9.1 and Figure 9.2. The base address
(BAn) field specifies the starting address for a chip select. Any set bit in the address mask field (MAn)
masks the corresponding base address bit. The address mask field determines the block size of a
particular chip select line. The address is compared on every bus cycle.
(1) Base address
The base address (BAn) field specifies the upper 16 bits (A31–A16) of the starting address for a
chip select. The lower 16 bits (A15–A0) are assumed to be zero. Thus, the base address is any
multiple of 64 Kbytes starting at 0x0000_0000. Figure 9.3 shows the relationships between starting
addresses and the BMAn values.
(2) Address mask
The address mask field defines whether any particular bits of the address should be compared or
masked. Any set bit masks the corresponding base address bit. The address compare logic uses
only the address bits that are not masked (i.e., mask bit cleared to 0) to detect an address match.
Address bits that can be masked (i.e., supported block sizes) differ for the four chip select spaces as
follows:
CS0 and CS1 spaces:
A29–A14
CS2 and CS3 spaces:
A30–A15
The address mask field defines the block size of a particular chip select line.
Note: Use physical addresses in the BMAn registers.
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7
BMA0
Name
(0xFFFF_E400)
Read/Write
Base/Mask Address Registers
6
5
4
2
1
0
1
1
1
MA0 (A29 – A14)
Reset Value
R/W
1
Function
1
1
CS0 block size
15
14
1
1
0: The address compare logic uses this address bit.
13
Name
12
11
10
9
8
0
0
1
1
19
18
17
16
0
0
0
0
MA0 (A29 – A14)
Read/Write
Reset Value
R/W
0
0
23
22
Function
0
0
Must be written as 0.
21
20
Name
BA0
Read/Write
R/W
Reset Value
0
0
0
Function
0
A23–A16 of the starting address for CS0
31
30
29
28
Name
BA0
Read/Write
R/W
Reset Value
0
0
0
Function
0
27
26
25
24
0
0
0
0
2
1
0
1
1
1
A31–A24 of the starting address for CS0
7
BMA1
Name
(0xFFFF_E404)
Read/Write
6
5
4
3
MA1 (A29 – A14)
Reset Value
R/W
1
Function
1
1
CS1 block size
15
14
1
1
0: The address compare logic uses this address bit.
13
Name
12
11
10
9
8
0
0
1
1
19
18
17
16
0
0
0
0
MA1 (A29 – A14)
Read/Write
Reset Value
R/W
0
0
Function
0
0
Must be written as 0.
23
22
21
20
Name
BA1
Read/Write
Reset Value
R/W
0
0
Function
0
0
A23–A16 of the starting address for CS1
31
30
29
28
Name
BA1
Read/Write
R/W
Reset Value
Function
3
0
0
0
0
27
26
25
24
0
0
0
0
A31–A24 of the starting address for CS1
Note: Bits 10–15 in the BMA0 and BMA1 must be written as zeros. The CS0 and CS1 block sizes can
vary from 16 Kbytes to 1 Gbytes. However, the TMP1941AF supports only 16 Mbytes of external
address space. Therefore, bits 10–15 in the BMA0 and BMA1 must be cleared so that A24–A29 of
an address will not be masked.
Figure 9.1 Base/Mask Address Registers (BMA0 and BMA1)
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7
BMA2
Name
(0xFFFF_E408)
Read/Write
6
5
4
1
1
CS2 block size
0
15
14
1
1
1
1
1
0: The address compare logic uses this address bit.
13
Name
12
11
10
9
8
0
0
0
1
19
18
17
16
0
0
0
0
MA2 (A30 – A15)
Read/Write
Reset Value
R/W
0
0
0
23
22
21
Function
0
Must be written as 0.
20
Name
BA2
Read/Write
Reset Value
R/W
0
0
0
Function
0
A23–A16 of the starting address for CS2
31
30
29
28
Name
BA2
Read/Write
R/W
Reset Value
0
0
0
Function
0
27
26
25
24
0
0
0
0
2
1
0
1
1
1
A31–A24 of the starting address for CS2
7
6
5
Name
4
3
MA3 (A30 – A15)
Read/Write
Reset Value
R/W
1
Function
1
1
CS3 block size
15
14
1
1
0: The address compare logic uses this address bit.
13
Name
12
11
10
9
8
0
0
0
1
19
18
17
16
0
0
0
0
MA3 (A30 – A15)
Read/Write
Reset Value
R/W
0
0
0
Function
0
Must be written as 0.
23
22
21
20
Name
BA3
Read/Write
Reset Value
R/W
0
0
31
30
Function
0
0
A23–A16 of the starting address for CS3
29
28
Name
BA3
Read/Write
R/W
Reset Value
Function
1
R/W
1
Function
(0xFFFF_E40C)
2
MA2 (A30 – A15)
Reset Value
BMA3
3
0
0
0
0
27
26
25
24
0
0
0
0
A31–A24 of the starting address for CS3
Note: Bits 9–15 in the BMA2 and BMA3 must be written as zeros. The CS2 and CS3 block sizes can
vary from 32 Kbytes to 1 Gbytes. However, the TMP1941AF supports only 16 Mbytes of external
address space. Therefore, bits 9–15 in the BMA0 and BMA1 must be cleared so that A24–A30 of
an address will not be masked.
Figure 9.2 Base/Mask Address Registers (BMA2 and BMA3)
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Address
0xFFFF_FFFF
0x0000_0000
Starting Address
64 Kbytes
Base Address Value (BAn)
0xFFFF_0000
FFFF
0x0006_0000
0006
0x0005_0000
0005
0x0004_0000
0004
0x0003_0000
0003
0x0002_0000
0002
0x0001_0000
0001
0x0000_0000
0000
Figure 9.3 Relationships Between Starting Addresses and Base Address Register Values
9.1.2
Base Address and Address Mask Value Calculations
•
Program the BMA0 register as follows to cause CS0 to be asserted in the 64 Kbytes of address
space starting at 0xC000_0000.
31
16 15
0
BA0
MA0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
C
0
0
0
0
0
0
3
BMA0 Register Value
The BA0 field specifies the upper 16 bits of the starting address, or 0xC000. The MA0 field
determines whether the A29–A14 bits of the address should be compared or masked. The A31 and
A30 bits are always compared. Bits 15–10 of the MA0 field must be cleared so that the A29–A24
bits are always compared.
When the BMA0 register is programmed as shown above, the A31–A16 bits of the address are
compared to the value of the BA0 field. Consequently, the 64-Kbyte address range between
0xC000_0000 and 0xC000_FFFF is defined as the CS0 space.
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•
Program the BMA2 register as follows to cause CS2 to be asserted in the 512 Kbytes of address
space starting at 0x1FC8_0000.
31
16 15
0
BA2
MA2
0 0 0 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
1
F
C
8
0
0
0
F
BMA2 Register Value
The BA2 field specifies the upper 16 bits of the starting address, or 0x1FC8. The MA2 field
determines whether the A30–A15 bits of the address should be compared or masked. The A31 bit
is always compared. Bits 15–9 of the MA2 field must be cleared so that the A30–A24 bits are
always compared.
When the BMA2 register is programmed as shown above, the A31–A19 bits of the address are
compared to the value of the BA2 field. Consequently, the 512-Kbyte address range between
0x1FC8_0000 and 0x1FCF_FFFF is defined as the CS2 space.
•
Program the BMA2 register as follows to cause CS2 to be asserted in the 1 Mbytes of address
space starting at 0x1FC8_0000.
31
16 15
0
BA2
MA2
0 0 0 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
1
F
C
8
0
0
1
F
BMA2 Register Value
The BA2 field specifies the upper 16 bits of the starting address, or 0x1FC8. The MA2 field
determines whether the A30–A15 bits of the address should be compared or masked. The A31 bit
is always compared. Bits 15–9 of the MA2 field must be cleared so that the A30–A24 bits are
always compared.
When the BMA2 register is programmed as shown above, the A31–A20 bits of the address are
compared to the value of the BA2 field. Note, however, that the 512-Kbyte range between
0x1FC0_0000 and 0x1FC7_FFFF is reserved for the on-chip ROM. Consequently, the 512Kbyte
address range between 0x1FC8_0000 and 0x1FCF_FFFF is defined as the CS2 space.
Note:
The TMP1941AF does not assert any CSn signal in the following address ranges:
0xFFFF_8000 through 0xFFFF_BFFF
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Table 9.1 shows the programmable block sizes for CS0 to CS3. Even if the user has accidentally
programmed more than one chip select line to the same area, only one chip select line is driven because
of internal line priorities. CS0 has the highest priority, and CS3 the lowest.
Example:
The starting address of the CS0 space is progammed as 0xC000_0000 with a size of 16 Kbytes.
The starting address of the CS1 space is programmed as 0xC000_0000 with a size of 64 Kbytes.
CS0 Space
CS1 Space
0xC000_FFFF
0xC000_3FFF
0xC000_3FFF
0xC000_0000
0xC000_0000
When an attempt is made to
access the overlapping area,
the CS0 area is selected.
Table 9.1 Supported Block Sizes
CS Space
Size (bytes)
16 K
32 K
64 K 128 K 256 K 512 K
1M
2M
4M
8M
16 M
CS0
✓
✓
✓
✓
✓
CS1
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
CS2
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
CS3
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
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9.2
Chip Select/Wait Control Registers
The organizations of the Chip Select/Wait Control registers are shown in Figure 9.4 to Figure 9.5. Each of
these registers consist of a chip select type field, a master enable bit, a data bus width bit, a wait state field
and a dummy cycle field.
The B01CS register defines the CS0 and CS1 lines; the B23CS register defines the CS2 and CS3 lines;
and the BEXCS register defines the access characteristics for the rest of the address locations.
7
B01CS
Name
(0xFFFF_E480)
Read/Write
Reset Value
Function
Chip Select/Wait Control Registers
6
5
4
3
B0OM

W

0
0

0
0
1
15
14
13
12
11
10




B0E

Read/Write




W

Reset Value




0

CS0
enable
Function
Read/Write
Reset Value
Function
0
22
21
20
B1OM

B1BUS
W

0

1
19
9
8
B0RCV
W
0
0
18
17
16
0
1
B1W
W
0
Data bus
width
0: 16-bit
1: 8-bit
Chip select output
waveform
00: ROM/RAM
Don’t use any other
value.
0
Number of dummy
cycles (Read recovery
time)
00: 2 dummy cycles
01: 1 dummy cycle
10: No dummy cycle
11: Don’t use.
0: Disable
1: Enable
23
0
Number of wait-state cycles
0000: No wait state, 0001: 1 wait state
0010: 2 wait states, 0011: 3 wait states
0100: 4 wait states, 0101: 5 wait states
0110: 6 wait states, 0111: 7 wait states
1111: (1+N) wait states, as determined by the
WAIT pin
Don’t use any other value.
Name
Name
1
B0W
W
Data bus
width
0: 16-bit
1: 8-bit
Chip select output
waveform
00: ROM/RAM
Don’t use any other
value.
2
B0BUS
0
1
Number of wait-state cycles
0000: No wait state, 0001: 1 wait state
0010: 2 wait states, 0011: 3 wait states
0100: 4 wait states, 0101: 5 wait states
0110: 6 wait states, 0111: 7 wait states
1111: (1+N) wait states, as determined by the
WAIT pin
Don’t use any other value.
31
30
29
28
27
26
Name




B1E

Read/Write




W

Reset Value




0

Function
CS1
enable
0: Disable
1: Enable
25
24
B1RCV
W
0
0
Number of dummy
cycles (Read recovery
time)
00: 2 dummy cycles
01: 1 dummy cycle
10: No dummy cycle
11: Don’t use.
Figure 9.4 Chip Select/Wait Control Registers
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7
B23CS
Name
(0xFFFF_E484)
Read/Write
Reset Value
Function
6
5
4
B2OM

B2BUS
W

0
2
0
Data bus
width
0: 16-bit
1: 8-bit
0
1
13
12
11
10
Name




B2E
B2M
Read/Write




Reset Value




Function
1
CS2
enable
21
20
Name
B3OM

B3BUS
Read/Write
W

W
Function
0

0
0
8
B2RCV
0
0
0
17
18
16
B3W
1
0
1
Number of wait-state cycles
0000: No wait state, 0001: 1 wait state
0010: 2 wait states, 0011: 3 wait states
0100: 4 wait states, 0101: 5 wait states
0110: 6 wait states, 0111: 7 wait states
1111: (1+N) wait states, as determined by the
WAIT pin
Don’t use any other value.
31
30
29
28
27
Name




B3E

Read/Write




W

Reset Value




0

Function
9
CS2 space Number of dummy
cycles (Read recovery
select
time)
00: 2 dummy cycles
0: Whole
4-Gbyte 01: 1 dummy cycle
space
10: No dummy cycle
1: CS
11: Don’t use.
space
19
0
Data bus
width
0: 16-bit
1: 8-bit
Chip select output
waveform
00: ROM/RAM
Don’t use any other
value.
1
W
0: Disable
1: Enable
Reset Value
0
Number of wait-state cycles
0000: No wait state, 0001: 1 wait state
0010: 2 wait states, 0011: 3 wait states
0100: 4 wait states, 0101: 5 wait states
0110: 6 wait states, 0111: 7 wait states
1111: (1+N) wait states, as determined by the
WAIT pin
Don’t use any other value.
14
22
0
B2W
15
23
1
W

0
Chip select output
waveform
00: ROM/RAM
Don’t use any other
value.
3
CS3
enable
0: Disable
1: Enable
26
25
24
B3RCV
W
0
0
Number of dummy
cycles (Read recovery
time)
00: 2 dummy cycles
01: 1 dummy cycle
10: No dummy cycle
11: Don’t use.
Figure 9.5 Chip Select/Wait Control Registers
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7
6
5
4
BEXCS
Name
BEXOM
BEXBUS
(0xFFFF_E488)
Read/Write
W
W
Reset Value
Function
0
0
14
13
2
1
0
BEXW
0
0
Data bus
width
0: 16-bit
1: 8-bit
Chip select output
waveform
00: ROM/RAM
Don’t use any other
value.
15
3
1
0
1
Sets the number of Wait cycles
0000–0111: 0–7 wait states
1111: (1 + N) wait states, as determined by the
WAIT pin
Don’t use any other value.
12
11
10
9
8
Name
BEXRCV
Read/Write
W
Reset Value
0
Function
0
Number of dummy
cycles (Read recovery
time)
00: 2 dummy cycles
01: 1 dummy cycle
10: No dummy cycle
11: Don’t use.
Figure 9.6 Chip Select/Wait Control Registers
9.3
Application Example
Figure 9.7 shows an example usage of the TMP1941AF programmable chip selects. In this example, 128
Kbytes of ROM and 256 Kbytes of RAM are connected off-chip through a 16-bit data bus.
TMP1941AF
A16–17
Latch × 16
ROM (128 Kbits × 16)
A16
A1–15
AD8–15
D Q
AD0–7
LE
ALE
CS2
A16–17
A1–15
RD
HWR
CS1
WR
A16–17
A1–15
AM1
AM0
A15
A0–14
OE
CE
D8–15
D0–7
RAM (128 Kbits × 8)
A15–16
A0–14
OE
R/W
Upper Byte
CE1
I/O1–8
RAM (128 Kbits × 8)
A15–16
A0–14
OE
R/W
Lower Byte
CE1
I/O1–8
Figure 9.7 External Memory Connections (ROM Width = 16 bits, RAM Width = 16 bits)
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10. DMA Controller (DMAC)
The TMP1941AF contains a four-channel DMA controller.
10.1 Features
The TMP1941AF DMAC has the following features:
(1) Four independent DMA channels
(2) Two types of bus requests, with and without bus snooping
(3) Transfer requests:
Internal transfer requests: Software initiated
External transfer requests: Hardware signals from on-chip peripherals and external interrupt pins
(4) Dual-address mode
(5) Memory-to-memory, memory-to-I/O, and I/O-to-memory transfers
(6) Transfer width:
•
Memory: 32-bit (8-bit and 16-bit memory devices are supported through the programming of the
CS/Wait Controller.)
•
I/O peripherals: 8-, 16-, and 32-bit
(7) Address pointers can increment, decrement or remain constant. The user can program the bit positions
at which address incrementation or decrementation occurs.
(8) Fixed channel priority
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10.2 Implementation
10.2.1
On-Chip DMAC Interface
Figure 10.1 shows how the DMAC is internally connected with the TX19 core processor and the
Interrupt Controller (INTC).
INTDREQ[3:0] †
TX19
Core Processor
Bus Grant
DACK[3:0] †
DMAC
Interrupt
Controller
(INTC)
External Interrupt
Requests
On-Chip I/O Peripheral
Interrupt Requests†
BUSGNT †
Bus Request
BUSREQ †
BUSREL †
Bus Release Request
Bus Grant Ackowledge
HAVEIT †
Control
Address
Data
† Internal signals
Figure 10.1 DMAC Connections within the TMP1941AF
The DMAC provides four independently programmable channels. With each DMA channel, there are
two associated signals: a DMA request (INTDREQn) and a DMA acknowledge ( DACKn ), where n is
a channel number from 0 to 3. INTDREQn is an input to the DMAC coming from the INTC, and
DACKn is an output signal from the DMAC going to the INTC.
Channel priority is fixed. Channel 0 has the highest priority, and Channel 3 has the lowest priority.
The TX19 core processor supports bus snooping. When snooping is enabled, the TX19 core
processor grants the processor data bus to the DMAC, so that the DMAC can access the on-chip RAM
connected to the processor. Snooping can be enabled and disabled under software control. The DMAC
bus snooping is discussed in the next subsection in more details.
There are two bus request signals from the DMAC going to the TX19 core processor, SREQ and
GREQ. GREQ is a bus request without snooping. SREQ is a bus request with snooping.
Note: DMA channel priority exists only among those using the same type of bus request signal (SREQ
or GREQ). For example, once a given DMA channel has acquired bus mastership using SREQ, no
other DMA channel can assume bus mastership using GREQ until the ongoing DMA transaction is
completed.
TMP1941AF-85
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10.2.2
DMAC Block
The DMAC block diagram is shown in Figure 10.2.
Channel 3
Channel 2
Channel 1
0
Source ƒ A
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ƒŒ
ƒ XR egisuter
0
31
ƒf
ƒX
ƒe
ƒB
ƒl[
ƒV
ƒ‡
ƒ “ƒ A
ƒh
ƒŒ
ƒ Xƒ Œ
ƒƒ
WX
ƒ^
Source
Address
Register
(SARn)
B yt
e C ount
ƒŒ
ƒ
ƒX
W
ƒ^
Destination Address Register (DARn)
ƒ `
ƒ ƒ l
ƒ ‹ƒ R
ƒ “
ƒ ƒ
g [
ƒ ‹ƒ Œ
ƒW
Register
atus ƒ(BCRn)
ƒƒ
`Byte
ƒ Count
ƒ ‹St
l
ƒƒ
Œ
WX
ƒ^
Control Register (CCRn)
ƒX
ƒChannel
^
31
Channel
0
Channel Status Register (CSRn)
DMA Transfer Control Register (DTCRn)
DMA Control Register (DCR)
Data Holding Register (DHR)
Figure 10.2 DMAC Block Diagram
10.2.3
Bus Snooping
The TX19 core processor supports snoop operations.
If snooping is enabled, the TX19 core processor grants the processor data bus to the DMAC. Because
the DMAC takes control of the processor data bus, the TX19 stops operating during snoop operations
until the DMAC relinquishes the bus to the processor. Snooping allows the DMAC to access the onchip RAM, and thus to use them as a DMA source or destination device.
The DMAC allows the enabling and disabling of the snooping function by software.
If snooping is disabled, the DMAC can not access the on-chip RAM. However, regardless of whether
snooping is enabled or disabled, the DMAC assumes mastership of the TMP1941AF on-chip bus (GBus) during DMA transfers. Therefore, as long as DMA transfers are in progress, the TX19 core
processor can not access memory or I/O peripherals via the G-Bus; any attempt to do so causes the
processor pipeline to stall.
Note: If snooping is disabled, the TX19 core processor does not grant mastership of the processor data
bus to the DMAC. Therefore, if the on-chip RAM is specified as a source or destination for DMA
transfers, a DMA acknowledge signal will never be returned, causing bus lockup.
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10.3 Register Description
The DMAC has twenty-six 32-bit registers. The DMAC register map is shown in Table 10.1.
Table 10.1 DMAC Registers
Address
Symbol
Register Name
0xFFFF_E200
CCR0
Channel Control Register (Ch. 0)
0xFFFF_E204
CSR0
Channel Status Register (Ch. 0)
0xFFFF_E208
SAR0
Source Address Register (Ch. 0)
0xFFFF_E20C
DAR0
Destination Address Register (Ch. 0)
0xFFFF_E210
BCR0
Byte Count Register (Ch. 0)
0xFFFF_E218
DTCR0
0xFFFF_E220
CCR1
0xFFFF_E224
CSR1
Channel Status Register (Ch. 1)
0xFFFF_E228
SAR1
Source Address Register (Ch. 1)
0xFFFF_E22C
DAR1
Destination Address Register (Ch. 1)
0xFFFF_E230
BCR1
Byte Count Register (Ch. 1)
0xFFFF_E238
DTCR1
0xFFFF_E240
CCR2
0xFFFF_E244
CSR2
Channel Status Register (Ch. 2)
0xFFFF_E248
SAR2
Source Address Register (Ch. 2)
0xFFFF_E24C
DAR2
Destination Address Register (Ch. 2)
0xFFFF_E250
BCR2
Byte Count Register (Ch. 2)
0xFFFF_E258
DTCR2
0xFFFF_E260
CCR3
0xFFFF_E264
CSR3
Channel Status Register (Ch. 3)
0xFFFF_E268
SAR3
Source Address Register (Ch. 3)
DMA Transfer Control Register (Ch. 0)
Channel Control Register (Ch. 1)
DMA Transfer Control Register (Ch. 1)
Channel Control Register (Ch. 2)
DMA Transfer Control Register (Ch. 2)
Channel Control Register (Ch. 3)
0xFFFF_E26C
DAR3
Destination Address Register (ch. 3)
0xFFFF_E270
BCR3
Byte Count Register (Ch. 3)
0xFFFF_E278
DTCR3
0xFFFF_E280
DCR
DMA Control Register (All channels)
0xFFFF_E28C
DHR
Data Holding Register (All channels)
DMA Transfer Control Register (Ch. 3)
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10.3.1
31
DMA Control Register (DCR)
30
16
Rst
0
: Read/Write
W
15
0
0
: Read/Write
Bits
Mnemonic
31
Rst
Field Name
Reset
Description
Performs a software reset of the DMAC. When the Rst bit is set to 1, all the DMAC
internal registers are initialized to their reset values. Any transfer requests are
removed and all the four DMA channels are put in Idle state.
0: Don’t-care
1: Resets the DMAC.
Note 1: When the snoop request is disabled (CCRn.SReq=0), a software reset of the DMAC must be performed in the
following sequence:
1. Disable interrupts.
2. Execute NOP four times.
3. Perform a software reset.
4. Perform a software reset again.
5. Re-enable interrupts.
Execute steps 3 and 4 consecutively.
Note 2: If the software reset command is written to the DCR register immediately after the completion of the last transfer
cycle of a DMA transaction, the DMA-done interrupt will not be cleared. In this case, the software reset only
initializes channel registers, etc.
Note 3: Don’t issue a software reset command to the DCR register via a DMA transfer.
Figure 10.3 DMA Control Register (DCR)
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10.3.2
31
Channel Control Registers (CCRn)
30
25
Str
0
W
21
20
19
18
17
16

NIEn
AblEn




Big

W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
0
0
0
1
6
5
4
3
2
1
7
0
: Reset Value
14
13
12
PosE
Lev
Sreq ReIEN
SIO
SAC
DIO
DAC
TrSiz
DPS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
: Read/Write
0
0
0
0
0
0
0
00
0
00
00
00
: Reset Value
Str
8
R/W : Read/Write
ExR
31
9
22

Mnemonic
10
23
15
Bits
11
24
Field Name
Channel Start
0
Description
Reset value: 
Enables a DMA channel. Setting this bit puts the DMA channel in Ready state. DMA
transfer starts as soon as a transfer request is received.
Only a write of 1 is valid, and a write of 0 has no effect on this bit. A 0 is returned on
read.
1: Enables a DMA channel.
24

Reserved
This bit is reserved and must be written as 0.
23
NIEn
Normal
Completion
Interrupt Enable
Reset value = 1
1: Enables an interrupt when the channel finishes a transfer without an error condition.
0: Does not enable an interrupt when the channel finishes a transfer without an error
condition.
22
AbIEn
Abnormal
Termination
Interrupt Enable
Reset value = 1
1: Enables an interrupt when the channel encounters a transfer error.
0: Does not enable an interrupt when the channel encounters a transfer error.
21

Reserved
This bit is reserved and must be written as 0.
20

Reserved
This bit is reserved and must be written as 0.
19

Reserved
This bit is reserved and must be written as 0.
18

Reserved
This bit is reserved and must be written as 0.
17
Big
Big-Endian
Reset value = 1
1: The DMA channel operates in big-endian mode.
0: The DMA channel operates in little-endian mode.
In the TMP1941AF, this bit must be cleared to 0.
16

Reserved
This bit is reserved and must be written as 0.
15

Reserved
This bit is reserved and must be written as 0.
14
ExR
External Request
Mode
Reset value = 0
Selects a transfer request mode.
1: External transfer requests (interrupt-driven)
0: Internal transfer requests (software-initiated)
13
PosE
Positive Edge
Reset value = 0
Defines the polarity of the internal DMA request signal (INTDREQn) for the channel.
This bit is valid for external transfer requests (i.e., when ExR=1), and has no effect on
internal transfer requests (i.e., when ExR=0).
In the TMP1941AF, the PosE bit must be cleared, and the Lev bit must be set.
12
Lev
Level Mode
Reset value = 0
Specifies whether external transfer requests are level-senstiive or edge-triggered.
This bit is valid for external transfer requests (i.e., when ExR=1), and has no effect on
internal transfer requests (i.e., when ExR=0).
In the TMP1941AF, this bit must be set.
Figure 10.4 Channel Control Registers (CCRn) (1/2)
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Bit
Mnemonic
Field Name
Description
11
SReq
Snoop Request
Reset value = 0
Controls whether or not to request bus mastership with snooping. If set, the TX19
core processor’s snoop function becomes valid, allowing the DMAC to use the
processor’s data bus. If cleared, the snoop function is disabled.
1: The snoop function is enabled (i.e., SREQ is used as a bus request signal).
0: The snoop function is disabled (i.e., GREQ is used as a bus request signal).
10
RelEn
Bus Release
Request Enable
Reset value = 0
Controls whether or not to respond to the bus release request signal from the TX19
core processor. This bit is valid when the DMAC uses GREQ as a bus request signal.
This bit has no meaning or effect when the DMAC uses SREQ as a bus request
signal because, in that case, the TX19 core processor does not have the capability to
generate a bus release request signal.
1: The DMAC will respond to the bus release request signal from the TX19 core
processor, if it has control of the bus. The DMAC will relinquish the bus when the
current DMA bus cycle completes.
0: The DMAC will ignore the bus release request signal from the TX19 core
processor.
9
SIO
I/O Source
Reset value = 0
Specifies the type of the source device.
1: I/O device
0: Memory
8:7
SAC
Source Address
Count
Reset value = 00
Selects the manner in which the source address changes after each cycle.
1x: Fixed (remains unchanged)
01: Decremented
00: Incremented
6
DIO
I/O Destination
Reset value = 0
Specifies the type of the destination device.
1: I/O device
0: Memory
5:4
DAC
Destination
Address Count
Reset value = 00
Selects the manner in which the destination address changes after each cycle.
1x: Fixed (remains unchanged)
01: Decremented
00: Incremented
3:2
TrSiz
Transfer Size
Reset value = 00
Specifies the amount of data to be transferred in response to a DMA request.
11: 8 bits (1 byte)
10: 16 bits (2 bytes)
0x: 32 bits (4 bytes)
1:0
DPS
Device Port Size
Reset value = 00
Specifies the port size of a source or destination I/O device.
11: 8 bits (1 byte)
10: 16 bits (2 bytes)
0x: 32 bits (4 bytes)
Figure 10.4 Channel Control Registers (CCRn) (2/2)
Note 1:
The DPS field has no meaning or effect on memory-to-memory transfers.
Note 2:
To access on-chip peripherals, the transfer size (TrSiz) must be equal to the device port size (DPS).
Note 3:
The CCRn register must be programmed before placing the DMAC in Ready state.
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10.3.3
31
Channel Status Registers (CSRn)
30
24
23
22
21
20
19
18
NC
AbC

BES
SED
Conf
R
R/W
R/W
R/W
R
R
R
: Read/Write
0
0
0
0
0
0
0
: Reset Value
Act
0
15
3
17
00
2
0

0
Field Name
16


R/W
: Read/Write
00
: Reset Value
Bit
Mnemonic
Description
31
Act
Channel Active
Reset value = 0
Indicates whether or not the DMA channel is in Ready state.
1: The DMA channel is in Ready state.
0: The DMA channel is not in Ready state.
23
NC
Normal
Completion
Reset value = 0
If set, the DMA channel has terminated by normal completion. If the NIEn bit in the
CCRn is set, an interrupt is generated. The NC bit is cleared by writing a 0 to it.
Clearing the NC bit causes the interrupt to be cleared.
The NC bit must be cleared prior to starting the next transfer. An attempt to set the Str
bit in the CCRn when NC=1 will cause an error.
A write of 1 has no effect on this bit.
1: The DMA channel has terminated by normal completion.
0: The DMA channel has not terminated by normal completion.
22
AbC
Abnormal
Completion
Reset value = 0
If set, the DMA channel has terminated with an error. If the AbIEn bit in the CCRn is
set, an interrupt is generated. The AbC bit is cleared by writing a 0 to it. Clearing the
AbC bit causes the interrupt to be cleared.
The AbC bit must be cleared prior to starting the next transfer. An attempt to set the
Str bit in the CCRn when AbC=1 will cause an error.
A write of 1 has no effect on this bit.
1: The DMA channel has terminated with an error.
0: The DMA channel has not terminated with an error.
21

Reserved
This bit is reserved and must be written as 0.
20
BES
Source Bus Error
Reset value = 0
1: A bus error has occurred during the source read cycle.
0: A bus error has not occurred during the source read cycle.
19
BED
Destination Bus
Error
Reset value = 0
1: A bus error has occurred during the destination write cycle.
0: A bus error has not occurred during the destination write cycle.
18
Conf
Configuration
Error
Reset value = 0
1: A configuration error is present.
0: No configuration error is present.
2:0

Reserved
These bits are reserved and must be written as 0s.
Figure 10.5 Channel Status Registers (CSRn)
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10.3.4
Source Address Registers (SARn)
31
16
SAddr
R/W
: Read/Write
0
: Reset Value
15
0
SAddr
Bit
Mnemonic
31:0
SAddr
R/W
: Read/Write

: Reset Value
Field Name
Source Address
Description
Reset value: 
Contains the physical address of the source device. The address changes as
programmed in the SAC and TrSiz fields in the CCRn and the SACM field in the
DTCRn.
Figure 10.6 Source Address Registers (SARn)
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10.3.5
Destination Address Registers (DARn)
31
16
DAddr
R/W
: Read/Write
0
: Reset Value
15
0
DAddr
Bit
Mnemonic
31:0
DAddr
R/W
: Read/Write

: Reset Value
Field Name
Destination
Address
Description
Reset value: 
Contains the physical address of the destination device. The address changes as
programmed in the DAC and TrSiz fields in the CCRn and the DACM field in the
DTCRn.
Figure 10.7 Destination Address Registers (DARn)
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10.3.6
Byte Count Registers (BCRn)
31
24
23
16
0
BC
R/W
: Read/Write

: Reset Value
15
0
BC
Bit
Mnemonic
23:0
BC
R/W
: Read/Write

: Reset Value
Field Name
Byte Count
Description
Reset value: 
Contains the number of bytes left to transfer on a DMA channel. The count is
decremented by 1, 2 or 4 (as determined by the TrSiz field in the CCRn register) for
each successful transfer.
Figure 10.8 Byte Count Registers (BCRn)
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10.3.7
DMA Transfer Control Registers (DTCRn)
31
16
0
: Read/Write
: Reset Value
15
6
0
Field Name
5
3
2
0
DACM
SACM
R/W
R/W
: Read/Write
000
000
: Reset Value
Bit
Mnemonic
Description
5:3
DACM
Destination
Address Count
Mode
Selects the manner in which the destination address is incremented or decremented.
000: Counting begins with bit 0 of the DARn.
001: Counting begins with bit 4 of the DARn.
010: Counting begins with bit 8 of the DARn.
011: Counting begins with bit 12 of the DARn.
100: Counting begins with bit 16 of the DARn.
101: Reserved
110: Reserved
111: Reserved
2:0
SACM
Source Address
Count Mode
Selects the manner in which the source address is incremented or decremented.
000: Counting begins with bit 0 of the SARn.
001: Counting begins with bit 4 of the SARn.
010: Counting begins with bit 8 of the SARn.
011: Counting begins with bit 12 of the SARn.
100: Counting begins with bit 16 of the SARn.
101: Reserved
110: Reserved
111: Reserved
Figure 10.9 DMA Transfer Control Registers (DTCRn)
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10.3.8
Data Holding Register (DHR)
31
16
DOT
R/W
: Read/Write

: Reset Value
15
0
DOT
Bit
Mnemonic
Field Name
31:0
DOT
Data on Transfer
R/W
: Read/Write

: Reset Value
Description
Reset value: 
Contains data read from the source address during a dual-address operation.
Figure 10.10 Data Holding Register (DHR)
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10.4 Operation
This section describes the operation of the DMAC.
10.4.1
Overview
The DMAC is a high-speed 32-bit DMA controller used to quickly move large blocks of data
between I/O peripherals and memory without intervention of the TX19 core processor.
(1) Devices Supported for the Source and Destination
The DMAC handles data transfers from memory to memory and between memory and I/O
peripherals. The device from which data is transferred is referred to as a source device, and the
device to which data is transferred is referred to as a destination device. Both memory and I/O
peripherals can be a source or destination device. The DMAC supports data transfers from memory
to I/O peripherals, from I/O peripherals to memory, and from memory to memory, but not from I/O
peripherals to I/O peripherals.
DMA protocols for memory and I/O peripherals differ in that when accessing an I/O peripheral,
the DMAC asserts the DACKn (n = channel number) signal to indicate that data is being
transferred in response to a previous transfer request. Because each DMA channel has only one
DACKn signal, the DMAC can not handle data transfers between two I/O peripherals.
Interrupt requests can be programmed to be a trigger to initiate a DMA process instead of
requesting an interrupt to the TX19 core processor. If so programmed, the Interrupt Controller
(INTC) forwards a DMA request to the DMAC (see 10.4.6, Interrupts). The DMA request coming
from the INTC is cleared when the INTC receives a DACKn from the DMAC. Consequently, a
DMA request for a transfer to/from an I/O peripheral is cleared after each DMA bus cycle (i.e.,
every time the number of bytes programmed into the CCRn.TrSiz field is transferred). On the other
hand, during memory-to-memory transfer, the DACKn signal is not asserted until the byte count
register (BCRn) reaches zero. Therefore, memory-to-memory transfer can continuously move large
blocks of data in response to a single DMA request.
For example, data transfers between the TMP1941AF on-chip peripheral and on- or off-chip
memory is discontinued after every DMA bus cycle. Nonetheless, until the BCRn register reaches
zero, the DMAC remains in Ready state to wait for the next transfer request.
(2) Exchanging Bus Mastership (Bus Arbitration)
In response to a DMA request, the DMAC issues a bus request to the TX19 core processor.
When the DMAC receives a bus grant signal from the TX19 core processor, it assumes bus
mastership to service the DMA request. There are two bus request signals from the DMAC going
to the TX19 core processor. One is a bus request without snooping (GREQ), and the other is a bus
request with snooping (SREQ). The SReq bit in the CCRn register is used to select a bus request
signal to use for each DMA channel.
While the DMAC has control of the bus, the TX19 core processor may issue a bus release
request to the DMAC. The RelEn bit of the CCRn register controls whether to honor this request
on a channel-by-channel basis. This setting has a meaning only when a DMA channel uses GREQ
(i.e., a bus request without snooping). It has no meaning or effect when a DMA channel uses
SREQ (i.e., a bus request with snooping) because, in this case, the TX19 core processor does not
have the capability to generate a bus release request.
The DMAC relinquishes the bus to the TX19 core processor when there is no pending DMA
request to be serviced.
Note 1: The NMI interrupt is left pending while the DMAC has control of the bus.
Note 2: Don’t place the TMP1941AF in Halt powerdown mode while the DMAC is operating.
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(3) Transfer Request Generation
Each DMA channel supports two types of request generation methods: internal and external.
Internal requests are those generated within the DMAC. The DMA channel is started as soon as
the Str bit in the CCRn register is set. The channel immediately requests the bus and begins
transferring data.
If a channel is programmed for external request and the Str bit is set, the transfer request signal
(INTDREQn) must be asserted by the Interrupt Controller before the channel requests the bus and
begins a transfer. Although INTDREQn can be programmed for level/edge sensitivity, the
TMP1941AF requires INTDREQn to be low-level sensitive.
(4) Data Transfer Modes
The TMP1941AF DMAC supports dual-address transfers, but not single-address transfers.
The dual-address mode allows data to be transferred from memory to memory and between
memory and an I/O peripheral. In this mode, the DMAC explicitly addresses both the source and
destination devices. The DMAC also generates a DACKn signal when accessing an I/O
peripheral.
In dual-address mode, a transfer takes place in two DMA bus cycles: a source read cycle and a
destination write cycle. In the source read cycle, the data being transferred is read from the source
address and put into the DMAC internal Data Holding Register (DHR). In the destination write
cycle, the DMAC writes data in the DHR to a destination address.
(5) DMA Channel Operation
The DMAC has four independent DMA channels 0 to 3. Setting the Start (Str) bit in the CCRn
(n = 0−3) enables a particular channel and puts it in Ready state.
When a DMA request is detected in any of the channels in Ready state, the DMAC arbitrates for
the bus and begins a transfer. When no DMA request is pending, the DMAC relinquishes the bus
to the TX19 core processor and returns to Ready state. The channel can terminate by normal
completion or from an error of a bus cycle. When a channel terminates, that channel is put in Idle
state. Interrupts can be generated by error termination or by normal channel termination.
Figure 10.11shows a general state transitions of a DMA channel.
The DMAC does not
have bus mastership.
Ready
Start
Idle
The DMAC gives
up bus mastership.
Transfer done
The DMAC assumes
bus mastership.
Transfer
The DMAC has bus
mastership.
Figure 10.11 DMA Channel State Transitions
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(6) Summary of Transfer Modes
The DMAC can perform data transfers as follows according to the combination of mode
settings.
Transfer Request Edge/Level Address Mode
Internal

Dual
External
Low Level
Dual
Data Flow
Memory-to-memory
Memory-to-memory
Memory-to-I/O
I/O-to-memory
(7) Address Change Options
Address pointers can increment, decrement or remain constant. The SAC and DAC fields in the
CCRn respectively select address change directions for the Source Address Register (SARn) and
the Destination Address Register (DARn). While memory addresses can be programmed to
increment, decrement or remain constant, I/O addresses must be programmed to remain constant.
The SACM and DACM fields in the DTCRn provide options to program bit positions at which
the source and destination addresses are incremented or decremented after each transfer. The bit
position can be bit 0, 4, 8, 12 or 16. Use of bit 0 is the regular increment/decrement mode in which
the address changes by 1, 2 or 4, according to the source or destination size. Two examples of how
other increment/decrement modes affect address changes are show below.
Example 1: When address bit 0 is selected in the SACM field and address bit 4 is selected in
the DACM field
SAC: Programmed to increment the source address
DAC: Programmed to increment the destination address
TrSiz: Programmed to a transfer size of 32 bits
Source address: 0xA000_1000
Destination address: 0xB000_0000
SACM: 000 → Bit 0 is the source address bit at which address incrementation occurs.
DACM: 001 → Bit 4 is the destination address bit at which address incrementation occurs.
1st transfer
2nd transfer
3rd transfer
4th transfer
Source
0xA000_1000
0xA000_1004
0xA000_1008
0xA000_100C
…
Destination
0xB000_0000
0xB000_0010
0xB000_0020
0xB000_0030
…
Example 2: When address bit 8 is selected in the SACM field and address bit 0 is selected in
the DACM field
SAC: Programmed to decrement the address
DAC: Programmed to decrement the address
TrSiz: Programmed to a transfer size of 16 bits
Source address: 0xA000_1000
Destination address: 0xB000_0000
SACM: 010 → Bit 8 is the source address bit at which address decrementation occurs.
DACM: 000 → Bit 0 is the destination address bit at which address decrementation occurs.
1st transfer
2nd transfer
3rd transfer
4th transfer
Source
0xA000_1000
0x9FFF_FF00
0x9FFF_FE00
0x9FFF_FD00
…
Destination
0xB000_0000
0xAFFF_FFFE
0xAFFF_FFFC
0xAFFF_FFFA
…
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10.4.2
Transfer Request Generation
A DMA request must be issued for the DMAC to initiate a data transfer. Each DMA channel in the
DMAC supports two types of request generation method: internal and external. In either request
generation mode, once a DMA channel is started, a DMA request causes the DMAC to arbitrate for the
bus and begin transferring data.
•
Internal Request Generation
A channel is programmed for internal request by clearing the ExR bit in the CCRn. In internal
request generation mode, a transfer request is generated as soon as the Str bit in the CCRn is set.
An internally generated request keeps a transfer request pending until the transfer is complete. If
no transition to a higher-priority DMA channel or a bus master occurs, the channel will use 100%
of the available bus bandwidth to transfer all data continuously.
Internally generated requests support only memory-to-memory transfer.
•
External Request Generation
A channel is programmed for external request by setting the ExR bit in the CCRn. In external
request generation mode, setting the Str bit in the CCRn puts the channel in Ready state. While in
Ready state, assertion of the INTDREQn signal (where n is the channel number) coming from the
Interrupt Controller (INTC) causes a transfer request to be generated. Externally generated requests
support data transfers from memory to memory and between memory and an I/O peripheral.
INTDREQn can be programmed for either edge or level sensitivity through the PosE bit in the
CCRn. However, in the TMP1941AF, INTDREQn is an active-low, level-sensitive signal.
Therefore, the PosE bit must be cleared to 0.
The transfer size, i.e., the amount of data to be transferred in response to a transfer request, is
programmed in the TrSize field in the CCRn. The transfer size can be 32 bits, 16 bits or 8 bits.
A transfer request is removed by assertion of the DACKn signal (where n is the channel
number). DACKn is asserted: 1) when an I/O peripheral bus cycle has completed and 2) when the
Byte Count Register (BCRn) has reached zero in memory-to-memory transfer. Consequently, a
memory-to-I/O or I/O-to-memory transfer request terminates after one DMA bus cycle completes,
whereas memory-to-memory transfer can continuously move large blocks of data in response to a
single DMA request.
The INTC might clear INTDREQn before the DMAC accepts it and begins a data transfer. It
must be noted that, even if that happens, a DMA bus cycle might be executed after the interrupt
request has been cleared.
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10.4.3
DMA Address Modes
The TMP1941AF supports only dual-address mode in which both the source and destination devices
are explicitly addressed.
In dual-address mode, two bus transfers occur: a read from a source device and a write to the
destination device. In the source read cycle, data is read from the source address and placed in the
DMAC internal Data Holding Register (DHR). Then, in the destination write cycle, the data held in the
DHR is written to the destination address.
DMAC
Source Device
Address
1. Source read
Address Bus
2. Desti. write
Data
1. Source read
Data Bus
2. Desti. write
Destination Device
Figure 10.12 Dual-Address Transfer Mode
The transfer size programmed into the CCRn.TrSiz field determines the amount of data that is
transferred from a source device to a destination device in response to a DMA request. The transfer size
can be 32 bits, 16 bits or 8 bits.
The internal DHR is a 32-bit register that serves as a buffer for the data being transferred from a
source device to a destination device during dual-address mode.
Memory accesses occur in a manner to fulfill the CCRn.TrSiz setting. Remember that the CS/Wait
Controller supports either 16-bit or 8-bit bus accesses for external memory. If the DMA transfer size is
programmed to 32 bits in CCRn.TrSiz, DMA read and write cycles each take up to four bus cycles to
complete. A 16-bit data bus, as programmed in the CS/Wait Controller, requires two independent bus
cycles to complete a 32-bit transfer. Likewise, an 8-bit data bus requires four independent bus cycles to
complete a 32-bit transfer.
Memory-to-I/O and I/O-to-memory DMA transfers are governed by the setting of the CCRn.DPS
field in addition to the setting of CCRn.TrSiz. The DPS field defines the port size of a source or
destination I/O peripheral. The I/O port size can be 32 bits, 16 bits or 8 bits.
If the transfer size is equal to the I/O port size, an I/O access takes a single read or single write cycle.
If the I/O port size is less than the programmed transfer size, the internal 32-bit DHR serves as a buffer
for the data being transferred. For example, assume that the transfer size is programmed to 32 bits. If
the source I/O port size is 8 bits and the destination memory width is 32 bits, then four 8-bit read cycles
occur, followed by a 32-bit write cycle. (If the destination is an external memory with a 16-bit data bus,
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the write cycle takes two bus cycles.) The 32 bits of data are buffered in the DHR until the destination
write cycle occurs.
Source and destination addresses can be programmed to increment or decrement after each transfer.
The SARn and DARn change, if so programmed, after each data transfer, depending on the transfer
size, i.e., the programmed TrSiz value. The BRCn is decremented by TrSiz for each data transfer.
It is forbidden to program the device port size (DPS) to a value greater than the DMA transfer size
(TrSiz).
The relationships between TrSiz and DPS are summarized below.
Table 10.2 DMA Transfer Sizes and Device Port Sizes (in Dual-Address Mode)
TrSiz
Note:
10.4.4
DPS
# of I/O Bus Cycles
0x (32 bits)
0x (32 bits)
1
0x (32 bits)
10 (16 bits)
2
0x (32 bits)
11 (8 bits)
4
10 (16 bits)
0x (32 bits)
Don’t use.
10 (16 bits)
10 (16 bits)
1
10 (16 bits)
11 (8 bits)
2
11 (8 bits)
0x (32 bits)
Don’t use.
11 (8 bits)
10 (16 bits)
Don’t use.
11 (8 bits)
11 (8 bits)
1
The DMAC does not incremnt or decrement the address for I/O peripherals. Therefore, if, for
example, TrSiz is programmed to 16 bits and DPS is programmed to 8 bits, both the first and second
bus cycles access the lower eight bits of the I/O data bus.
DMA Channel Operation
Each DMA channel is started by setting the Str bit in the CCRn to 1. Once started, the DMAC checks
the channel setups for configuration errors. If no configuration error is present, the channel enters
Ready state.
When a DMA request is detected while in Ready state, the DMAC arbitrates for the bus and begins
transferring data.
The channel can terminate by normal completion or from an error.
(1) Channel Startup
A DMA channel is started by setting the Str bit in the CCRn.
Once started, the DMAC checks the channel setups for configuration errors. If a configuration
error is detected, the channel terminates abnormally. If no configuration error is present, the
channel enters Ready state. Once a channel enters Ready state, the Act bit in the CSRn is set to 1.
If the channel is programmed for internal request, the channel requests the bus and starts
transferring data immediately. If the channel is programmed for external request, INTDREQn must
be asserted before the channel requests the bus.
(2) Channel Termination
A DMA channel can terminate by normal completion or from an error. The status of a DMA
operation can be determined by reading the CSRn.
A channel terminates abnormally when an attempt is made to set the Str bit in the CCRn when
the NC or AbC bit in the CSRn is set.
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Normal Termination
A DMA channel terminates by normal completion in the following case. Normal completion
always occurs at the boundary of transfers programmed into the CCRn.TrSize field.
•
Data transfers have terminated, with the BCRn decremented to 0.
Abnormal Termination
The paragraphs that follow summarize the cases in which a DMA channel terminates from an
error.
•
Configuration errors
A configuration error results when the channel initialization contains inconsistencies or
errors. A configuration error is reported before any data transfer takes place; therefore, in
case of a configuration error, the SARn, DARn and BCRn remain unaltered. When a DMA
channel has terminated from a configuration error, the AbC and Conf bits in the CSRn are
set. A configuration error occurs for the following cases:
− Both the CCRn.SIO and CCRn.DIO bits are set.
− The CCRn.Str bit is set when the NC or AbC bit in the CSRn is set.
− The BCRn contains a value that is not an integer multiple of the transfer size
programmed into the CCRn.TrSiz field.
− The SARn or DARn contains a value that is not an integer multiple of the transfer size
programmed into the CCRn.TrSiz field.
− The CCRn.TrSiz and CCRn.DPS fields contain illegal combinations.
− The CCRn.Str bit is set when the the BCRn contains a value of zero.
•
Bus errors
When a DMA channel has terminated from a bus error, the AbC bit and the BES or BED
bit in the CSRn is set.
− A bus error has been reported during a source read or destination write cycle.
Note:
The contents of the BCRn, SARn and DARn are not guaranteed when a channel has
terminated due to a bus error. Chapter 19 lists the reserved addresses that, if accessed,
cause a bus error.
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10.4.5
DMA Channel Priority
The DMAC provides a fixed priority for the four channels, with channel 0 always having the highest
priority and channel 3 the lowest. For example, when transfer requests occur on channels 0 and 1
simultaneously, the channel 0 request is serviced first. The channel 1 request is left pending. So that the
channel 1 request is serviced, it must be maintained until data transfer completes on channel 0.
Remember that the internally generated request is kept until the servicing of the request is finished.
External transfer requests come from the Interrupt Controller (INTC). The INTC can program any
interrupts to be used as a DMA trigger instead of as an interrupt request. If such an interrupt is
programmed for edge sensitivity, the INTC internally maintains a transfer request. However, a levelsensitive interrupt is not held in the INTC; thus the interrupt request signal must remain asserted until
the servicing of the DMA request begins.
A higher-priority channel always gets the attention of the DMAC. If a transfer request occurs on
channel 0 while a request on channel 1 is being serviced, the servicing of the channel 1 request is
suspended temporarily in order to service the channel 0 request first. After the channel 0 request has
been serviced, channel 1 resumes the remaining data transfer.
Channel transitions take place at the boundary of a transfer size programmed for the current channel
being serviced; that is, after all data in the DHR are written to a destination.
Note:
DMA channel priority exists only among those using the same type of bus request signal (SREQ
or GREQ).
10.4.6
Interrupts
The DMAC can generate an interrupt request (INTDMAn) to the TX19 core processor on completion
of a channel operation: either by normal channel termination or by abnormal termination of a bus cycle.
•
Normal Completion Interrupt
When a channel operation terminates by normal completion, the NC bit in the CSRn is set to 1.
At this time, if the NIEn bit in the CCRn is set, an interrupt request is generated to the TX19 core
processor.
•
Abnormal Completion Interrupt
When a channel operation terminates abnormally, the AbC bit in the CSRn register is set to 1. At
this time, if the AbIEn bit in the CCRn register is set, an interrupt request is generated to the TX19
core processor.
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10.4.7
Data Packing and Unpacking
In dual-address mode, the internal 32-bit DHR allows the data to be packed and unpacked by the
DMAC if the programmed transfer size is not equal to the device port size.
For example, if a source I/O peripheral is 8-bits wide and a destination memory device is 32-bits
wide, four byte-read cycles occur. The four bytes of data are buffered in the DHR before a destination
word-write cycle occurs.
The following illustrates the byte ordering for packing and unpacking of data.
DHR
I/O Device
0
8
4n + 3
4n + 2
4n + 1
4n + 0
D
C
B
A
31
Little-Endian
0
D
C
B
A
Figure 10.13 Data Packing and Unpacking
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10.5 DMA Transfer Timing
All DMAC operations are synchronous to the rising edges of the internal system clock.
10.5.1
Dual-Address Mode
•
Memory-to-memory transfer
Figure 10.14 shows a DMA cycle from one external 16-bit memory to another, with the transfer
size programmed to 16 bits. A block of data is transferred until the BCRn register reaches 0.
tsys
A[23:16]
CS0
CS1
RD
WR / HWR
Addr
AD [15:0]
Data
Addr
Read
Data
Write
Figure 10.14 Memory-to-Memory Transfer (Dual-Address Mode)
•
Memory-to-I/O transfer
Figure 10.15 shows a DMA cycle from a 16-bit memory to an 8-bit I/O peripheral, with the
transfer size programmed to 16 bits.
tsys
A[23:16]
CS0
CS1
RD
WR
AD[15:0]
Addr
Data
Read
Addr
Data
Write
Addr
Data
Write
Figure 10.15 Memory-to-I/O Transfer (Dual-Address Mode)
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•
I/O-to-memory transfer
Figure 10.16 shows a DMA cycle from an 8-bit I/O peripheral to a 16-bit memory, with the
transfer size programmed to 16 bits.
tsys
A[23:16]
CS0
CS1
RD
WR
AD[15:0]
Addr
Data
Addr
Read
Data
Read
Addr
Data
Write
Figure 10.16 I/O-to-Memory Transfer (Dual-Address Mode)
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10.6 Programming Example
The following illustrates the programming required to transfer data from an SIO receive buffer (SCnBUF)
to the on-chip RAM. The assumptions are as follows:
DMAC Settings:
•
DMA channel used: Channel 0
•
Source address: SC1BUF
•
Destination address: 0xFFFF_9800 (physical address)
•
Number of bytes transferred: 256
SIO Settings:
•
Data format: 8 bits, UART
•
SIO channel used: Channel 1
•
Transfer rate: 9600 bps
DMA channel 0 is used for the transfer. The SIO1 receive interrupt is used as a trigger to start the DMA
channel.
DMA channel 0 settings:
←
0x8000_0000
/* Reset DMAC * /
IMCFL ←
15
7
0
xxxx, xxxx, xx10, x100
/* Bit positions */
/* Interrupt level = 4 (arbitrary) * /
INTCLR ←
0x3c
/*IVR[9:4]; clear INTDMA0 * /
DTCR0 ←
0x0000_0000
/* DACM = 000 * /
/* SACM = 000 * /
SAR0
←
0xFFFF_F208
/* Physical address of SC1BUF */
DAR0
←
0xFFFF_9800
/* Physical address of destination */
BCR0
←
0x0000_00FF
/* 256 (Number of bytes to be transferred) */
CCR0
←
0x80c0_5b0f
DCR
(Contents) 31
27
23
19
1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
15
11
7
3
0 1 0 1 1 x 1 1 x 0 0 0 1 1 1 1
SIO channel 1 settings:
IMCCH
← 31
16 /* Bit positions */
xxxx, xxxx, xx11, 1000 /* Use INTRX1 as a DMA trigger and select DMA ch. 0 * /
INTCLR ← 0x32
/* IVR[9:4]; clear INTRX1 * /
SC1MOD0 ← 0x09
/* UART mode, 8-bit data format, baud rate generator * /
SC1CR
← 0x00
BR1CR
← 0x1d
SC1MOD0 ← 0x29
/* @fc = 32 MHz (approx. 9615 bps) */
/* Enable receiver * /
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11. 8-Bit Timers (TMRAs)
The TMP1941AF has a four-channel 8-bit timer (TMRA0–TMRA3), which is comprised of two modules
named TMRA01 and TMRA23. The TMRA01 contains the TMRA0 and the TMRA1, and the TMRA23
contains the TMRA2 and TMRA3. Each timer module has the following operating modes:
•
8-bit interval timer mode
•
16-bit interval timer mode
•
8-bit programmable pulse generation (PPG) mode (Variable frequency, variable duty cycle)
•
8-bit pulse width modulated (PWM) signal generation mode (Fixed frequency, variable duty cycle)
Figure 11.1 and Figure 11.2 are block diagrams of the TMRA01 and TMRA23 respectively. The main
components of a timer channel are an 8-bit up-counter, an 8-bit comparator and an 8-bit timer register. Two
timer channels share a prescalar and a timer flip-flop.
A total of six 8-bit registers provide control over the operating modes and timer flip-flops for the TMRA01
and the TMRA23 each, which can be independently programmed. The TMRA01 and the TMRA23 are
functionally equivalent. In the following sections, any references to the TMRA01 also apply to the TMRA23.
Table 11.1 gives the pins and registers for the two timer modules.
Table 11.1 Pins and Registers for the TMRA01 and the TMRA23
External
Pins
Registers
(Addresses)
TMRA01
TMRA23
External clock input
TA0IN
(Shared with P70)
TA2IN
(Shared with P72)
Timer flip-flop output
TA1OUT
(Shared with P71)
TA3OUT
(Shared with P73)
Timer Run register
TA01RUN (0xFFFF_F100)
TA23RUN (0xFFFF_F108)
Timer registers
TA0REG (0xFFFF_F102)
TA1REG (0xFFFF_F103)
TA2REG (0xFFFF_F10A)
TA3REG (0xFFFF_F10B)
Timer Mode register
TA01MOD (0xFFFF_F104)
TA23MOD (0xFFFF_F10C)
Timer Flip-Flop Control
register
TA1FFCR (0xFFFF_F105)
TA3FFCR (0xFFFF_F10D)
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External Clock
Input: TA0IN
Prescalar Clock
Source: φT0
TMP1941AF-110
φT4
8
Internal Data Bus
Register Buffer 0
8-Bit
Timer Register
TA0REG
8-Bit Comparator
(CP0)
TMRA0
Match Output:
TA0TRG
Internal
Data Bus
8-Bit Timer
Register
TA1REG
8-Bit
Comparator
(CP1)
8-Bit
Up-Counter
(UC1)
TA1FFCR
Timer
Flip-Flop
TA1FF
TMRA1
Interrupt Output:
INTTA1
Match
Detect
TA01RUN.TA1RUN
TA01MOD.
TA1CLK[1:0]
φT1
φT16
φT256
TA01MOD.
TA01M[1:0]
TMRA0
Interrupt Output:
INTTA0
Match
Detect
TA01MOD.
PWM[01:00]
2n−1
Overflow
8-Bit Up-Counter
(UC0)
Selector
TA01RUN.TA01PRUN
TA0TRG
Run/Clear
φT256
TA01RUN.TA0RUN
φT16
16 32 64 128 256 512
TA01MOD.
TA0CLK[1:0]
TA01RUN.
TA0RDE
φT1
φT4
φT16
4
Selector
φT1
2
Prescaler
Timer Flip-Flop
Output:
TA1OUT
TMP1941AF
11.1 Block Diagrams
Figure 11.1 TMRA01 Block Diagram
2003-03-27
External Clock
Input: TA2IN
Prescalar Clock
Source: φT0
TMP1941AF-111
8
φT4
Match
Detect
φT1
φT16
φT25
TA23MOD.
8-Bit
Up-Counter
(UC3)
TMRA2
Match Output:
TA2TRG
Internal
Data Bus
8-Bit Timer
Register
TA3REG
8-Bit
Comparator
(CP3)
TA3FFCR
Timer
Flip-Flop
TA3FF
TMRA3
Interrupt Output:
INTTA3
Match
Detect
TA23RUN.TA3RUN
TA3CLK[1:0]
TA23M[1:0]
TA23MOD.
Internal Data Bus TMRA2
Interrupt Output:
INTTA2
Register Buffer 2
8-Bit
Timer Register
TA2REG
8-Bit Comparator
(CP2)
TA23MOD.
PWM[21:20]
2n−1
Overflow
8-Bit Up-Counter
(UC2)
Selector
TA23RUN.TA23PRUN
TA2TRG
Run/Clear
φT256
TA23RUN.TA2RUN
φT16
16 32 64 128 256 512
TA23MOD.
TA2CLK[1:0]
TA23RUN.
TA2RDE
φT1
φT4
φT16
4
Selector
φT1
2
Prescaler
Timer Flip-Flop
Output:
TA3OUT
TMP1941AF
Figure 11.2 TMRA23 Block Diagram
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TMP1941AF
11.2 Timer Components
11.2.1
Prescaler
The TMRA01 has a 9-bit prescalar that slows the rate of a clocking source to the counters. The
prescalar clock source (φT0) can be selected from fperiph, fperiph/2 and fperiph/4 by programming the
PRCK[1:0] field of the SYSCR0 located within the CG. fperiph can be selected from fgear (geared
clock) and fc (non-geared clock) by programming the FPSEL bit of the SYSCR1 located within the CG.
The TA01PRUN bit in the TA01RUN register allows the enabling and disabling of the prescalar for
the TMRA01. A write of 1 to this bit starts the prescalar. A write of 0 to this bit clears and halts the
prescalar.
Prescalar output taps can be divide-by-2 (φΤ1), divide-by-8 (φT4), divide-by-32 (φT16) and divideby-512 (φT256). Table 11.2 shows prescalar output clock resolutions (@fc = 32 MHz).
Table 11.2 Prescalar Output Clock Resolutions
@fc = 40 MHz
Peripheral
Clock Select
SYSCR1.
FPSEL
Clock Gear
Value
SYSCR1.
GEAR[1:0]
00 (fc)
Prescaler
Clock Source
SYSCR0.
PRCK[1:0]
Prescalar Output Clock Resolution
φT1
3
fc/2 (0.8 µs)
2
fc/2 (0.4 µs)
00 (fperiph/4)
fc/2 (0.2 µs)
01 (fperiph/2)
fc/2 (0.1 µs)

10 (fperiph)
00 (fperiph/4)
01 (fc/2)
01 (fperiph/2)
4
fc/2 (0.4 µs)
3
fc/2 (0.2 µs)

10 (fperiph)
0 (fgear)
00 (fperiph/4)
10 (fc/4)
01 (fperiph/2)
5
fc/2 (0.8 µs)
4
11 (fc/8)
01 (fperiph/2)
fc/2 (1.6 µs)
5
fc/2 (0.8 µs)


01 (fperiph/2)
10 (fperiph)
1 (fc)
00 (fperiph/4)
10 (fc/4)
11 (fc/8)
fc/2 (0.2 µs)



fc/2 (0.8 µs)
8
fc/2 (1.6 µs)
fc/2 (6.4 µs)
5
7
fc/2 (0.8 µs)
fc/2 (3.2 µs)
4
6
fc/2 (0.4 µs)
fc/2 (1.6 µs)
7
9
fc/2 (3.2 µs)
fc/2 (12.8 µs)
6
fc/2 (6.4 µs)
5
fc/2 (3.2 µs)
8
fc/2 (6.4 µs)
8
7
10
fc/2
7
fc/2 (3.2 µs)
6
fc/2 (1.6 µs)
fc/2 (0.4 µs)
3
5
6
fc/2 (0.8 µs)
fc/2 (0.1 µs)
6
fc/2 (0.2 µs)
2
fc/2 (0.2 µs)
01 (fperiph/2)
7
3
3
10 (fperiph)
01 (fc/2)
fc/2 (1.6 µs)
fc/2 (0.8 µs)
00 (fperiph/4)
00 (fperiph/4)
4
fc/2 (1.6 µs)
10 (fperiph)
00 (fc)
fc/2 (3.2 µs)

6
φT16
5
fc/2 (0.4 µs)
10 (fperiph)
00 (fperiph/4)
φT4
(25.6 µs)
9
fc/2 (12.8 µs)
8
fc/2 (6.4 µs)
5
fc/2 (3.2 µs)
4
fc/2 (1.6 µs)
3
fc/2 (0.2 µs)
5
fc/2 (0.8 µs)
4
fc/2 (0.4 µs)
3
fc/2 (0.2 µs)
5
fc/2 (0.8 µs)
4
7
6
5
fc/2 (0.8 µs)
7
fc/2 (3.2 µs)
6
fc/2 (1.6 µs)
5
fc/2 (0.8 µs)
7
fc/2 (3.2 µs)
6
01 (fperiph/2)

fc/2 (0.4 µs)
fc/2 (1.6 µs)
10 (fperiph)


fc/2 (0.8 µs)
00 (fperiph/4)

fc/2 (0.8 µs)
fc/2 (3.2 µs)
01 (fperiph/2)
10 (fperiph)


5


5
7
6
fc/2 (1.6 µs)
5
fc/2 (0.8 µs)
φT256
11
(51.2 µs)
10
(25.6 µs)
fc/2
fc/2
9
fc/2 (12.8 µs)
12
fc/2
(102.4 µs)
11
(51.2 µs)
10
(25.6 µs)
fc/2
fc/2
13
(204.8 µs)
12
(102.4 µs)
fc/2
fc/2
11
fc/2
(51.2 µs)
14
(409.6 µs)
13
(204.8 µs)
12
(102.4 µs)
fc/2
fc/2
fc/2
11
(51.2 µs)
10
(25.6 µs)
fc/2
fc/2
9
fc/2 (12.8 µs)
11
(51.2 µs)
10
(25.6 µs)
fc/2
fc/2
9
fc/2 (12.8 µs)
11
(51.2 µs)
10
(25.6 µs)
fc/2
fc/2
9
fc/2 (12.8 µs)
11
(51.2 µs)
10
(25.6 µs)
fc/2
fc/2
9
fc/2 (12.8 µs)
Note 1: The prescaler's output clock φTn must be selected so that φTn < fsys/2 is satisfied.
Note 2: Do not change the clock gear value while the timer is running.
Note 3: The — character means “Don’t use.”
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11.2.2
Up-Counters (UC0 and UC1)
The timer module contains two 8-bit binary up-counters, each of which is driven by a clock
independently selected by the TA01MOD register.
The clock input to the UC0 is either one of three prescalar outputs (φΤ1,φT4, φT16) or the external
clock applied to the TA0IN pin. Which clock is to use is programmed into the TA0CLK[1:0] field of the
TA01MOD register.
Possible clock sources for the UC1 depend on the selected operating mode. In 16-bit interval timer
mode, the clock input to the UC1 is always the UC0 overflow output. In other operating modes, the
clock input to the UC1 is either one of three prescalar outputs (φΤ1,φT16, φT256) or the TMRA0
comparator match-detect output.
The TA0RUN and TA1RUN bits in the TA01RUN register are used to start counting and to stop and
clear the counter. Upon reset, the up-counter is set to 00H and the whole timer module is disabled.
11.2.3
Timer Registers (TA0REG and TA1REG)
Each timer register is an 8-bit register containing a time constant. When the up-counter reaches the
time constant value in the timer register, the comparator block generates a match-detect signal. When
the time constant is set to 00H, a match occurs upon a counter overflow.
One of the two timer registers, TA0REG, is double-buffered. The double-buffering function can be
enabled and disabled through the programming of the TA0RDE bit in the TA01RUN: 0=disable,
1=enable.
If double-buffering is enabled, the TA0REG latches a new time constant value from the register
buffer. This takes place upon detection of a 2n–1 overflow in PWM mode and upon a match between the
UC0 and the TA1REG in PPG mode. Double-buffering must be disabled in interval timer modes.
A reset clears the TA01RUN.TA0RDE bit to 0, disabling the double-buffering function. To use this
function, the TA01RUN.TA0RDE bit must be set to1 after loading the TA0REG with a time constant.
When TA01RUN.TA0RDE=1, the next time constant can be written to the register buffer.
Figure 11.13 illustrates the double-buffer structure for the TA0REG.
Up-Counter
Comparator (CP0)
Timer Register 0 (TA0REG)
Selector
B
Y
TA1REG Match in PPG Mode
2n-1 Overflow in PWM Mode
A
Shift Trigger
Write to TA0REG
Register Buffer 0
S
Write
TA01RUN.TA0RDE
Internal Data Bus
Figure 11.3 Timer Register 0 (TA0REG) Structure
Note:
The timer register and the corresponding register buffer are mapped to the same address. When
TA01RUN.TA0RDE=0, a time constant value is written to both of the timer register and the register
buffer; when TA01RUN.TA0RDE=1, a time constant value is written only to the register buffer.
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The addresses of the timer registers are as follows:
TA0REG:
0xFFFF_F102
TA1REG:
0xFFFF_F103
TA2REG:
0xFFFF_F10A
TA3REG:
0xFFFF_F10B
The timer registers are write-only registers.
11.2.4
Comparators (CP0 and CP1)
The comparator compares the output of the 8-bit up-counter with a time constant value in the 8-bit
timer register. When a match is detected, an interrupt (INTTA0/INTTA1) is generated and the timer
flip-flop is toggled, if so enabled.
11.2.5
Timer Flip-Flop (TA1FF)
The timer flip-flop (TA1FF) is toggled, if so enabled, each time the comparator match-detect output
is asserted. The toggling of the timer flip-flop can be enabled and disabled through the programming of
the TAFF1IE bit in the TA1FFCR.
A reset clears the TAFF1IE bit, disabling the toggling of the TA1FF. The TA1FF can be initialized to
1 or 0 by writing 01 or 10 to the TAFF1C[1:0] field in the TA1FFCR. Additionally, a write of 00 by
software causes the TA1FF to be toggled to the opposite value.
The value of the TA1FF can be driven onto the TA1OUT pin, which is multiplexed with P71. The
Port 7 registers (P7CR and P7FC) must be programmed to configure the P71/TA1OUT pin as
TA1OUT.
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11.3 Register Description
TMRA01 Run Register
TA01RUN
(0xFFFF_F100)
Name
Read/Write
Reset Value
7
6
5
4
3
2
TA0RDE



I2TA01
TA01PRUN
R/W



0



Function
0
TA1RUN
TA0RUN
R/W
0
IDLE
0: Off
1: On
Double
Buffering
0: Disable
1: Enable
1
0
0
Prescalar
Run/Stop
Control
0: Stop
1: Run
0
Timer Run/Stop Control
0: Stop & clear
1: Run
I2TA01: Timer on/off in IDLE mode
TA01PRUN: Prescaler
TA1RUN: TMRA1
TA0RUN: TMRA0
Note:
Bits 4, 5 and 6 are read as undefined.
TMRA23 Run Register
TA23RUN
(0xFFFF_F108)
Name
Read/Write
Reset Value
Function
7
6
5
4
3
2
1
0
TA2RDE



I2TA23
TA23PRUN
TA3RUN
TA2RUN
R/W



0
Double
Buffering
0: Disable
1: Enable



R/W
0
IDLE
0: Off
1: On
0
Prescalar
Run/Stop
Control
0: Stop
1: Run
0
0
Timer Run/Stop Control
0: Stop & clear
1: Run
I2TA23: Timer on/off in IDLE mode
TA23PRUN: Prescaler
TA3RUN: TMRA3
TA2RUN: TMRA2
Note:
Bits 4, 5 and 6 are read as undefined.
Figure 11.4 Timer Run Registers
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TMRA01 Mode Register
TA01MOD
Name
(0xFFFF_F104) Read/Write
Reset Value
Function
7
6
5
4
3
2
1
0
TA01M1
TA01M0
PWM01
PWM00
TA1CLK1
TA1CLK0
TA0CLK1
TA0CLK0
0
0
R/W
0
0
0
Operating mode
00: 8-bit interval timer
01: 16-bit interval timer
10: 8-bit PPG
11: 8-bit PWM
0
0
PWM period
00: Reserved
01: 26-1
10: 27-1
11: 28-1
0
TMRA1 clock source
00: TA0TRG
01: φT1
10: φT16
11: φT256
TMRA0 clock source
00: TA0IN input
01: φT1
10: φT4
11: φT16
TMRA0 clock source
00
External input (TA0IN)
01
φT1
10
φT4
(Prescaler)
11
φT16
(Prescaler)
(Prescaler)
TMRA1 clock source
TA01MOD.TA01M[1:0]≠01
TA01MOD.TA01M[1:0]=01
TMRA0 match output TMRA0 overflow
output
φT1
00
01
10
φT16
11
φT256
16-Bit Timer
Mode
Period select in 8-bit PWM mode
00
Reserved
01
(26-1) × clock source
10
(27-1) × clock source
11
(28-1) × clock source
TMRA01 operating mode
00
Two 8-bit timers
01
16-bit timer
10
8-bit PPG
11
8-bit PWM generation (TMRA0) &
8-bit timer (TMRA1)
Figure 11.5 Timer Mode Register
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TMRA23 Mode Register
TA23MOD
(0xFFFF_F10C)
Name
7
6
5
4
3
2
1
0
TA23M1
TA23M0
PWM21
PWM20
TA3CLK1
TA3CLK0
TA2CLK1
TA2CLK0
0
0
Read/Write
Reset Valu
Function
R/W
0
0
0
Operating mode
00: 8-bit interval timer
01: 16-bit interval timer
10: 8-bit PPG
11: 8-bit PWM
0
0
PWM period
00: Reserved
01: 26-1
10: 27-1
11: 28-1
0
TMRA3 clock source
00: TA2TRG
01: φT1
10: φT16
11: φT256
TMRA2 clock source
00: TA2IN
01: φT1
10: φT4
11: φT16
TMRA2 clock source
00
External input (TA2IN)
01
φT1
10
φT4
(Prescaler)
11
φT16
(Prescaler)
(Prescaler)
TMRA3 clock source
TA23MOD.TA23M[1:0]≠01
TA23MOD.TA23M[1:0]=01
00
TMRA2 match output
01
φT1
TMRA2 overflow
output
10
φT16
11
φT256
16-Bit Timer
Mode
Period select in 8-bit PWM mode
00
Reserved
01
(26-1) × clock source
10
(27-1) × clock source
11
(28-1) × clock source
TMRA23 operating mode
00
Two 8-bit timers
01
16-bit timer
10
8-bit PPG
11
8-bit PWM generation (TMRA2) &
8-bit timer (TMRA3)
Figure 11.6 Timer Mode Register
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TMRA01 Timer Flip-Flop Control Register
TA1FFCR
(0xFFFF_F105)
7
6
5
4
3
2
Name




TAFF1C1
TAFF1C0
Read/Write




Reset Value




1
0
TAFF1IE
TAFF1IS
R/W
1
1
00: Toggles TA1FF.
(software toggle)
01: Sets TA1FF to 1.
10: Clears TA1FF to 0.
11: Don’t-care
This field is always
read as 11.
Function
0
0
TA1FF
toggle
enable
0: Disable
1: Enable
TA1FF
toggle
trigger
0: TMRA0
1: TMRA1
Selects a signal to toggle Timer Flip-Flop 1 (TA1FF)
(Don’t-care in other than 8-bit timer mode)
Note:
0
Toggled by TMRA0
1
Toggled by TMRA1
Bits 4 to 7 are read as undefined.
Figure 11.7 TMRA01 Flip-Flop Control Register
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TMRA23 Flip-Flop Control Register
TA3FFCR
(0xFFFF_F10D)
7
6
5
4
3
2
1
0
Name




TAFF3C1
TAFF3C0
TAFF3IE
TAFF3IS
Read/Write




Reset Value




R/W
1
1
00: Toggles TA3FF
(software toggle).
01: Sets TA3FF to 1
10: Clears TA3FF to 0
11: Don’t care
This field is always
read as 11.
Function
0
0
TA3FF
toggle
enable
0: Disable
1: Enable
TA3FF
trigger
0: TMRA2
1: TMRA3
Selects a signal to toggle Timer Flip-Flop 3 (TA3FF)
(Don’t-care in other than 8-bit timer mode)
Note:
0
Toggled by TMRA2
1
Toggled by TMRA3
Bits 4 to 7 are read as undefined values.
Figure 11.8 TMRA23 Flip-Flop Control Register
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11.4 Operating Modes
11.4.1
8-Bit Interval Timer Mode
The TMRA0 and the TMRA1 can be independently programmed as 8-bit interval timers.
Programming these timers should only be attempted when the timers are not running.
(1) Generating Periodic Interrupts
In the following example, the TMRA1 is used to accomplish periodic interrupt generation. First,
stop the TMRA1 (if it is running). Then, set the operating mode, clock source and interrupt interval
in the TA01MOD and TA1REG registers. Then, enable the INTTA1 interrupt and start the
TMRA1.
Example: Generating the INTTA1 interrupt at a 20-µs interval (fc = 32 MHz)
Clocking conditions:
System clock:
High-speed (fc)
Prescaler clock: fperiph/4 (fperiph = fsys)
MSB
LSB
TA01RUN
TA01MOD
7
← −
← 0
6
−
0
5
X
X
4
X
X
3
−
1
2
−
0
1
0
X
0
−
X
TA1REG
←
0
1
0
1
0
0
0
0
IMC5LH
←
X
X
1
1
0
1
0
1
TA01RUN
←
−
X
X
X
−
1
1
−
X = Don’t care,
Stops and clears the TMRA1.
Selects 8-bit interval timer mode and
φT1 as the clock source (which provides a 0.2µs resolution @fc = 40 MHz.)
Sets the time constant value in the TA1REG.
20 µs ÷ φT1 = 80 (50H)
Enables INTTA1 and sets the interrupt level to
5. INTTA1 must always be programmed to be
rising-edge triggered.
Starts the TMRA1.
– = No change
Refer to Table 11.2 when selecting a timer clock source.
Note:
The clock inputs to the TMRA0 and the TMRA1 can be one of the following:
TMRA0: TA0IN input, φT1, φT4 or φT16
TMRA1: Match-detect signal from the TMRA0, φT1, φT16 or φT256
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(2) Generating a SquareWave with a 50% Duty Cycle
The 8-bit interval timer mode can be used to generate square-wave output. This is accomplished
by toggling the timer flip-flop (TA1FF) periodically. The TA1FF state can be driven out to the
TA1OUT pin. Both the TMRA0 and the TMRA1 can be used as square-wave generators. The
following shows an example using the TMRA1.
Example: Generating square-wave output with a 1.2-µs period on the TA1OUT pin
(fc = 40 MHz)
Clocking conditions:
System clock:
High-speed (fc)
High-speed clock gear: ↕1 (fc)
Prescaler clock:
fperiph/4 (fperiph = fsys)
MSB
LSB
TA01RUN
TA01MOD
7
← −
← 0
6
X
0
5
X
X
4
X
X
3
−
0
2
−
1
1
0
−
0
−
−
TA1REG
← 0
0
0
0
0
0
1
1
TA1FFCR
← X
X
X
X
1
0
1
1
P7CR
P7FC
TA01RUN
← −
← −
← −
−
−
X
−
−
X
−
−
X
−
−
−
−
−
1
1
1
1
−
−
−
X = Don’t care,
Stops and clears the TMRA1.
Selects 8-bit interval timer mode and
φT1 as the clock source (which provides a 0.2µs resolution @fc = 40 MHz).
Sets the time constant value in the TA1REG.
1.2 µs ÷ φT1 ÷ 2 = 3
Clears the TA1FF to 0 and selects the TMRA1
match-detect output as a toggle-trigger signal.
Configures P71 as the TA1OUT output pin.
Starts the TMRA1.
– = No change
φT1
TA01RUN.TA1RUN
Bits 7–2
UpCounter
Bit 1
Bit 0
0
1
2
3
0
1
2
3
0
1
2
3
0
Comparator Timing
Comparator Output
(Match Detect)
INTTA1
Up-Counter Clear
TA1FF
TA1OUT
0.6 µs @fc = 40 MHz
Figure 11.9 Square-Wave Generation (50% Duty Cycle)
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(3) Using the TMRA0 Match-Detect Output as a Trigger for the TMRA1
Set the TMRA01 in 8-bit interval timer mode. Select the TMRA0 comparator match-detect
output (TA0TRG) as the clock source for the TMRA1.
TMRA0 Comparator
Match Output
TMRA0 Up-Counter
(when TA0REG = 5)
1
2
TMRA1 Up-Counter
(when TA1REG = 2)
3
4
5
1
2
3
1
4
5
1
2
2
3
1
TMRA1 Match Output
Figure 11.10 Using the TMRA0 Match-Detect Output as a Trigger for the TMRA1
11.4.2
16-Bit Interval Timer Mode
The TMRA0 and the TMRA1 are cascadable to form a 16-bit interval timer. The TMRA01 is put in
16-bit interval timer mode by programming the TA01M[1:0] field in the TA01MOD register to 01.
In 16-bit interval timer mode, the TMRA1 is clocked by the counter overflow output from the
TMRA0. In this mode, the TA1CLK[1:0] bits in the TA01MOD register are don’t-cares. The clock
input to the TMRA0 can be selected from an external clock and one of three prescalar outputs (see
Table 11.2).
Write the lower eight bits of a time constant value to the TA0REG and the upper eight bits to the
TA1REG. Programming these registers should only be attempted when the timers are not running.
Example: Generating the INTTA1 interrupt at a 0.2-second interval (fc = 40 MHz)
Clocking conditions:
System clock:
High-speed (fc)
High-speed clock gear: ↕1 (fc)
Prescaler clock:
fperiph/4 (fperiph = fsys)
Under the above conditions, φT16 has a period of 3.2 µs @ 40 MHz. When φT16 is used as the
TMRA0 clock source, the required time constant value is calculated as follows:
0.2 s ÷ 3.2 µs = 62500 = H424H
Thus, the TA1REG is to be set to F4H and the TA0REG to 24H.
Every time the up-counter UC0 reaches the value in the TA0REG, the TMRA0 comparator
generates a match-detect output, but the TMRA0 continues counting up. A match between the
UC0 and the TA0REG does not cause an INTTA0 interrupt.
Every time the up-counter UC1 reaches the value in the TA1REG, the TMRA1 comparator
generates a match-detect output. When the TMRA0 and TMRA1 match-detect outputs are asserted
simultaneously, both the up-counters (UC0 and UC1) are reset to 00H and an interrupt is
generated on INTTA1. Also, if so enabled, the timer flip-flop (TA1FF) is toggled.
Example: TA1REG = 04H and TA0REG = 80H
Up-Counter Values 0000H
(UC1/UC0)
0080H
0180H
0280H
0380H
0480H
Match-Detect Signal from the
TMRA0 Comparator
INTTA1 Interrupt
Toggled
TA1OUT Timer Output
Figure 11.11 Timer Output in 16-Bit Interval Timer Mode
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11.4.3
8-Bit Programmable Pulse Generation (PPG) Mode
The 8-bit PPG mode can be used to generate a square wave with any frequency and duty cycle, as
shown below. The pulse can be high-going and low-going, as determined by the initial setting of the
timer flip-flop (TA1FF). This mode is supported by the TMRA0, but not by the TMRA1. The squarewave output is driven to the TA1OUT pin (which is multiplexed with P71).
tH
tL
t
Match Between TA0REG and
Up-Counter 0 (INTTA0)
Match Between TA1REG and
Up-Counter 0 (INTTA1)
TA1OUT
TA0REG
TA1REG
Figure 11.12 8-Bit PPG Output Waveform
In this mode, a square wave is generated by toggling the timer flip-flop (TA1FF). The TA1FF
changes state every time a match is detected between the UC0 and the TA0REG and between the UC0
and the TA1REG.
The TA0REG must be set to a value less than the TA1REG value.
In this mode, the TMRA1 up-counter (UC1) can not be independently used; however, the TMRA1
must be put in a running state by setting the TA1RUN bit in the TA01RUN register to 1.
Figure 11.3 shows a functional diagram of 8-bit PPG mode.
TA1OUT
Selector
TA01RUN.TA0RUN
φT1
φT4
φT16
8-Bit Up-Counter
(UC0)
TA1FF
TA1FFCR.TAFF1IE
Toggle
TA01MOD.TA0CLK[1:0]
INTTA0
Comparator
Selector
TA0REG-WR
Comparator
INTTA1
TA0REG
Shift-Trigger
Register Buffer
TA1REG
TA01RUN.TA0RDE
Internal Data Bus
Figure 11.13 Functional Diagram of 8-Bit PPG Mode
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In 8-bit PPG mode, if the double-buffering function is enabled, the TA0REG value can be changed
dynamically by writing a new value into the register buffer. Upon a match between the TA1REG and
the UC0, the TA0REG latches a new value from the register buffer.
The TA0REG can be loaded with a new value upon every match, thus making it easy to generate a
square wave with virtually any (and variable) duty cycle.
Match Between TA0REG
and Up-Counter 0
(Up-Counter = Q1)
(Up-Counter = Q2)
Match Between TA1REG
and Up-Counter
Shift-Trigger for Register Buffer
TA0REG (compare value)
Q1
Q2
Register Buffer
Q2
Q3
Write to TA0REG
(Register Buffer).
Figure 11.14 Register Buffer Operation
Example: Generating a 50-kHz square wave with a 25% duty cycle (fc = 40 MHz)
20 µs
Clocking conditions:
System clock:
High-speed (fc)
High-speed clock gear: ↕1 (fc)
Prescaler clock:
fperiph/4 (fperiph = fsys)
The time constant values to be loaded into the TA0REG and TA1REG are determined as
follows:
A 50-kHz waveform has a period of 20 µs. Under the above clocking conditions, φT1 has a 0.2-µs
resolution (@fc = 40 MHz). When φT1 is used as the timer clock source, the TA1REG should be
loaded with:
20 µs ÷ 0.2 µs = 100 (64H)
With a 25% duty cycle, the high pulse width is calculated as 20 µs × 1/4 = 5 µs. Thus, the
TA0REG should be loaded with:
5 µs ÷ 0.2 µs = 25 (19H)
MSB
LSB
TA01RUN
TA01MOD
7
← 0
← 1
6
X
0
5
X
X
4
X
X
3
−
X
2
0
X
1
0
0
0
0
1
TA0REG
TA1REG
TA1FFCR
← 0
← 0
← X
0
1
X
0
1
X
1
0
X
1
0
0
0
1
1
0
0
1
1
0
X
Stops and clears the TMRA0.
Selects 8-bit PPG mode and φT1 as the clock
source.
Writes 19H.
Writes 64H.
Sets the TA1FF to 1 and enables toggling.
If these bits are set to 10, a low-going pulse is
generated.
P7CR
P7FC
TA01RUN
X = Don’t care,
← −
← −
← 1
−
−
X
−
−
X
−
−
X
−
−
−
−
−
1
1
1
1
−
−
1
Configures P71 as the TA1OUT output pin.
Starts the TMRA0 and the TMRA1.
– = No change
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11.4.4
8-Bit PWM Generation Mode
The TMRA0 can be used as a pulse-width modulated (PWM) signal generator with up to 8 bits of
resolution. This mode is supported by the TMRA0, but not by the TMRA1. The PWM signal is driven
out on the TA1OUT pin (which is multiplexed with P71).
While the TMRA01 is in this mode, the TMRA1 is usable as an 8-bit interval timer. However, the
TMRA0 match-detect output can not be used as a clock source for the TMRA1, and the timer output is
not available for the TMRA1.
The timer flip-flop toggles when the up-counter (UC0) reaches the TA0REG value and when a 2n-1
counter overflow occurs, where n is programmable to 6, 7 or 8 through the PWM[01:00] field in the
TA01MOD register. The UC0 is reset to 00H upon a 2n-1 overflow.
In 8-bit PWM generation mode, the following must be satisfied:
(TA0REG value) < (2n-1 counter overflow value)
(TA0REG value) ≠ 0
Match Between TA0REG
and Up-Counter 0
2n-1 Overflow
(INTTA0 Interrupt)
TA1OUT
tPWM
(PWM Cycle)
Figure11.15 8-Bit PWM Signal Generation
Figure 11.16 shows a functional diagram of 8-bit PWM generation mode.
TA01RUN.TA0RUN
φT1
φT4
φT16
Selector
8-Bit Up-Counter
(UC0)
Comparator
TA1FFCR.
TAFF1IE
TA1FF
Clear
2n-1
Overflow
Control
TA01MOD.TA0CLK[1:0]
TA1OUT
Toggle
TA01MOD.
PWM[01:00]
Overflow
INTTA0
TA0REG
TA0REG-WR
Selector Shift-Trigger
Register Buffer
TA01RUN.TA0RDE
Internal Data Bus
Figure 11.16 Functional Diagram of 8-Bit PWM Generation Mode
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In 8-bit PWM generation mode, if the double-buffering function is enabled, the TA0REG value (i.e.,
the duty cycle) can be changed dynamically by writing a new value into the register buffer. Upon a 2n-1
counter overflow, the TA0REG latches a new value from the register buffer.
The TA0REG can be loaded with a new value upon every counter overflow, thus generating a PWM
signal with variable duty cycle.
Match Between TA0REG
and Up-Counter 0
Up-Counter = Q1
Up-Counter = Q2
n
2 -1 Overflow
Shift into TA0REG
TA0REG
(Compare Value)
Q1
Register Buffer
Q2
Q2
Q3
Write to TA0REG
(Register Buffer)
Figure11.17 Register Buffer Operation
Example: Generating a PWM signal as shown below on the TA1OUT pin (fc = 40 MHz)
14 µs
25.4 µs
Clocking conditions:
System clock:
High-speed (fc)
High-speed clock gear: ↕1 (fc)
Prescaler clock:
fperiph/4 (fperiph = fsys)
Under the above conditions, φT1 has a 0.2-µs period (@fc = 40 MHz).
25.4 µs ÷ 0.2 µs = 127
which is equal to 27 – 1.
14 µs ÷ 0.2 µs = 70 = 46H
Hence, the time constant value to be programmed into the TA0REG is 48H.
MSB
LSB
TA01RUN
TA01MOD
7
← −
← 1
6
X
1
5
X
1
4
X
0
3
−
−
2
−
−
1
−
0
0
0
1
TA0REG
TA1FFCR
← 0
← X
1
X
0
X
0
X
0
1
1
0
1
1
0
X
P7CR
P7FC
TA01RUN
← −
← −
← 1
−
−
X
−
−
X
−
−
X
−
−
−
−
−
1
1
1
−
−
−
1
X = Don’t care,
Stops and clears the TMRA0.
Selects 8-bit PWM mode (period = 27−1) and φT1 as
the clock source.
Writes 46H.
Clears the TA1FF to 0 and enables toggling.
Configures P71 as the TA1OUT output pin.
Starts the TMRA0.
– = No change
TMP1941AF-126
2003-03-27
TMP1941AF
Table 11.3 PWM Period
@fc = 40 MHz
Prescaler
Peripheral
Clock Gear
Clock
Clock
Value
Source
Select
SYSCR1.
SYSCR0.
SYSCR1.
GEAR[1:0]
PRCK[1:0]
FPSEL
00 (fc)
10 (fc/4)
00 (fperiph/4)
12.6 µs
50.4 µs
201.6 µs
25.4 µs
101.6 µs 406.4 µs
01 (fperiph/2)
6.3 µs
25.2 µs
100.8 µs
12.7 µs
50.8 µs
203.2 µs

12.6 µs
50.4 µs

25.4 µs
101.6 µs

51 µs
1 (fc)
10 (fc/4)
11 (fc/8)
φT16
φT1
φT4
φT16
51 µs
204 µs
816 µs
25.5 µs
102 µs
408 µs
204 µs
00 (fperiph/4)
25.2 µs
100.8 µs 403.2 µs
50.8 µs
203.2 µs 812.8 µs
102 µs
408 µs
1632 µs
01 (fperiph/2)
12.6 µs
50.4 µs
201.6 µs
25.4 µs
101.6 µs 406.4 µs
51 µs
204 µs
816 µs

25.2 µs
100.8 µs


102 µs
408 µs
50.8 µs
203.2 µs
00 (fperiph/4)
50.4 µs
201.6 µs 806.4 µs 101.6 µs 406.4 µs 1626 µs
204 µs
816 µs
3264 µs
01 (fperiph/2)
25.2 µs
100.8 µs 403.2 µs
102 µs
408 µs
1632 µs

201.6 µs
203.2 µs 812.8 µs

101.6 µs 406.4 µs

204 µs
816 µs
100.8 µs 403.2 µs 1613 µs 203.2 µs 812.8 µs 3251 µs
408 µs
1632 µs
6528 µs
01 (fperiph/2)
50.4 µs
204 µs
816 µs
3264 µs

408 µs
1632 µs

50.4 µs
50.8 µs
00 (fperiph/4)
201.6 µs 806.4 µs 101.6 µs 406.4 µs 1626 µs
100.8 µs 403.2 µs

203.2 µs 812.8 µs
00 (fperiph/4)
12.6 µs
50.4 µs
201.6 µs
25.4 µs
101.6 µs 406.4 µs
51 µs
204 µs
816 µs
01 (fperiph/2)
6.3 µs
25.2 µs
100.8 µs
12.7 µs
50.8 µs
203.2 µs
25.5 µs
102 µs
408 µs

12.6 µs
50.4 µs

25.4 µs
101.6 µs

51 µs
204 µs
00 (fperiph/4)
12.6 µs
50.4 µs
201.6 µs
25.4 µs
51 µs
204 µs
816 µs
01 (fperiph/2)

25.2 µs
100.8 µs

50.8 µs
203.2 µs

102 µs
408 µs
10 (fperiph)

12.6 µs
50.4 µs

25.4 µs
101.6 µs

51 µs
204 µs
00 (fperiph/4)

50.4 µs
201.6 µs

101.6 µs 406.4 µs

204 µs
816 µs
01 (fperiph/2)

25.2 µs
100.8 µs

50.8 µs
203.2 µs

102 µs
408 µs

101.6 µs


204 µs
101.6 µs 406.4 µs

204 µs
816 µs
10 (fperiph)
01 (fc/2)
φT4
8
φT1
10 (fperiph)
00 (fc)
2 −1
7
φT16
10 (fperiph)
11 (fc/8)
2 −1
φT4
10 (fperiph)
0 (fgear)
2 −1
φT1
10 (fperiph)
01 (fc/2)
PWM Period
6
101.6 µs 406.4 µs
10 (fperiph)


50.4 µs

00 (fperiph/4)

50.4 µs
201.6 µs

01 (fperiph/2)


100.8 µs


203.2 µs


408 µs
10 (fperiph)


50.4 µs


101.6 µs


204 µs
Note 1: The prescaler's output clock φTn must be selected so that φTn < fsys/2 is satisfied.
Note 2: Do not change the clock gear value while the timer is running.
Note 3: The — character means “Don’t use.”
TMP1941AF-127
2003-03-27
TMP1941AF
11.4.5
Operating Mode Summary
Table 11.4 shows the settings for the TMRA01 for each of the operating modes.
Table 11.4 Register Settings for Each Operating Mode
Register
TA01MOD
TA1FFCR
Field
TA01M[1:0]
PWM[01:00]
TA1CLK[1:0]
TA0CLK[1:0]
TAFF1IS
Function
Interval Timer
Mode
PWM Period
UC1 Clock
Source
UC0 Clock
Source
Timer Flip-Flop
Toggle-Trigger
External clock,
φT1, φT4, φT16
(00, 01, 10, 11)
0: UC0 output
1: UC1 output
8-Bit Timer × 2ch
00

Match output
from UC0
φT1, φT16, φT256
(00, 01, 10, 11)
16-Bit Timer Mode
01


External clock,
φT1, φT4, φT16
(00, 01, 10, 11)

8-Bit PPG × 1ch
10


External clock,
φT1, φT4, φT16
(00, 01, 10, 11)

11
26 − 1, 27 − 1,
28 − 1
(01, 10, 11)
φT1, φT16, φT256
(01, 10, 11)
External clock,
φT1, φT4, φT16
(00, 01, 10, 11)
PWM output
8-Bit PWM × 1ch
8-Bit Timer × 1ch (Note)
– = Don’t care
Note:
In 8-bit PWM generation mode, the UC1 can be used as an 8-bit timer. However, the match-detect output
from the UC0 can not be used as a clock source for the UC1, and the timer output is not avaialble for the
UC1.
TMP1941AF-128
2003-03-27
TMP1941AF
12. 16-Bit Timer/Event Counters (TMRBs)
The TMP1941AF has a 16-bit timer/event counter consisting of four identical channels (TMRB0–TMRB3).
Each channel has the following three basic operating modes:
•
16-bit interval timer mode
•
16-bit event counter mode
•
16-bit programmable pulse generation (PPG) mode
Each channel has the capture capability used to latch the value of the counter. The capture capability allows:
•
Frequency measurement
•
Pulse-width measurement
•
Time difference measurement
Figure 12.1 to Figure 12.4 are block diagrams of the TMRB0 to TMRB3.
The main components of a TMRBn block are a 16-bit up-counter, two 16-bit timer registers (one of which is
double-buffered), two 16-bit capture registers, two comparators, capture control logic, a timer flip-flop and its
associated control logic.
Each channel is independently programmable and functionally equivalent except that the TMRB3 has no
external clock/capture trigger inputs. Table 12.1 gives the pins and registers for the four channels. In the
following sections, any references to the TMRB0 also apply to all the other channels.
Table 12.1 Pins and Registers for the Four TMRBn Channels
TMRB0
External Pins
TMRB2
TMRB3
TB0IN0
(Shared with P74)
TB1IN0
(Shared with P80)
TB2IN0
(Shared with P83)
TB0IN1
(Shared with P75)
TB1IN1
(Shared with P81)
TB2IN1
(Shared with P84)
TB0OUT0
(Shared with P76)
TB1OUT0
(Shared with P82)
TB2OUT
(Shared with P85)
TB3OUT
(Shared with P86)
Timer Run register
TB0RUN
(0xFFFF_F180)
TB1RUN
(0xFFFF_F190)
TB2RUN
(0xFFFF_F1A0)
TB3RUN
(0xFFFF_F1B0)
Timer Mode register
TB0MOD
(0xFFFF_F182)
TB1MOD
(0xFFFF_F192)
TB2MOD
(0xFFFF_F1A2)
TB3MOD
(0xFFFF_F1B2H
Timer Flip-Flop
Control register
TB0FFCR
(0xFFFF_F183)
TB1FFCR
(0xFFFF_F193)
TB2FFCR
(0xFFFF_F1A3)
TB3FFCR
(0xFFFF_F1B3)
TB0RG0L
(0xFFFF_F188)
TB1RG0L
(0xFFFF_F198)
TB2RG0L
(0xFFFF_F1A8)
TB3RG0L
(0xFFFF_F1B8)
TB0RG0H
(0xFFFF_F189)
TB1RG0H
(0xFFFF_F199)
TB2RG0H
(0xFFFF_F1A9)
TB3RG0H
(0xFFFF_F1B9)
TB0RG1L
(0xFFFF_F18A)
TB1RG1L
(0xFFFF_F19A)
TB2RG1L
(0xFFFF_F1AA)
TB3RG1L
(0xFFFF_F1BA)
TB0RG1H
(0xFFFF_F18B)
TB1RG1H
(0xFFFF_F19B)
TB2RG1H
(0xFFFF_F1AB)
TB3RG1H
(0xFFFF_F1BB)
TB0CP0L
(0xFFFF_F18C)
TB1CP0L
(0xFFFF_F19C)
TB2CP0L
(0xFFFF_F1AC)
TB3CP0L
(0xFFFF_F1BC)
TB0CP0H
(0xFFFF_F18D)
TB1CP0H
(0xFFFF_F19D)
TB2CP0H
(0xFFFF_F1AD)
TB3CP0H
(0xFFFF_F1BD)
TB0CP1L
(0xFFFF_F18E)
TB1CP1L
(0xFFFF_F19E)
TB2CP1L
(0xFFFF_F1AE)
TB3CPIL
(0xFFFF_FIBE)
TB0CP1H
(0xFFFF_F18F)
TB1CP1H
(0xFFFF_F19F)
TB2CP1H
(0xFFFF_F1AF)
TB3CPIH
(0xFFFF_FIBF)
External clock /
Capture trigger
inputs
Timer flip-flop output
Registers
(Addresses)
TMRB1
Timer registers
Capture registers
TMP1941AF-129

2003-03-27
TA1OUT
(From TMRA01)
TB0IN0
TB0IN1
Prescaler Clock
Source: φT0
4
φT4
φT16
8 16 32
TMP1941AF-130
TB0RUN.
TB0RDE
Counter
Clock
Internal Data Bus
Register Buffer 0
16-Bit Timer Register
TB0RG0H/L
16-Bit Comparator
(CP0)
Internal Data Bus
16-Bit Timer Register
TB0RG1H/L
TB0FF0
Timer
Flip-Flop
Match Detect
Timer FlipFlop
Control
16-Bit Comparator
(CP1)
TB0RUN.TB0RUN
TB0MOD.TB0CLE
Capture Register 1
TB0CP1H/L
Internal Data Bus
16-Bit Up-Counter (UC0)
Match Detect
TB0MOD.TB0CLK[1:0]
Selector
Capture Register 0
TB0CP0H/L
TB0RUN.
TB0PRUN
TB0MOD.
TB0CP0
TB0MOD.
φT1
TB0CPM[1:0] φT4
φT16
Capture &
External
Interrupt Control
φT1
2
Run/
Clear
Internal Data Bus
Interrupt Output
Register 0 Register 1
INTTB00 INTTB01
Overflow
Interrupt
INTTBOF0
Timer FlipFlop Output
TB0OUT
TMP1941AF
12.1 Block Diagrams
Figure 12.1 TMRB0 Block Diagram
2003-03-27
TA1OUT
(From TMRA01)
TB1IN0
TB1IN1
Prescalar Clock
Source: φT0
4
φT4
φT16
TMP1941AF-131
TB1RUN.
TB1RDE
Count
Clock
Internal Data Bus
Register Buffer 0
16-Bit Timer Register
TB1RG0H/L
16-Bit Comparator
(CP0)
Match
Detect
Internal Data Bus
16-Bit Timer Register
TB1RG1H/L
Match
Detect
Timer FlipFlop
Control
16-Bit Comparator
(CP1)
TB1RUN.TB1RUN
TB1MOD.TB1CLE
Capture Register 1
TB1CP1H/L
Internal Data Bus
16-Bit Up-Counter (UC1)
Capture Register 0
TB1CP0H/L
TB1MOD.TB1CLK[1:0]
Selector
TB1MOD.
TB1CP0
TB1MOD.
φT1
TB1CPM[1:0] φT4
φT16
Capture &
External
Interrupt Control
φT1
2
Run/
Clear TB1RUN.
8 16 32
TB1PRUN
Internal Data Bus
Overflow
Interrupt
INTTBOF1
Timer
Timer FlipFlip-Flop Flop Output
TB1OUT
TB1FF0
Interrupt Output
Register 0 Register 1
INTTB10 INTTB11
TMP1941AF
Figure 12.2 TMRB1 Block Diagram
2003-03-27
TA1OUT
(From TMRA01)
TB2IN0
TB2IN1
Prescalar Clock
Source: φT0
4
φT4
φT16
TMP1941AF-132
TB2RUN.
TB2RDE
Count
Clock
Internal Data Bus
Register Buffer 0
16-Bit Timer Register
TB2RG0H/L
16-Bit Comparator
(CP0)
Match
Detect
Internal Data Bus
16-Bit Timer Register
TB2RG1H/L
Match
Detect
Timer FlipFlop
Control
16-Bit Comparator
(CP1)
TB2RUN.TB2RUN
TB2MOD.TB2CLE
Capture Register 1
TB2CP1H/L
Internal Data Bus
16-Bit Up-Counter (UC2)
Capture Register 0
TB2CP0H/L
TB2MOD.TB2CLK[1:0]
Selector
TB2MOD.
TB2CP0
TB2MOD.
φT1
TB2CPM[1:0] φT4
φT16
Capture &
External
Interrupt Control
φT1
2
Run/
Clear TB2RUN.
8 16 32
TB2PRUN
Internal Data Bus
Overflow
Interrupt
INTTBOF2
Timer
Timer FlipFlip-Flop Flop Output
TB2OUT
TB2FF0
Interrupt Output
Register 0 Register 1
INTTB20 INTTB21
TMP1941AF
Figure 12.3 TMRB2 Block Diagram
2003-03-27
TA1OUT
(From TMRA01)
Prescalar Clock
Source: φT0
4
φT4
φT16
TMP1941AF-133
TB3RUN.
TB3RDE
Count
Clock
Internal Data Bus
Register Buffer 0
16-Bit Timer Register
TB3RG0H/L
16-Bit Comparator
(CP0)
Match
Detect
Internal Data Bus
16-Bit Timer Register
TB3RG1H/L
Match
Detect
Timer FlipFlop
Control
16-Bit Comparator
(CP1)
TB3RUN.TB3RUN
TB3MOD.TB3CLE
Capture Register 1
TB3CP1H/L
Internal Data Bus
16-Bit Up-Counter (UC3)
Capture Register 0
TB3CP0H/L
TB3MOD.TB3CLK[1:0]
Selector
TB3MOD.
TB3CP0
TB3MOD.
φT1
TB3CPM[1:0] φT4
φT16
Capture &
External
Interrupt Control
φT1
2
Run/
Clear TB3RUN.
8 16 32
TB3PRUN
Internal Data Bus
Overflow
Interrupt
INTTBOF3
Timer
Timer FlipFlip-Flop Flop Output
TB3OUT
TB3FF0
Interrupt Output
Register 0 Register 1
INTTB30 INTTB31
TMP1941AF
Figure 12.4 TMRB3 Block Diagram
2003-03-27
TMP1941AF
12.2 Timer Components
12.2.1
Prescaler
The TMRB0 has a 5-bit prescalar that slows the rate of a clocking source to the counter. The
prescalar clock source (φT0) can be selected from fperiph, fperiph/2 and fperiph/4 by programming the
PRCK[1:0] field of the SYSCR0 located within the CG. fperiph can be selected from fgear (geared
clock) and fc (non-geared clock) by programming the FPSEL bit of the SYSCR1 located within the CG.
The TB0RUN bit in the TB0RUN register allows the enabling and disabling of the TMRB0 prescalar.
A write of 1 to this bit starts the prescalar. A write of 0 to this bit clears and halts the prescalar.
Prescalar output taps can be divide-by-2 (φT1), divide-by-8 (φT4) and divide-by-32 (φT16). Table
12.2 shows prescalar output clock resolutions (@fc = 32 MHz).
Table 12.2 Prescaler Output Clock Resolutions
@fc = 40 MHz
Peripheral Clock
Select
SYSCR1.FPSEL
Clock Gear Value
SYSCR1.GEAR[1:0]
Prescaler Clock
Source
SYSCR0.PRCK[1:0]
00 (fperiph/4)
00 (fc)
Prescaler Output Clock Resolution
φT1
3
fc/2 (0.2 µs)
2
01 (fperiph/2)
01 (fc/2)
10 (fc/4)
fc/2 (3.2 µs)
fc/2 (0.8 µs)
fc/2 (1.6 µs)
fc/2 (6.4 µs)
8
fc/2 (0.8 µs)
7
6
9
8
7
10
fc/2
(25.6 µs)
9
8
5
fc/2 (3.2 µs)
4
fc/2 (1.6 µs)
3
fc/2 (0.8 µs)
fc/2 (0.1 µs)
fc/2 (0.4 µs)

fc/2 (0.2 µs)
fc/2 (0.2 µs)
fc/2 (0.8 µs)

8
fc/2 (6.4 µs)
fc/2 (0.2 µs)
3
5
6
fc/2 (1.6 µs)
2
6
fc/2 (12.8 µs)

3
7
7
fc/2 (3.2 µs)
01 (fperiph/2)
11 (fc/8)
5

fc/2 (0.8 µs)
00 (fperiph/4)
10 (fc/4)
fc/2 (6.4 µs)
fc/2 (1.6 µs)
10 (fperiph)
1 (fc)
fc/2 (12.8 µs)
6
fc/2 (0.4 µs)
5
01 (fperiph/2)
01 (fc/2)
7
fc/2 (3.2 µs)
10 (fperiph)
00 (fc)
fc/2 (1.6 µs)
fc/2 (0.8 µs)
6
01 (fperiph/2)
00 (fperiph/4)
fc/2 (3.2 µs)
4
fc/2 (0.8 µs)
fc/2 (0.4 µs)
10 (fperiph)
11 (fc/8)
fc/2 (6.4 µs)
5

4
00 (fperiph/4)
6
fc/2 (1.6 µs)
5
01 (fperiph/2)
fc/2 (0.8 µs)
fc/2 (0.4 µs)
fc/2 (0.2 µs)
00 (fperiph/4)
3
fc/2 (0.2 µs)
10 (fperiph)
0 (gear)
fc/2 (1.6 µs)

3
01 (fperiph/2)
fc/2 (3.2 µs)
fc/2 (0.4 µs)
4
φT16
4
fc/2 (0.8 µs)
fc/2 (0.1 µs)
10 (fperiph)
00 (fperiph/4)
φT4
5
7
6
5
5
fc/2 (3.2 µs)
4
fc/2 (1.6 µs)
3
fc/2 (0.8 µs)
5
fc/2 (3.2 µs)
4
fc/2 (0.4 µs)
10 (fperiph)

fc/2 (0.2 µs)
00 (fperiph/4)

fc/2 (0.8 µs)
7
6
5
7
6
01 (fperiph/2)

fc/2 (0.4 µs)
fc/2 (1.6 µs)
10 (fperiph)


fc/2 (0.8 µs)
00 (fperiph/4)

fc/2 (0.8 µs)
fc/2 (3.2 µs)
01 (fperiph/2)


fc/2 (1.6 µs)
10 (fperiph)


fc/2 (0.8 µs)
5
5
7
6
5
Note 1: The prescaler's output clock φTn must be selected so that the relationship φTn < fsys/2 is satisfied.
Note 2: Do not change the clock gear value while the timer is running.
Note 3: The — character means “Don’t use.”
TMP1941AF-134
2003-03-27
TMP1941AF
12.2.2
Up-Counter (UC0)
The TMRB0 contains a 16-bit binary up-counter, which is driven by a clock selected by the
TB0CLK[1:0] field in the TB0MOD register. The clock input to the UC0 is either one of three prescalar
outputs (φΤ1,φT4, φT16) or the external clock applied to the TB0IN0 pin. The clock input can be
selected through the programming of the TB0CLK[1:0] field in the TB0MOD register.
The TB0RUN bit in the TB0RUN register is used to start the UC0 and to stop and clear the UC0. The
UC0 is cleared to 0000H, if so enabled, when it reaches the value in the TB0RG1H/L register. The
TB0CLE bit in the TB0MOD register allows the user to enable and disable this clearing. If it is
disabled, the UC0 acts as a free-running counter.
An overflow interrupt (INTTBOF0) is generated upon a counter overflow.
Note:
12.2.3
Programming the TB0CLK[1:0] and TB0CLE bits in the TB0MOD register should only be attempted
when the timer is not running.
Timer Registers (TB0RG0H/L and TB0RG1H/L)
Each timer channel has two 16-bit timer registers containing a time constant. When the up-counter
reaches the time constant value in each timer register, the associated comparator block generates a
match-detect signal.
Each of the timer registers (TB0RG0H/L, TB0RG1H/L) can be written with either a halfword-store
instruction or a series of two byte-store instructions. When byte-store instructions are used, the loworder byte must be stored first, followed by the high-order byte. The 16-bit timer registers are often
simply referred to as TB0RG0 and TB0RG1 without the H and L suffix.
One of the two timer registers, TB0RG0, is double-buffered. The double-buffering function can be
enabled and disabled through the programming of the TB0RDE bit in the TB0RUN: 0=disable,
1=enable.
If double-buffering is enabled, the TB0RG0 latches a new time constant value from the register
buffer. This takes place when a match is detected between the UC0 and the TB0RG1.
Upon reset, the contents of the TB0RG0 and TB0RG1 are undefined; thus, they must be loaded with
valid values before the timer can be used. A reset clears the TB0RUN.TB0RDE bit to 0, disabling the
double-buffering function. To use this function, the TB0RUN.TB0RDE bit must be set to 1 after
loading the TB0RG0 and TB0RG1 with time constants. When TB0RUN.TB0RDE=1, the next time
constant can be written to the register buffer.
Note 1: The TB0RG0 and the corresponding register buffer are mapped to the same address (0xFFFF_F188
thru 0xFFFF_F189). When TB0RUN.TB0RDE=0, a time constant value is written to both the TB0RG0
and the register buffer; when TB0RUN.TB0RDE=1, a time constant value is written only to the
register buffer. Therefore, the double-buffering function should be disabled when writing an initial
time constant to the timer register.
Note 2: Programming the TB0RDE bit should only be attempted when the timer is not running.
The following diagram shows the addresses of each timer register.
TMP1941AF-135
2003-03-27
TMP1941AF
TMRB0
TB0RG0
TB0RG1
8 high-order bits
8 low-order bits
8 high-order bits
8 low-order bits
0xFFFF_F189
0xFFFF_F188
0xFFFF_F18B
0xFFFF_F18A
TMRB1
TB1RG0
TB1RG1
8 high-order bits
8 low-order bits
8 high-order bits
8 low-order bits
0xFFFF_F199
0xFFFF_F198
0xFFFF_F19B
0xFFFF_F19A
TMRB2
TB2RG0
TB2RG1
8 high-order bits
8 low-order bits
8 high-order bits
8 low-order bits
0xFFFF_F1A9
0xFFFF_F1A8
0xFFFF_F1AB
0xFFFF_F1AA
TMRB3
TB3RG0
TB3RG1
8 high-order bits
8 low-order bits
8 high-order bits
8 low-order bits
0xFFFF_F1B9
0xFFFF_F1B8
0xFFFF_F1BB
0xFFFF_F1BA
The Timer registers are write-only registers and cannot be read.
12.2.4
Capture Registers (TB0CP0H/L and TB0CP1H/L)
The capture registers are 16-bit registers used to latch the value of the up-counter (UC0).
Each of the capture registers can be read with either a halfword-load instruction or a series of two
byte-load instructions. When byte-load instructions are used, the low-order byte must be read first,
followed by the high-order byte. The 16-bit capture registers are often simply referred to as TBnCP and
TBnCP1 without the H and L suffix.
The following diagram shows the addresses of each capture register.
TMP1941AF-136
2003-03-27
TMP1941AF
TMRB0
TB0CP0
TB0CP1
8 high-order bits
8 low-order bits
8 high-order bits
8 low-order bits
0xFFFF_F18D
0xFFFF_F18C
0xFFFF_F18F
0xFFFF_F18E
TMRB1
TB1CP0
TB1CP1
8 high-order bits
8 low-order bits
8 high-order bits
8 low-order bits
0xFFFF_F19D
0xFFFF_F19C
0xFFFF_F19F
0xFFFF_F19E
TMRB2
TB2CP0
TB2CP1
8 high-order bits
8 low-order bits
8 high-order bits
8 low-order bits
0xFFFF_F1AD
0xFFFF_F1AC
0xFFFF_F1AF
0xFFFF_F1AE
TMRB3
TB3CP0
TB3CP1
8 high-order bits
8 low-order bits
8 high-order bits
8 low-order bits
0xFFFF_F1BD
0xFFFF_F1BC
0xFFFF_F1BF
0xFFFF_F1BE
The Capture registers are read-only registers and cannot be written by software.
12.2.5
Capture Control Logic
The capture control logic controls the capture of an up-counter (UC0) value into the capture registers
(TB0CP0 and TB0CP1). The TB0CPM[1:0] field in the TB0MOD register selects a capture trigger
input to be sensed by the capture control logic.
Futhermore, a counter value can be captured under software control; a write of 0 to the
TB0MOD.TB0CP0 bit causes the current UC0 value to be latched into the TB0CP0. To use the capture
capability, the prescalar must be running (i.e., TB0RUN.TB0PRUN=1).
Note 1: Reading the eight low-order bits of a capture register disables the capture capability. Reading the
eight high-order bits thereafter re-enables the capture capability. The reading of a whole capture
register should be completed during an interval between active transitions on the defined capture
trigger input.
Note 2: Don’t stop the timer after only reading the eight low-order bits of a capture register. If this is done,
the capture capability continues to remain in the disabled state even after the timer is restarted.
Note 3: When the TB0IN0 pin is selected as a capture trigger input, it can not function as a timer clock
source.
TMP1941AF-137
2003-03-27
TMP1941AF
12.2.6
Comparators (CP0 and CP1)
The TMRB0 contains two 16-bit comparators. The CP0 block compares the output of the up-counter
(UC0) with a time constant value in the TB0RG0. The CP1 block compares the output of the UC0 with
a time constant value in the TB0RG1. When a match is detected, an interrupt (INTTB00/INTTB01) is
generated.
12.2.7
Timer Flip-Flop (TB0FF0)
The timer flip-flop (TB0FF0) is toggled, if so enabled, upon assertion of match-detect signals from
the comparators and latch signals from the capture control logic. The toggling of the TB0FF0 can be
enabled and disabled through the programming of the TB0C1T1, TB0C0T1, TB0E1T1 and TB0E0T1
bits in the TB0FFCR register.
Upon reset, the TB0FF0 assumes an undefined state. The TB0FF0 can be initialized to 1 or 0 by
writing 01 or 10 to the TB0FF0C[1:0] field in the TB0FFCR. A write of 01 to this field sets the
TB0FF0; a write of 10 to this field clears the TB0FF0. Additionally, a write of 00 causes the TB0FF0 to
be toggled to the opposite value.
The value of the TB0FF0 can be driven onto the TB0OUT pin, which is multiplxed with P76. The
Port 7 registers (P7CR and P7FC) must be programmed to configure the P76/TB0OUT pin as TB0OUT.
Note: Programming the TB0FF0C[1:0] field should only be attempted when the timer is not running.
TMP1941AF-138
2003-03-27
TMP1941AF
12.3 Register Description
TMRB0 Run register
7
Name
TB0RUN
(0xFFFF_F180) Read/Write
Reset Value
Function
6
5
4
3
2
1
0
TB0RDE



I2TB0
TB0PRUN

TB0RUN
R/W
R/W


R/W
R/W

R/W
0
0


0
0

Double
Buffering
0: Disable
1: Enable
Must be
written as
0.
IDLE
0: Off
1: On
0
Run/Stop
Control
0: Stop &
clear
1: Run
Prescalar
Run/Stop
Control
0: Stop
1: Run
I2TB0: Timer on/off in IDLE mode
TB0PRUN: Prescaler
TB0RUN: TMRB0
Note:
Bits 1, 4 and 5 are read as undefined.
TMRB1 Run register
TB1RUN
(0xFFFF_F190)
7
6
5
4
3
2
1
0
TB1RDE



I2TB1
TB1PRUN

TB1RUN
Read/Write
R/W
R/W


R/W
R/W

R/W
Reset Value
0
0


0
0

0
Double
Buffering
0: Disable
1: Enable
Must be
written as
0.
Name
Function
IDLE
0: Off
1: On
Prescalar
Run/Stop
Control
0: Stop
1: Run
Run/Stop
Control
0: Stop &
clear
1: Run
I2TB1: Timer on/off in IDLE mode
TB1PRUN: Prescaler
TB1RUN: TMBR1
Note:
Bits 1, 4 and 5 are read as undefined.
Figure 12.5 Timer Run Registers
TMP1941AF-139
2003-03-27
TMP1941AF
TMRB2 Run register
TB2RUN
(0xFFFF_F1A0)
Name
Read/Write
Reset Value
Function
7
6
5
4
3
2
1
0
TB2RDE



I2TB2
TB2PRUN

TB2RUN
R/W
R/W


R/W
R/W

R/W
0
0


0

Double
Buffering
0: Disable
1: Enable
Must be
written as
0.
0
IDLE
0: Off
1: On
0
Run/Stop
Control
0: Stop &
clear
1: Run
Prescalar
Run/Stop
Control
0: Stop
1: Run
I2TB2: Timer on/off in IDLE mode
TB2PRUN: Prescaler
TB2RUN: TMRB2
Note:
Bits 1, 4 and 5 are read as undefined.
TMRB3 Run register
7
TB3RUN
(0xFFFF_F1B0)
6
5
4
3
2
1
0
TB3RDE



I2TB3
TB3PRUN

TB3RUN
Read/Write
R/W
R/W


R/W
R/W

R/W
Reset Value
0
0


0
0

Double
Buffering
0: Disable
1: Enable
Must be
written as
0.
Name
Function
IDLE
0: Off
1: On
Prescalar
Run/Stop
Control
0: Stop
1: Run
0
Run/Stop
Control
0: Stop &
clear
1: Run
I2TB3: Timer on/off in IDLE mode
TB3PRUN: Prescaler
TB3RUN: TMRB3
Note:
Bits 1, 4 and 5 are read as undefined.
Figure 12.6 Timer Run Registers
TMP1941AF-140
2003-03-27
TMP1941AF
TMRB0 Mode Register
TB0MOD
(0xFFFF_F182)
Name
7
6
5


TB0CP0
Read/Write
Reset Value
R/W
0
3
W*
0
1
Must be written as 00.
Function
4
TB0CPM1 TB0CPM0
1
0
TB0CLK1
TB0CLK0
0
0
R/W
0
Software
capture
0: Capture
1: Don’t
care
2
TB0CLE
0
Capture triggers
00: Disabled
01: TB0IN0↑TB0IN1↑
10: TB0IN0↑TB0IN0↓
11: TA1OUT↑TA1OUT↓
0
UC0 clear
control
0: Disable
1: Enable
TMRB0 clock source
00: TB0IN0 input
01: φT1
10: φT4
11: φT16
Up-counter (UC0) clear control
0
Disabled
1
UC0 is reset upon a match with TB0RG1.
Capture triggers
00
Capture disabled
01
Latches UC0 value into TB0CP0 at rising edges of TB0IN0
Latches UC0 value into TB0CP1 at rising edges of TB0IN1.
10
Latches UC0 value into TB0CP0 at rising edges of TB0IN0.
Latches UC0 value into TB0CP1 at falling edges of TB0IN0.
11
Latches UC0 value into TB0CP0 at rising edges of TA1OUT.
Latches UC0 value into TB0CP1 at falling edges of TA1OUT.
Software capture
0
Latches UC0 value into TB0CP0.
1
Don’t care
Figure 12.7 TMRB0 Mode Register
TMP1941AF-141
2003-03-27
TMP1941AF
TMRB1 Mode Register
TB1MOD
(0xFFFF_F192)
Name
7
6
5


TB1CP0
Read/Write
Reset Value
R/W
0
3
W*
0
1
Must be written as 00.
Function
4
TB1CPM1 TB1CPM0
1
0
TB1CLK1
TB1CLK0
0
0
R/W
0
Software
capture
0: Capture
1: Don’t
care
2
TB1CLE
0
Capture triggers
00: Disabled
01: TB1IN0↑TB1IN1↑
10: TB1IN0↑TB1IN0↓
11: TA1OUT↑TA1OUT↓
0
UC1 clear
control
0: Disable
1: Enable
TMRB1 clock source
00: TB1IN0 input
01: φT1
10: φT4
11: φT16
Up-counter (UC1) clear control
0
Disabled
1
UC1 is reset upon a match with TB1RG1.
Capture triggers
00
Capture disabled
01
Latches UC1 value into TB1CP0 at rising edges of TB1IN0
Latches UC1 value into TB1CP1 at rising edges of TB1IN1.
10
Latches UC1 value into TB1CP0 at rising edges of TB1IN0.
Latches UC1 value into TB1CP1 at falling edges of TB1IN0.
11
Latches UC1 value into TB1CP0 at rising edges of TA1OUT.
Latches UC1 value into TB1CP1 at falling edges of TA1OUT.
Software capture
0
Latches UC1 value into TB1CP0.
1
Don’t care
Figure 12.8 TMRB1 Mode Register
TMP1941AF-142
2003-03-27
TMP1941AF
TMRB2 Mode Register
Name
TB2MOD
(0xFFFF_F1A2) Read/Write
Reset Value
7
6
5


TB2CP0
R/W
0
3
W*
0
1
Must be written as 00.
Function
4
TB2CPM1 TB2CPM0
1
0
TB2CLK1
TB2CLK0
0
0
R/W
0
Software
capture
0: Capture
1: Don’t
care
2
TB2CLE
0
0
Capture triggers
00: Disabled
01: TB2IN0↑TB2IN1↑
10: TB2IN0↑TB2IN0↓
11: TA1OUT↑TA1OUT↓
UC2 clear
control
0: Disable
1: Enable
TMRB2 clock source
00: TB2IN0 input
01: φT1
10: φT4
11: φT16
Up-counter (UC2) clear control
0
Disabled
1
UC2is reset upon a match with TB2RG1.
Capture triggers
Capture Triggers
00
Capture disabled
01
Latches UC2 value into TB2CP0 at rising edges of TB2IN0.
Latches UC2 value into TB2CP1 at rising edges of TB2IN1.
10
Latches UC2 value into TB2CP0 at rising edges of TB2IN0.
Latches UC2 value into TB2CP1 at falling edges of TB2IN0.
11
Latches UC2 value into TB2CP0 at rising edges of TA1OUT.
Latches UC2 value into TB2CP1 at falling edges of TA1OUT.
Software capture
0
Latches UC2 value into TB2CP0.
1
Don’t care
Figure 12.9 TMRB2 Mode Register
TMP1941AF-143
2003-03-27
TMP1941AF
TMRB3 Mode Register
Name
TB3MOD
(0xFFFF_F1B2) Read/Write
Reset Value
7
6
5


TB3CP0
R/W
0
3
W*
0
1
Must be written as 00.
Function
4
TB3CPM1 TB3CPM0
1
0
TB3CLK1
TB3CLK0
0
0
R/W
0
Software
capture
0: Capture
1: Don’t
care
2
TB3CLE
0
Capture triggers
00: Disabled
01: Disabled
10: Disabled
11: TA1OUT↑TA1OUT↓
0
UC3 clear
control
0: Disable
1: Enable
TMRB3 clock source
00: TB3IN0 input
01: φT1
10: φT4
11: φT16
Up-counter (UC3) clear control
0
Disabled
1
UC3 is reset upon a match with TB3RG1.
Capture triggers
00
Capture disabled
01
Capture disabled
10
Capture disabled
11
Latches UC3 value into TB3CP0 at rising edges of TA1OUT.
Latches UC3 value into TB3CP1 at falling edges of TA1OUT.
Software capture
0
Latches UC3 value into TB3CP0.
1
Don’t care
Figure 12.10 TMRB3 Mode Register
TMP1941AF-144
2003-03-27
TMP1941AF
TMRB0 Timer Flip-Flop Control Register
Name
TB0FFCR
(0xFFFF_F183) Read/Write
Reset Value
Function
7
6
5
4
3


TB0C1T1
TB0C0T1
TB0E1T1
W*
1
2
1
R/W
1
0
Must be written as 11.
* This field is always
read as 11.
0
W*
0
0
TB0FF0 toggle-trigger
0: Trigger disabled
1: Trigger enabled
UC0
UC0 →
→TB0CP1 TB0CP0
0
TB0E0T1 TB0FF0C1 TB0FF0C0
UC0 =
TB0RG1
UC0 =
TB0RG0
1
1
TB0FF0 control
00: Toggle
01: Set
10: Clear
11: Don’t care
* This field is always
read as 11.
Timer flip-flop (TB0FF0) control
00
Toggles TB0FF0. (software toggle)
01
Sets TB0FF0 to 1.
10
Clears TB0FF0 to 0.
11
Don’t care (read as 11)
When UC0 reaches TB0RG0 value.
0
Toggle-trigger disabled
1
Toggle-trigger enabled
When UC0 reaches TB0RG1 value.
0
Toggle-trigger disabled
1
Toggle-trigger enabled
When UC0 value is latched into TB0CP0 (see Note).
0
Toggle-trigger disabled
1
Toggle-trigger enabled
When UC0 value is latched into TB0CP1.
0
Toggle-trigger disabled
1
Note:
Toggle-trigger enabled
Capturing the counter value into TB0CP0 via a software capture also generates a toggle-trigger
to TB0FF0.
Figure 12.11 TMRB0 Timer Flip-Flop Control Register
TMP1941AF-145
2003-03-27
TMP1941AF
TMRB1 Timer Flip-Flop Control Register
Name
TB1FFCR
(0xFFFF_F193) Read/Write
Reset Value
Function
7
6
5
4
3


TB1C1T1
TB1C0T1
TB1E1T1
W*
1
2
1
R/W
1
0
Must be written as 11.
* This field is always
read as 11.
0
W*
0
0
TB1FF0 toggle-trigger
0: Trigger disabled
1: Trigger enabled
UC1 →
TB1CP1
UC1 →
TB1CP0
0
TB1E0T1 TB1FF0C1 TB1FF0C0
UC1 =
TB1RG1
UC1 =
TB1RG0
1
1
TB1FF0 control
00: Toggle
01: Set
10: Clear
11: Don’t care
* This field is always
read as 11.
Timer flip-flop (TB1FF0) control
00
Toggles TB1FF0. (software toggle)
01
Set TB1FF0 to 1.
10
Clears TB1FF0 to 0.
11
Don’t care (read as 11)
When UC1 reaches TB1RG0 value.
0
Toggle-trigger disabled
1
Toggle-trigger enabled
When UC1 reaches TB1RG1 value.
0
Toggle-trigger disabled
1
Toggle-trigger enabled
When UC1 value is latched into TB1CP0 (see Note).
0
Toggle-trigger disabled
1
Toggle-trigger enabled
When UC1 value is latched into TB1CP1.
0
Toggle-trigger disabled
1
Note:
Toggle-trigger enabled
Capturing the counter value into TB1CP0 via a software capture also generates a toggle-trigger
to TB1FF0.
Figure 12.12 TMRB1 Timer Flip-Flop Control Register
TMP1941AF-146
2003-03-27
TMP1941AF
TMRB2 Timer Flip-Flop Control Register
Name
TB2FFCR
(0xFFFF_F193) Read/Write
Reset Value
Function
7
6
5
4
3


TB2C1T1
TB2C0T1
TB2E1T1
W*
1
2
1
R/W
1
0
Must be written as 11.
* This field is always
read as 11.
0
W*
0
0
TB2FF0 toggle-trigger
0: Trigger disabled
1: Trigger enabled
UC2 →
TB2CP1
UC2 →
TB2CP0
0
TB2E0T1 TB2FF0C1 TB2FF0C0
UC2 =
TB2RG1
UC2 =
TB2RG0
1
1
TB2FF0 control
00: Toggle
01: Set
10: Clear
11: Don’t care
* This field is always
read as 11.
Timer flip-flop (TB2FF0) control
00
Toggles TB2FF0. (software toggle)
01
Set TB2FF0 to 1.
10
Clears TB2FF0 to 0.
11
Don’t care (read as 11)
When UC2 reaches TB2RG0 value.
0
Toggle-trigger disabled
1
Toggle-trigger enabled
When UC2 reaches TB2RG1 value.
0
Toggle-trigger disabled
1
Toggle-trigger enabled
When UC2 value is latched into TB2CP0 (see Note).
0
Toggle-trigger disabled
1
Toggle-trigger enabled
When UC2 value is latched into TB2CP1.
0
Toggle-trigger disabled
1
Note:
Toggle-trigger enabled
Capturing the counter value into TB2CP0 via a software capture also generates a toggle-trigger
to TB2FF0.
Figure 12.13 TMRB2 Timer Flip-Flop Control Register
TMP1941AF-147
2003-03-27
TMP1941AF
TMRB3 Timer Flip-Flop Control Register
Name
TB3FFCR
(0xFFFF_F1B3) Read/Write
Reset Value
Function
7
6
5
4
3


TB3C1T1
TB3C0T1
TB3E1T1
W*
1
2
1
R/W
1
0
Must be written as 11.
* This field is always
read as 11.
0
W*
0
0
TB3FF0 toggle-trigger
0: Trigger disabled
1: Trigger enabled
UC3 →
TB3CP1
UC3 →
TB3CP0
0
TB3E0T1 TB3FF0C1 TB3FF0C0
UC3 =
TB3RG1
UC3 =
TB3RG0
1
1
TB3FF0 control
00: Toggle
01: Set
10: Clear
11: Don’t care
* This field is always
read as 11.
Timer flip-flop (TB3FF0) control
00
Toggles TB3FF0. (software toggle)
01
Set TB3FF0 to 1.
10
Clears TB3FF0 to 0.
11
Don’t care (read as 11)
When UC3 reaches TB3RG0 value.
0
Toggle-trigger disabled
1
Toggle-trigger enabled
When UC3 reaches TB3RG1 value.
0
Toggle-trigger disabled
1
Toggle-trigger enabled
When UC3 value is latched into TB3CP0 (see Note).
0
Toggle-trigger disabled
1
Toggle-trigger enabled
When UC3 value is latched into TB3CP1.
0
Toggle-trigger disabled
1
Note:
Toggle-trigger enabled
Capturing the counter value into TB3CP0 via a software capture also generates a toggle-trigger
to TB3FF0.
Figure 12.14 TMRB3 Timer Flip-Flop Control Register
TMP1941AF-148
2003-03-27
TMP1941AF
12.4 Operating Modes
12.4.1
16-Bit Interval Timer Mode
In the following example, the TMRB0 is used to accomplish periodic interrupt generation. The
interval time is set in Timer Register 1 (TB0RG1), and the INTTB01 interrupt is enabled.
←
←
←
←
←
TB0RG1
← *
*
← 0
TB0RUN
X = Don’t care,
12.4.2
7
0
X
X
1
0
TB0RUN
IMC7LL
IMC7LH
TB0FFCR
TB0MOD
6
0
X
X
1
0
5
X
1
1
0
1
(**
* *
* *
0 X
4 3
X −
1 0
1 0
0 0
0 0
= 01,
* *
* *
X −
2 1 0
0 X 0
0 0 0
1 0 0
0 1 1
1 * *
10, 11)
* * *
* * *
1 X 1
Stops the TMRB0.
Enables INTTB01, sets its priority level to 4 and disables
INTTB00.
Disables the timer flip-flop toggle-trigger.
Selects a prescalar output clock as the timer clock source
and disables the capture function.
Sets the interval time.
(16 bits)
Starts the TMRB0.
– = No change
16-Bit Event Counter Mode
This mode is used to count events by interpreting the rising edges of the external counter clock
(TB0IN0) as events.
The up-counter (UC0) counts up on each rising clock edge. The counter value is be latched into a
capture register under software control. To determine the number of events (i.e., cycles) counted, the
value in the capture register must be read.
TB0RUN
P7CR
P7FC
IMC7LL
IMC7LH
TB0FFCR
TB0MOD
TB0RG1
TB0RUN
X = Don’t care,
Note:
←
←
←
←
←
←
←
←
←
7
0
−
−
X
X
1
0
*
0
6
0
−
−
X
X
1
0
*
0
5
X
−
−
1
1
0
1
*
X
4
X
0
1
1
1
0
0
*
X
3
−
−
−
0
0
0
0
*
−
2
0
−
−
0
1
0
1
*
1
1
X
−
−
0
0
1
0
*
X
0
0
−
−
0
0
1
0
*
1
Stops the TMRB0.
Configures the P74 pin for input mode.
Enables INTTB01 (interrupt level = 4) and disables INTTB00.
Disables the timer flip-flop toggle-trigger.
Selects the TB0IN0 input as the timer clock source.
Sets a count value (16 bits).
Starts the TMRB0.
– = No change
Even when the timer is used for event counting, the prescaler must be programmed to run (i.e., the
TB0RUN.TB0PRUN bit must be set to 1).
TMP1941AF-149
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TMP1941AF
12.4.3
16-Bit Programmable Pulse Generation (PPG) Mode
The 16-bit PPG mode can be used to generate a square wave with any frequency and duty cycle. The
pulse can be high-going and low-going, as determined by the initial setting of the timer flip-flop
(TB0FF0).
A square wave is generated by toggling the timer flip-flop every time the up-counter UC0 reaches the
values in each timer register (TB0RG0 and TB0RG1). The square-wave output is driven to the
TB0OUT pin. In this mode, the following relationship must be satisfied:
(TB0RG0 value) < (TB0RG1 value)
TB0RG0 Match
(INTTB00 Interrupt)
TB0RG1 Match
(INTTB01 Interrupt)
TB0OUT Pin
Figure 12.15 PPG Output Waveform
Note:
Stop the timer when changing the duty cycle in PPG mode.
(Don’t use the double-buffering function for this purpose.)
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Figure 12.16 shows a functional diagram of 16-bit PPG mode.
TB0RUN.TB0RUN
TB0OUT (PPG output)
Selector
TB0IN0
φT1
φT4
φT16
16-Bit Up-Counter UC0
Clear
F/F
(TB0FF0)
Match
16-Bit Comparator
16-Bit Comparator
Register Buffer 0
TB0RG1
Internal Data Bus
Figure 12.16 Functional Diagram of 16-Bit PPG Mode
The following is an example of running the timer in 16-bit PPG mode.
TB0RUN
7
← 0
6
0
5
X
4
X
3
−
2
0
1
X
0
0
TB0RG0
TB0RG1
TB0FFCR
← *
← *
← X
*
*
X
*
*
0
*
*
0
*
*
1
*
*
1
*
*
1
*
*
0
TB0MOD
← 0
0
P7CR
P7FC
TB0RUN
← −
← −
← 1
X = Don’t care,
1
(**
1 −
1 −
0 X
0 0
= 01,
− −
− −
X −
1 * *
10, 11)
− − −
− − −
1 X 1
Disables the TB0RG0 double-buffering and stops the
TMRB0.
Defines the duty cycle (16 bits).
Defines the cycle period (16 bits).
Toggles the TB0FF0 when a match is detected between
UC0 and TB0RG0 and between UC0 and TB0RG1. Initially
clears the TB0FF0 to 0.
Selects a prescaler output clock as the timer clock source
and disables the capture function.
Configures the P76 pin as TB1OUT.
Starts the TMRB0.
– = No change
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12.4.4
Timing and Measurement Functions Using the Capture Capability
The capture capability of the TMRBn provides versatile timing and measurement functions,
including the following:
•
One-shot pulse generation using an external trigger pulse
•
Frequency measurement
•
Pulse width measurement
•
Time difference measurement
(1) One-Shot Pulse Generation Using an External Trigger Pulse
The TMRBn can be used to produce a one-time pulse as follows.
The 16-bit up-counter (UC0) is programmed to function as a free-running counter, clocked by
one of the prescalar outputs. The TB0IN0 pin is used as an active-high external trigger pulse input
for latching the counter value into Capture Register 0 (TB0CP0).
The TB0IN0 pin is shared with P74 and INT5. The Interrupt Controller (INTC) must be
programmed to generate an INT5 interrupt upon detection of a rising edge on the TB0IN0/INT5
pin. A one-shot pulse has a delay and width controlled by the values stored in the timer registers
(TB0RG0 and TB0RG1). Programming the TB0RG0 and TB0RG1 is the responsibility of the
INT5 interrupt handler. The TB0RG0 is loaded with the sum of the TB0CP0 value (c) plus the
pulse delay (d) − i.e., (c) + (d). The TB0RG1 is loaded with the sum of the TB0RG0 value plus the
pulse width (p) − i.e., (c) + (d) + (p).
Next, the TB0E1T1 and TB0E0T1 bits in the Timer Flip-Flop Control register (TB0FFCR) are
set to 11, so that the timer flip-flop (TB0FF0) will toggle when a match is detected between the
UC0 and the TB0RG0 and between the UC0 and the TB0RG1. With the TB0FF0 toggled twice, a
one-shot pulse is produced. Upon a match between the UC0 and the TB0RG1, the TMRB0
generates the INTTB01 interrupt, which must disable the toggle-trigger for the TB0FF0.
Figure 12.17 depicts one-shot pulse generation, with annotations showing (c), (d) and (p).
The counter is free-running.
Counter Clock
(Internal Clock)
c+d
c
c+d+p
TB0IN0 Input Pin
(External Trigger Pulse)
The UC0 value is latched into TB0CP1.
INT5 is generated.
TB0RG0 Match
TB0RG1 Match
INTTB01 is
generated.
Toggle is
enabled.
Toggle is disabled for a
capture into TB0CP1.
Toggle is
enabled.
TB0OUT (Timer Output) Pin
Delay
(d)
Pulse Width
(p)
Figure 12.17 One-Shot Pulse Generation (with a Delay)
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Example: Generating a one-shot pulse with a width of 2 ms and a delay of 3 ms on assertion of an
external trigger pulse on the TB0IN0 pin
Clocking conditions:
System clock:
High-speed (fc)
High-speed clock gear: ×1 (fc)
Prescaler clock:
fperiph/4 (fperiph = fsys)
Settings in the main routine
7
6
5
4
3
2
1
0
TB0MOD
← X
X
1
0
1
0
0
1
TB0FFCR
← X
X
0
0
0
0
1
0
Places the counter in free-running mode.
Selects φT1 as the counter clock source.
Latches UC0 value into TB0CP0 at rising edges of
the TB0IN0 input.
Clears TB0FF0 to 0.
Disables the toggle-trigger for TB0FF0.
P7CR
P7FC
← −
← −
1
1
−
−
−
−
−
−
−
−
−
−
−
−
IMC2HL
IMC7LL
IMC7LH
TB0RUN
←
←
←
←
X
X
X
0
1
1
1
X
1
1
1
X
0
0
0
−
1
0
0
1
0
0
0
X
0
0
0
1
← TB0CP0 + 3ms/φT1
← TB0RG0 + 2ms/φT1
← X X − − 1 1 −
−
X
X
X
−
Configures the P76 pin as TB1OUT.
Enables INT5 and disables INTTB00 and INTTB01.
Starts the TMRB0.
Settings in INT5
TB0RG0
TB0RG1
TB0FFCR
Enables the TB0FF0 toggle-trigger for TB0RG0 and
TB0RG1 matches.
IMC7LH
← X
X
1
1
0
1
0
0
X
−
−
0
0
−
−
Enables INTTB01.
Settings in INTTB01
TB0FFCR
← X
Disables the TB0FF0 toggle-trigger for TB0RG0 and
TB0RG1 matches.
IMC7LH
X = Don’t care,
← X
X
1
1
0
0
0
0
Disables INTTB01.
– = No change
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If no delay is necessary, enable the TB0FF0 toggle-trigger for a capture of the UC0 value into
the TB0CP0. Use the INT5 interrupt to load the TB0RG1 with a sum of the TB0CP0 value (c) plus
the pulse width (p) and to enable the TB0FF0 toggle-trigger for a match between the UC0 and
TB0RG1 values. A match generates the INTTB01 interrupt, which then is to disable the TB0FF0
toggle-trigger.
Counter Clock
(Prescaler Output Clock)
c+p
c
TB0IN0 Input
(External Trigger Pulse)
The UC0 value is latched into TB0CP0.
INT5 is generated.
INTTB01 is
generated.
TB0RG1 Match
The UC0 value is
latched into TB0CP1.
Toggle is
enabled.
TB0OUT (Timer Output) Pin
Toggle is enabled for a
capture into TB0CP0.
Pulse Width
(p)
Toggle is left disabled for a capture into
TB0CP1 so that it will not be toggled.
Figure 12.18 One-Shot Pulse Generation (without a Delay)
(2) Frequency Measurement
The capture function can be used to measure the frequency of an external clock. Frequency
measurement requires a 16-bit TMRBn channel running in event counter mode and the 8-bit
TMRA01. The timer flip-flop (TA1FF) in the TMRA01 is used to define the duration during which
a measurement is taken.
Select the TB0IN0 pin as the clock source for the TMRB0. Set the TB0CPM[1:0] field in the
TB0MOD to 11 to select the TA1FF output signal from the TMRA01 as a capture trigger input.
This causes the TMRB0 to latch the 16-bit up-counter (UC0) value into Capture Register 0
(TB0CP0) on the low-to-high transition of the TA1FF and into Capture Register 1 (TB0CP1) on
the next high-to-low transition of the TA1FF.
Either the INTTA0 or INTTA1 interrupt generated by the 8-bit timer can be used to make a
frequency calculation.
Counter Clock
(TB0IN0 Input)
C1
C2
TA1OUT
Capture into TB0CP0
Capture into TB0CP1
C1
C1
C2
C2
INTTA0/INTTA1
Figure 12.19 Frequency Measurement
For example, if the TA1FF of the 8-bit timer is programmed to be at logic 1 for a period of 0.5
seconds and the difference between the values captured into the TB0CP0 and TB0CP1 is 100, then
the TB0IN0 frequency is calculated as 100 ÷ 0.5 s = 200 Hz.
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(3) Pulse Width Measurement
The capture function can be used to measure the pulse width of an external clock. The external
clock is applied to the TB0IN0 pin. The up-counter (UC0) is programmed to operate as a freerunning counter, clocked by one of the prescalar outputs. The capture function is used to latch the
UC0 value into Capture Register 0 (TB0CP0) at the clock rising edge and into Capture Register 1
(TB0CP1) at the next clock falling edge. The TB0IN0 input is shared with the INT5 input; the
Interrupt Controller (INTC) is to be programmed to generate the INT5 interrupt at the falling edge
of the TB0IN0 input.
Multplying the counter clock period by the difference between the values captured into the
TB0CP0 and TB0CP1 gives the high pulse width of the TB0IN0 clock.
For example, if the prescalar output clock has a period of 0.5 µs and the difference between the
TB0CP0 and TB0CP1 is 100, the high pulse width is calculated as 0.5 µs × 100 = 50 µs.
Prescaler Output Clock
C2
C1
TB0IN0 Input
(External Clock)
Capture into TB0CP0
C1
C1
C2
Capture into TB0CP1
C2
INT5
Figure 12.20 Pulse Width Measurement
The low pulse width can be measured by the second INT5 interrupt. This is accomplished by
multiplying the counter clock period by the difference between the TB0CP0 value at the first C2
and the TB0CP1 value at the second C1.
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(4) Time Difference Measurement
The capture function can be used to measure the time difference between two event occurrences.
The 16-bit up-counter (UC0) is programmed to operate as a free-running counter. The UC0 value
is latched into Capture Register 0 (TB0CP0) on the rising edge of TB0IN0. The TB0IN0 pin is
shared with INT5; the Interrupt Controller (INTC) is to be programmed to generate the INT5
interrupt at this time.
Then, the UC0 value is latched into Capture Register 1 (TB0CP1) on the rising edge of TB0IN1.
The TB0IN1 pin is shared with INT6; the INTC is to be programmed to generate the INT6
interrupt at this time.
The time difference between the two events that occurred on the TB0IN0 and TB0IN1 pins is
calculated by multiplying the counter clock period by the difference between the TB0CP1 and
TB0CP0 values.
Prescaler Output Clock
C1
C2
TB0IN0 Input
TB0IN1 Input
Capture into TB0CP0
Capture into TB0CP1
INT5
INT6
Time Difference
Figure 12.21 Time Difference Measurement
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13. Serial I/O (SIO)
The TMP1941AF serial I/O contains four channels named SIO0, SIO1, SIO3 and SIO4 (there is not SIO2).
The SIO0 and SIO1 provide Universal Asynchronous Receiver/Transmitter (UART) mode and synchronous I/O
Interface mode. The SIO2 and SIO3 provide only UART mode.
•
I/O Interface Mode
Mode 0: Transmits/receives a serial clock (SCLK) as well as data streams for a synchronous clock
mode of operation.
•
UART mode
Mode 1: 7 data bits
Mode 2: 8 data bits
Mode 3: 9 data bits
In Mode 1 and Mode 2, each character can include a parity bit. In Mode 3, an SIO channel operates in a wakeup mode for multidrop applications in which a master station is connected to several slave stations through a
serial link.
Figure 13.2 to Figure 13.5 are block diagrams of each SIO channel. The main components of an SIO channel
are a clock prescalar, a serial clock generator, a receive buffer, a receive controller, a transimit buffer and a
transmit controller.
Each SIO channel is independently programmable, and functionally equivalent with a few exceptions listed
below. In the following sections, any references to the SIO0 also apply to the other channels.
Table 13.1 Differences Between the SIO Channels
SIO0
SIO1
Pins Used
TXD0 (P90)
RXD0 (P91)
CTS0 /SCLK0 (P92)
TXD1 (P93)
RXD1 (P94)
CTS 1 /SCLK1 (P95)
TXD3 (P70)
RXD3 (P71)
TXD4 (P72)
RXD4 (P73)
I/O Interface Mode
Available
Available
Not available
Not available
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•
Mode 0 (I/O Interface Mode)
bit 0
1
2
3
4
5
6
7
Goes out first
•
•
•
Mode 1 (7-Bit UART Mode)
Without parity
start
bit 0
1
2
3
4
5
6
stop
With parity
start
bit 0
1
2
3
4
5
6
parity stop (1 bit)
Mode 2 (8-Bit UART Mode)
Without parity
start
bit 0
1
2
3
4
5
6
7
stop (1 bit)
With parity
start
bit 0
1
2
3
4
5
6
7
parity stop (1 bit)
Mode 3 (9-Bit UART Mode)
start
bit 0
1
2
3
4
5
6
7
8
stop (1 bit)
start
bit 0
1
2
3
4
5
6
7
8
stop (wake-up, 1 bit)
Bit 8: Address/data bit flag
1: Address character (select code)
0: Data character
Figure 13.1 Data Formats
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13.1 Block Diagrams
φT0
Prescaler
4 8 16 32 64
2
φT2
φT8 φT32
Serial Clock Generator
TA0TRG
(from TMRA0)
BR0CR.
BR0CK[1:0]
UART
Mode
Selector
Selector
BR0CR.
BR0ADDE
Baud Rate
Generator
SIOCLK
SC0MOD0. SC0MOD0.
SC[1:0]
SM[1:0]
Selector
fsys/2
BR0ADD.
BR0K[3:0]
Divider
φT0
φT2
φT8
φT32
Selector
BR0CR.
BR0S[3:0]
÷2
SCLK0 Input
(Shared with P92)
I/O Interface
Mode
SC0CR.
IOC
I/O Interface Mode
INTRX0 Interrupt
Request
SCLK0 Output
(Shared with P92)
INTTX0 Interrupt
Request
SC0MOD0. Serial Channel
WU
Interrupt Control
Receive Counter
(÷16 for UART)
RXDCLK
SC0MOD0.
Receive
RXE
Control
Transmit Counter
(÷16 for UART)
TXDCLK
Transmit
Control
SC0CR
PE
EVEN
SC0MOD0.
CTSE
Parity Control
RXD0
(Shared with P91)
CTS0
(Shared with P92)
Receive Buffer 1 (Shift Register)
RB8 Receive Buffer 2 (SC0BUF)
Error Flag
TB8
Transmit Buffer (SC0BUF)
SC0CR
OERR PERR FERR
Internal Data Bus
Internal Data Bus
TXD0
(Shared with P90)
Internal Data Bus
Figure 13.2 SIO0 Block Diagram
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φT0
Prescaler
4 8 16 32 64
2
φT2
φT8 φT32
Serial Clock Generator
TA0TRG
(from TMRA0)
BR1CR.
BR1CK[1:0]
UART
Mode
Selector
Selector
BR1CR.
BR1ADDE
Baud Rate
Generator
SIOCLK
SC1MOD0. SC1MOD0.
SC[1:0]
SM[1:0]
Selector
fsys/2
BR1ADD.
BR1K[3:0]
Divider
φT0
φT2
φT8
φT32
Selector
BR1CR.
BR1S[3:0]
÷2
SCLK1 Input
(Shared with P95)
I/O Interface
Mode
SC1CR.
IOC
I/O Interface Mode
INTRX1 Interrupt
Request
SCLK1 Output
(Shared with P95)
INTTX1 Interrupt
Request
SC1MOD0. Serial Channel
WU
Interrupt Control
Receive Counter
(÷16 for UART)
RXDCLK
SC1MOD0.
Receive
RXE
Control
Transmit Counter
(÷16 for UART)
TXDCLK
Transmit
Control
SC1CR
PE
EVEN
SC1MOD0.
CTSE
Parity Control
RXD1
(Shared with P94)
CTS 1
(Shared with P95)
Receive Buffer 1 (Shift Register)
RB8 Receive Buffer 2 (SC1BUF)
Error Flag
TB8
Transmit Buffer (SC1BUF)
SC1CR
OERR PERR FERR
Internal Data Bus
Internal Data Bus
TXD1
(Shared with P93)
Internal Data Bus
Figure 13.3 SIO1 Block Diagram
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φT0
Prescaler
4 8 16 32 64
2
φT2
φT8 φT32
Serial Clock Generator
TA0TRG
(from TMRA0)
BR3CR.
BR3CK[1:0]
fsys/2
BR3CR.
BR3ADDE
Baud Rate
Generator
UART
Mode
Selector
Selector
BR3ADD.
BR3K[3:0]
Divider
φT0
φT2
φT8
φT32
Selector
BR3CR.
BR3S[3:0]
SIOCLK
SC3MOD0. SC3MOD0.
SC[1:0]
SM[1:0]
INTRX3 Interrupt
Request
INTTX3 Interrupt
Request
SC3MOD0. Serial Channel
WU
Interrupt Control
Receive Counter
(÷16 for UART)
RXDCLK
SC3MOD0.
Receive
RXE
Control
Transmit Counter
(÷16 for UART)
TXDCLK
Transmit
Control
SC3CR
PE
EVEN
Parity Control
RXD3
(Shared with P71)
Receive Buffer 1 (Shift Register)
RB8 Receive Buffer 2 (SC3BUF)
Error Flag
TB8
Transmit Buffer (SC3BUF)
SC3CR
OERR PERR FERR
Internal Data Bus
Internal Data Bus
TXD3
(Shared with P70)
Internal Data Bus
Figure 13.4 SIO3 Block Diagram
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φT0
Prescaler
4 8 16 32 64
2
φT2
φT8 φT32
Serial Clock Generator
TA0TRG
(from TMRA0)
BR4CR.
BR4CK[1:0]
fsys/2
BR4CR.
BR4ADDE
Baud Rate
Generator
UART
Mode
Selector
Selector
BR4ADD.
BR4K[3:0]
Divider
φT0
φT2
φT8
φT32
Selector
BR4CR.
BR4S[3:0]
SIOCLK
SC4MOD0. SC4MOD0.
SC[1:0]
SM[1:0]
INTRX4 Interrupt
Request
INTTX4 Interrupt
Request
SC4MOD0. Serial Channel
WU
Interrupt Control
Receive Counter
(÷16 for UART)
RXDCLK
SC4MOD0.
Receive
RXE
Control
Transmit Counter
(÷16 for UART)
TXDCLK
Transmit
Control
SC4CR
PE
EVEN
Parity Control
RXD4
(Shared with P71)
Receive Buffer 1 (Shift Register)
RB8 Receive Buffer 2 (SC4BUF)
Error Flag
TB8
Transmit Buffer (SC4BUF)
SC4CR
OERR PERR FERR
Internal Data Bus
Internal Data Bus
TXD4
(Shared with P70)
Internal Data Bus
Figure 13.5 SIO4 Block Diagram
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13.2 SIO Components
13.2.1
Prescaler
The SIO0 has a 6-bit prescalar that slows the rate of a clocking source to the serial clock generator.
The prescalar clock source (φT0) can be selected from fperiph, fperiph/2 and fperiph/4 by programming
the PRCK[1:0] field of the SYSCR0 located within the CG. fperiph can be selected from fgear (geared
clock) and fc (non-geared clock) by programming the FPSEL bit of the SYSCR1 located within the CG.
The serial clock is selectable from several clocks; the prescalar is only enabled when the baud rate
generator output clock is selected as a serial clock. Table 13.2 shows prescalar output clock resolutions
(@fc = 32 MHz).
Table 13.2 Prescaler Output Clock Resolutions
@ fc = 40 MHz
Peripheral
Clock Select
SYSCR1.
FPSEL
Clock Gear
Value
SYSCR1.
GEAR[1:0]
00 (fperiph/4)
00 (fc)
0 (fgear)
01 (fc/2)
1 (fc)
10 (fc/4)
11 (fc/8)
φT32
fc/24 (0.4 µs)
fc/26 (1.6 µs)
fc/28 (6.4 µs)
fc/25 (0.8 µs)
fc/27 (3.2 µs)
10 (fperiph)

fc/2 (0.1 µs)
fc/2 (0.4 µs)
fc/26 (1.6 µs)
fc/2 (0.8 µs)
fc/2 (3.2 µs)
fc/29 (12.8 µs)
fc/2 (0.2 µs)
3
2
5
4
7
01 (fperiph/2)

fc/2 (0.4 µs)
fc/2 (1.6 µs)
fc/28 (6.4 µs)
10 (fperiph)

fc/2 (0.2 µs)
fc/2 (0.8 µs)
fc/27 (3.2 µs)
fc/26 (1.6 µs)
fc/28 (6.4 µs)
fc/210 (25.6µs)
fc/24 (0.4 µs)
4
3
6
5
01 (fperiph/2)

fc/2 (0.8 µs)
fc/2 (3.2 µs)
fc/29 (12.8 µs)
10 (fperiph)

fc/2 (0.4 µs)
fc/2 (1.6 µs)
fc/28 (6.4 µs)
fc/27 (3.2 µs)
fc/29 (12.8µs)
fc/211 (51.2µs)
fc/25 (0.8 µs)
5
4
7
6
01 (fperiph/2)

fc/2 (1.6 µs)
fc/2 (6.4 µs)
fc/210 (25.6µs)
10 (fperiph)

fc/2 (0.8 µs)
fc/2 (3.2 µs)
fc/29 (12.8µs)
fc/2 (0.4 µs)
fc/2 (1.6 µs)
fc/28 (6.4 µs)
00 (fperiph/4)
00 (fc)
φT8
fc/23 (0.2 µs)
00 (fperiph/4)
11 (fc/8)
fc/22 (0.1 µs)
φT2

00 (fperiph/4)
10 (fc/4)
φT0
01 (fperiph/2)
00 (fperiph/4)
01 (fc/2)
Prescaler Output Clock Resolution
Prescaler Clock
Source
SYSCR0.PRCK[1:0]
fc/2 (0.1 µs)
2
6
5
4
8
7
6
01 (fperiph/2)

fc/23 (0.2 µs)
fc/25 (0.8 µs)
fc/27 (3.2 µs)
10 (fperiph)

fc/2 (0.1 µs)
fc/2 (0.4 µs)
fc/26 (1.6 µs)
00 (fperiph/4)

fc/2 (0.4 µs)
fc/2 (1.6 µs)
fc/28 (6.4 µs)
01 (fperiph/2)

fc/2 (0.2 µs)
fc/2 (0.8 µs)
fc/27 (3.2 µs)
10 (fperiph)

fc/2 (0.4 µs)
fc/26 (1.6 µs)
00 (fperiph/4)

fc/26 (1.6 µs)
fc/28 (6.4 µs)
01 (fperiph/2)


fc/2 (0.8 µs)
fc/27 (3.2 µs)
10 (fperiph)


fc/2 (0.4 µs)
fc/26 (1.6 µs)
00 (fperiph/4)


fc/26 (1.6 µs)
fc/28 (6.4 µs)
01 (fperiph/2)


fc/2 (0.8 µs)
fc/27 (3.2 µs)
10 (fperiph)


2
4
3

fc/24 (0.4 µs)
4
6
5
4
5
4
5

fc/26 (1.6 µs)
Note 1: The prescaler's output clock φTn must be selected so that the relationship φTn < fsys/2 is satisfied.
Note 2: Do not change the clock gear value while the timer is running.
Note 3: The — character means “Don’t use.”
Prescalar output taps can be divide-by-1 (φT0), divide-by-4 (φT2), divide-by-16 (φT8) and divide-by64 (φT32).
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13.2.2
Baud Rate Generator
(1) Baud Rate Generator Configuration
The frequency used to transimit and receive data through the SIO0 is derived from the baud rate
generator. The clock source for the baud rate generator can be selected from the 6-bit prescalar
outputs (φT0, φT2, φT8, φT32) through the programming of the BR0CK[1:0] field in the BR0CR.
The baud rate generator contains a clock divider that can divide the selected clock by 1, n + (m /
16), or 16 (where n is an integer between 2 and 15, and m is an integer between 0 and 15). The
clock divisor is programmed into the BR0ADDE and BR0S[3:0] bits in the BR0CR and the
BR0K[3:0] bits in the BR0ADD.
•
UART Mode
a. When BR0CR.BR0ADDE = 0
When the BR0CR.BR0ADDE bit is cleared, the BR0ADD.BR0K[3:0] field has no
meaning or effect. In this case, the baud rate generator input clock is divided down by a value
of N (1 to 16) programmed in the BR0CR.BR0S[3:0] field.
b. When BR0CR.BR0ADDE = 1
Setting the BR0CR.BR0ADDE bit enables the N + (16 – K) / 16 clock division function.
The baud rate generator input clock is divided down according to the value of N (2 to 15)
programmed in the BR0CR.BR0S[3:0] field and the value of K (1 to 15) programmed in the
BR0ADD.BR0K[3:0] field.
Note:
•
Setting N to 0 or 16 disables the N + (16 – K) / 16 clock division function. When N = 0 or
16, the BR0CR.BR0ADDE bit must be cleared.
I/O Interface Mode
I/O Interface mode can not utilize the N + (16 – K) / 16 clock division function. The
BR0CR.BR0ADDE must be cleared, so the baud rate generator input clock is divided down
by a value of N (1 to 16) programmed in the BR0CR.BR0S[3:0] field.
(2) Baud Rate Calculations
•
UART Mode
Baud Rate =
baud rate generator input clock
÷ 16
baud rate generator divisor
When the clock input to the baud rate generator is 8-MHz φT0, the maximum baud rate is
500 kbps (with no clock division by the baud rate generator).
The baud rate generator can by bypassed if the user wants to use the fsys/2 clock as a serial
clock. In this case, the maximum baud rate is 1 Mbps @fsys = 32 MHz.
•
I/O Interface Mode
Baud Rate =
baud rate generator input clock
÷2
baud rate generator divisor
When the clock input to the baud rate generator is 8-MHz φT0, the maximum baud rate is
2 Mbps (with the clock divided by 2 by the baud rate generator).
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(3) Calculation Examples
•
Integral Clock Division (Divide-by-N)
fperiph = 24.576-MHz fc
φT0 = fperiph/4
Baud rate generator input clock: φT2
Clock divisor N (BR0CR.BR0S[3:0]) = 10
BR0CR.BR0ADDE = 0
Clocking conditions
System clock:
High-speed (fc)
High-speed clock gear:↕1 (fc)
Prescaler clock:
fperiph/4 (fperiph = fsys)
The baud rate is determined as follows:
fc/16
÷ 16
10
= 24.576 × 106 ÷ 16 ÷ 10 ÷ 16 = 9600 (bps)
Baud Rate =
Note:
•
Clearing the BR0CR.BR0ADDE bit to 0 disables the N + (16 – K) / 16 clock division
function. At this time, the BR0ADD.BR0K[3:0] field is ignored.
N + (16 – K) / 16 Clock Division (UART mode only)
fperiph = 19.2-MHz fc
φT0 = fperiph/4
Baud rate generator input clock: φT2
N (BR0CR.BR0S[3:0]) = 7
K (BR0ADD.BR0K[3:0]) = 3
BR0CR.BR0ADDE = 1
Clocking conditions
System clock:
High-speed (fc)
High-speed clock gear:↕1 (fc)
Prescaler clock:
fperiph/4 (fperiph = fsys)
The baud rate is determined as follows:
fc /16
÷ 16
(16 - 3)
7+
16
13
6
= 19.2 × 10 ÷ 16 ÷ (7 +
) ÷ 16 = 9600 (bps)
16
Table 13.3 and Table 13.4 show the UART baud rates obtained with various combinations of
clock inputs and clock divisor values.
Baud Rate =
(4) Using an External Clock as a Serial Clock
The SIO0 and SIO1 can use an external clock as a serial clock, bypassing the baud rate
generator. When an external clock is used, the baud rate is determined as shown below.
•
UART Mode
Baud Rate = external clock input ÷ 16
The external clock period must be greater than or equal to 4/fsys. Therefore, when fsys =
40 MHz, the maximum baud rate is 625 kbps (40 ÷ 4 ÷ 16).
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•
I/O Interface Mode
Baud Rate = external clock input clock
The external clock period must be greater than 16/fsys. Therefore, when fsys = 40 MHz,
the maximum baud rate is 2.5 Mbps (40 ÷16). For the timing parameters, refer to Section
18.6, Serial Channel Timing.
Table 13.3 UART Baud Rate Selection
When the baud rate generator is used and BR0CR.BR0ADDE = 0
Unit: kbps
Baud Rate Generator Input Clock
fc (MHz)
Divisor N
(Programmed in BR0CR.BR0S[3:0])
19.6608
1
307.200
76.800
19.200
4.800
2
153.600
38.400
9.600
2.400
4
76.800
19.200
4.800
1.200
8
38.400
9.600
2.400
0.600
0
19.200
4.800
1.200
0.300
1.200
24.576
29.4912
Note:
φT0
(fc/4)
φT2
(fc/16)
φT8
(fc/64)
φT32
(fc/256)
5
76.800
19.200
4.800
A
38.400
9.600
2.400
0.600
1
460.800
115.200
28.800
7.200
2
230.400
57.600
14.400
3.600
3
153.600
38.400
9.600
2.400
4
115.200
28.800
7.200
1.800
6
76.800
19.200
4.800
1.200
C
38.400
9.600
2.400
0.600
This table assumes: fsys = fc, clock gear = fc/1, prescaler clock source = fperiph/4
Table 13.4 UART Baud Rate Selection
When the TMRA0 timer trigger output is used and the TMRA0 input clock is φT1
TA0REG0
1H
2H
3H
4H
5H
6H
8H
AH
10H
14H
Unit: kbps
fc (MHz)
29.4912
24.576
24
19.6608
16
12.288
230.4
115.2
76.8
57.6
46.08
38.4
28.8
23.04
14.4
11.52
192
96
64
48
38.4
32
24
19.2
12
9.6
187.5
93.75
62.5
46.88
37.5
31.25
23.44
18.75
11.72
9.38
153.6
76.8
51.2
38.4
30.72
25.6
19.2
15.36
9.6
7.68
125
62.5
41.67
31.25
25
20.83
15.63
12.5
7.81
6.25
96
48
32
24
19.2
16
12
9.6
6
4.8
Note 1: I/O Interface mode can not utilize the trigger output signal from the 8-bit timer TMRA0 as a serial
clock.
Note 2: This table assumes: fsys = fc, clock gear = fc/1, and prescaler clock source = fperiph/4
When the 8-bit timer TMRA0 is used to generate a serial clock, the baud rate is determined
by the following equation:
Baud Rate =
clock frequency selected by SYSCR0.PRCK[1: 0]
TA0REG × 2 × 16
When theTMRA0 clock source is φT1.
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13.2.3
Serial Clock Generator
This block generates a basic clock (SIOCLK) that controls the transimit and receive circuit.
•
I/O Interface Mode
When the SCLK0 pin is configured as an output by clearing the SC0CR.IOC bit to 0, the output
clock from the baud rate generator is divided by two to generate the SIOCLK clock. When the
SCLK0 pin is configured as an input by setting the SC0CR.IOC bit to 1, the external SCLK0 clock
is used as the SIOCLK clock; the SC0CR.SCLKS bit determines the active clock edge.
•
UART Mode
The SIOCLK clock is selected from a clock produced by the baud rate generator, the system
clock (fsys/2), the trigger output signal from the 8-bit timer TMRA0, and the external SCLK0
clock, according to the setting of the SC0MOD0.SC[1:0] field.
13.2.4
Receive Counter
The receive counter is a 4-bit binary up-counter used in UART mode. This counter is clocked by
SIOCLK. The receiver utilizes 16 clocks for each received bit, and oversamples each bit three times
around their center (with 7th to 9th clocks). The value of a bit is determined by voting logic which takes
the value of the majority of three samples. For example, if the three samples of a bit are 1, 0 and 1, then
that bit is interpreted as a 1; if the three samples of a bit are 0, 0 and 1, then that bit is interpreted as a 0.
13.2.5
Receive Controller
•
I/O Interface Mode
If the SCLK0 pin is configured as an output by clearing the SC0CR.IOC bit to 0, the receive
controller samples the RXD0 input at the rising edge of the shift clock driven out from the SCLK0
pin. If the SCLK0 pin is configured as an input by setting the SC0CR.IOC bit to 1, the receive
controller samples the RXD0 input at either the rising or falling edge of the SCLK0 clock, as
programmed in the SC0CR.SCLKS bit.
•
UART Mode
The receive controller contains the start bit detection logic. Once a valid start bit is detected, the
receive controller begins sampling the incoming data streams. The start bit, each data bit and the
stop bit are sampled three times for 2-of-3 majority voting.
13.2.6
Receive Buffer
The receive buffer is double-buffered to prevent overrun errors. Received data is serially shifted bit
by bit into Receive Buffer 1. When a whole character (i.e., 7 or 8 bits, as programmed) is loaded into
Receive Buffer 1, it is transferred to Receive Buffer 2 (SC0BUF), and a receive-done interrupt
(INTRX0) is generated.
•
I/O Interface Mode
The double-buffer structure can be used in full-duplex mode, but not in half-duplex mode. For
details, refer to Section 13.4.
•
UART Mode
The CPU reads a character from Receive Buffer 2 (SC0BUF). Receive Buffer 1 can accept a
new character through the RXD0 pin before the CPU picks up the previous character in Receive
Buffer 2. However, the CPU must read Receive Buffer 2 before Receive Buffer 1 is filled with a
new character. Otherwise, an overrun error occurs, causing the character previouly in Receive
Buffer 1 to be lost. Even in that case, the contents of Receive Buffer 2 and the SC0CR.RB8 bit are
preserved.
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The SC0CR.RB8 bit holds the parity bit for an 8-bit UART character and the most-significant bit
(i.e., address/data flag) bit for a 9-bit UART character.
In 9-bit UART mode, the receiver wake-up feature allows the slave station in a multidrop system
to wake up whenever an address character is received. Setting the SC0MOD0.WU bit enables the
wake-up feature. When the SC0CR.RB8 bit has received an address/data flag bit set to 1, the
receiver generates the INTRX0 interrupt.
13.2.7
Transmit Counter
The transmit counter is a 4-bit binary up-counter used in UART mode. Like the receive counter, the
transmit counter is also clocked by SIOCLK. The transmitter generates a transimit clock (TXDCLK)
pulse every 16 SIOCLK pulses.
SIOCLK
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
TXDCLK
Figure 13.6 Transimit Clock Generation
13.2.8
Transmit Controller
•
I/O Interface Mode
If the SCLK0 pin is configured as an output by clearing the SC0CR.IOC bit to 0, the transimit
controller shifts out each bit in the transmit buffer to the TXD0 pin at the rising edge of the shift
clock driven out on the SCLK0 pin. If the SCLK0 pin is configured as an input by setting the
SC0CR.IOC bit to 1, the transimit controller shifts out each bit in the transmit buffer to the TXD0
pin at either the rising or falling edge of the SCLK0 input, as programmed in the SC0CR.SCLKS
bit.
•
UART Mode
Once the CPU loads a character into the transimit buffer, the transmit controller begins
transmission at the next rising edge of TXDCLK, producing a transmit shift clock (TXDSFT).
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Handshaking
The SIO0 and SIO1 have the clear-to-send ( CTS ) pin. If the CTS operation is enabled, the CTS
input must be low in order for the character to be transmitted. This feature can be used for flow control
to prevent overrun in the receiver. The SC0MOD.CTSE bit enables and disables the CTS operation.
If the CTS pin goes high in the middle of a transmission, the transimit controller stops transmission
upon completion of the current character until CTS again goes low. If so enabled, the transmit
controller generates the INTTX0 interrupt to notify the CPU that the transmit buffer is empty. After the
CPU loads the next character into the transmit buffer, the transmit controller remains in idle state until it
detects CTS going low.
Although the SIO0 and SIO1 do not have the RTS pin, any general-purpose port pins can serve as
the RTS pin. The receiving device uses the RTS output to control the CTS input of the transmitting
device. Once the receiving device has received a character, RTS should be set to high in the receivedone interrupt handler to temporarily stop the transmitting device from sending the next character. This
way, the user can easily implement a two-way handshake protocol.
TMP1941AF
TMP1941AF
RXD
TXD
RTS (Any port)
CTS
Transmitting Device
Receiving Device
Figure 13.7 Handshaking Signals
Write to the Transmit Buffer
(Note 2)
CTS
No transmission
takes place during this period.
(Note 1)
13
14
15
16
1
2
3
14
15
16
1
2
3
SIOCLK
TXDCLK
TXD
Note 1:
start bit
bit 0
When CTS goes high in the middle of transmission, the transmitter stops transmission
after the current character has been sent.
Note 2:
The transmitter starts tansmission at the first falling edge of the TXDCLK clock after the
CTS signal goes low.
Figure 13.8 Clear-To-Send ( CTS ) Signal Timing
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13.2.9
Transmit Buffer
Once the CPU loads a character into the transmit buffer (SC0BUF), it is shifted out on the TXD0
output, with the least-significant bit first, clocked by the transmit shift clock from the transmit
controller. When the transmit buffer is empty and ready to be loaded with the next character, the
INTTX0 interrupt is generated to the CPU. A character can not be written to the transmit buffer in the
middle of a transmission.
13.2.10 Parity Controller
For transmit operations, setting the SC0CR.PE enables parity generation in 7- and 8-bit UART
modes. The SC0CR.EVEN bit selects either even or odd parity.
If enabled, the parity controller automatically generates parity for the character in the transmit buffer
(SC0BUF). In 7-bit UART mode, the TB7 bit in the SC0BUF holds the parity bit. In 8-bit UART mode,
the TB8 bit in the SC0MOD holds the parity bit. The parity bit is set after the character has been
transmitted. The SC0CR.PE and SC0CR.EVEN bits must be programmed prior to a write to the
transmit buffer.
For receive operations, the parity controller automatically computes the expected parity when a
character in Receive Buffer 1 is transferred to Receive Buffer 2 (SC0BUF). The received parity bit is
compared to the SC0BUF.RB7 bit in 7-bit UART mode and to the SC0CR.RB8 bit in 8-bit UART
mode. If a character is received with incorrect parity, the SC0CR.PERR bit is set.
13.2.11 Error Flags (UART mode only)
The SC0CR has the following error flag bits that indicate the status of the received character for
improved data reception reliability.
•
Overrun error (OERR)
An overrun error is reported if all bits of a new character are received into Receive Buffer 1
when Receive Buffer 2 (SC0BUF) still contains a valid character.
•
Parity error (PERR)
A parity error is reported when the parity bit attached to a character received on the RXD pin
does not match the expected parity computed from the character transferred to Receive Buffer 2
(SC0BUF).
•
Framing error (FERR)
A framing error is reported when a 0 is detected where a stop bit was expected. (The middle
three of the 16 samples are used to determine the bit value.)
Note 1:
Even if an error is present in a received character, the receive operation for the next character
continues normally.
Note 2:
Error flags are kept until read.
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13.2.12 Signal Generation Timing
(1) UART Mode
Receive Operation
9 Data Bits
8 Data Bits with
Parity
8 Data Bits with No Parity
7 Data Bits with Parity
7 Data Bits with No Parity
Interrupt
Middle of the stop bit
Middle of the stop bit
Middle of the stop bit
Framing Error
Middle of the stop bit
Middle of the stop bit
Middle of the stop bit

Middle of the last bit
(i.e., parity bit)
Middle of the last bit
(i.e., parity bit)
Middle of the last bit
(i.e., parity bit)
Middle of the stop bit
Parity Error
Overrun Error
Middle of the last bit
(i.e., bit 8)
Transmit Operation
9 Data Bits
Interrupt
Immediately before
the stop bit is shifted
out
8 Data Bits with
Parity
Immediately before the
stop bit is shifted out
8 Data Bits with No Parity
7 Data Bits with Parity
7 Data Bits with No Parity
Immediately before the stop bit
is shifted out
(2) I/O Interface Mode
SCLK Output Mode
Transmit
Interrupt
Immediately after the rising edge of the last SCLK pulse (See Figure
13.29)
SCLK Input Mode
Immediately after the rising or falling edge of the last SCLK pulse,
as programmed (See Figure 13.30)
SCLK Output Mode
When a received character has been transferred to Receive Buffer
2 (SC0BUF) (i.e., immediately after the last SCLK pulse) (See
Figure 13.31)
SCLK Input Mode
When a received character has been transferred to Receive Buffer
2 (SC0BUF) (i.e., immediately after the last SCLK pulse) (See
Figure 13.32)
Receive Interrupt
Note 1:
Don’t modify any control register during transmit or receive operations.
Note 2:
Don’t disable receive operations by clearing the SC0MOD0.RXE bit while any character is
being received.
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13.3 Register Description
SC0MOD0
(0xFFFF_F202)
Name
7
6
5
4
TB8
CTSE
RXE
WU
Read/Write
Reset Value
Function
3
2
1
0
SM1
SM0
SC1
SC0
0
0
0
0
R/W
0
0
0
Bit 8 of a
Handshake Receive
control
transmitted control
character 0: Disables 0: Disables
receiver
CTS
operation 1: Enables
1: Enables
receiver
CTS
operation
0
Wake-up
function
0: Disabled
1: Enabled
Serial transfer mode
00: I/O Interface mode
01: 7-bit UART mode
10: 8-bit UART mode
11: 9-bit UART mode
Serial clock (for UART)
00: TA0TRG (timer)
01: Baud rate generator
10: Internal fsys/2 clock
11: External clock
(SCLK0 input)
Wake-up function
9-Bit UART Mode
0
Interrupt on every received
character
1
Interrupt only when RB8 = 1
Other Modes
Don’t care
Handshake ( CTS ) control
Note:
0
Disable (Accepts data streams at all times)
1
Enable
In I/O Interface mode, a serial clock is selected by the SIO0 Control Register (SC0CR).
Figure 13.9 SIO0 Mode Register 0 (SC0MOD0)
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Name
SC1MOD0
(0xFFFF_F20A) Read/Write
Reset Value
Function
7
6
5
4
3
2
1
0
TB8
CTSE
RXE
WU
SM1
SM0
SC1
SC0
0
0
0
0
R/W
0
0
0
Bit 8 of a
Handshake Receive
transmitted control
control
character 0: Disables 0: Disables
receiver
CTS
operation 1: Enables
receiver
1: Enables
CTS
operation
0
Wake-up
function
0: Disabled
1: Enabled
Serial transfer mode
00: I/O Interface mode
01: 7-bit UART mode
10: 8-bit UART mode
11: 9-bit UART mode
Serial clock (for UART)
00: TA0TRG (timer)
01: Baud rate generator
10: Internal fsys/2 clock
11: External clock
(SCLK1 input)
Wake-up function
9-Bit UART Mode
0
Interrupt on every received
character
1
Interrupt only when RB8 = 1
Other Modes
Don’t care
Handshake ( CTS ) control
Note:
0
Disable (Accepts data streams at all times)
1
Enable
In I/O Interface mode, a serial clock is selected by the SIO1 Control Register (SC1CR).
Figure 13.10 SIO1 Mode Register 0 (SC1MOD0)
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SC3MOD0
(0xFFFF_F282)
Name
7
6
5
4
3
2
1
0
TB8

RXE
WU
SM1
SM0
SC1
SC0
0
0
0
0
Read/Write
Reset Value
Function
R/W
0
0
Bit 8 of a
Must be
transmitted written as
character 0.
0
0
Receive
control
0: Disables
receiver
1: Enables
receiver
Wake-up
function
0: Disabled
1: Enabled
Serial transfer mode
00: Reserved
01: 7-bit UART mode
10: 8-bit UART mode
11: 9-bit UART mode
Serial clock (for UART)
00: TA0TRG (timer)
01: Baud rate generator
10: Internal fsys/2 clock
11: Don’t care
Wake-up function
9-Bit UART Mode
0
Interrupt on every received
character
1
Interrupt only when RB8 = 1
Other Modes
Don’t care
Figure 13.11 SIO3 Mode Register 0 (SC3MOD0)
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SC4MOD0
Name
(0xFFFF_F28A) Read/Write
Reset Value
Function
7
6
5
4
3
2
1
0
TB8

RXE
WU
SM1
SM0
SC1
SC0
0
0
0
0
R/W
0
0
Bit 8 of a
Must be
transmitted written as
character 0.
0
0
Receive
control
0: Disables
receiver
1: Enables
receiver
Wake-up
function
0: Disabled
1: Enabled
Serial transfer mode
00: Reserved
01: 7-bit UART mode
10: 8-bit UART mode
11: 9-bit UART mode
Serial clock (for UART)
00: TA0TRG (timer)
01: Baud rate generator
10: Internal fsys/2 clock
11: Don’t care
Wake-up function
9-Bit UART Mode
0
Interrupt on every received
character
1
Interrupt only when RB8 = 1
Other Modes
Don’t care
Figure 13.12 SIO4 Mode Register 0 (SC4MOD0)
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Name
SC0CR
(0xFFFF_F201) Read/Write
7
6
5
4
3
2
1
0
RB8
EVEN
PE
OERR
PERR
FERR
SCLKS
IOC
R
Reset Value
Function
R/W
0
Bit 8 of a
received
character
R (Cleared when read)
0
Parity type Parity
0: Disabled
0: Odd
1: Enabled
1: Even
0
0
R/W
0
0
0
0: SCLK0
1: Error has occurred.
Overrun
Parity
1: SCLK0
Framing
0: Baud rate
generator
1: SCLK0
input
Input clock in I/O Interface mode
0
Baud rate generator
1
SCLK0 input
Active edge for the SCLK0 input
0
Data is transmitted/received
on the SCLK0 rising edge.
1
Data is transmitted/received
on the SCLK0 falling edge.
Framing error flag
Parity error flag
Overrun error flag
These bits are cleared
to 0 when read.
Input clock in I/O Interface mode
0
Odd parity
1
Even parity
Note 1: All error flags are cleared to 0 when read.
Note 2: When SCLK0 is configured as an output, the SCLKS bit must be cleared (rising-edge triggered).
Figure 13.13 SIO0 Control Register (SC0CR)
TMP1941AF-176
2003-03-27
TMP1941AF
Name
SC1CR
(0xFFFF_F209) Read/Write
7
6
5
4
3
2
1
0
RB8
EVEN
PE
OERR
PERR
FERR
SCLKS
IOC
R
Reset Value
Function
R/W
0
Bit 8 of a
received
character
R (Cleared when read)
0
Parity type Parity
0: Disabled
0: Odd
1: Enabled
1: Even
0
0
R/W
0
0
0
0: SCLK1
1: Error has occurred.
Overrun
Parity
1: SCLK1
Framing
0: Baud rate
generator
1: SCLK1
input
Input clock in I/O Interface mode
0
Baud rate generator
1
SCLK1 input
Active edge for the SCLK1 input
0
Data is transmitted/received
on the SCLK1 rising edge.
1
Data is transmitted/received
on the SCLK1 falling edge.
Framing error flag
Parity error flag
Overrun error flag
These bits are cleared
to 0 when read.
Input clock in I/O Interface mode
0
Odd parity
1
Even parity
Note 1: All error flags are cleared to 0 when read.
Note 2: When SCLK1 is configured as an output, the SCLKS bit must be cleared (rising-edge triggered).
Figure 13.14 SIO1 Control Register (SC1CR)
TMP1941AF-177
2003-03-27
TMP1941AF
Name
SC3CR
(0xFFFF_F281) Read/Write
7
6
5
4
3
2
1
0
RB8
EVEN
PE
OERR
PERR
FERR


R
Reset Value
Function
R/W
0
Bit 8 of a
received
character
R (Cleared when read)
0
0
0
R/W
0
Parity type Parity
1: Error has occurred.
0: Disabled
0: Odd
Overrun
Parity
Framing
1: Enabled
1: Even
Framing error flag
Parity error flag
Overrun error flag
0
0
Must be written as 00.
These bits are cleared
to 0 when read.
Parity type
Note:
0
Odd parity
1
Even parity
All error flags are cleared to 0 when read.
Figure 13.15 SIO3 Control Register (SC3CR)
TMP1941AF-178
2003-03-27
TMP1941AF
Name
SC4CR
(0xFFFF_F289) Read/Write
7
6
5
4
3
2
1
0
RB8
EVEN
PE
OERR
PERR
FERR


R
Reset Value
Function
R/W
0
Bit 8 of a
received
character
R (Cleared when read)
0
0
0
R/W
0
Parity type Parity
1: Error has occurred.
0: Disabled
0: Odd
Overrun
Parity
Framing
1: Enabled
1: Even
Framing error flag
Parity error flag
Overrun error flag
0
0
Must be written as 00.
These bits are cleared
to 0 when read.
Parity type
Note:
0
Odd parity
1
Even parity
All error flags are cleared to 0 when read.
Figure 13.16 SIO4 Control Register (SC4CR)
TMP1941AF-179
2003-03-27
TMP1941AF
BR0CR
(0xFFFF_F203)
Name
7
6
5
4
3
2
1
0

BR0ADDE
BR0CK1
BR0CK0
BR0S3
BR0S2
BR0S1
BR0S0
0
0
0
0
Read/Write
R/W
Reset Value
Function
0
Must be
written as
0.
0
0
N+
(16–K)/16
function
0: Disabled
1: Enabled
0
00: φT0
01: φT2
10: φT8
11: φT32
Clock divisor value N
Clock source for baud rate generator
BR0ADD
(0xFFFF_F204)
00
Internal clock φT0
01
Internal clock φT2
10
Internal clock φT8
11
Internal clock φT32
7
6
5
4
3
2
1
0
Name




BR0K3
BR0K2
BR0K1
BR0K0
Read/Write




Reset Value




0
0
Function
R/W
0
0
Value of K in N+(16–K)/16
Clock divisor value for baud rate generator
BR0CR.BR0ADDE = 1
BR0CR.BR0ADDE = 0
BR0CR. BR0S[3:0]
BR0ADD. BR0K[3:0]
0000 (N = 16) 0010 (N = 2) 0001 (N = 1) (Only UART)
or
thru
thru
0001 (N = 1) 1111 (N = 15) 1111 (N = 15)
0000 (N = 16)
0000
Don’t use.
Don’t use.
0001(K = 1)
thru
1111(K = 15)
Don’t use.
Divided by N
+
(16 – K) / 16
Divided by N
Note 1: The baud rate generator divisor can not be set to 1 in UART mode if the N + (16 – K) / 16 clock
division function is enabled. The divisor should be set to 2 or greater in I/O Interface mode.
Note 2: To use the N + (16 – K) / 16 clock division function, the value of K must be programmed in the
BR0ADD.BR0K[3:0] field before setting BR0CR.BR0ADDE to 1. However, the N + (16 – K) / 16
clock division function is not usable when BR0CR.BR0S[3:0] = 0000 (N = 16) or 0001 (N = 1).
Note 3: The N + (16 – K) / 16 clock division function can only be used in UART mode. In I/O Interface
mode, this must be disabled by clearing BR0CR.BR0ADDE to 0.
Figure 13.17 SIO0 Baud Rate Generator Control Registers (BR0CR and BR0ADD)
TMP1941AF-180
2003-03-27
TMP1941AF
Name
BR1CR
(0xFFFF_F20B) Read/Write
6
5
4
3
2
1
0
BR1ADDE
BR1CK1
BR1CK0
BR1S3
BR1S2
BR1S1
BR1S0
0
0
0
0
R/W
Reset Value
Function
7

0
Must be
written as
0.
0
0
N+
(16–K)/16
function
0: Disabled
1: Enabled
0
00: φT0
01: φT2
10: φT8
11: φT32
Clock divisor value N
Clock source for baud rate generator
Name
BR1ADD
(0xFFFF_F20C) Read/Write
Reset Value
00
Internal clock φT0
01
Internal clock φT2
10
Internal clock φT8
11
Internal clock φT32
7
6
5
4
3
2
1
0




BR1K3
BR1K2
BR1K1
BR1K0








0
0
Function
R/W
0
0
Value of K in N+(16–K)/16
Clock divisor value for baud rate generator
BR1CR.BR1ADDE = 1
BR1CR.BR1ADDE = 0
BR1CR. BR1S[3:0]
BR1ADD. BR1K[3:0]
0000 (N = 16) 0010 (N = 2) 0001 (N = 1) (Only UART)
or
thru
thru
0001 (N = 1) 1111 (N = 15) 1111 (N = 15)
0000 (N = 16)
0000
Invalid
Invalid
0001(K = 1)
thru
1111(K = 15)
Invalid
Divided by N
+
(16 – K) / 16
Divided by N
Note 1: The baud rate generator divisor can not be set to 1 in UART mode if the N + (16 – K) / 16 clock
division function is enabled. The divisor should be set to 2 or greater in I/O Interface mode.
Note 2: To use the N + (16 – K) / 16 clock division function, the value of K must be programmed in the
BR0ADD.BR0K[3:0] field before setting BR0CR.BR0ADDE to 1. However, the N + (16 – K) / 16
clock division function is not usable when BR0CR.BR0S[3:0] = 0000 (N = 16) or 0001 (N = 1).
Note 3: The N + (16 – K) / 16 clock division function can only be used in UART mode. In I/O Interface
mode, this must be disabled by clearing BR0CR.BR0ADDE to 0.
Figure 13.18 SIO1 Baud Rate Generator Control Registers (BR1CR and BR1ADD)
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BR3CR
(0xFFFF_F283)
Name
7
6
5
4
3
2
1
0

BR3ADDE
BR3CK1
BR3CK0
BR3S3
BR3S2
BR3S1
BR3S0
0
0
0
0
Read/Write
R/W
Reset Value
Function
0
Must be
written as
0.
0
0
N+
(16–K)/16
function
0: Disabled
1: Enabled
0
00: φT0
01: φT2
10: φT8
11: φT32
Clock divisor value N
Clock source for baud rate generator
BR3ADD
(0xFFFF_F284)
00
Internal clock φT0
01
Internal clock φT2
10
Internal clock φT8
11
Internal clock φT32
7
6
5
4
3
2
1
0
Name




BR3K3
BR3K2
BR3K1
BR3K0
Read/Write




Reset Value




0
0
Function
R/W
0
0
Value of K in N+(16–K)/16
Clock divisor value for baud rate generator
BR3CR.BR3ADDE = 1
BR3CR.BR3ADDE = 0
BR3CR. BR3S[3:0]
BR3ADD. BR3K[3:0]
0000 (N = 16) 0010 (N = 2) 0001 (N = 1) (Only UART)
or
thru
thru
0001 (N = 1) 1111 (N = 15) 1111 (N = 15)
0000 (N = 16)
0000
Invalid
Invalid
0001(K = 1)
thru
1111(K = 15)
Invalid
Divided by N
+
(16 – K) / 16
Divided by N
Note 1: The baud rate generator divisor can not be set to 1 in UART mode if the N + (16 – K) / 16 clock
division function is enabled. The divisor should be set to 2 or greater in I/O Interface mode.
Note 2: To use the N + (16 – K) / 16 clock division function, the value of K must be programmed in the
BR0ADD.BR0K[3:0] field before setting BR0CR.BR0ADDE to 1. However, the N + (16 – K) / 16
clock division function is not usable when BR0CR.BR0S[3:0] = 0000 (N = 16) or 0001 (N = 1).
Note 3: The N + (16 – K) / 16 clock division function can only be used in UART mode. In I/O Interface
mode, this must be disabled by clearing BR0CR.BR0ADDE to 0.
Figure 13.19 SIO3 Baud Rate Generator Control Registers (BR3CR and BR3ADD)
TMP1941AF-182
2003-03-27
TMP1941AF
Name
BR4CR
(0xFFFF_F28B) Read/Write
6
5
4
3
2
1
0
BR4ADDE
BR4CK1
BR4CK0
BR4S3
BR4S2
BR4S1
BR4S0
0
0
0
0
R/W
Reset Value
Function
7

0
Must be
written as
0.
0
0
N+
(16–K)/16
function
0: Disabled
1: Enabled
0
00: φT0
01: φT2
10: φT8
11: φT32
Clock divisor value N
Clock source for baud rate generator
Name
BR4ADD
(0xFFFF_F28C) Read/Write
Reset Value
00
Internal clock φT0
01
Internal clock φT2
10
Internal clock φT8
11
Internal clock φT32
7
6
5
4
3
2
1
0




BR4K3
BR4K2
BR4K1
BR4K0








0
0
Function
R/W
0
0
Value of K in N+(16–K)/16
Clock divisor value for baud rate generator
BR4CR.BR4ADDE = 1
BR4CR.BR4ADDE = 0
BR4CR. BR4S[3:0]
BR4ADD. BR4K[3:0]
0000 (N = 16) 0010 (N = 2) 0001 (N = 1) (Only UART)
or
thru
thru
0001 (N = 1) 1111 (N = 15) 1111 (N = 15)
0000 (N = 16)
0000
Invalid
Invalid
0001(K = 1)
thru
1111(K = 15)
Invalid
Divided by N
+
(16 – K) / 16
Divided by N
Note 1: The baud rate generator divisor can not be set to 1 in UART mode if the N + (16 – K) / 16 clock
division function is enabled. The divisor should be set to 2 or greater in I/O Interface mode.
Note 2: To use the N + (16 – K) / 16 clock division function, the value of K must be programmed in the
BR0ADD.BR0K[3:0] field before setting BR0CR.BR0ADDE to 1. However, the N + (16 – K) / 16
clock division function is not usable when BR0CR.BR0S[3:0] = 0000 (N = 16) or 0001 (N = 1).
Note 3: The N + (16 – K) / 16 clock division function can only be used in UART mode. In I/O Interface
mode, this must be disabled by clearing BR0CR.BR0ADDE to 0.
Figure 13.20 SIO4 Baud Rate Generator Control Registers (BR4CR and BR4ADD)
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2003-03-27
TMP1941AF
7
6
5
4
3
2
1
0
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
7
6
5
4
3
2
1
0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
(For tranmit)
SC0BUF
(0xFFFF_F200)
(For receive)
Figure 13.21 SIO0 Transmit/Receive Buffer Register (SC0BUF)
SC0MOD1
(0xFFFF_F205)
7
6
5
4
3
2
1
0
Name
I2S0
FDPX0






Read/Write
R/W
R/W






Reset Value
0
0






Function
SIO
operation
in IDLE
mode
0: Off
1: On
Synchronous
0: Halfduplex
1: Fullduplex
Figure 13.22 SIO0 Mode Register 1 (SC0MOD1)
7
6
5
4
3
2
1
0
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
7
6
5
4
3
2
1
0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
(For tranmit)
SC1BUF
(0xFFFF_F208)
(For receive)
Figure 13.23 SIO1 Transmit/Receive Buffer Register (SC1BUF)
Name
SC1MOD1
(0xFFFF_F20D) Read/Write
Reset Value
Function
7
6
5
4
3
2
1
0
I2S0
FDPX0






R/W
R/W






0
0






SIO
operation
in IDLE
mode
0: Off
1: On
Synchronous
0: Halfduplex
1: Fullduplex
Figure 13.24 SIO1 Mode Register 1 (SC1MOD1)
TMP1941AF-184
2003-03-27
TMP1941AF
7
6
5
4
3
2
1
0
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
7
6
5
4
3
2
1
0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
(For tranmit)
SC3BUF
(0xFFFF_F280)
(For receive)
Figure 13.25 SIO3 Transmit/Receive Buffer Register (SC3BUF)
Name
SC3MOD1
(0xFFFF_F285) Read/Write
7
6
5
4
3
2
1
0
I2S0







R/W







0







Reset Value
Function
SIO
operation
in IDLE
mode
0: Off
1: On
Figure 13.26 SIO3 Mode Register 1 (SC3MOD1)
7
6
5
4
3
2
1
0
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
7
6
5
4
3
2
1
0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
(For tranmit)
SC4BUF
(0xFFFF_F288)
(For receive)
Figure 13.27 SIO4 Transmit/Receive Buffer Register (SC4BUF)
7
Name
SC4MOD1
(0xFFFF_F28D) Read/Write
Reset Value
Function
6
5
4
3
2
1
0
I2S0







R/W







0
SIO
operation
in IDLE
mode
0: Off
1: On







Figure 13.28 SIO4 Mode Register 1 (SC4MOD1)
TMP1941AF-185
2003-03-27
TMP1941AF
13.4 Operating Modes
13.4.1
Mode 0 (I/O Interface Mode)
Mode 0 utilizes a synchronization clock (SCLK), which can be configured for either output mode in
which the SCLK clock is driven out from the TMP1941AF or input mode in which the SCLK clock is
supplied externally.
(1) Transmit Operations
In SCLK Output mode, each time the CPU writes a character to the transmit buffer, the eight
bits of the character is shifted out on the TXD0 pin, and the synchronization clock is driven out
from the SCLK0 pin. When all the bits have been shifted out, the transmit-done interrupt
(INTTX0) is generated.
Transmit Data Write
Timing
SCLK0 Output
TXD0
bit 0
bit 1
bit 6
bit 7
bit 0
INTTX0 Interrupt
Figure 13.29 Transmit Operation in I/O Interface Mode (SCLK0 Output Mode)
In SCLK0 Input mode, the CPU must write a character to the transmit buffer before the SCLK0
input is activated. The eight bits of a character in the transmit buffer are shifted out on the TXD0
pin, synchronous to the programmed edge of the SCLK0 input. When all the bits have been
shifted out, the transmit-done interrupt (INTTX0) is generated. The CPU must load the next
character into the transmit buffer by point A.
Transmit Data Write
Timing
A
SCLK0 Input
(SCLKS = 0: Rising Edge)
SCLK0 Input
(SCLKS = 1: Falling Edge)
TXD0
bit 0
bit 1
bit 5
bit 6
bit 7
bit 0
bit 1
INTTX0 Interrupt
Figure 13.30 Transmit Operation in I/O Interface Mode (SCLK0 Input Mode)
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2003-03-27
TMP1941AF
(2) Receive Operations
In SCLK Output mode, each time the CPU picks up the character in Receive Buffer 2, the
synchronization clock is driven out from the SCLK0 pin to shift the next character into Receive
Buffer 1. When a whole 8-bit character has been loaded into Receive Buffer 1, it is transferred to
Receive Buffer 2, and the receive-done interrupt (INTRX0) is generated.
The SCLK output is initiated by setting the SC0MOD0.RXE bit to 1.
Receive Data
Read Timing
SCLK0 Output
RXD0
bit 0
bit 1
bit 6
bit 7
bit 0
INTTX0 Interrupt
Figure 13.31 Receive Operation in I/O Interface Mode (SCLK0 Output Mode)
In SCLK Input mode, the CPU must pick up the character in the Receive Buffer 2 before the
SCLK0 input is activated to shift the next character into Receive Buffer 1. When a whole 8-bit
character has been loaded into Receive Buffer 1, it is transferred to Receive Buffer 2, and the
receive-done interrupt (INTRX0) is generated.
The CPU must read the character in Receive Buffer 2 by point A. Until that is done, the
receiver is not ready to accept the next character. In case the CPU reads the character in Receiver
Buffer 2 after point A, reception of the next character begins at that point, causing the received
data to be corrupted. For system applications in which the CPU might not be able to keep pace
with incoming data streams, handshaking is required.
Receive Data
Read Timing
A
SCLK0 Input
(SCLKS = 0: Rising Edge)
SCLK0 Input
(SCLKS = 1: Falling Edge)
RXD0
bit 0
bit 1
bit 5
bit 6
bit 7
bit 0
INTRX0 Interrupt
Figure 13.32 Receive Operation in I/O Interface Mode (SCLK0 Input Mode)
Note:
Regardless of whether SCLK is in input mode or output mode, the receiver must be enabled by
setting the SC0MOD.RXE bit to 1 in order to perform receive operations.
TMP1941AF-187
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(3) Full-Duplex Transmit/Receive Operations
Setting the SC0MOD1.FDPX0 bit enables full-duplex communication. In this mode of
operation, the double-buffering is enabled. When Receive Buffer 1 is filled with an 8-bit character,
it is transferred to Receive Buffer 2 (SC0BUF), and the receive-done interrupt (INTRX0) is
generated. While an 8-bit character is being received, an 8-bit character can be transmitted from
the TXD0 pin simultaneously. When a whole 8-bit character has been shifted out, the transmitdone interrupt (INTTX0) is generated.
In SCLK Output mode, loading the transimit buffer with a character restarts the transmit/receive
operation. The CPU must pick up the received character before the next character fills Receive
Buffer 1. Otherwise, the latter character is discarded. (The previous character is preserved.
Transmission proceeds with no error.)
Receive Data
Read Timing
Transmit Data
Write Timing
SCLK0 Output
TXD0
bit 0
bit 1
bit 5
bit 6
bit 7
bit 0
bit 1
RXD0
bit 0
bit 1
bit 5
bit 6
bit 7
bit 0
bit 1
INTTX0 Interrupt
INTRX0 Interrupt
Figure 13.33 Full-Duplex Transmit/Receive Operation in I/O Interface Mode
(SCLK0 Output Mode)
In SCLK Input Mode, the CPU must write a character to be transmitted into the transmit buffer
by point A. No transimi/receive operation occurs until the transmit buffer is filled. In case the
transmit buffer is loaded after point A, the transmit/receive operation begins at that point, causing
the transimit/receive data to be corrupted. For system applications in which transmit underrun
conditions could occur, handshaking is required.
Receive Data
Read Timing
Transmit Data
Write Timing
A
A
SCLK0 Output
TXD0
bit 0
bit 1
bit 5
bit 6
bit 7
bit 0
bit 1
RXD0
bit 0
bit 1
bit 5
bit 6
bit 7
bit 0
bit 1
INTTX0 Interrupt
INTRX0 Interrupt
Figure 13.34 Full-Duplex Transmit/Receive Operation in I/O Interface Mode
(SCLK0 Input Mode)
•
Restrictions on SCLK Configured as an Input
In I/O Interface mode, the CPU may be unable to access the receive or transmit buffer fast
enough to support back-to-back transfers. When SCLK is configured as an output, one or more
wait cycles are automatically inserted to prolong the SCLK intervals. However, when SCLK is
TMP1941AF-188
2003-03-27
TMP1941AF
configured as an input, the SCLK input must be delayed by external hardware so that the CPU can
keep pace with the data rate. Generally, the wait period is a function of the fsys frequency and the
data rate. The following figure gives some indication of the relationsip between SCLK and fsys
frequencies for different wait periods. In reality, processing load during transfers also affect the
maximum SCLK frequency.
Sufficient wait period
Wait period of one SCLK cycle
Wait period of one-half SCLK cycle
MHz
2.0
SCLK Frequency
1.5
No wait (free-running SCLK)
1.0
0.5
0
0
10
20
30
40
MHz
fsys
Note:
13.4.2
The above figure assumes that the DMAC is utilized for reads of the receive buffer and
writes of the transmit buffer.
Mode 1 (7-Bit UART Mode)
Setting the SM[1:0] field in the SC0MOD0 to 01 puts the SIO0 in 7-bit UART mode. In this mode of
operation, the parity bit can be added to the transmitted character, and the receiver can perform a parity
check on incoming data. Parity can be enabled and disabled through the programming of the PE bit in
the SC0CR. When PE = 1, the SCR0CR.EVEN bit selects even or odd parity.
Example: Transmitting 7-bit UART characters with an even-parity bit
start
bit 0
1
2
3
4
5
6
even
parity
stop
Goes out first (transfer rate = 2400 bps @fc = 24.576 MHz)
Clocking conditions:
System clock:
High-speed (fc)
High-speed clock gear: ↕ 1 (fc)
Prescaler clock:
fperiph/4 (fperiph = fsys)
Settings in the main routine
P9CR
P9FC
SC0MOD
SC0CR
BR0CR
IMCCLH
←
←
←
←
←
←
7
−
−
X
X
0
−
6
−
−
0
1
0
−
5
−
−
−
1
1
1
4
−
−
X
X
0
1
3
−
−
0
X
1
0
2
−
−
1
X
0
1
1
−
−
0
0
1
0
0
1
1
1
0
0
0
SC0BUF
← *
*
*
*
*
*
*
*
Selects 7-bit UART mode.
Selects even parity.
Sets the transfer rate to 2400 bps.
Enables the INTTX0 interrupt and sets its priority
level to 4.
Loads the transmit buffer with a character.
0
0
0
1
Clears the interrupt request.
Configures the P90 pin as TXD0.
Transmit-done interrupt routine
INTCLR
← X
X
1
1
Interrupt processing
End of interrupt processing
X = Don’t care, – = No change
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13.4.3
Mode 2 (8-Bit UART Mode)
Setting the SM[1:0] field in the SC0MOD0 to 10 puts the SIO0 in 8-bit UART mode. In this mode of
operation, the parity bit can be added to the transmitted character, and the receiver can perform a parity
check on incoming data. Parity can be enabled and disabled through the programming of the PE bit in
the SC0CR. When PE = 1, the SCR0CR.EVEN bit selects even or odd parity.
Example: Transmitting 8-bit UART characters with an odd-parity bit
start
bit 0
1
2
3
4
5
6
odd
parity
stop
Goes out first (transfer rate = 9600 bps @fc = 24.576 MHz)
Clocking conditions:
System clock:
High-speed (fc)
High-speed clock gear: ↕ 1 (fc)
Prescaler clock:
fperiph/4 (fperiph = fsys)
Settings in the main routine
P9CR
SC0MOD
SC0CR
BR0CR
IMCCLL
←
←
←
←
←
7
−
−
X
0
−
6
−
0
0
0
−
5
−
1
1
0
1
4
−
X
X
1
1
3
−
1
X
0
0
2
−
0
X
1
1
1
0
0
0
0
0
0
−
1
0
1
0
1
0
0
0
Configures P91 (RXD0) to be an input.
Selects 8-bit UART mode and enables the receiver.
Selects odd parity.
Sets the transfer rate to 9600 bps.
Enables the INTRX0 interrupt and sets its priority
level to 4.
Example of interrupt routine processing
INTCLR
7
← X
6
X
5
1
4
1
3
0
2
0
Reg.
← SC0CR AND 0x1C
if Reg. ≠ 0 then Error
Reg.
← SC0BUF
End of interrupt processing
X = Don’t care,
13.4.4
Clears the interrupt request.
Checks for errors.
– = No change
Mode 3 (9-Bit UART Mode)
Setting the SM[1:0] field in the SC0MOD0 to 11 puts the SIO0 in 9-bit UART mode. In this mode, a
parity bit cannot be used; thus, parity should be disabled by clearing the SC0CR.PE bit to 0.
For transmit operations, the most-significant bit (9th bit) is stored in the TB8 bit in the SC0MOD0.
For receive operations, the most-significant bit is stored in the RB8 bit in SC0CR. Reads and writes of
the transmit/receive character must be done with the most-significant bit first, followed by the SC0BUF.
Wake-up Feature
In 9-bit UART mode, the receiver wake-up feature allows the slave station in a multidrop system to
wake up whenever an address character is received. Setting the SC0MOD0.WU bit enables the wake-up
feature. When the SC0CR.RB8 bit has received an address/data flag bit set to 1, the receiver generates
the INTRX0 interrupt.
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TXD
RXD
TXD
Master
Note:
RXD
TXD
Slave 1
RXD
TXD
RXD
Slave 2
Slave 3
The slave controller’s TXD pin must be configured as an open-drain output by programming the
ODE register.
Figure 13.35 Serial Link Using the Wake-Up Function
Protocol
(1) Put all the master and slave controllers in 9-bit UART mode.
(2) Enables the receiver in each slave controller by setting the SC0MOD0.WU bit to 1.
(3) The master controller transmits an address character (i.e, select code) that identifies a slave
controller. The address character has the most-significant bit (bit 8) set to 1.
start
bit 0
1
2
3
4
5
6
7
Slave controller select code
8
stop
“1”
(4) Each slave controller compares the received address to its station address and clears the WU bit if
they match.
(5) The master controller transmits data characters or block of data to the selected slave controller
(with SC0MOD0.WU bit cleared). Data characters have the most-significant bit (bit 8) cleared to
0.
start
bit 0
1
2
3
4
Data
5
6
7
bit 8
stop
“0”
(6) Slave controllers not addressed continue to monitor the data stream, but discard any characters
with the most-significant bit (RB8) cleared, and thus does not generate receive-done interrupts
(INTRX0). The addressed slave controller with its WU bit cleared can transmit data to the master
controller to notify that it has successfully received the message.
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Example: Connecting a master station with two slave stations through a serial link using the fsys/2
clock as a serial clock
TXD
RXD
TXD
Master
•
RXD
TXD
RXD
Slave 1
Slave 2
Select Code
0x0000_0001
Select Code
0x0000_1010
Master controller settings
Main routine
7
6
5
4
3
2
1
0
P9CR
P9FC
IMCCLL
IMCCLH
SC0MOD0
←
←
←
←
←
−
−
−
−
1
−
−
−
−
0
−
−
1
1
1
−
−
1
1
0
−
−
0
0
1
−
−
1
1
1
0
X
0
0
1
1
1
1
0
0
SC0BUF
← 0
0
0
0
0
0
0
1
Enables INTRX0 and sets its interrupt level to 5.
Enables INTTX0 and sets its interrupt level to 4.
Selects 9-bit UART mode and selects fsys/2 as
a serial clock.
Loads the select code for slave 1.
1
−
*
0
−
*
0
−
*
0
−
*
1
−
*
Clears the interrupt request.
Clears the TB0 bit to 0.
Loads the transmit data.
Configures the P90 pin as TXD0 and the P91
pin as RXD0
Interrupt routine (INTTX0)
INTCLR
← X
SC0MOD0 ← 0
SC0BUF
← *
X
−
*
1
−
*
End of interrupt processing
•
Slave controller settings
Main routine
P9CR
P9FC
ODE
IMCCLL
IMCCLH
SC0MOD0
←
←
←
←
←
←
7
6
5
4
3
2
1
0
−
−
X
−
−
0
−
−
X
−
−
0
−
−
−
1
1
1
−
−
−
1
1
1
−
−
−
0
0
1
−
−
−
1
1
1
0
X
−
1
0
1
1
1
1
0
1
0
1
0
0
0
0
Clears the interrupt request.
0
−
−
−
−
Clears the WU bit to 0.
Configures the P90 pin as TXD (open-drain
output) and the P91 pin as RXD.
Enables INTTX0 and INTRX0.
Selects 9-bit UART mode, selects fsys/2 as the
serial clock and and sets the WU bit to 1.
Interrupt routine (INTRX0)
← X X 1
INTCLR
← SC0BUF
Reg.
if Reg. = Select code
Then
SC0MOD0 ← − − −
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14. Serial Bus Interface (SBI)
The TMP1941AF contains a Serial Bus Interface (SBI) channel, which has the following two operating
modes:
•
I2C Bus mode (with multi-master capability)
•
Clock-Synchronous 8-Bit SIO mode
In I2C Bus mode, the SBI is connected to external devices via two pins, PA6 (SDA) and PA7 (SCL). In
Clock-Synchronous 8-Bit SIO mode, the SBI is connected to external devices via three pins, PA5 (SCK),
PA6 (SO) and PA7 (SI).
The following table shows the programming required to put the SBI in each operating mode.
ODE.ODEA7
thru
ODE.ODEA6
PACR.PA7C
thru
PACR.PA5C
PAFC.PA7F
thru
PAFC.PA5F
I2C Bus Mode
11
11X
110
Clock-Synchronous
8-Bit SIO Mode
XX
011
010
111
X = Don’t care
Note: With the TMP1940FDBF with flash memory, the SBI is unusable when the DSU feature is enabled.
14.1 Block Diagram
INTS2 Interrupt Request
SCL
SCK
SIO
Clock
Control
φT0
Noise
Canceller
PA5
(SCK)
Input/
Output
Control
Divider
I2C Bus
Clock
Synchronization /
Control
Transfer
Control Logic
SI
PA7
(SI/SCL)
2
Shift Register
SBI0CR2/
SBI0SR
PA6
(SO/SDA)
SO
SIO Data
Control
I2C0AR
SBI Control Register 2 /
I2C Bus
SBI Status Register Address Register
I C Bus
Data Control
SBI0DBR
SBI0CR1
SBI Data
Buffer Register
SBI Control
Register 1
Noise
Canceller
SDA
SBI0BR0/1
SBI Baud Rate
Registers 0 and 1
Figure 14.1 SBI Block Diagram
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14.2 Registers
A listing of the registers used to control the SBI follows:
•
Serial Bus Interface Control Register 1 (SBI0CR1)
•
Serial Bus Interface Control Register 2 (SBI0CR2)
•
Serial Bus Interface Data Buffer Register (SBI0DBR)
•
I2C Bus Address Register (I2C0AR)
•
Serial Bus Interface Status Register (SBI0SR)
•
Serial Bus Interface Baud Rate Register 0 (SBI0BR0)
•
Serial Bus Interface Baud Rate Register 1 (SBI0BR1)
The functions of these registers vary, depending on the mode in which the SBI is operating. For a
detailed description of the registers, refer to Section 14.5, I2C Bus Mode Configuration, and Section
14.8, Clock-Synchronous 8-Bit SIO Mode Operation.
14.3 I2C Bus Mode Data Formats
Figure 14.2 shows the serial bus interface data formats used in I2C Bus mode.
(a) Addressing format
8 bits
S
Slave address
1
R A
/ C
W K
1 to 8 bits
Data
Once
1
A
C
K
1 to 8 bits
Data
1
A
C P
K
Repeated
(b) Addressing format (with repeated START condition)
8 bits
S
Slave address
1
R A
/ C
W K
Once
1 to 8 bits
Data
1
A
C S
K
Repeated
8 bits
Slave address
1
R A
/ C
WK
Once
1 to 8 bits
1
A
C P
K
Data
Repeated
(c) Free data format (master-transmitter to slave-receiver)
8 bits
S
Data
1
A
C
K
1 to 8 bits
Data
Once
1
A
C
K
1 to 8 bits
Data
1
A
C P
K
Repeated
S = START condition
R/ W = Direction bit
ACK = Acknowledge bit
P = STOP condition
2
Figure 14.2 I C-Bus Mode Data Formats
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14.4 Description of the Registers Used in I2C Bus Mode
This section provides a summary of the registers which control I2C bus operation and provide I2C bus
status information for bus access/monitoring.
Serial Bus Interface Control Register 1
7
Name
SBI0CR1
(0x FFFF_F240)
Read/Write
Reset Value
Function
6
BC2
5
BC1
BC0
W
0
0
4
3
ACK

R/W

0

0
2
1
SCK2
0
SCK1
W
0
SCK0/
SWRMON
R/W
0
1
Internal SCL output clock frequency
(Note 2) / Software reset monitor
Number of bits per transfer (Note 1) ACK clock
pulse
0: No ACK
1: ACK
On writes: SCK[2:0] = Internal SCL output clock frequency
000
001
010
011
100
101
110
111
500 kHz
278 kHz
147 kHz
75.8 kHz
38.5 kHz
19.4 kHz
9.73 kHz
Reserved
n=4
n=5
n=6
n=7
n=8
n=9
n=10
Assumptions:
System clock: fc (= 40 MHz)
Clock gear: fc/1
φT0 = fperiph/4 (= 10 MHz)
φT0
Frequency =
(Hz)
2n + 4
On reads: SWRMON = Software reset monitor
0
Software reset operation is in progress.
1
Software reset operation is not in progress.
Number of bits per transfer
BC
[2:0]
000
001
010
011
100
101
110
111
ACK = 0
# of clock
cycles
8
1
2
3
4
5
6
7
ACK = 1
Data length
# of clock
cycles
Data length
8
1
2
3
4
5
6
7
9
2
3
4
5
6
7
8
8
1
2
3
4
5
6
7
Note 1: Clear the BC[2:0] field to 000 before switching the operating mode to Clock-Synchronous 8-Bit
SIO mode.
Note 2: For details on the SCL bus clock frequency, refer to Section 14.5.3, Serial Clock.
2
Figure 14.3 I C Bus Mode Registers (1)
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Serial Bus Interface Control Register 2
SBI0CR2
Name
(0xFFFF_F243) Read/Write
Reset Value
Function
7
6
MST
TRX
5
4
3
BB
PIN
SBIM1
W
0
Master/
slave
0: Slave
1: Master
2
1
0
SBIM0
SWRST1
SWRST0
W (Note 1)
0
0
1
Transmit/
receive
0: Receive
1: Transmit
START /
STOP
generation
0: STOP
condition
1: START
condition
INTS2
interrupt
clear
0: Don’t
care
1: Interrupt
clear
0
W (Note 1)
0
0
Operating mode
(Note 2)
00: Port mode
01: SIO mode
10: I2C Bus mode
11: Reserved
0
Software reset
A write of 10 followed
by a write of 01
Operating mode (Note 2)
00
Port mode (serial bus interface output disabled)
01
Clock-Synchronous 8-Bit SIO mode
10
I2C Bus mode
11
Reserved
Note 1: Reading this register causes it to function as a status register (SBI0SR). See the next page.
Note 2: Ensure that the bus is free before switching the operating mode to Port mode. Ensure that the
port is at logic high before switching from Port mode to I2C Bus or SIO mode.
2
Figure 14.4 I C Bus Mode Registers (2)
Table 14.1 Prescalar Output Clock (φT0) Resolutions
@fc = 40 MHz
Peripheral Clock
Prescalar Clock
Prescalar Output Clock Resolution
Clock Gear Value
Select
Select
SYSCR1.GEAR[1:0]
φT0
SYSCR1.FPSEL
SYSCR0.PRCK[1:0]
00 (fperiph/4)
00 (fc)
01 (fc/2)
0 (fgear)
10 (fc/4)
11 (fc/8)
00 (fc)
01 (fc/2)
1 (fc)
10 (fc/4)
11 (fc/8)
fc/22 (0.1 µs)
01 (fperiph/2)

10 (fperiph)

00 (fperiph/4)
fc/23 (0.2 µs)
01 (fperiph/2)

10 (fperiph)

00 (fperiph/4)
fc/24 (0.4 µs)
01 (fperiph/2)

10 (fperiph)

00 (fperiph/4)
fc/25 (0.8 µs)
01 (fperiph/2)

10 (fperiph)

00 (fperiph/4)
fc/22 (0.2 µs)
01 (fperiph/2)

10 (fperiph)

00 (fperiph/4)

01 (fperiph/2)

10 (fperiph)

00 (fperiph/4)

01 (fperiph/2)

10 (fperiph)

00 (fperiph/4)

01 (fperiph/2)

10 (fperiph)

Note: The — character means “Don’t use.”
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Serial Bus Interface Status Register
SBI0SR
Name
(0xFFFF_F243) Read/Write
Reset Value
Function
7
6
5
4
MST
TRX
BB
PIN
3
2
1
0
AL
AAS
AD0
LRB
R
0
0
Master/
slave
0: Slave
1: Master
0
Transmit/
receive
0: Receive
1: Transmit
I2C Bus
status
0: Free
1: Busy
1
0
0
0
INTS2
interrupt
status
0: Asserted
1: Not
asserted
Arbitration
lost
0: 
1: Detected
Addressed
as slave
0: 
1: Detected
Address 0
(general
call)
0: 
1: Detected
0
Last
received
bit
0: 0
1: 1
Last received bit
0
The last bit received was 0.
1
The last bit received was 1.
Addressed as slave
0

1
The address on the bus matches the
I2COAR or general-call address
(slave receiver mode only)
Arbitration lost
Note:
0

1
Arbitration was lost to another master.
Writing to this register causes it to function as a control register (SBI0CR2). See the previous
page.
2
Figure 14.5 I C Bus Mode Registers (3)
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Serial Bus Interface Baud Rate Register 0
Name
SBI0BR0
(0xFFFF_F244) Read/Write
Reset Value
7
6
5
4
3
2
1
0

I2SBI0







R/W





W

0






Must be
written as
0.
IDLE
0: Off
1: On
Function
SBI on/off in IDLE mode
0
Off
1
On
Serial Bus Interface Baud Rate Register 1
Name
SBI0BR1
(0xFFFF_F245) Read/Write
Reset Value
7
6
5
4
3
2
1
0
P4EN







R/W







0







Internal
clock
0: Off
1: On
Function
Controls the iternal baud rate generator
0
Off
1
On
Serial Bus Interface Data Buffer Register
Name
SBI0DBR
(0xFFFF_F241) Read/Write
7
6
5
DB7
DB6
DB5
4
3
2
1
0
DB4
DB3
DB2
DB1
DB0
R (receive) / W (transmit)
Reset Value
Note:
Undefined
In transmitter mode, data must be written to this register, with bit 7 being the most-significant
bit (MSB).
2
I C Bus Address Register
Name
I2C0AR
(0xFFFF_F242) Read/Write
Reset Value
Function
7
6
5
4
3
2
1
0
SA6
SA5
SA4
SA3
SA2
SA1
SA0
ALS
0
0
0
W
0
0
0
0
When the SBI is addressed as a slave, this field specifies a 7-bit I2C-bus address to
which the SBI responds.
0
Address
recognition
mode
Address recognition mode
0
Recognizes the slave address.
1
Does not recognize the slave address.
2
Figure 14.6 I C Bus Mode Registers (4)
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14.5 I2C Bus Mode Configuration
14.5.1
Acknowledgment Mode
Setting the SBI0CR1.ACK bit selects Acknowledge mode. When operating as a master, the SBI
generates a clock pulse for acknowledge automatically after each data. As a transmitter, the SBI
releases the SDA line during this acknowledge cycle so that the receiver of the data transfer can drive
the SDA line low to acknowledge receipt of the data. As a receiver, the SBI pulls the SDA line low
during the acknowledge cycle after each data has been received.
Clearing the SBI0CR1.ACK bit selects Non-Acknowledge mode. When operating as a master, the
SBI does not generate acknowledge clock pulses.
14.5.2
Number of Bits Per Transfer
The SBI0CR1.BC[2:0] field specifies the number of bits of the next data item to be transmitted or
received. After a reset, this field is cleared to 000, causing a 7-bit slave address and the data direction
( R / W ) bit to be transferred in a packet of eight bits. At other times, the SBI0CR1.BC[2:0] field keeps
a previously programmed value.
14.5.3
Serial Clock
(1) I2C Bus Clock Source
The SBI0CR1.SCK[2:0] field controls the maximum frequency of the SCL clock driven out on
the SCL pin in master mode, as illustrated below.
tHIGH
tLOW
tLOW = 2n – 1/φT0
tHIGH = 2 n – 1/φT0 + 4/φT0
fscl = 1/(tLow + tHIGH)
φT0
=
2n+4
1/fscl
SBI0CR1.SCK[2:0]
000
001
010
011
100
101
110
n
4
5
6
7
8
9
10
2
Figure 14.7 I C Bus Clock Source
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(2) Clock Synchronization
Clock synchronization is performed using the wired-AND connection of all I2C-bus components
to the bus. If two or more masters try to transfer messages on the I2C bus, the first to pull its clock
line low wins the arbitration, overriding other masters producing a high on their clock lines.
Clock signals of two or more devices on the I2C-bus are synchronized to ensure correct data
transfers. Figure 14.8 shows a depiction of the clock synchronization mechanism for the I2C bus
with two masters.
Wait State
Start counting HIGH period
Internal SCL Level (Master A)
Counter reset
Internal SCL Level (Master B)
SCL Bus Line
a
b
c
Figure 14.8 Clock Synchronization Example
At point a, Master A pulls its internal SCL level low, bringing the SCL bus line low. The highto-low transition on the SCL bus line causes Master B to reset its high-level counter and pulls its
internal SCL level low.
Master A completes its low period at point b. However, the low-to-high transition on its internal
SCL level does not change the state of the SCL bus line if Master B’s internal SCL level is still
within its low period. Therefore, Master A enters a high wait state, where it does not start counting
off its high period.
When Master B has counted off its low period at point c, its internal SCL level goes high,
releasing the SCL bus line (high). There will then be no difference between the internal SCL levels
and the state of the SCL bus line, and both Master A and Master B start counting off their high
periods.
This way, a synchronized SCL clock is generated with its high period determined by the master
with the shortest clock high period and its low period determined by the one with the longest clock
low period.
14.5.4
Slave Addressing and Address Recognition Mode
When the SBI is configured to operate as a slave, the SA[6:0] field in the I2C0AR must be loaded
with the 7-bit I2C-bus address to which the SBI is to respond. The ALS bit must be cleared for the SBI
to recognize the incoming slave address.
14.5.5
Configuring the SBI as a Master or a Slave
Setting the SBI0CR2.MST bit configures the SBI as a master, and clearing it configures the SBI as a
slave. This bit is cleared by hardware when a STOP condition has been detected and when arbitration
for the I2C bus has been lost.
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14.5.6
Configuring the SBI as a Transmitter or a Receiver
The SBI0CR2.TRX bit is set or cleared by hardware to configure the SBI as a transmitter or a
receiver.
As a slave, the SBI is put in either slave-receiver or slave-transmitter mode, depending on the value
of the data direction ( R / W ) bit transmitted by the master. When the SBI is addressed as a slave, the
TRX bit reflects the value of the R / W bit. The TRX bit is set or cleared on the following occasions:
•
when transferring data using addressing format
•
when the received slave address matches the value in I2C0CR
•
when a general-call address is received; i.e., the eight bits following the START condition are all
zeros.
As a master, the SBI is put in either master-transmitter or a master-receiver mode upon reception of
an acknowledge from an addressed slave. The TRX bit changes to the opposite value of the R / W bit
sent by the SBI. If the SBI does not receive an acknowledge from a slave, the TRX bit retains the
previous value.
The TRX bit is cleared by hardware when a STOP condition has been detected and when arbitration
for the I2C bus has been lost.
14.5.7
Generating START and STOP Conditions
When the SBI0SR.BB bit is cleared, the bus is free. At this time, writing 1s to the MST, TRX, BB
and PIN bits in the SBI0CR2 causes the SBI to generate a START condition on the bus and shift out 8bit I2C-bus data. Before generating a START condition, the ACK bit must be set to 1.
SCL Line
1
2
3
4
5
6
7
8
SDA Line
A6
A5
A4
A3
A2
A1
A0
R/W
9
Acknowledge Signal
START Condition
Slave Address and Direction bit
Figure 14.9 Generating a START Condition and a Slave Address
When the SBI0SR.BB bit is set, the bus is busy. When SBI0SR.BB=1, writing 1s to the MST, TRX
and PIN bits and a 0 to the BB bit causes the SBI to start a sequence for generating a STOP condition
on the bus to abort the transfer. The MST, TRX, BB and PIN bits should not be altered until a STOP
condition appears on the bus.
SCL Line
SDA Line
STOP Condition
Figure 14.10 Generating a STOP Condition
The BB bit can be read to determine if the I2C bus is in use. The BB bit is set when a START
condition is detected and cleared when a STOP condition is detected.
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14.5.8
Asserting and Deasserting Interrupt Requests
When an SBI interrupt (INTS2) is generated, the Pending Interrupt Not (PIN) bit in the SBI0CR2 is
cleared to 0. While the PIN bit is 0, the SBI pulls the SCL line low.
After transmission or reception of one data word on the I2C bus, the PIN bit is automatically cleared.
In transmitter mode, the PIN bit is subsequently set to 1 each time the SBI0DBR is written. In receiver
mode, the PIN bit is set to 1 each time the SBI0DBR is read.
It takes a period of tLOW for the SCL line to be released after the PIN bit is set.
In Address Recognition mode (ALS=0), the PIN bit is cleared when the SBI is addressed as a slave
and the received slave address matches the value in the I2C0CR or is all 0s (i.e., a general call).
A write of 1 by software sets the PIN bit, but a write of 0 has no effect on this bit.
14.5.9
SBI Operating Modes
The SBIM[1:0] field in the SBI0CR2 is used to select an operating mode of the SBI. To configure the
SBI for I2C Bus mode, set the SBIM[1:0] field to 10.
A switch to Port mode should only be attempted when the bus is free.
14.5.10 Lost-Arbitration Detection Monitor
The I2C bus is a multi-master bus and has an arbitration procedure to ensure correct data transfers.
A master may start a transfer only if the bus is free. A master that attempts to generate a START
condition while the bus is busy loses bus arbitration, with no START condition occurring on the SDA
and SCL lines.
The I2C-bus arbitration takes place on the SDA line.
Figure 14.11 shows the arbitration procedure for two masters. Up until point a, the internal data levels
of Master A and Master B are the same. At point a Master B’s internal data level makes a low-to-high
transition while Master A’s internal data level remains at logic low. However, the SDA bus line is held
low because it is the wired-AND of the two data outputs. When the SCL bus clock goes high at point b,
the addressed slave device reads the data transmitted by Master A (i.e., winning master). Master B loses
arbitration and switches off its data output stage, releasing its SDA line (high), so that it does not affect
the data transfer initiated by the winning master.
In case two competing masters have transmitted exactly the same first data word, the arbitration
procedure continues with the second data word.
SCL Bus Line
Internal SDA Level
(Master A)
Internal SDA Level
(Master B)
Master B loses arbitration and
connects a high output level to the bus.
SDA Bus Line
a
b
Figure 14.11 Arbitration Procedure of Two Masters
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A master compares its internal data level to the actual level on the SDA line at the rising edge of the
SCL clock. The master loses arbitration if there is a difference between these two values. The losing
master sets the AL bit in the SBI0SR to 1, which causes the MST and TRX bits in the same register to
be cleared. That is, the losing master switches to slave-receiver mode.
The AL bit is subsequently cleared when data is written to or read from the SBI0DBR and when the
SBI0CR2 is programmed with new parameters.
Master
A
Internal SCL
Level
Internal SDA
Level
1
D7A
2
3
4
5
6
7
8
D6A
D5A
D4A
D3A
D2A
D1A
D0A
9
1
2
3
4
D7A’ D6A’ D5A’ D4A’
Clock output stops here
Master
B
Internal SCL
Level
Internal SDA
Level
1
D7B
2
D6B
3
4
Internal SDA level is held high
because Master B has lost arbitration.
AL
MST
TRX
Access to the SBI0DBR
or SBI0CR2
Figure 14.12 Master B Loses Arbitration (D7A – D7B, D6A – D6B)
14.5.11 Slave Address Match Monitor
When acting as a slave-receiver, the ALS bit in the I2C0CR determines whether the SBI recognizes
the incoming slave address or not. In Address Recognition mode (i.e., ALS=0), the Addressed-As-Slave
(AAS) bit in the SBI0SR is set when an incoming address over the I2C bus matches the value in the
I2C0CR or when the general-call address has been received. When ALS=1, the AAS bit is set when the
first data word has been received. The AAS bit is cleared each time the SBI0DBR is read or written.
14.5.12 General-Call Detection Monitor
When acting as a slave receiver, the AD0 bit in the SBI0SR is set when a general-call address has
been received. The general-call address is detected when the eight bits following a START condition
are all zeros. The AD0 bit is cleared when a START or STOP condition is detected on the bus.
14.5.13 Last Received Bit Monitor
The LRB bit in the SBI0SR holds the value of the last bit received over the SDA line at the rising
edge of the SCL clock. In Acknowledge mode, reading this bit immediately after generation of the
INTS2 interrupt returns the value of the ACK signal.
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14.5.14 Software Reset
The SBI provides a software reset, which permits recovery from system lockups caused by external
noise. A software reset is performed by a write of 10 followed by a write of 01 to the SWRST[1:0] field
in the SBI0CR2. After a software reset, all control and status register bits are initialized to their reset
values. Upon resetting the SBI, the SWRST[1:0] field is automatically cleared to 00.
Note:
A software reset causes the SBI operating mode to switch from I2C Bus mode to Port mode. This
does not affect the Port A Function register, however.
14.5.15 Serial Bus Interface Data Buffer Register (SBI0DBR)
The SBI0DBR is a data buffer interfacing to the I2C bus. All read and write operations to/from the
I C bus are done via this register.
2
When the SBI is acting as a master, loading this register with a slave address and a data direction bit
causes a START condition to be generated.
14.5.16 I2C Bus Address Register (I2C0AR)
When the SBI is configured as a slave, the SA[6:0] field in the I2C0AR must be loaded with the 7-bit
I2C-bus address to which the SBI is to respond.
If the ALS bit in the I2C0AR is cleared, the SBI recognizes a slave address transmitted by the master
device, interpreting incoming frame structures as per addressing format. If the ALS bit is set, the SBI
does not recognize a slave address and interprets all frame structures as per free data format.
14.5.17 Baud Rate Register 1 (SBI0DBR1)
Before the I2C bus can be used, the P4EN bit in the SBI0BR1 must be set to enable the SBI internal
baud rate generation logic.
14.5.18 Baud Rate Register 0 (SBI0BR0)
The I2SBI0 bit in the SBI0BR0 determines whether the SBI is shut down or not when the
TMP1941AF is put in IDLE standby mode. This register must be programmed before executing an
instruction for entering a standby mode.
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14.6 Programming Sequences in I C Bus Mode
14.6.1
SBI Initialization
First, program the P4EN bit in the SBI0BR1, and the ACK and SCK[2:0] bits in the SBI0CR1. Set
the SBI0BR1.P4EN bit to 1 to enable the internal baud rate generation logic. Write 0s to bits 7–5 and
bit 3 in the SBI0CR1.
Next, program the I2C0AR. The SA[6:0] field in the I2C0AR defines the chip’s slave address, and
the ALS bit (bit 0) selects an address recognition mode. (The ALS bit must be cleared when using the
addressing format.)
Next, program the SBI0CR2 to initially configure the SBI in slave-receiver mode; i.e., clear the MST,
TRX and BB bits to 0, set the PIN bit to 1 and set the SBIM[1:0] field to 10. Write 00 to the
SWRST[1:0] field.
SBI0BR1
SBI0CR1
I2C0AR
SBI0CR2
←
←
←
←
7
1
0
X
0
6
0
0
X
0
5
0
0
X
0
4
0
X
X
1
3
0
0
X
1
2
0
X
X
0
1
0
X
X
0
0
0
X
X
0
Enable internal baud rate generator.
Disable generation of ACK and select SCL clock frequency.
Load a slave address and selects address recognition mode.
Configure the SBI in slave-receiver mode.
Note: X = Don’t care
14.6.2
Generating a START Condition and a Slave Address
(1) Master Mode
In master mode, the following steps are required to generate a START condition and a slave
address on the I2C-bus.
First, ensure that the bus is free (i.e., SBI0CR2.BB = 0).
Next, set the ACK bit in the SBI0CR1 to enable generation of acknowledge clock pulses. Then,
loads the SBI0DBR with a slave address and a data direction bit to be transmitted via the I2C bus.
When BB=0, writing 1s to the MST, TRX, BB and PIN bits in the SBI0CR2 causes a START
condition to be generated on the bus. Following a START condition, the SBI generates SCL clock
pulses nine times: the SBI shifts out the contents of the SBI0DBR with the first eight SCL clocks,
and releases the SDA line during the last (i.e., ninth) SCL clock to receive an acknowledgement
signal from the addressed slave.
The INTS2 interrupt request is generated on the falling edge of the ninth SCL clock pulse, and
the PIN bit in the SBI0CR2 is cleared to 0. In master mode, the SBI holds the SCL line low while
the PIN bit is 0. Upon interrupt, the TRX bit either remains set or is cleared according to the value
of the transmitted direction bit, provided an acknowledgement signal has been returned from the
slave.
Settings in main routine
Reg.
Reg.
if Reg.
7 6 5 4 3 2 1 0
← SBI0SR
← Reg. & 0x20
≠ 0x00
Ensure that the bus is free.
Then
SBI0CR1 ← X X X 1 0 X X X
SBI0DBR ← X X X X X X X X
SBI0CR2 ← 1 1 1 1 1 0 0 0
Select Acknowledgement mode.
Load the slave address and a data direction bit.
Generate a START condition.
INTS2 interrupt routine
INTCLR
← 0x34
Clear the interrupt request.
Interrupt processing
End of interrupt
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(2) Slave Mode
In slave mode, the following steps are required to receive a START condition and a slave
address via the I2C bus.
Upon detection of a START condition, the SBI clocks in a 7-bit slave address and a data
direction bit transmitted by the master during the first eight SCL clock pulses. If the received slave
address matches its own address in the I2C0AR or is equal to the general-call address (00H), the
SBI pulls the SDA line low during the last (i.e., ninth) SCL clock for acknowledgement.
The INTS2 interrupt request is generated on the falling edge of the ninth SCL clock pulse, and
the PIN bit in the SBI0CR2 is cleared to 0. In slave mode, the SBI holds the SCL line low while
the PIN bit is 0.
Note:
The user can only use a DMA transfer:
- when there is only one master and only one slave on the I2C bus; and
- continuous transmission or reception is possible.
SCL
1
2
3
4
5
6
7
8
SDA
A6
A5
A4
A3
A2
A1
A0
R/ W
START Condition
Slave Address + Direction Bit
9
ACK
Acknowledgment
from slave
PIN Bit
INTS2 Interrupt
Request
Master to Slave
Slave to Master
Figure 14.13 Generation of a START Condition and a Slave Address
14.6.3
Transferring a Data Word
Each time a data word has been transmitted or received, the INTS2 interrupt is generated. It is the
responsibility of the INTS2 interrupt service routine to test the MST bit in the SBI0CR to determine
whether the SBI is in master or slave mode.
(1) Master Mode (SBI0CR2.MST = 1)
If the MST bit in the SBI0CR2 is set, then test the TRX bit in the same register to determine
whether the SBI is in master-transmitter or master-receiver mode.
Master-Transmitter Mode (SBI0CR2.TRX = 1)
Test the LRB bit in the SBI0SR. If the LRB bit is set, that means the slave-receiver requires no
further data to be sent from the master-transmitter. The master-transmitter must then generate a
STOP condition as described later to stop transmission.
If the LRB bit is cleared, that means the slave-receiver requires further data. If the number of
bits per transfer is 8, then write the transmit data into the SBI0DBR. When using other data length,
program the BC[2:0] and ACK bits in the SBI0CR1, and then write the transmit data into the
SBI0DBR. When the SBI0DBR is loaded, the PIN bit in the SBI0SR is set to 1, and the transmit
data is shifted out from the SDA pin, clocked by the SCL clock. Once the transfer is complete, the
INTS2 interrupt is generated, the PIN bit is cleared, and the SCL line is pulled low. To transmit
further data, test the LRB bit again and repeat the above procedure.
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INTS2 interrupt
if MST = 0
Then go to slave-mode processing
if TRX = 0
Then go to receiver-mode processing
if LRB = 0
Then go to processing for generating a STOP condition
Set number of bits to be transmitted and specify whether
SBI0DBR ← X X X X X X X X
ACK is required.
Load the transmit data.
SBI0DBR
End of interrupt processing
X = Don’t care
SCL Pin
1
2
3
4
5
6
7
8
D7
D6
D5
D4
D3
D2
D1
D0
9
Write to SBI0DBR
SDA Pin
ACK
Acknowledgement
signal from receiver
PIN Bit
INTS2 Interrupt
Request
Master to Slave
Slave to Master
Figure 14.14 SBI0CR1.BC[2:0] = 000 and SBI0CR1.ACK = 1 (Master-Transmitter Mode)
Master-Receiver Mode (SBI0CR2.TRX = 0)
If the number of bits per transfer is 8, read the SBI0DBR. When using other data length,
program the BC[2:0] and ACK bits in the SBI0CR1, and then read the SBI0DBR. The first read of
the SBI0DBR is a dummy read because data has not yet been received. A dummy read returns an
undefined value. Upon this read, the SCL line is released, the PIN bit in the SBI0SR is set, and the
SCL clock is driven out to receive a data word into the SBI0DBR. The master-transmitter
generates an acknowledgement signal (i.e., a low level) on the SDA line following the last received
bit.
Read of the received data.
SCL
1
2
3
4
5
6
7
8
SDA
D7
D6
D5
D4
D3
D2
D1
D0
9
Next D7
ACK
Acknowledgement
signal to transmitter
PIN Bit
INTS2 Interrupt
Request
Master to Slave
Slave to Master
Figure 14.15 SBI0CR1.BC[2:0] = 000 and SBI0CR1.ACK = 1 (Master-Receiver Mode)
To prepare to terminate the data transfer, the master-receiver must clear the ACK bit in the
SBI0CR1 immediately before the read of the second to last data word. This causes an
acknowledge clock pulse not to be generated on the last data word.
When the transfer is complete, the INTS2 interrupt is generated. After interrupt processing, the
INTS2 interrupt handler must set the BC[2:0] field in the SBI0CR1 to 001 and read the SBI0DBR,
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so that a clock is generated on the SCL line once. With the ACK bit cleared, the master-receiver
holds the SDA line high, which signals the end of transfer to the slave-transmitter.
Then, the SBI generates the INTS2 interrupt again, whereupon the INTS2 interrupt service
routine must generate a STOP condition to stop communication via the I2C bus.
SCL 9
SDA
1
2
3
4
5
6
7
8
D7
D6
D5
D4
D3
D2
D1
D0
1
Negative acknowledge
(high) to transmitter
PIN Bit
INTS2 Interrupt
Request
Read out the received data
after setting the
SBI0CR1.BC[2:0] field to 001.
Read out the received data after clearing the SBI0CR1.ACK bit.
Master to Slave
Slave to Master
Figure 14.16 Terminating Data Transmission in Master-Receiver Mode
Example: When receiving N data words
INTS2 interrupt (after data transmission)
7 6 5 4 3 2 1 0
SBI0CR1 ← X X X X 0 X X X
Reg.
← SBI0DBR
End of interrupt
Set the number of bits to be received and specify whether
ACK is required.
Dummy read
INTS2 interrupt (first to (N-2)th data reception)
7 6 5 4 3 2 1 0
Reg.
← SBI0DBR
End of interrupt
Read the first to (N-2)th data words.
INTS2 interrupt ((N-1)th data reception)
7 6 5 4 3 2 1 0
SBI0CR1 ← X X X 0 0 X X X
Reg.
← SBI0DBR
End of interrupt
Disable generation of acknowledgement clock.
Read the (N-1)th data word.
INTS2 interrupt (Nth data reception)
7 6 5 4 3 2 1 0
SBI0CR1 ← 0 0 1 0 0 X X X
Reg.
← SBI0DBR
End of interrupt
Generate a clock once.
Read the Nth data word.
INTS2 interrupt (after completing data reception)
7 6 5 4 3 2 1 0
SBI0CR1 ← 0 0 1 0 0 X X X
Reg.
← SBI0DBR
End of interrupt
Generate a clock once.
Read the Nth data word.
X = Don’t care
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(2) Slave Mode (SBI0CR2.MST = 0)
If the MST bit in the SBI0CR2 is cleared, the SBI is in slave mode. In slave mode, the SBI
generates the INTS2 interrupt on four occasions: 1) when the SBI has received any slave address;
2) when the SBI has received a general-call address; 3) when the received slave address matches its
own address in the I2C0AR; and 4) when a data transfer has been completed in response to a
general-call.
Also, if the SBI, as a master, loses arbitration for the I2C bus, it switches to slave mode. If
arbitration is lost during a data transfer, SCL continues to be generated until the data word is
complete; then the INTS2 interrupt is generated.
When the INTS2 interrupt occurs, the PIN bit in the SBI0SR is cleared, and the SCL line is
pulled low. When the SBI0DBR is read or written or when the PIN bit is set back to 1, the SCL
line is released after a period of tLOW.
Processing to be done in slave mode varies, depending on whether or not the SBI has switched
over to slave mode as a result of lost arbitration.
Test the AL, TRX, AAS and AD0 bits in the SBI0SR to determine the processing required, as
summarized in Table 14.2.
Example: When the received slave address matches the SBI’s own address and the data direction
( R / W ) bit is 1
INTS2 interrupt
if TRX = 0
Then go to other processing
if AL = 1
Then go to other processing
if AAS = 0
Then go to other processing
SBI0CR1 ← X X X 1 0 X X X
SBI0DBR ← X X X X 0 X X X
Set the number of bits to be transmitted.
Load the transmit data.
X = Don’t care
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Table 14.2 Processing in Slave Mode
TRX
AL
1
1
1
0
0
1
0
14.6.4
AAS AD0
State
Processing
0
Arbitration was lost while the slave address
was being transmitted, and the SBI
received a slave address with the direction
bit set transmitted by another master.
Set the SBI0CR1.BC[2:0] field to the
number of bits in a data word and write the
transmit data into the SBI0DBR.
1
0
In slave-receiver mode, the SBI received a
slave address with the direction bit set
transmitted by the master.
0
0
In slave-transmitter mode, the SBI has
Test the SBI0SR.LRB bit. If the LRB bit is
completed a transmission of one data word. set, that means the master-receiver does
not require further data. Set the
SBI0CR2.PIN bit to 1 and clear the TRX bit
to 0 to release the bus.
If the LRB bit is cleared, that means the
master-receiver requires further data. Set
the SBI0CR1.BC[2:0] field to the number of
bits in the data word and write the transmit
data to the SBI0DBR.
1
1/0
Read the SBI0DBR (a dummy read) to set
Arbitration was lost while a slave address
was being transmitted, and received either a the SBI0CR2.PIN bit to 1, or write a 1 to
slave address with the direction bit cleared this bit.
or a general-call address transmitted by
another master.
0
0
Arbitration was lost while a slave address
or a data word was being transmitted, and
the transfer terminated.
1
1/0
In slave-receiver mode, the SBI received
either a slave address with the direction bit
cleared or a general-call address
transmitted by the master.
0
1/0
In slave-receiver mode, the SBI has
completed a reception of a data word.
Set the SBI0CR1.BC[2:0] field to the
number of bits in the data word and read
the received data from the SBI0DBR.
Generating a STOP Condition
When the SBI0SR.BB bit is set, setting the MST, TRX and PIN bits in the SBI0CR2 to 1 and
clearing the BB bit in the same register causes the SBI to start a sequence for generating a STOP
condition on the I2C bus. Do not alter the contents of these bits until the STOP condition is present on
the bus.
If another device is holding down the SCL bus line, the SBI waits until the SCL line is released
(high) again; when SCL is high, the SBI drives the SDA pin high to generate a STOP condition.
7 6 5 4 3 2 1 0
SBI0CR2 ← 1 1 0 1 1 0 0 0
Generate a STOP condition.
1 → MST
1 → TRX
0 → BB
1 → PIN
STOP Condition
SCL Pin
SDA Pin
PIN Bit
BB Bit (read)
Figure 14.17 Generating a STOP Condition
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14.6.5
Repeated START Condition
A data transfer is always terminated by a STOP condition. However, if a master still wishes to
communicate on the bus, it can generate a repeated START condition and address another slave or
change the data direction without first generating a STOP condition. The following describes the steps
required to generate a repeated START condition.
First, clear the MST, TRX and BB bits in the SBI0CR2 and set the PIN bit in the same register to
release the bus. This causes the SDA pin to be held high and the SCL pin to be released. Because no
STOP condition is generated on the bus, other devices think that the bus is busy.
Then, poll the SBI0SR.BB bit until it is cleared to ensure that the SCL pin is released. Next, poll the
LRB bit until it is set to ensure that no other device is pulling the SCL bus line low. Once the bus is
determined to be free this way, use the steps described in Section 14.6.2 to generate a START
condition.
To satisfy the minimum setup time of the START condition, in Standard-mode, at least 4.7-µs wait
period must be created by software after the bus becomes free.
7 6 5 4 3 2 1 0
SBI0CR2 ← 0 0 0 1 1 0 0 0
if SBI0SR<BB> ≠ 0
Then
if SBI0SR<LRB> ≠ 1
Then
Release the bus.
Check that the SCL pin is released.
Check that no other device is pulling the SCL line low.
4.7-µs Wait
SBI0CR1 ← X X X 1 0 X X X
SBI0DBR ← X X X X X X X X
SBI0CR2 ← 1 1 1 1 1 0 0 0
Select Acknowledge mode.
Load a slave address and the direction bit.
Generate a START condition.
X = Don’t care
0 → MST
0 → TRX
0 → BB
1 → PIN
1 → MST
1 → TRX
1 → BB
1 → PIN
4.7 µs (min)
START Condition
SCL Bus Line
SCL Pin
9
SDA Pin
LRB Bit
BB Bit
PIN Bit
Figure 14.18 Repeated START Condition
TMP1941AF-211
2003-03-27
TMP1941AF
14.7 Description of Registers Used in Clock-Synchronous 8-Bit SIO Mode
This section provides a summary of the registers which control clock-synchronous 8-bit SIO operation and
provides its status information for monitoring.
Serial Bus Interface Control Register 1
SBI0CR1
(0xFFFF_F240)
Name
7
6
SIOS
SIOINH
Read/Write
Reset Value
4
3
2
SIOM1
SIOM0

SCK2

W
0
0
Start
transfer
0: Stop
1: Start
Function
5
0
Abort
transfer
0: Continue
1: Abort
0
SCK1
SCK0
W

0
1
0
R/W
0
1
Serial clock frequency / Software
reset monitor
Transfer mode
00: Transmit mode
01: Reserved
10: Transmit/Receive
mode
11: Receive mode
On writes: SCK[2:0] = Serial clock frequency
n=3
1.25 MHz
n=4
625 kHz
n = 5 312.5 kHz
n = 6 156.3 kHz
n = 7 78.13 kHz
n = 8 39.06 kHz
n = 9 19.53 kHz
 External clock
000
001
010
011
100
101
110
111
Note:
Assumptions:
System clock: fc (= 40 MHz)
Clock gear: fc/1
φT0 = fperiph/4 (= 10 MHz)
φT0
Frequency = n (Hz)
2
Clear the SIOS bit and set the SIOINH bit before programming the transfer mode and serial
clock frequency bits.
Serial Bus Interface Data Buffer Register
SBI0DBR
(0xFFFF_F241)
Name
7
6
5
4
3
2
1
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Read/Write
R (receive)/ W (transmit)
Reset Value
Undefined
Figure 14.19 SIO Mode Registers (1)
TMP1941AF-212
2003-03-27
TMP1941AF
Serial Bus Interface Control Register 2
SBI0CR2
(0xFFFF_F243)
7
6
5
4
3
Name




SBIM1
Read/Write




Reset Value




2
SBIM0
0






2
1
0
SEF


W
0
1
0
SBI operating mode
00: Port mode
01: Clock-Synchronous
8-Bit SIO mode
10: I2C Bus mode
11: Reserved
Function
Serial Bus Interface Register
SBI0SR
(0xFFFF_F243)
7
6
5
4
3
Name




SIOF
Read/Write




Reset Value




R
0
Serial
transfer
status
Function
0




Shift
operation
status
0: Terminated
1: In progress
Serial Bus Interface Baud Rate Register 0
SBI0BR0
(0xFFFF_F244)
7
6
5
4
3
2
1
0
Name

I2SBI0






Read/Write

R/W





W
Reset Value

0





Must be
written as
0.
IDLE
0: Off
1: On
Function
Serial Bus Interface Baud Rate Register 1
SBI0BR1
(0xFFFF_F245)
7
6
5
4
3
2
1
0
P4EN







Read/Write
R/W







Reset Value
0






Name
Function

Must be
written as
0.
Internal
clock
0: Off
1: On
Figure 14.20 SIO Mode Registers (2)
TMP1941AF-213
2003-03-27
TMP1941AF
14.8 Clock-Synchronous 8-Bit SIO Mode Operation
14.8.1
Serial Clock
(1) Clock Source
The clock source for the SIO mode can be selected from internal and external clocks through the
programming of the SCK[2:0] field in the SBI0CR1.
•
Internal clocks
One of the seven internal clocks can be used as a serial clock, which is driven onto the
SCK pin. At the beginning of a transfer, the SCK clock will start out at logic high.
If software is slow and the reading of the received data or the writing of the transmit data
can not keep up with the serial clock rate, the SBI automatically inserts a wait period, as
shown below. During this period, the serial clock is temporarily stopped to suspend a shift
operation.
Automatically inserted wait period
SCK Output
SO Output
Writes of the
transmit data
1
2
3
7
8
1
a0
a1
a2 a5
a6
a7
b0
a
b
2
b1 b4
6
7
8
1
2
3
b5
b6
b7
c0
c1
c2
c
Figure 14.21 Automatic Wait Insertion
•
External clock (SBI0CR1.SCK[2:0] = 111)
If the SCK[2:0] field in the SBI0CR1 contains 111, the SBI uses an external clock supplied
from the SCK pin as a serial clock. For proper shift operations, the clock high width and the
clock low width must satisfy the following relationship.
SCK Pin
tSCKL tSCKH
tSCKL, tSCKH > 8/fsys
Figure 14.22 Maximum External Clock Frequency
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2003-03-27
TMP1941AF
(2) Shift Edge Types
In transmit mode, leading-edge shift is used. In receive mode, trailing-edge shift is used.
•
Leading-edge shift
Every bit of SIO data is shifted by the leading edge of the serial clock (falling edge of
SCK).
•
Trailing-edge shift
Every bit of SIO data is shifted by the trailing edge of the serial clock (rising edge of
SCK).
SCK Pin
SO Pin
Shift Register
bit 0
bit 1
bit 2
bit 3
76543210 *7654321 **765432 ***76543
bit 4
bit 5
bit 6
bit 7
****7654
*****765
******76
******7
bit 4
bit 5
bit 6
bit 7
(a) Leading-Edge Shift
SCK Pin
SI Pin
Shift Register
bit 0
********
bit 1
0*******
bit 2
10******
bit 3
210*****
3210****
43210***
543210** 6543210* 76543210
(b) Trailing-Edge Shift
Figure 14.23 Shift Edge Types
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2003-03-27
TMP1941AF
14.8.2
SIO Transfer Modes
The SBI supports three SIO transfer modes: receive mode, transmit mode and transmit/receive mode.
The SIOM[1:0] field in the SBI0CR1 is used to select a transfer mode.
(1) 8-Bit Transmit Mode
Configure the SIO interface in transmit mode and write the transmit data into the SBI0DBR.
Then setting the SIOS bit in the SBI0CR1 initiates a transmission. The contents of the SBI0DBR is
moved to an internal shift register and then shifted out on the SO pin, with the least-significant bit
(LSB) first, synchronous to the serial clock. Once the transmit data is transferred to the shift
register, the SBI0DBR becomes empty, and the buffer-empty interrupt (INTS2) is generated.
In internal clock mode, the SIO interface will be in wait state (SCK will stop) until the INTS2
interrupt service routine provides the next transmit data to the SBI0DBR. Once the SBI0DBR is
loaded, the SIO interface will automatically get out of the wait state.
In external clock mode, the INTS2 interrupt service routine must provide the next transmit data
to the SBI0DBR before the previous transmit data has been shifted out. Therefore, the data rate is a
function of the maximum latency between when the INTS2 interrupt is generated and when the
SBI0DBR is loaded by the interrupt service routine.
At the beginning of a transmission, the value of the last bit of the previously transmitted byte
appears on the SO pin between when the SBI0SR.SIOF bit is set and when SCK subsequently goes
low.
Transmission can be terminated by the INTS2 interrupt service routine clearing the SIOS bit to 0
or setting the SIOINH bit to 1. If the SIOS bit is cleared, the remaining bits in the SBI0DBR
continue to be shifted out before transmission ends. In this case, software can check the
SBI0SR.SIOF bit to determine whether transmission has come to an end (0 = end-of-transmission).
If the SIOINH bit is set, the ongoing transmission is aborted immediately, and the SIOF bit is
cleared at that point.
In external clock mode, the SIOS bit must be cleared before the SIO interface begins shifting out
the next transmit data. Otherwise, the SIO will stop after sending out dummy data.
7 6 5 4 3 2 1 0
SBI0CR1 ← 0 1 0 0 0 X X X
Select transmit mode.
SBI0DBR ← X X X X X X X X
SBI0CR1 ← 1 0 0 0 0 X X X
Write the transmit data.
Start transmission.
INTS2 interrupt
SBI0DBR ← X X X X X X X X
Write the next transmit data.
TMP1941AF-216
2003-03-27
TMP1941AF
The SIOS bit is cleared.
SIOS Bit
SIOF Bit
SEF Bit
SCK Output
SO Pin
*
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
INTS2 Interrupt Request
a
SBI0DBR
b
Writes of the transmit data
(a) Internal Clock Mode
The SIOS bit is cleared.
SIOS Bit
SIOF Bit
SEF Bit
SCK Input
SO Pin
*
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
INTS2 Interrupt Request
a
SBI0DBR
b
Writes of the transmit data
(b) External Clock Mode
Figure 14.24 Transmit Mode
Example: MIP16 code to terminate transmission by SIOS (external clock mode)
STEST1
STEST2
ADDIU
: LB
AND
BNEZ
ADDIU
: LB
AND
BEQZ
ADDIU
STB
r3, r0, 0x04
r2,(SBI0SR)
r2, r3
r2, STEST1
r3, r0, 0x20
r2, (PA)
r2, r3
r2, STEST2
r3, r0, 0x00000111
r3, (SBI0CR1)
TMP1941AF-217
; If SBI0SR.SEF = 1 then loop
; If SCK = 0 then loop
; SIOS ← 0
2003-03-27
TMP1941AF
SCK Pin
SIOF Bit
SO Pin
bit 6
bit 7
tSODH = 3.5 / fsys /2 seconds (min.)
Figure 14.25 Retention Time of the Last Transmitted Bit
(2) 8-Bit Receive Mode
Configure the SIO interface in receive mode. Then setting the SIOS bit in the SBI0CR1 enables
reception. The receive data is clocked into the internal shift register via the SI pin, synchronous to
the serial clock. Once the shift register is fully loaded, the received byte is transferred to the
SBI0DBR, and the buffer-full interrupt (INTS2) is generated. The INTS2 interrupt service routine
must then pick up the received data from the SBI0DBR.
In internal clock mode, the SIO interface will be in wait state (SCK will stop) until the INTS2
interrupt service routine reads the data from the SBI0DBR.
In external clock mode, shift operations continue, synchronous to the external clock. In this
mode, the maximum data rate is a function of the maximum latency between when the INTS2
interrupt is generated and when the SBI0DBR is read by the interrupt service routine.
Reception can be terminated by the INTS2 interrupt service routine clearing the SIOS bit to 0 or
setting the SIOINH bit to 1. If the SIOS bit is cleared, reception continues until the shift register is
fully loaded and transferred to the SBI0DBR. In this case, software can check the SBI0SR.SIOF
bit to determine whether reception has come to an end (0 = end-of-reception). If the SIOINH bit is
set, the ongoing reception is aborted immediately, and the SIOF bit is cleared at that point. (The
received data becomes invalid; there is no need to read it out.)
Note:
The contents of the SBI0DBR is not preserved after changing the transfer mode. Before
changing the transfer mode, clear the SIOS bit to complete the ongoing reception and have
the INTS2 interrupt service routine pick up the last received data.
7 6 5 4 3 2 1 0
SBI0CR1 ← 0 1 1 1 0 X X X
Select receive mode.
SBI0CR1 ← 1 0 1 1 0 0 0 0
Start reception.
INTS2 interrupt
Reg.
← SBI0DBR
Read the received data.
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2003-03-27
TMP1941AF
The SIOS bit is cleared.
SIOS Bit
SIOF Bit
SEF Bit
SCK Output
a0
SI Pin
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
IINTS2 Interrupt
Request
a
SBI0DBR
Read of the received data
b
Read of the received data
Figure 14.26 Receive Mode (Internal Clock Mode)
(3) 8-Bit Transmit/Receive Mode
Configure the SIO interface in transmit/receive mode and write the transmit data into the
SBI0DBR. Then setting the SIOS bit in the SBI0CR1 initiates transmission and reception. The
transmit data is shifted out through the SO pin, with the least-significant bit (LSB) first, with the
falling edge of the serial clock, while at the same time the receive data is shifted in through the SI
pin with the rising edge of the serial clock. Once the shift register is fully loaded with eight bits of
the received data, it is transferred to the SBI0DBR, and the INTS2 interrupt is generated. The
INTS2 interrupt service routine must then pick up the received data from the SBI0DBR and writes
the next transmit data into the SBI0DBR. Because the SBI0DBR is shared between transmit and
receive operations, the received data must be read before the next transmit data is written.
In internal clock mode, the SIO interface will be in wait state (SCK will stop) after a read of the
received data until a write of the transmit data.
In external clock mode, shift operations continue, synchronous to the external clock. Therefore,
software must read the received data and write the transmit data before the next shift operation
begins. In this mode, the maximum data rate is a function of the maximum latency between when
the INTS2 interrupt is generated and when the interrupt service routine reads the received data and
writes the transmit data.
At the beginning of a transmission, the value of the last bit of the previously transmitted byte
appears on the SO pin between when the SBI0SR.SIOF bit is set and when SCK subsequently goes
low.
Transmission/reception can be terminated by the INTS2 interrupt service routine clearing the
SIOS bit to 0 or setting the SIOINH bit to 1. If the SIOS bit is cleared, reception continues until the
shift register is fully loaded and transferred to the SBI0DBR. In this case, software can check the
SBI0SR.SIOF bit to determine whether transmission/reception has come to an end (0 = end-ofreception/transmission). If the SIOINH bit is set, the ongoing transmission/reception is aborted
immediately, and the SIOF bit is cleared at that point.
Note:
The contents of the SBI0DBR is not preserved after changing the transfer mode. Before
changing the transfer mode, clear the SIOS bit to complete the ongoing
transmission/reception and have the INTS2 interrupt service routine pick up the last
received data.
TMP1941AF-219
2003-03-27
TMP1941AF
The SIOS bit is cleared.
SIOS Bit
SIOF Bit
SEF Bit
SCK Output
SO Pin
*
SI Pin
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
c0
c1
c2
c3
c4
c5
c6
c7
d0
d1
d2
d3
d4
d5
d6
d7
IINTS2 Interrupt
Request
a
SBI0DBR
c
b
(c) Read of the (b) Write of the
received data transmit data
(a) Write of the transmit data
d
(d) Read of the
received data
Figure 14.27 Receive/Transmit Mode (Internal Clock Mode)
SCK Pin
SIOF Bit
SO Pin
bit 6
Bit 7 of the last byte transmitted
tSODH = 4/fsys/2 seconds (min.)
Figure 14.28 Retention Time of the Transmit Data in Receive/Transmit Mode
7 6 5 4 3 2 1 0
SBI0CR1 ← 0 1 1 0 0 X X X
Select receive/transmit mode.
SBI0DBR ← X X X X X X X X
SBI0CR1 ← 1 0 1 0 0 X X X
Write the transmit data.
Start reception/transmission.
INTS2 interrupt
← SBI0DBR
SBI0DBR ← X X X X X X X X
Reg.
Read the received data.
Write the transmit data.
TMP1941AF-220
2003-03-27
TMP1941AF
15. Analog-to-Digital Converter (ADC)
The TMP1941AF has a 8-channel, multiplexed-input, 10-bit successive-approximation ananlog-to-digital
converter (ADC).
Figure 15.1 shows a block diagram of the ADC. The eight analog input channels (AN0–AN7) can be used as
general-purpose digital inputs (Port 5) if not needed as analog channels.
Note:
Ensure that the ADC has halted before executing an insturction to place the TMP1941AF in IDLE, SLEEP
or STOP mode to reduce power supply current. Otherwise, the TMP1941AF might go into a standby
mode while the internal analog comparator is still active. In SLOW mode, the ADC must be disabled.
Internal Data Bus
Internal Data Bus
A/D Mode Control Register 1
(ADMOD1)
ADTRGE
ADCH[2:0]
VREFON
Internal Data Bus
A/D Mode Control Register 0 (ADMOD0)
EOCF
ADBF
ITM0
REPEAT SCAN ADS
scan
Channel Selection
Control Circuit
repeat
interrupt
ADTRG
busy
end
start
A/D Converter Control
Circuit
Interrupt
Request
(INTAD)
AN7 (P57)
AN5 (P55)
AN4 (P54)
AN3/ ADTRG (P53)
Multiplexer
AN6 (P56)
Sample-andHold
+
−
AN2 (P52)
AN1 (P51)
Comparator
AN0 (P50)
VREFH
A/D Conversion
Result Registers
(ADREG04L–37L)
(ADREG04H–37H)
D/A Converter
VREFL
Figure 15.1 ADC Block Diagram
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2003-03-27
TMP1941AF
15.1 Register Description
The ADC has two mode control registers (ADMOD0 and ADMOD1), four conversion result high/low
register pairs (ADREG04H/L, ADREG15H/L, ADREG26H/L, ADREG37H/L) and a clock select register
(ADCCLK). The conversion result registers contain the digital values of completed conversions. The clock
select register selects an A/D conversion clock.
Figure 15.2 to Figure 15.6 show the registers available in the ADC.
A/D Mode Control Register 0
7
Name
ADMOD0
(0xFFFF_F310) Read/Write
Reset Value
EOCF
5
4
3
ADBF


ITM0
R
0
End-ofconversion
flag
Function
6
2
1
0
REPEAT
SCAN
ADS
R/W
0
0
A/D
conversion
busy flag
0: Before or 0: Idle
during
1: During
conversion conversion
1: Completed
0
0
0
Must be
Must be
Interrupt
Continuous
written as 0. written as 0. See below. conversion
mode
0: Single
1: Continuous
0
0
Channel
scan mode
0: Fixedchannel
1: Channel
scan
A/D
conversion
start
0: Don’t
care
1: Start
This bit is
always read
as 0.
Interrupt in fixed-channel continuous conversion mode
Fixed-Channel Continuous Conversion Mode
SCAN = 0, REPEAT = 1
Note:
0
Generates INTAD interrupt when a single
conversion has been completed.
1
Generates INTAD interrupt when a sequence
of four conversions has been completed.
The EOCF bit is cleared when read.
Figure 15.2 A/D Mode Control Register 0 (ADMOD0)
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2003-03-27
TMP1941AF
A/D Mode Control Register 1
Name
ADMOD1
(0xFFFF_F311) Read/Write
Reset Value
Function
7
6
5
4
3
2
1
0
VREFON
I2AD


ADTRGE
ADCH2
ADCH1
ADCH0
R/W
R/W


0


0
0
0
VREF
control
0: Off
1: On
R/W
0
0
Analog input channel select
External
conversion
trigger
0: Disable
1: Enable
ADC
operation
in IDLE
mode
0: Off
1: On
Analog Input Channel Select
SCAN
ADCH[2:0]
0
Fixed-Channel Mode
1
Channel Scan Mode
000
AN0
AN0
001
AN1
AN0→AN1
010
AN2
AN0→AN1→AN2
011 (Note)
AN3
AN0→AN1→AN2→AN3
100
AN4
AN4
101
AN5
AN4→AN5
110
AN6
AN4→AN5→AN6
111
AN7
AN4→AN5→AN6→AN7
A/D external conversion trigger ( ADTRG input)
0
Disable
1
Enable
Note 1: Set the VREFON bit to 1 before setting the ADS bit in the ADMOD0 to start a conversion.
Note 2: The AN3 pin is shared with the ADTRG pin. Therefore, when the external conversion trigger
input ( ADTRG ) is enabled (i.e., when ADMOD1.ADTRGE = 1), the ADCH[2:0] field must not be
programmed to 011.
Figure 15.3 A/D Mode Control Register (ADMOD1)
TMP1941AF-223
2003-03-27
TMP1941AF
A/D Conversion Result Low Register 0/4
Name
ADREG04L
(0xFFFF_F300) Read/Write
7
6
5
4
3
2
1
0
ADR01
ADR00





ADR0RF
R





R
Undefined





Reset Value
Function
0
Lower 2 bits of an A/D
conversion result
Conversion
result store
flag
1: Stored
A/D Conversion Result High Register 0/4
Name
ADREG04H
(0xFFFF_F301) Read/Write
7
6
5
4
3
2
1
0
ADR09
ADR08
ADR07
ADR06
ADR05
ADR04
ADR03
ADR02
R
Reset Value
Undefined
Function
Upper 8 bits of an A/D conversion result
A/D Conversion Result Low Register 1/5
7
Name
ADREG15L
(0xFFFF_F302) Read/Write
Function
5
4
3
2
1
0
ADR10





ADR1RF
R





R
Undefined





ADR11
Reset Value
6
0
Lower 2 bits of an A/D
conversion result
Conversion
result store
flag
1: Stored
A/D Conversion Result High Register 1/5
Name
ADREG15H
(0xFFFF_F303) Read/Write
7
6
5
4
ADR19
ADR18
ADR17
ADR16
3
2
1
0
ADR15
ADR14
ADR13
ADR12
R
Reset Value
Undefined
Function
Upper 8 bits of an A/D conversion result
9
8
7
6
5
4
3
2
1
0
Channel x conversion result bits
ADREGxH
7 6 5
4
3
2
1
0
7
6
5
4
3
ADREGxL
2 1 0
Note 1: Bits 5–1 are always read as 1s.
Note 2: Bit 0 (ADRxRF), when set, indicates that the conversion result has been stored in the
ADREGxH/L register pair. This bit is cleared when either the ADREGxH or the ADREGxL is read.
Figure 15.4 A/D Convesion Result High/Low Registers (1)
TMP1941AF-224
2003-03-27
TMP1941AF
A/D Conversion Result Low Register 2/6
Name
ADREG26L
(0xFFFF_F304) Read/Write
7
6
5
4
3
2
1
0
ADR21
ADR20





ADR2RF
R





R
Undefined





Reset Value
0
Lower 2 bits of an A/D
conversion result
Function
Conversion
result store
flag
1: Stored
A/D Conversion Result High Register 2/6
Name
ADREG26H
(0xFFFF_F305) Read/Write
7
6
5
4
3
2
1
0
ADR29
ADR28
ADR27
ADR26
ADR25
ADR24
ADR23
ADR22
0
R
Reset Value
Undefined
Function
Upper 8 bits of an A/D conversion result
A/D Conversion Result Low Register 3/7
7
Name
ADREG37L
(0xFFFF_F306) Read/Write
5
4
3
2
1
ADR30





R





Undefined





ADR31
Reset Value
6
ADR3RF
R
0
Lower 2 bits of an AD
conversion result
Function
Conversion
result store
flag
1: Stored
A/D Conversion Result High Register 3/7
Name
ADREG37H
(0xFFFF_F307) Read/Write
7
6
5
4
ADR39
ADR38
ADR37
ADR36
3
2
1
0
ADR35
ADR34
ADR33
ADR32
R
Reset Value
Undefined
Function
Upper 8 bits of A/D conversion result
9
8
7
6
5
4
3
2
1
0
Channel x conversion result bits
ADREGxH
7 6 5
4
3
2
1
0
7
6
5
4
3
ADREGxL
2 1 0
Note 1
Bits 5–1 are always read as 1s.
Note 2
Bit 0 (ADRxRF), when set, indicates that the conversion result has been stored in the
ADREGxH/L register pair. This bit is cleared when either the ADREGxH or the ADREGxL is read.
Figure 15.5 A/D Conversion Result High/Low Registers (2)
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A/D Conversion Clock Select Register
Name
ADCCLK
(0xFFFF_EE04) Read/Write
Reset Value
7
6
5
4
3
2
1
0






ADCCK1
ADCCK0






R/W
R/W






0
0
Function
A/D conversion clock
(fadc) select
00: fsys/2
01: fsys/4
10: fsys/8
11: Reserved
Note 1: The ADC operates off the selected A/D conversion clock, which must be selected from Table
15.3, Conversion Time, to assure conversion accuracy.
Note 2: Programming the ADCCLK register should only be attempted when an A/D conversion is not in
progress.
Figure 15.6 A/D Conversion Clock Select Register (ADCCLK)
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15.2 Operation
15.2.1
Analog Reference Voltages
The VREFH and VREFL pins provide the reference voltages for the ADC. These pins estabilish the
full-scale range for the internal resistor string, which divides the range into 1024 steps. The digital result
of the conversion is derived by comparing the sampled analog input voltage to the resistor string
voltages.
Clearing the VREFON bit in the ADMOD1 turns off the switch between VREFH and VREFL. Once
the VREFON bit is cleared, the internal reference voltage requires a recovery time of 3 µs to stabilize
after the VREFON bit is again set to 1. This recovery time is independent of the system clock
frequency. The ADS bit in the ADMOD0 must then be set to initiate an conversion.
15.2.2
Selecting an Analog Input Channel (s)
There are two basic conversion modes: fixed-channel mode and channel scan mode. The SCAN bit in
the ADMOD0 affects the conversion channel(s) that will be selected as follows.
•
Fixed-channel mode (ADMOD0.SCAN = 0)
When the SCAN bit in the ADMOD0 is cleared, the ADC runs conversions on a single input
channel selected from AN0–AN7 via the ADCH[2:0] field in the ADMOD1.
•
Channel scan mode (ADMOD0.SCAN = 1)
When the SCAN bit in the ADMOD0 is set, the ADC runs conversions on sequential channels in
a specific group selected via the ADCH[2:0] field in the ADMOD1.
Refer to Table 15.1. After a reset, the ADMOD0.SCAN bit defaults to 0, and the
ADMOD1.ADCH[2:0] field defaults to 000. Thus, the AN0 pin is selected as the conversion channel.
The AN0–AN7 pins can be used as general-purpose input ports if not used as analog input channels.
Table 15.1 Analog Input Channel Selection
15.2.3
ADMOD1.ADCH[2:0]
Fixed-Channel Mode
ADMOD1.SCAN = 0
Channel Scan Mode
ADMOD0.SCAN = 1
000
AN0
AN0
001
AN1
AN0→AN1
010
AN2
AN0→AN1→AN2
011
AN3
AN0→AN1→AN2→AN3
100
AN4
AN4
101
AN5
AN4→AN5
110
AN6
AN4→AN5→AN6
111
AN7
AN4→AN5→AN6→AN7
Starting an A/D Conversion
The ADC initiates a conversion or a sequence of conversions when the ADS bit in the ADMOD0 is
set, or when a falling edge is applied to the ADTRG pin if the ADTRGE bit in the ADMOD1 is set.
When a conversion starts, the Busy flag (ADMOD0.ADBF) is set.
Writing a 1 to the ADS bit causes the ADC to abort any ongoing conversion and start sampling the
selected channel to begin a new conversion. The Conversion Result Store flag (ADREGxL.ADRxRF)
indicates whether the result register contains a valid digital result at that point.
In external conversion trigger mode, a falling edge on the ADTRG pin is ignored while a conversion
is in progress.
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15.2.4
Conversion Modes and Conversion-Done Interrupts
The ADC supports the following four conversion modes:
•
Fixed-channel single conversion mode
•
Channel scan single conversion mode
•
Fixed-channel continuous conversion mode
•
Channel scan continuous conversion mode
The REPEAT and SCAN bits in the ADMOD1 select the conversion mode.
The ADC generates the INTAD interrupt and sets the EOCF bit in the ADMOD0 at the end of the
conversion process.
•
Fixed-Channel Single Conversion Mode
This mode is selected by programming the REPEAT and SCAN bits in the ADMOD0 to 00. In
this mode, the ADC performs a single conversion on a single selected channel. When a conversion
is completed, the ADC sets the ADMOD0.EOCF bit, clears the ADMOD0.ADBF bit and generates
the INTAD interrupt.
•
Channel Scan Single Conversion Mode
This mode is selected by programming the REPEAT and SCAN bits in the ADMOD0 to 01. In
this mode, the ADC performs a single conversion on each of a selected group of channels. When a
single conversion sequence is completed, the ADC sets the ADMOD0.EOCF bit, clears the
ADMOD0.ADBF bit and generates the INTAD interrupt.
•
Fixed-Channel Continuous Conversion Mode
This mode is selected by programming the REPEAT and SCAN bits in the ADMOD0 to 10. In
this mode, the ADC repeatedly converts a single selected channel. When a conversion process is
completed, the ADC sets the ADMOD.EOCF bit. The ADMOD0.ADBF bit remains set.
The ITM0 bit in the ADMOD0 controls interrupt generation in this mode. If the ITM0 bit is
cleared, the ADC generates an interrupt after each conversion. If the ITM0 bit is set, the ADC
generates an interrupt after every four conversions.
•
Channel Scan Continuous Conversion Mode
This mode is selected by programming the REPEAT and SCAN bits in the ADMOD0 to 11. In
this mode, the ADC repeatedly converts the selected group of channels. When a single conversion
sequence is completed, the ADC sets the ADMOD0.EOCF bit and generates the INTAD interrupt.
The ADMOD0.ADBF bit remains set.
In continuous conversion modes, clearing the ADMOD0.REPEAT bit stops the conversion sequence
after the ongoing conversion process is completed.
If the I2AD bit in the ADMOD1 is cleared, putting the TMP1941AF in any standby mode (IDLE,
SLEEP or STOP) causes the ADC to be immediately disabled, even if a conversion is in progress. Once
the TMP1941AF exits the standby mode, the ADC restarts a conversion sequence when in a continuous
conversion mode, but remains inactive when in a single conversion mode.
Table 15.2 summarizes interrupt request generation in each of the conversion modes.
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Table 15.2 Interrupt Request Generation in Each AD Conversion Mode
Interrupt Request
Generation
Mode
ADMOD0
ITM0
REPEAT
SCAN
Fixed-Channel Single
Conversion Mode
After a conversion
X
0
0
Channel Scan Single
Conversion Mode
After a scan conversion
sequence
X
0
1
Fixed-Channel Continuous
Conversion Mode
After each conversion
0
After every four conversions
1
1
0
Channel Scan Continuous
Conversion Mode
After each scan conversion
sequence
X
1
1
X = Don’t care
15.2.5
Conversion Time
The conversion process requires 86 conversion clocks per channel. For example, this results in a
conversion time of 8.6 µs with 10-MHz fadc. The A/D conversion clock can be selected from fsys/2,
fsys/4 and fsys/8 through the programming of the ADCCK[1:0] field in the ADCCLK register. To
assure conversion accuracy, conversion time must be no shorter than 8.6 µs.
Table 15.3 Conversion Time
15.2.6
Conversion Clock
fsys
fsys/2
40 MHz
32 MHz
fsys/4
fsys/8
Don’t use.
8.6 µs
17.2 µs
Don’t use.
10.75 µs
21.5 µs
20 MHz
8.6 µs
17.2 µs
34.4 µs
16 MHz
10.75 µs
21.5 µs
43.0 µs
10 MHz
17.2 µs
34.4 µs
68.8 µs
8 MHz
21.5 µs
43.0 µs
86.0 µs
Storing and Reading the A/D Conversion Result
Conversion results are loaded into conversion result high/low register pairs (ADREG04H/L to
ADREG37H/L). These registers are read-only.
In fixed-channel continuous conversion mode, conversion data goes into the ADREG04H/L to the
ADREG37H/L sequentially. In other modes, channels AN0 and AN4 share the ADREG04H/L;
channels AN1 and AN5 share the ADREG15H/L; channels AN2 and AN6 share the ADREG26H/L;
and channels AN3 and AN7 share the ADREG37H/L.
Table 15.4 shows the relationships between the analog input channels and the A/D conversion result
registers.
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Table 15.4 Relationships Between Analog Input Channels
and A/D Conversion Result Registers
A/D Conversion Result Register
Analog Input Channel
(Port 5)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Fixed-Channel Continuous
Conversion Mode
(for each sequence of four
conversions)
ADREG04H/L
ADREG15H/L
ADREG26H/L
ADREG37H/L
Other Modes
ADREG04H/L
ADREG15H/L
ADREG26H/L
ADREG37H/L
ADREG04H/L
ADREG15H/L
ADREG26H/L
ADREG37H/L
Bit 0 (ADRxRF) in each ADREGxL register indicates whether the conversion result has been read.
This bit is set when the conversion result is loaded into the ADREGxH/L pair, and cleared when either
the ADREGxH or ADREGxL is read.
Reading the conversion result clears the End-of-Conversion flag (ADMOD0.EOCF).
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15.3 Programming Examples
•
Converting the analog input voltage on the AN3 pin to a digital value and storing the converted value in
a memory location (0xFFFF_B800) using an A/D interrupt (INTAD) handler routine
Settings in the main routine
7 6 5
← X X 0
← 1 X X
← X X 0
IMCEHH
ADMOD1
ADMOD0
4
1
X
0
3
0
0
0
2
1
0
0
1
0
1
0
0
0
1
1
Enables INTAD and sets its priority level to 4.
Selects AN3 as the analog input channel.
Starts conversion in fixed-channel single conversion mode.
Interrupt routine processing example
r4
←
r4
> > 6
(FFFFB800H) ←
•
Loads the conversion result into general-purpose register r4 from
ADREG37L and ADREG37H.
Shifts the contents of r4 six bits to the right, padding 0s to the
vacated MSB bits.
Stores the contents of r4 to address 0xFFFF_B800.
ADREG37
r4
Converting the analog input voltages on AN0–AN2 sequentially in channel scan continuous conversion
mode
← X X 0 1 0 0 0 0
← 1 X X X 0 0 1 1
← X X 0 0 0 0 0 1
IMCEHH
ADMOD1
ADMOD0
Disables INTAD.
Selects AN0–AN2 as analog input channels.
Starts conversion in channel scan continuous conversion mode.
X = Don't care
Notes:
The ADC supports both polled and interrupt-driven operation. The CPU can perform polling
operation to detect completion of a conversion.
•
•
•
Don’t poll the ADRxRF bit in the ADREGxxL register.
In single conversion modes, poll the ADBF bit in the ADMOD0.
In any conversion modes, the EOCF bit in the ADMOD0 can be polled. After the EOCF bit is
set, one or two fadc clocks are required as shown below before the ADREGxH/L can be
read.
Conversion Mode
Time Required Before Reading the ADREGxx
Fixed-channel single conversion mode
1 fadc clock
Fixed-channel continuous conversion mode
1 fadc clock
Channel scan single scan conversion mode
2 fadc clocks
Channel scan continuous conversion mode
2 fadc clocks
fadc: A/D conversion clock selected by the ADCCLK register
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16. Watchdog Timer (WDT)
The TMP1941AF contains a watchdog timer (WDT). The WDT is used to regain control of the system in the
event of software or system lockups due to spurious noises, etc. When a watchdog timer time-out occurs, the
WDT generates a nonmaskable interrupt to the CPU.
Also, the time-out event can be programmed for system reset generation, which is accomplished by routing
the time-out signal to the internal reset pin.
16.1 Implementation
Figure 16.1 shows a block diagram of the WDT.
WDMOD.RESCR
Reset Control
RESET Pin
Internal Reset
Interrupt Request
(INTWDT)
WDMOD.
WDTP[1:0]
Selector
21
215 217 219 2
Q
fsys/2
R
22-Stage Binary Counter
S
Reset
Internal
Reset
WDMOD.WDTE
Write of
4EH
Write of
B1H
Watchdog Timer Control Register
(WDCR)
Internal Data Bus
Figure 16.1 WDT Block Diagram
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The WDT contains a 22-stage binary counter clocked by the fsys/2 clock. This binary counter provides
215, 217, 219 or 221 as a counter overflow signal, as programmed into the WDTP[1:0] field in the WDMOD.
When a counter overflow occurs, the WDT generates a WDT interrupt, as shown below.
WDT Counter
Overflow
n
0
WDT Interrupt
A write of a special clear-count code
WDT Clear
(via software)
Figure 16.2 Default Operation
Also, the counter overflow can be programmed to cause a system reset as the time-out action. If so
programmed, a counter overflow causes the WDT to assert the internal reset signal for a 22- to 29-state time.
After a reset, the fsys clock is, by default, generated by dividing the high-speed oscillator clock (fc) by eight
through the clock gear function; the WDT clock source (fsys/2) is derived from this fsys clock.
Overflow
WDT Counter
n
WDT Interrupt
Internal Reset
22–29 States (8.8–11.6 µs @ fc = 40 MHz, fsys = 5 MHz, fsys/2 = 2.5 MHz)
Note:
The TMP1941AF continues sampling the PLLOFF pin during a reset operation caused by the WDT.
Therefore, the PLLOFF pin must be tied to either logic high or logic low.
Figure 16.3 Reset Operation
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16.2 Register Description
The WDT is controlled by two registers called WDMOD and WDCR.
16.2.1
Watchdog Timer Mode Register (WDMOD)
•
Time-out Period (WDMOD.WDTP[1:0])
This 2-bit field determines the duration of the WDT time-out interval. Upon reset, the
WDTP[1:0] field defaults to 00. Figure 16.5 shows possible time-out periods.
•
WDT Enable (WDMOD.WDTE)
Upon reset, the WDTE bit is set to 1, enabling the WDT. To disable the WDT, the clearing of
the WDTE bit must be followed by a write of a special key code (B1H) to the WDCR register.
This prevents a “lost” program from disabling the WDT operation. The WDT can be re-enabled
only by setting the WDTE bit.
•
System Reset (WDMOD.RESCR)
This bit is used to program the WDT to generate a system reset on a time-out. Upon reset, this
bit is cleared; thus the time-out does not cause a system reset.
16.2.2
Watchdog Timer Control Register (WDCR)
This register is used to disable the WDT and to clear the WDT binary counter.
•
Disabling the WDT
The WDT can be disabled by clearing the WDMOD.WDTE to 0 and then writing the special
disable code (B1H) to the WDCR register.
WDMOD
WDCR
•
← 0 − − − − − − −
← 1 0 1 1 0 0 0 1
Clears the WDTE bit to 0.
Writes the disable code (B1H) to the WDCR.
Enabling the WDT
The WDT can be enabled only by setting the WDTE bit in the WDMOD to 1.
•
Clearing the WDT counter
Writing the special clear-count code (4EH) to the WDCR resets the binary counter to zero. The
counting process begins again.
WDCR
Note:
← 0 1 0 0 1 1 1 0
Writes the clear-count code (4EH) to the WDCR.
Writing the disable code (B1H) to the WDCR causes the binary counter to be reset to zero.
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WDMOD
Name
(0xFFFF_F090)
Read/Write
7
6
5
4
3
2
1
0
WDTE
WDTP1
WDTP0


I2WDT
RESCR





R/W
Reset Value
1
WDT
enable
Function
1: Enable
R/W
0
0
R/W
0
Time-out period
00: 216/fsys
01: 218/ fsys
10: 220/ fsys
11: 222/ fsys
IDLE
0: Off
1: On
R/W
0
0
1: System
reset
Must be
written as
0.
System reset
0

1
Internally routes the WDT time-out signal
to the system reset
Time-out peiord (@ fc = 40 MHz, fs = 32.768 kHz)
System Clock
Select
SYSCR1.SYSCK
1 (fs)
0 (fgear)
Watchdog Timer Time-out Period
Clock Gear Value
SYSCR1.GEAR[1:0]
WDMOD.WDTP[1:0]
00
01
10
11
xxx
2.0 s
8.0 s
32.0 s
128.0 s
00 (fc)
1.638 ms
6.554 ms
26.214 ms
104.858 ms
01 (fc/2)
3.277 ms
13.107 ms
52.429 ms
209.715 ms
10 (fc/4)
6.554 ms
26.214 ms
104.858 ms
419.430 ms
11 (fc/8)
13.107 ms
52.429 ms
209.715 ms
838.861 ms
WDT enable
0
Disable
1
Enable
Figure 16.4 Watchdog Timer Mode Register (WDMOD)
7
WDCR
6
5
4
(0xFFFF_F091) Read/Write
2
1
0
W

Reset Value
Function
3

Name
B1H: WDT disable code
4EH : WDT clear-count code
Special code
B1H
WDT disable code
4EH
WDT clear-count code
Other values
Don’t care
Figure 16.5 Watchdog Timer Control Register (WDCR)
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16.3 Operation
The watchdog timer is a kind of timer that generates an interrupt request if it times out. The WDT of the
TMP1941AF allows the user to program the time-out period in the WDTP[1:0] field in the WDMOD. While
enabled, the software can reset the counter to zero at any time by writing a special clear-count code. If the
software is unable to reset the counter before it reaches the time-out count, the WDT generates the INTWDT
interrupt. In response to the interrupt, the CPU jumps to a system recovery routine to regain control of the
system.
The WDT begins counting immediately after reset.
When the TMP1941AF goes into SLEEP or STOP mode, the WDT counter is reset to zero automatically
and stops counting. The WDT continues counting while an off-chip peripheral has mastership of the bus (i.e.,
BUSAK = 0).
In IDLE mode, the I2WDT bit in the WDMOD determines whether or not to disable the WDT. The
I2WDT bit can be programmed before putting the TMP1941AF in IDLE mode.
Examples:
•
Clearing the WDT binary counter
WDCR
•
Writes the clear-count code (4EH) to the WDCR.
Programming the time-out interval to 218/fsys
WDMOD
•
7 6 5 4 3 2 1 0
← 0 1 0 0 1 1 1 0
7 6 5 4 3 2 1 0
←1 0 1 − − − − −
Disabling the watchdog timer
WDMOD
WDCR
7 6 5 4 3 2 1 0
← 0 − − − − − − −
← 1 0 1 1 0 0 0 1
Clears the WDTE bit to 0.
Writes the disable code (B1H) to the WDCR.
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17. Real-Time Clock (RTC)
The TMP1941AF contains a real-time clock (RTC). Clocked by a 32.768-kHz clock, the RTC provides a
periodic interrupt at a programmed interval: 0.0625 seconds, 0.125 seconds, 0.25 seconds or 0.50 seconds.
The RTC can continue operating in any standby modes in which the low-speed oscillator is active.
The RTC interrupt (INTRTC) can be used as a wake-up signal to exit a standby mode (except STOP mode).
The IMCGB3 register located within the CG must be programmed to use the INTRTC interrupt.
17.1 Implemention
Figure 17.1 shows a block diagram of the RTC.
RTCCR.RTCSEL
Interrupt Request
(INTRTC)
Selector
RTCCR.RTCRUN
8-Bit
Accumulator
Run/Clear
fs
(32.768 kHz)
211 212 213 214
RTCREG
14-Stage Binary Counter
Figure 17.1 RTC Block Diagram
The RTC Control Register (RTCCR) provides control over the RTC. The organization of the RTCCR is
shown below.
7
Name
RTCCR
(0xFFFF_F0A0) Read/Write
Reset Value
Function
3
2
1
0

6
5
4
RTCRCLR
RTCSEL1
RTCSEL0
RTCRUN
R/W
R/W
0
0
Must be
written as
0.
Accumulator clear
0: Clear
RTCREG
1: Don’t
care
R/W
0
R/W
0
0
00: 214/fs
01: 213/fs
10: 212/fs
11: 211/fs
0: Stop and
clear the
counter.
1: Begin
counting.
Interrupt interval (fs = 32.768 kHz)
00
0.50 seconds
01
0.25 seconds
10
0.125 seconds
11
0.0625 seconds
Figure 17.2 RTC Control Register (RTCCR)
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The RTC provides an 8-bit read-only accumulator (RTCREG) that counts the number of INTRTC
interrupts that have occurred. The accumulator allows the user to keep track of time up to 127.5 seconds if
the interrupt interval is programmed to 0.5 seconds.
Accumulator
RTCREG
Name
(0xFFFF_F0A4) Read/Write
7
6
5
4
3
2
1
0
RUI7
RUI6
RUI5
RUI4
RUI3
RUI2
RUI1
RUI0
0
0
0
0
0
0
0
0
R
Reset Value
Function
Accumulate count value
Figure 17.3 RTC Accumulator Register (RTCREG)
The RTCREG is incremented with a delay of one fs clock after the INTRTC interrupt is generated. Reads
of the RTCREG must be performed in SLOW mode. The resetting of the RTCREG is inhibited for one fs
clock cycle after the INTRTC interrupt is generated. The RTCREG can be reset to zero by executing the
accumulator-clear command twice in SLOW mode.
fs Clock
INTRTC Interrupt
Accumulate
Count Value
n
n+1
Don’t execute an instruction
to reset the accumulator
during this period.
Example 1: Clearing the accumulator
SYSCR1
RTCCR
RTCCR
SYSCR1
←
←
←
←
7
X
0
0
X
6
X
X
X
X
5
1
X
X
0
4
−
X
X
−
3
−
0
0
−
2
X
−
−
X
1
−
−
−
−
0
−
1
1
−
Puts the TMP1941AF in SLOW mode.
Executes accumulator-clear command twice.
Puts the TMP1941AF back in NORMAL Mode.
Example 2: Programming the RTC interrupt interval
Initialization
IMCGB3
IMCEHL
EICRCG
INTCLR
RTCCR
←
←
←
←
←
7
0
0
0
0
0
6
0
0
0
0
0
5
1
0
0
1
0
4
1
1
0
1
0
3
0
0
0
1
1
2
0
X
1
0
X
1
0
X
1
1
X
0
1
X
1
0
1
Sets the interrupt level.
Clears the interrupt request via the CG block.
Clears the interrupt request via the INTC block.
Starts counting.
INTRTC interrupt
EICRCG
INTCLR
7 6 5 4 3 2 1 0
← 0 0 0 0 0 1 1 1
← 0 0 1 1 1 0 1 0
Clears the interrupt request via the CG block.
Clears interrupt request via the INTC block.
Interrupt processing
End of interrupt
X = Don't care
Note: To disable interrupts, program the IMCEHL and then the IMCGB3 in this order.
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18. Electrical Characteristics
The letter x in equations presented in this chapter represents the cycle period of the fsys clock selected
through the programming of the SYSCR1.SYSCK bit. The fsys clock may be derived from either the highspeed or low-speed crystal oscillator. The programming of the clock gear function also affects the fsys
frequency. All relevant values in this chapter are calculated with the high-speed (fc) system clock
(SYSCR1.SYSCK=0) and a clock gear factor of 1/fc (SYSCR1.GEAR[1:0]=00).
18.1 Maximum Ratings
Parameter
Symbol
Supply voltage
High-level output current
Unit
−0.5 to 4.0
V
V
VIN
−0.5 to VCC + 0.5
IOL
5
Total
ΣIOL
80
Per pin
IOH
−5
Input voltage
Low-level output current
Rating
VCC
Per pin
Total
Power dissipation (Ta = 85°C)
ΣIOH
−80
PD
600
mA
mW
Soldering temperature (10 s)
TSOLDER
260
°C
Storage temperature
TSTG
−65 to 150
°C
Operating temperature
TOPR
−40 to 85
°C
VCC = DVCC = AVCC; VSS = DVSS= AVSS
Note:
Maximum ratings are limiting values of operating and environmental conditions which should not
be exceeded under the worst possible conditions. The equipment manufacturer should design so
that no maximum rating value is exceeded with respect to current, voltage, power dissipation,
temperature, etc. Exposure to conditions beyond those listed above may cause permanent
damage to the device or affect device reliability, which could increase potential risks of personal
injury due to IC blowup and/or burning.
TMP1941AF-239
2003-03-27
TMP1941AF
18.2 DC Electrical Characteristics (1/2)
Ta = −40 to 85°C
Parameter
Symbol
Condition
PLLON
Supply voltage
AVCC = VCC
AVSS = VSS = 0 V
VCC
PLLOFF
(Crystal)
Low-level input voltage
fosc = 4 to 10 MHz
fsys = 2 to 40 MHz
fs = 30 to 34 kHz
3.0
fosc = 4 to 7 MHz
fsys = 2 to 28 MHz
fs = 30 to 34 kHz
2.7
fosc = 16 to 20 MHz
fsys = 1 to 20 MHz
fs = 30 to34 kHz
2.7
Typ (Note 1)
Max
Unit
3.6
V
fosc = 16 to 20 MHz
fsys = 1 to 20 MHz
fs = 30 to 34 kHz
PLLOFF
(External
clock)
High-level input voltage
Min
fosc = 20 to 40 MHz
fsys = 1.25 to 20 MHz
fs = 30 to 34 kHz
(SYSCR1.DFOSC = 0)
(Note 2)
2.7
AD0−15
VIL
0.6
A16−23, A0−7,
RD , WR , HWR ,
WAIT , BUSRQ ,
BUSAK , R / W ,
P37−PA7
(except P77)
VIL1
0.3VCC
−0.3
PLLOFF , BW0,
BW1, RESET , NMI ,
0.25VCC
VIL2
P77 (INT0)
X1
VIL4
AD0−15
VIH
A16−23, A0−7,
RD , WR , HWR ,
WAIT , BUSRQ ,
BUSAK , R / W ,
P37−PA7
(except P77)
VIH1
0.2VCC
VCC ≥ 2.7 V
V
2.0
0.7VCC
VCC + 0.3
PLLOFF , BW0,
BW1, RESET , NMI ,
0.80VCC
VIH2
P77 (INT0)
X1
VIH4
0.8VCC
Low-level output voltage
VOL
IOL = 1.6 mA
High-level output voltage
VOH
IOH = −400 µA
VCC ≥ 2.7 V
0.45
2.4
V
Note 1: VCC = 3.3 V, Ta = 25°C, unless otherwise noted.
Note 2: The DFOSC bit in the SYSCR1 register must be cleared to 0.
TMP1941AF-240
2003-03-27
TMP1941AF
18.3 DC Electrical Characteristics (2/2)
Ta = −40 to 85°C
Parameter
Symbol
Condition
Min
Typ (Note 1) Max
Unit
Input leakage current
ILI
0.0 ≤ VIN ≤ VCC
0.02
±5
Output leakage current
ILO
0.2 ≤ VIN ≤ VCC − 0.2
0.05
± 10
Power-down voltage
(STOP mode, RAM backup)
VSTOP
VIL2 = 0.2VCC, VIH2 = 0.8VCC
2.2
3.6
V
Pull-up resistor at Reset
RRST
VCC = 3.3 V ± 0.3 V
100
450
kΩ
Pin capacitance
(except power/ground pins)
CIO
fc = 1 MHz
10
pF
VTH
VCC ≥ 2.7 V
0.4
PKH
VCC = 3.3 V ± 0.3 V
100
µA
Schmitt hysteresis
PLLOFF , BW0, BW1,
V
RESET , NMI , INT0
Programmable pull-up resistor
VCC = 3.3 V ± 0.3 V
fsys = 40 MHz
(fOSC = 10 MHz, PLLON)
NORMAL (Note 2); Gear = 1/1
IDLE (Doze)
IDLE (Halt)
NORMAL (Note 2); Gear = 1/1
IDLE (Doze)
IDLE (Halt)
ICC
VCC = 3.3 V ± 0.3 V
fsys = 20 MHz
(fOSC = 20 MHz, PLLOFF)
450
75
kΩ
85
27
40
22
36
25
40
13
20
11
18
mA
mA
SLOW
VCC = 3.3 V ± 0.3 V
fs = 32.768 kHz
70
220
µA
SLLEP
VCC = 3.3 V ± 0.3 V
fs = 32.768 kHz
20
180
µA
STOP
VCC = 2.7 to 3.6 V
5
150
µA
Note 1: VCC = 3.3 V, Ta = 25°C, unless otherwise noted.
Note 2: Measured with the operating CPU (scanning ports), 16-bit bus (ALE = 1.5 cycles, 1 wait state), open output
pins and input pins levels held at fixed logic values. IREF excluded.
TMP1941AF-241
2003-03-27
TMP1941AF
18.4 AC Electrical Characteristics
(1) VCC = 3.0 to 3.6 V, Ta = 0 to 70°C, ALE width = 0.5 clock cycle (recommended when tSYS is 50 ns or
longer)
No.
Parameter
fsys = 20 MHz *
Equation
Symbol
Min
Max
Min
31.25
33333
Max
Unit
1
System clock period (x)
tSYS
50
ns
2
A0–A15 valid to ALE low
tAL
0.4x – 12
8
ns
3
A0–A15 hold after ALE low
tLA
0.4x – 8
12
ns
4
ALE pulse width high
tLL
0.4x – 6
14
ns
5
ALE low to RD or WR asserted
tLC
0.4x – 8
12
ns
6
RD or WR negated to ALE high
tCL
x − 15
35
ns
7
A0–A15 valid to RD or WR asserted
tACL
x − 20
30
ns
8
A0–A23 valid to RD or WR asserted
tACH
x − 20
30
ns
9
tCAR
x − 15
35
10
A0–A23 hold after RD or WR negated
A0–A15 valid to D0–D15 data in
tADL
x (2 + W) − 37
63
ns
11
A0–A23 valid to D0–D15 data in
tADH
x (2 + W) − 37
63
ns
12
RD asserted to D0–D15 data in
tRD
13
RD width low
tRR
14
D0–D15 hold after RD negated
tHR
0
0
ns
x − 15
35
ns
15
x (1 + W) − 22
x (1 + W) − 10
ns
28
40
ns
ns
RD negated to next A0–A15 output
tRAE
16
WR width low
tWW
x (1 + W) − 10
40
ns
17
D0–D15 valid to WR negated
tDW
x (1 + W) − 18
32
ns
18
D0–D15 hold after WR negated
tWD
x − 15
35
19
A0–A23 valid to WAIT input
tAWH
20
A0–A15 valid to WAIT input
tAWL
21
WAIT hold after RD or WR asserted
tCW
1.5x − 30
1.5x − 30
(0.5 + N − 1) x + 2 (0.5 + N) x − 17
ns
45
27
ns
45
ns
58
ns
*W=0
W: Number of wait-state cycles inserted (0 to 7 for programmed wait insertion)
N: Value of N for (1 + N) wait insertion
AC measurement conditions:
• Output levels: High = 2.4 V, Low = 0.45 V, CL = 30 pF
• Input levels: High = 2 V, Low = 0.6 V
TMP1941AF-242
2003-03-27
TMP1941AF
(2) VCC = 3.0 to 3.6 V, Ta = 0 to 70°C, ALE width = 1.5 clock cycles
No.
Parameter
fsys = 40 MHz*
Equation
Symbol
Max
31.25
33333
Min
Max
Unit
1
System clock period (x)
2
A0–A15 valid to ALE low
tAL
1.4x – 12
23
3
A0–A15 hold after ALE low
tLA
0.4x – 8
2
ns
4
ALE pulse width high
tLL
1.4x – 6
29
ns
5
ALE low to RD or WR asserted
tLC
0.4x – 8
2
ns
6
RD or WR negated to ALE high
tCL
x – 15
10
ns
7
A0–A15 valid to RD or WR asserted
tACL
2x – 20
30
ns
8
A0–A23 valid to RD or WR asserted
tACH
2x – 20
30
ns
x – 15
10
ns
10
A0–A23 hold after RD or WR negated
A0–A15 valid to D0–D15 data in
tCA
tADL
x (3 + W) − 37
38
ns
11
A0–A23 valid to D0–D15 data in
tADH
x (3 + W) − 37
38
ns
12
RD asserted to D0–D15 data in
tRD
x (1 + W) − 22
3
13
RD width low
tRR
14
D0–D15 hold after RD negated
tHR
0
0
ns
15
RD negated to next A0–A15 output
tRAE
x – 15
10
ns
16
9
tSYS
Min
x (1 + W) − 10
ns
ns
15
ns
ns
WR width low
tWW
x (1 + W) − 10
15
ns
17
D0–D15 valid to WR negated
tDW
x (1 + W) − 18
7
ns
18
D0–D15 hold after WR negated
tWD
x – 15
19
A0–A23 valid to WAIT input
tAWH
20
A0–A15 valid to WAIT input
tAWL
WAIT hold after RD or WR asserted
tCW
21
10
2.5x − 30
2.5x − 30
(0.5 + N − 1) x + 2 (0.5 + N) x − 17
ns
32
15
ns
32
ns
20
ns
*W=0
W: Number of wait-state cycles inserted (0 to 7 for programmed wait insertion)
N: Value of N for (1 + N) wait insertion
AC measurement conditions:
• Output levels: High = 2.4 V, Low = 0.45 V, CL = 30 pF
• Input levels: High = 2 V, Low = 0.6 V
TMP1941AF-243
2003-03-27
TMP1941AF
Bus Cycle = 4 CLK Cycles
Internal
CLK
S0
S1
S2
S3
S0
tLL
ALE
tAL
tCL
tLA
AD0–AD15
A0–A15
D0–D15
tADL
tADH
AD16–AD23
tHR
tACH
tACL
tLC
tRR
tCAR
tRAE
RD
tRD
CS0 – CS3
R/W
Note: The internal CLK is not the system clock driven out from the SCOUT pin.
Figure 18.1 Read Cycle Timing (ALE = 1.5, Zero Wait State)
TMP1941AF-244
2003-03-27
TMP1941AF
Bus Cycle = 5 CLK Cycles
Internal
CLK
S0
S1
W1
S2
S3
S0
tLL
ALE
tAL
tCL
tLA
AD0–AD15
A0–A15
D0–D15
tADL
tADH
A16–A23
tHR
tACH
tACL
tLC
RD
tRR
tCAR
tRAE
tRD
CS0 – CS3
R/ W
Note: The internal CLK is not the system clock driven out from the SCOUT pin.
Figure 18.2 Read Cycle Timing (ALE = 1.5, 1 Programmed Wait State)
TMP1941AF-245
2003-03-27
TMP1941AF
Bus Cycle = 6 CLK Cycles
Internal
CLK
S1
W
W
S2
S3
S0
ALE
AD0–AD15
A0–A15
D0–D15
AD16–AD23
RD
tCW
CS0 – CS3
R/ W
tAWL/H
WAIT
Note1:
If tAWH and/or tAWL cannot be satisified, a bus cycle must be initiated with the WAIT pin asserted.
Note2:
The internal CLK is not the system clock driven out from the SCOUT pin.
Figure 18.3 Read Cycle Timing (ALE = 1.5, 2 Externally Generated Wait States with N=1)
TMP1941AF-246
2003-03-27
TMP1941AF
Bus Cycle = 4 CLK Cycles
Internal
CLK
tLL
ALE
tAL
tCL
tLA
AD0–AD15
A0–A15
D0–D15
tDW
AD16–AD23
tWD
tACH
tACL
tLC
tWW
tCAR
WR , HWR
CS0 – CS3
R/ W
Note:
The internal CLK is not the system clock driven out from the SCOUT pin.
Figure 18.4 Write Cycle Timing (ALE = 1, Zero Wait State)
TMP1941AF-247
2003-03-27
TMP1941AF
18.5 ADC Electrical Characteristics
AVCC = VCC, AVSS = VSS
Parameter
Symbol
Condition
Min
Typ
Analog reference voltage (+)
VREFH
VCC = 3.3 ± 0.3 V
VCC − 0.2 V
VCC
VCC
Analog reference voltage (–)
VREFL
VCC = 3.3 ± 0.3 V
VSS
VSS
VSS + 0.2 V
Analog input voltage
Analog supply current
VAIN
ADMOD1.VREFON = 1
IREF
(VREFL = VSS)
ADMOD1.VREFON = 0 (VREFH = VCC)
Total error (not including quantization error)

VREFL
Max
Unit
V
VREFH
VCC = 3.3V ± 0.3 V
1.05
1.5
mA
VCC = 2.7 to 3.6 V
0.02
5.0
µA
VCC = 3.3 V ± 0.3 V
±1
±3
LSB
Note 1: 1 LSB = (VREFH – VREFL) / 1024 (V)
Note 2: The A/D converter must be stopped when operating the TMP1941AF with the low-speed clock (fs).
Note 3: The supply current flowing through the AVCC pin is included in the digital supply current parameter (ICC).
TMP1941AF-248
2003-03-27
TMP1941AF
18.6 SIO Timing
18.6.1
I/O Interface Mode
In the tables below, the letter x represents the fsys cycle period, which varies, depending on the
programming of the clock gear function.
(1) SCLK Input Mode
Parameter
Equation
Symbol
20 MHz
Min
Max Min Max
40 MHz
Min Max
Unit
SCLK period
tSCY
16x
800
400
ns
TxD data to SCLK rise or fall*
tOSS
(tSCY/2) − 5x − 23
127
52
ns
(tSCY/2) + 3x
550
275
ns
2x + 8
108
58
ns
0
0
ns
20 MHz
40 MHz
TxD data hold after SCLK rise or fall* tOHS
RxD data valid to SCLK rise or fall*
tSRD
RxD data hold after SCLK rise or fall* tHSR
0
* SCLK rise or fall: Measured relative to the programmed active edge of SCLK.
(2) SCLK Output Mode
Parameter
Equation
Symbol
Min
Max Min Max
Min Max
Unit
SCLK period (programmable)
tSCY
16x
800
400
ns
TxD data to SCLK rise
tOSS
(tSCY/2) − 15
385
185
ns
TxD data hold after SCLK rise
tOHS
(tSCY/2) − 15
385
185
ns
RxD data valid to SCK rise
tSRD
x + 23
73
48
ns
RxD data hold after SCK rise
tHSR
0
0
0
ns
tSCY
SCLK
SCK Output Mode /
Active-High SCL
Input Mode
SCLK
Active-Low SCK
Input Mode
Transmit Data
(TxD)
tOSS
0
tOHS
1
2
tSRD
Receive Data
(RxD)
3
tHSR
0
1
2
3
VALID
VALID
VALID
VALID
TMP1941AF-249
2003-03-27
TMP1941AF
18.7 SBI Timing
18.7.1
I2C Mode
In the table below, the letters x and T represent the fsys and φT0 cycle periods, respectively. The
letter n denotes the value of n programmed into the SCK[2:0] (SCL output frequency select) field in the
SBI0CR1.
Parameter
Standard Mode
Fast Mode
fsys = 8 MHz, n = 4 fsys = 32 MHz, n = 4 Unit
Max
Min
Max
Min
Max
Equation
Symbol
Min
SCL clock frequency
tSC
Hold time for START condition
tHD:STA
4.0
0.6
tLOW
4.7
1.3
µs
4 (Note 1)
1 (Note 1)
µs
Low period of the SCL
clock
SCL clock high width
Input
0
0
2(n−1) T
Output
Input
0
400
kHz
µs
4.0
0.6
µs
(2(n−1) + 4) T
6
1.5
µs
Softwaredependent
4.7
0.6
µs
tHIGH
Output
100
Setup time for a repeated START
condition
tSU;STA
Data hold time
tHD;DAT
0
0
µs
Data setup time
tSU;DAT
250
100
ns
Setup time for STOP condition
tSU;STO
4.0
0.6
µs
4.7
1.3
µs
Bus free time between STOP and
START conditions
tBUF
Softwaredependent
Note 1: Different from the Philips I2C-bus specification.
Note 2: The ouptut data hold time is equal to 12x.
Note 3: The Philips I2C-bus specification states that a device must internally provide a hold time of at least 300 ns for
the SDA signal to bridge the undefined region of the fall edge of SCL. However, the TMP1941AF SBI does not
satisfy this requirement. Also, the output buffer for SCL does not incorporate slope control of the falling
edges; therefore, the equipment manufacturer should design so that the input data hold time shown in the
table is satisfied, including tr/tf of the SCL and SDA lines.
tSCL
tf
tLOW
tr
tHIGH
SCL
tHD;STA
tSU;DAT
tHD;DAT
tSU;STA
tSU;STO
tBUF
SDA
S
Sr
P
S: START condition, Sr: Repeated START condition, P: STOP condition
Note 4: To operate the SBI in I2C Fast mode, the fsys frequency must be no less than 20 MHz. To operate the SBI in I2C
Standard mode, the fsys frequency must be no less than 4 MHz.
Note 5: Although THE I2C BUS SPECIFICATION from Philips states that I/O pins of Fast-mode devices must not
obstruct the SDA and SCL lines if VDD is switched off, the TMP1941AF does not comply with this requirement.
ns
400
Required Hold Time
Note 6: The SDA hold time from the falling edge of
SCL varies with the fsys frequency, as
shown at left. The fsys frequency must be
determined, considering the devices
connected on the I2C bus. If the devices on
the I2C bus drive the SDA line within a
minimum delay of 100 ns from the falling
edge of SCL, the required hold time must be
less than 100 ns; thus the fsys frequency
must be 20 MHz or larger.
300
200
100
0
TMP1941AF-250
10
20
fsys
30
40
MHz
2003-03-27
TMP1941AF
18.7.2
Clock-Synchronous 8-Bit SIO Mode
In the tables below, the letters x and T represent the fsys and φT0 cycle periods, respectively. The
letter n denotes the value of n programmed into the SCK[2:0] (SCL output frequency select) field in the
SBI0CR1.
The electrical specifications below are for an SCK signal with a 50% duty cycle.
(1) SCK Input Mode
Parameter
Equation
Symbol
40 MHz
Min
Max
Min
Max
Unit
SCK period
tSCY
16x
400
ns
SO data to SCK rise
tOSS
(tSCY/2) − (6x + 30)
20
ns
SO data hold after SCK rise
tOHS
(tSCY/2) + 4x
300
ns
SI data valid to SCK rise
tSRD
0
0
ns
SI data hold after SCK rise
tHSR
4x + 10
110
ns
(2) SCK Output Mode
Parameter
Equation
Symbol
40 MHz
Min
Max
Min
Max
Unit
SCK period (programmable)
tSCY
2n × T
800
ns
SO data to SCK rise
tOSS
(tSCY/2) − 20
380
ns
SO data hold after SCK rise
tOHS
(tSCY/2) − 20
380
ns
SI data valid to SCK rise
tSRD
2x + 30
80
ns
SI data hold after SCK rise
tHSR
0
0
ns
tSCY
SCK
tOSS
Transmit Data
(SO)
0
tOHS
1
2
tSRD
Receive Data
(SI)
3
tHSR
0
1
2
3
VALID
VALID
VALID
VALID
TMP1941AF-251
2003-03-27
TMP1941AF
18.8 Event Counters (TA0IN, TA2IN, TB0IN0, TB0IN1, TB2IN0)
In the table below, the letter x represents the fsys cycle period.
Parameter
Symbol
Equation
Min
40 MHz
Max
Min
Max
Unit
Clock low pulse width
tVCKL
2x + 100
150
ns
Clock high pulse width
tVCKH
2x + 100
150
ns
18.9 Timer Capture (TB0IN0, TB0IN1, TB1IN0, TB1IN1, TB2IN0, TB2IN1)
In the table below, the letter x represents the fsys cycle period.
Parameter
Symbol
Equation
Min
40 MHz
Max
Min
Max
Unit
Low pulse width
tCPL
2x + 100
150
ns
High pulse width
tCPH
2x + 100
150
ns
18.10 General Interrupts
In the table below, the letter x represents the fsys cycle period.
Parameter
Symbol
Equation
Min
40 MHz
Max
Min
Max
Unit
Low pulse width for INT0–INTA
tINTAL
x + 100
125
ns
High pulse width for INT0–INTA
tINTAH
x + 100
125
ns
18.11 NMI and STOP/SLEEP Wake-up Interrupts
Parameter
Symbol
Equation
Min
40 MHz
Max
Min
Max
Unit
Low pulse width for NMI and
INT0–INT4
tINTBL
100
100
ns
High pulse width for INT0–INT4
tINTBH
100
100
ns
18.12 SCOUT Pin
In the table below, the letter T represents the cycle period of the SCOUT output clock.
Parameter
Symbol
Equation
Min
40 MHz
Max
Min
Max
Unit
Clock low pulse width
tSCH
0.5T − 5
7.5
ns
Clock high pulse width
tSCL
0.5T − 5
7.5
ns
tSCH
tSCL
SCOUT
TMP1941AF-252
2003-03-27
TMP1941AF
18.13 Bus Request and Bus Acknowledge Signals
BUSRQ
(Note 1)
BUSAK
tBAA
tABA
(Note 2)
AD0–AD15
(Note 2)
A0–A23,
RD , WR
CS0 – CS3 ,
R / W , HWR
ALE
Parameter
Symbol
Equation
40 MHz
Min
Max
Min
Max
Unit
Bus float to BUSAK asserted
tABA
0
80
0
80
ns
Bus float after BUSAK negated
tBAA
0
80
0
80
ns
Note 1:
If the current bus cycle has not terminated due to wait-state insertion, the TMP1941AF does not
respond to BUSRQ until the wait state ends.
Note 2:
This broken lines indicate that output buffers are disabled, not that the signals are at indeterminate
states. The pin holds the last logic value present at that pin before the bus is relinquished. This is
dynamically accomplished through external load capacitances. The equipment manufacturer may
maintain the bus at a predefined state by means of off-chip resistors, but he or she should design,
considering the time (determined by the CR constant) it takes for a signal to reach a desired state. The
on-chip, integrated programmable pullup/pulldown resistors remain active, depending on internal
signal states.
TMP1941AF-253
2003-03-27
TMP1941AF
19. I/O Register Summary
The internal I/O registers configure and access the I/O ports, and control on-chip functions. These registers
occupy 8-kbyte addresses from 0xFFFF_E000 through 0xFFFF_FFFF.
1.
I/O ports
2.
Watchdog Timer (WDT)
3.
Real-Time Clock (RTC)
4.
8-Bit Timers (TMRAs)
5.
16-Bit Timer/Event Counters (TMRBs)
6.
Serial I/O (SIO0 and SIO1)
7.
Serial Bus Interface (SBI)
8.
Serial I/O (SIO3 and SIO4)
9.
A/D Converter (ADC)
10. Interrupt Controller (INTC)
11. DMA Controller (DMAC)
12. Chip Select/Wait Controller
13. Clock Generator (CG)
Table Organization
Mnemonic
Register Name
Address
7
6
1
0
Bit Name
Read/Write
Reset Value
Function
Access
R/W: Read/write. The user can read and write the register bit.
R:
Read only.
W:
Write only.
W*: The user can read and write the register bit, but a read always returns a value of 1.
TMP1941AF-254
2003-03-27
TMP1941AF
1. I/O Ports
Address
Mnemonic
0xFFFF_F010
1
2
3
Address
Mnemonic
0xFFFF_F020 P4CR
1 P4FC
2
3
Address
Mnemonic
0xFFFF_F030
1
2
3
P8
P9
P8CR
P8FC
Address
Mnemonic
0xFFFF_F050 ODE
1
2
3
4
5
6
7
4
5 P5
6
7
4 P9CR
5 P9FC
6 PA
7
4
5
6
7
8 P3
9
A P3CR
B P3FC
8
9
A
B P7
8 PACR
9 PAFC
A
B
8
9
A
B
C
C
C
C
D
E P4
F
D
E P7CR
F P7FC
D
E
F
D
E
F
2. WDT
3. RTC
Address
Mnemonic
0xFFFF_F090 WDMOD
1 WDCR
2
3
4. 8-Bit Timers
Address
Mnemonic
0xFFFF_F0A0 RTCCR
1
2
3
Address
Mnemonic
0xFFFF_F100 TA01RUN
1
2 TA0REG
3 TA1REG
4
4 RTCREG
4 TA01MOD
5
6
7
5
6
7
5 TA1FFCR
6
7
8
9
A
B
8
9
A
B
8 TA23RUN
9
A TA2REG
B TA3REG
C
D
E
F
C
D
E
F
C TA23MOD
D TA3FFCR
E
F
5. 16-Bit Timer/Event Counters
Address
Mnemonic
0xFFFF_F180 TB0RUN
1
2 TB0MOD
3 TB0FFCR
4
5
6
7
8
9
A
B
Address
Mnemonic
0xFFFF_F190 TB1RUN
1
2 TB1MOD
3 TB1FFCR
Address
0xFFFF_F1A0 TB2RUN
1
2 TB2MOD
3 TB2FFCR
4
5
6
7
TB0RG0L
TB0RG0H
TB0RG1L
TB0RG1H
8
9
A
B
Mnemonic
4
5
6
7
TB1RG0L
TB1RG0H
TB1RG1L
TB1RG1H
8
9
A
B
Address
Mnemonic
0xFFFF_F1B0 TB3RUN
1
2 TB3MOD
3 TB3FFCR
4
5
6
7
TB2RG0L
TB2RG0H
TB2RG1L
TB2RG1H
8
9
A
B
TB3RG0L
TB3RG0H
TB3RG1L
TB3RG1H
C TB0CP0L
C TB1CP0L
C TB2CP0L
C TB3CP0L
D TB0CP0H
E TB0CP1L
F TB0CP1H
D TB1CP0H
E TB1CP1L
F TB1CP1H
D TB2CP0H
E TB2CP1L
F TB2CP1H
D TB3CP0H
E TB3CP1L
F TB3CP1H
Figure 19.1 I/O Register Address Map (1/5)
TMP1941AF-255
2003-03-27
TMP1941AF
6. SIO0 and SIO1
Address
Mnemonic
0xFFFF_F200
1
2
3
SC0BUF
SC0CR
SC0MOD0
BR0CR
4 BR0ADD
5 SC0MOD1
6
7
8
9
A
B
7. SBI
8. SIO3 and SIO4
Address
Mnemonic
Address
0xFFFF_F240
1
2
3
SBI0CR1
SBI0DBR
I2C0AR
SBI0CR2/SR
0xFFFF_F280
1
2
3
4 SBI0BR0
5 SBI0BR1
6
7
SC1BUF
SC1CR
SC1MOD0
BR1CR
C BR1ADD
D SC1MOD1
E
F
Address
Mnemonic
9. ADC
Address
Mnemonic
SC3BUF
SC3CR
SC3MOD0
BR3CR
0xFFFF_F300
1
2
3
ADREG04L
ADREG04H
ADREG15L
ADREG15H
4 BR3ADD
5 SC3MOD1
6
7
4
5
6
7
ADREG26L
ADREG26H
ADREG37L
ADREG37H
8
9
A
B
SC4BUF
SC4CR
SC4MOD0
BR4CR
8
9
A
B
C BR4ADD
D SC4MOD1
E
F
C
D
E
F
Mnemonic
0xFFFF_F310 ADMOD0
1 ADMOD1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Figure 19.1 I/O Register Address Map (2/5)
TMP1941AF-256
2003-03-27
TMP1941AF
10. INTC
Address
Mnemonic
0xFFFF_E000 IMC0L
1
2 IMC0H
3
Mnemonic
Address
Mnemonic
0xFFFF_E020 IMC8L
1
2 IMC8H
3
Address
Mnemonic
0xFFFF_E030 IMCCL
1
2 IMCCH
3
4 IMC1L
5
6
7
4 IMC5L
5
6 IMC5H
7
4
5
6
7
4 IMCDL
5
6 IMCDH
7
8
9
A IMC2H
B
8
9
A
B
8 IMCAL
9
A IMCAH
B
8 IMCEL
9
A IMCEH
B
C IMC3L
C IMC7L
C
C IMCFL
D
E IMC3H
F
D
E IMC7H
F
D
E
F
D
E IMCFH
Address
Mnemonic
0xFFFF_E040 IVR
1
2
3
Note:
Address
0xFFFF_E010
1
2
3
Address
Mnemonic
0xFFFF_E050
1
2
3
Address
Mnemonic
0xFFFF_E060 INTCLR
1
2
3
Address
Mnemonic
0xFFFF_E070
1
2
3
4
5
6
7
4
5
6
7
4
5
6
7
4
5
6
7
8
9
A
B
8
9
A
B
8
9
A
B
8
9
A
B
C
D
E
F
C
D
E
F
C
D
E
F
C
D
E
F
Any attempt to access an address in the shaded areas causes a bus error to be signaled to the TX19 core
processor. Any attempt to access an address in the ranges 0xFFFF_E080 through 0xFFFF_E0FF and
0xFFFF_E10C through 0xFFFF_E1FF also causes a bus error.
Figure 19.1 I/O Register Address Map (3/5)
TMP1941AF-257
2003-03-27
TMP1941AF
11. DMAC
Address
Mnemonic
0xFFFF_E200 CCR0
1
2
3
Mnemonic
Address
Mnemonic
0xFFFF_E220 CCR1
1
2
3
Address
Mnemonic
0xFFFF_E230 BCR1
1
2
3
4 CSR0
5
6
7
4
5
6
7
4 CSR1
5
6
7
4
5
6
7
8 SAR0
9
A
B
8 DTCR0
9
A
B
8 SAR1
9
A
B
8 DTCR1
9
A
B
C DAR0
C
C DAR1
C
D
E
F
D
E
F
D
E
F
D
E
F
Address
Mnemonic
0xFFFF_E240 CCR2
1
2
3
Address
Mnemonic
0xFFFF_E250 BCR2
1
2
3
Address
Mnemonic
0xFFFF_E260 CCR3
1
2
3
Address
Mnemonic
0xFFFF_E270 BCR3
1
2
3
4 CSR2
5
6
7
4
5
6
7
4 CSR3
5
6
7
4
5
6
7
8 SAR2
8 DTCR2
8 SAR3
8 DTCR3
9
A
B
9
A
B
9
A
B
9
A
B
C DAR2
D
E
F
C
D
E
F
C DAR3
D
E
F
C
D
E
F
Address
Mnemonic
0xFFFF_E280 DCR
1
2
3
Note:
Address
0xFFFF_E210 BCR0
1
2
3
Address
Mnemonic
Address
Mnemonic
Address
Mnemonic
0xFFFF_E290
1
2
3
0xFFFF_E2A0
1
2
3
0xFFFF_E2B0
1
2
3
4
4
4
4
5
6
7
5
6
7
5
6
7
5
6
7
8
9
A
B
8
9
A
B
8
9
A
B
8
9
A
B
C DHR
D
E
F
C
D
E
F
C
D
E
F
C
D
E
F
Any attempt to access an address in the shaded areas causes a bus error to be signaled to the TX19 core
processor. Any attempt to access an address in the range 0xFFFF_E2C0 through 0xFFFF_E2FF also causes a
bus error. Any attempt to access an address in the range 0xFFFF_E300 through 0xFFFF_E3FF is disallowed.
Figure 19.1 I/O Register Address Map (4/5)
TMP1941AF-258
2003-03-27
TMP1941AF
12. CS/Wait Controller
Address
Mnemonic
Address
Mnemonic
Address
Mnemonic
Address
Mnemonic
0xFFFF_E400 BMA0
1
2
3
0xFFFF_E410
1
2
3
0xFFFF_E480 B01CS
1
2
3
0xFFFF_E490
1
2
3
4 BMA1
5
6
7
4
5
6
7
4 B23CS
5
6
7
4
5
6
7
8 BMA2
9
A
B
8
9
A
B
8 BEXCS
9
A
B
8
9
A
B
C BMA3
C
C
C
D
E
F
D
E
F
D
E
F
D
E
F
13. CG
Address
Mnemonic
0xFFFF_EE00
1
2
3
Note:
SYSCR0
SYSCR1
SYSCR2
SYSCR3
Address
Mnemonic
0xFFFF_EE10
1
2
3
IMCGA0
IMCGA1
IMCGA2
IMCGA3
Address
Mnemonic
0xFFFF_EE20 EICRCG
1
2
3
4 ADCCLK
4 IMCGB0
4
5
6
7
5
6
7 IMCGB3
5
8
9
A
B
8
9
A
B
8
C
D
E
F
C
D
E
F
6
7
9
A
B
C
D
E
F
Any attempt to access an address in the shaded
areas causes a bus error to be signaled to the TX19
core processor. Any attempt to access an address
in the following ranges also cause a bus error.
0xFFFF_E420 thru 0xFFFF_E47F
0xFFFF_E450 thru 0xFFFF_E4FF
0xFFFF_E700 thru 0xFFFF_EDFF
0xFFFF_EE30 thru 0xFFFF_EEFF
An attempt to access an address in the following
ranges also cause a bus error.
0xFFFF_F040 thru 0xFFFF_F04F
0xFFFF_F060 thru 0xFFFF_F08F
0xFFFF_F0B0 thru 0xFFFF_F0FF
0xFFFF_F110 thru 0xFFFF_F17F
0xFFFF_F1C0 thru 0xFFFF_F1FF
0xFFFF_F210 thru 0xFFFF_F23F
0xFFFF_F248 thru 0xFFFF_F27F
0xFFFF_F290 thru 0xFFFF_F2FF
0xFFFF_F320 thru 0xFFFF_FFFF
Figure 19.1 I/O Register Address Map (5/5)
TMP1941AF-259
2003-03-27
TMP1941AF
19.1 I/O Ports
I/O Port Data Registers
Mnemonic Name Address
7
6
5
4
3
2
1
0







P42
R/W
1
Input mode
P41
P40
1
1
P52
P51
P50
P73
P72
P71
P70
1
1
1
1
P83
P82
P81
P80
1
1
1
1
P93
P92
P91
P90
1
1
1
1
PA3
PA2
PA1
PA0
1
1
1
1
P3
Port 3
Register
FFFF
F018H
P37
R/W
1
Input mode
P4
Port 4
Register
FFFF
F01EH








Port 5
Register
FFFF
F025H
P57
P5
P77
P7
Port 7
Register
FFFF
F02BH
R/W
1
1




P44
P43
1
1
P56
P55
P54
P76
P75
P74
P53
R
Input mode
R/W
1
1
1
1
Input mode
P87
P8
Port 8
Register
FFFF
F030H
P86
P85
P84
R/W
1
1
1
1
Input mode
P97
P9
Port 9
Register
FFFF
F031H
Port A
Register
FFFF
F036H
P95
P94
R/W
1
1
Output mode
PA7
PA
P96
PA6
1
1
Input mode
PA5
PA4
R/W
1
1
1
1
Input mode
I/O Port Control and Function Registers (1 of 2)
Mnemonic Name Address
P3CR
Port 3
Control
Register
FFFF
F01AH
P4CR
Port 4
Control
Register
FFFF
F020H
P4FC
P7CR
P7FC
Note:
Port 4
Function
Register
FFFF
F021H
Port 7
Control
Register
FFFF
F02EH
Port 7
Function
Register
7
6
5
4
3
2
P37C
P36C
P35C
P34C
P33C
P32C
0
0
0
0
0
0


P44C
P43C
P42C
W
1
0: IN, 1: OUT
P41C
P40C
0
0
0
0
P44F
P43F
P41F
P40F
0
0: Port
0
0: Port
W
0
0: IN,
1: OUT


P77C
FFFF
F02FH
1


P76C


P75C
0
0: Port
0
0: Port
P42F
W
1
0: Port
1: SCOUT
output
1: CS3
output
1: CS2
output
1: CS1
output
1: CS0
output
P73C
P72C
P71C
P70C
0
0
0
P72F
P71F
P70F
P74C
W
0
0
0
P77F
P76F
P75F
0
0: Port
1: Wake-up
INT0
input
0
0: Port
1: TB0OUT
output
0
0: Port
1: TB0IN1
input
0
0
0: IN 1: OUT
P74F
0
0: Port
1: TB0IN0
input
P73F
0
0: Port
1: TA3OUT
output /
RXD4
input
0
0: Port
1: TA2IN
input /
TXD4
output
0
0: Port
1: TA1OUT
output /
RXD3
input
0
0: Port
1: TA0IN
input /
TXD3
output
P77F must be set to 1 when INT0 is used to exit STOP mode with SYSCR2.DRVE cleared.
TMP1941AF-260
2003-03-27
TMP1941AF
I/O Port Control and Function Registers (2 of 2)
Mnemonic Name Address
P8CR
Port 8
Port 8
Control
Register
P8FC
Port 8
Port 8
Function
Register
FFFF
F033H
P9CR
Port 9
Port 9
Control
Register
FFFF
F034H
P9FC
Port 9
Port 9
Function
Register
FFFF
F032H
7
6
5
4
3
2
1
0
P87C
P86C
P85C
P84C
P83C
P82C
P81C
P80C
0
0
0
0
0
0

P86F
P85F
P82F
P81F
P80F
W
0
0
0: IN, 1: OUT
P84F
P83F
W
0
0
Must be
0: Port
written as 0. 1: TB3OUT
output
P97C
FFFF
F035H
P96C
0
0: Port
1: TB2OUT
output
P95C
0
0: Port
1: TB2IN1
input
0
0: Port
1: TB2IN0
input
P94C
0
0: Port
1: TB1OUT
output
P93C
Port A
Control
Register
0

PAFC
Port A
Port A
Function
Register
Note:
PA7C
FFFF
F038H
0
0: Port
1: TB1IN0
input
P92C
P91C
P90C
0
0
0
W
0

0
0
0
0: IN, 1: OUT
P95F
W
0
0: Port
1: SCLK1
output or
P93F
P92F
PA6C
PA5C
P90F
W
0
0: Port
1: TXD0
output
W

0
0: Port
1: TXD1
output
0
0: Port
1: SCLK0
output or
CTS1 /
SCLK1
input
PACR
Port A
0
0: Port
1: TB1IN1
input

CTS0 /
SCLK0
input
PA4C
PA3C
PA2C
PA1C
PA0C
0
0
0
PA2F
PA1F
PA0F
W
0
0
0
PA7F
PA6F
PA5F
0
0
0: IN, 1: OUT

PA3F
W
FFFF
F039H
0
0: Port
1: SCL
output
0
0: Port
1: SDA/SO
output
0
0: Port
1: SCK
output
0
0
0
0
0
Must be
0: Port
0: Port
0: Port
0: Port
written as 0. 1: Wake-up 1: Wake-up 1: Wake-up 1: Wake-up
INT4 input
INT3 input
INT2 input
INT1 input
PA0F–PA3F must be set to 1 when INT1–INT4 are used to exit STOP mode with SYSCR2.DRVE cleared.
Open-Drain Enable Register
Mnemonic Name Address
ODE
OpenDrain
Enable
Register
FFFF
F050H
7
6
5
4
3
2
1
0






ODE72
ODE70
ODEA7
ODEA6
ODE93
ODE90
0
0
0
R/W
0
0
0
P72
P70
PA7
PA6
P93
P90
0: Push-pull 0: Push-pull 0: Push-pull 0: Push-pull 0: Push-pull 0: Push-pull
1: Open1: Open1: Open1: Open1: Open1: Opendrain
drain
drain
drain
drain
drain
TMP1941AF-261
2003-03-27
TMP1941AF
19.2 Interrupt Controller
Interrupt Controller (1 of 12)
Mnemonic Name Address
IMC0L
IMC0H
Note1:
Interrupt
Mode
Control
Register
0L
Interrupt
Mode
Control
Register
0H
FFFF
E000H
FFFF
E002H
7
6
5
4
3
2
1
0






EIM01
EIM00
DM0
IL02
IL01
IL00
R/W
0
0
Interrupt sensitivity
00: Low level
Must be written as 00.
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM0 = 0
Interrupt Number 0 (Software Set)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM0 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
15
14
13
12
11
10
9
8






EIM11
EIM10
DM1
IL12
IL11
IL10
R/W
0
0
Interrupt sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
0
DMA
trigger
0: Disable
1: Enable
0
0
When DM1 = 0
Interrupt Number 1 (INT0 pin)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM1 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
0
23
22
21
20
19
18
17
16






EIM21
EIM20
DM2
IL22
IL21
IL20
R/W
0
0
Interrupt sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
0
DMA
trigger
0: Disable
1: Enable
0
0
When DM2 = 0
Interrupt Number 2 (INT1 pin)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM2 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
0
31
30
29
28
27
26
25
24






EIM31
EIM30
DM3
IL32
IL31
IL30
R/W
0
0
Interrupt sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
0
DMA
trigger
0: Disable
1: Enable
0
0
When DM3 = 0
Interrupt Number 3 (INT2 pin)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM3 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
0
When using INT0–INT4 to exit STOP and SLEEP modes, program their sensitivity in the IMCGA0 to IMCGA3 and
IMCGB0 located within the CG. In this case, the EIMx[1:0] fields in the IMC0L, IMC0H and IMC1L have no effect,
but must always be set to “high-level” (i.e., 01).
Note 2: Interrupt sensitivity must be programmed before interrupt priority levels are programmed into the ILx[2:0] field.
TMP1941AF-262
2003-03-27
TMP1941AF
Interrupt Controller (2 of 12)
Mnemonic Name Address
IMC1L
IMC2H
Interrupt
Mode
Control
Register
1L
Interrupt
Mode
Control
Register
2H
FFFF
E004H
FFFF
E00AH
7
6
5
4
3
2
1
0






EIM41
EIM40
DM4
IL42
IL41
IL40
R/W
0
0
Interrupt sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM4 = 0
Interrupt Number 4 (INT3 pin)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM4 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
15
14
13
12
11
10
9
8






EIM51
EIM50
DM5
IL52
IL51
IL50
R/W
0
0
Interrupt sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM5 = 0
Interrupt Number 5 (INT4 pin)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM5 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
23
22
21
20
19
18
17
16






EIMA1
EIMA0
DMA
ILA2
ILA1
ILA0
R/W
0
0
Interrupt sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
0
DMA
trigger
0: Disable
1: Enable
31
30
29
28
27






EIMB1
EIMB0
DMB
0
0
0
When DMA = 0
Interrupt Number 10 (INT5 pin)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DMA = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
26
25
24
ILB2
ILB1
ILB0
R/W
0
0
Interrupt sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
TMP1941AF-263
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DMB = 0
Interrupt Number 11 (INT6 pin)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DMB = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
2003-03-27
TMP1941AF
Interrupt Controller (3 of 12)
Mnemonic Name Address
IMC3L
IMC3H
Interrupt
Mode
Control
Register
3L
Interrupt
Mode
Control
Register
3H
FFFF
E00CH
FFFF
E00EH
7
6
5
4
3
2
1
0


EIMC1
EIMC0
DMC
ILC2
ILC1
ILC0




R/W
0
0
Interrupt sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DMC = 0
Interrupt Number 12 (INT7 pin)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DMC = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
15
14
13
12
11
10
9
8


EIMD1
EIMD0
DMD
ILD2
ILD1
ILD0




R/W
0
0
Interrupt sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DMD = 0
Interrupt Number 13 (INT8 pin)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DMD = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
23
22
21
20
19
18
17
16


EIME1
EIME0
DME


ILE2
ILE1
ILE0


31
30
29
28
27
26
25
24






EIMF1
EIMF0
DMF
ILF2
ILF1
ILF0
R/W
1
0
Interrupt sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DME = 0
Interrupt Number 14 (INT9 pin)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DME = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
R/W
0
0
Interrupt sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
TMP1941AF-264
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DMF = 0
Interrupt Number 15 (INTA pin)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DMF = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
2003-03-27
TMP1941AF
Interrupt Controller (4 of 12)
Mnemonic Name Address
IMC5L
IMC5H
Interrupt
Mode
Control
Register
5L
Interrupt
Mode
Control
Register
5H
FFFF
E014H
FFFF
E016H
7
6
5
4
3
2
1
0






EIM141
EIM140
DM14
IL142
IL141
IL140
R/W
0
0
Must be written as 11.
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM14 = 0
Interrupt Number 20 (INTTA0)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM14 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
15
14
13
12
11
10
9
8






EIM151
EIM150
DM15
IL152
IL151
IL150
R/W
0
0
Must be written as 11.
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM15 = 0
Interrupt Number 21 (INTTA1)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM15 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
23
22
21
20
19
18
17
16






EIM161
EIM160
DM16
IL162
IL161
IL160
R/W
0
0
Must be written as 11.
0
DMA
trigger
0: Disable
1: Enable
31
30
29
28
27






EIM171
EIM170
DM17
0
0
0
When DM16 = 0
Interrupt Number 22 (INTTA2)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM16 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
26
25
24
IL172
IL171
IL170
R/W
0
0
Must be written as 11.
TMP1941AF-265
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM17 = 0
Interrupt Number 23 (INTTA3)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM17 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
2003-03-27
TMP1941AF
Interrupt Controller (5 of 12)
Mnemonic Name Address
IMC7L
IMC7H
Interrupt
Mode
Control
Register
7L
Interrupt
Mode
Control
Register
7H
FFFF
E01CH
FFFF
E01EH
7
6
5
4
3
2
1
0






EIM1C1
EIM1C0
DM1C
IL1C2
IL1C1
IL1C0
R/W
0
0
Must be written as 11.
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM1C = 0
Interrupt Number 28 (INTTB00)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM1C = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
15
14
13
12
11
10
9
8






EIM1D1
EIM1D0
DM1D
IL1D2
IL1D1
IL1D0
R/W
0
0
Must be written as 11.
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM1D = 0
Interrupt Number 29 (INTTB01)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM1D = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
23
22
21
20
19
18
17
16






EIM1E1
EIM1E0
DM1E
IL1E2
IL1E1
IL1E0
R/W
0
0
Must be written as 11.
0
DMA
trigger
0: Disable
1: Enable
31
30
29
28
27






EIM1F1
EIM1F0
DM1F
0
0
0
When DM1E = 0
Interrupt Number 30 (INTTB10)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM1E = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
26
25
24
IL1F2
IL1F1
IL1F0
R/W
0
0
Must be written as 11.
TMP1941AF-266
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM1F = 0
Interrupt Number 31 (INTTB11)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM1F = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
2003-03-27
TMP1941AF
Interrupt Controller (6 of 12)
Mnemonic Name Address
IMC8L
IMC8H
Interrupt
Mode
Control
Register
8L
Interrupt
Mode
Control
Register
8H
FFFF
E020H
FFFF
E022H
7
6
5
4
3
2
1
0






EIM201
EIM200
DM20
IL202
IL201
IL200
R/W
0
0
Must be written as 11.
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM20 = 0
Interrupt Number 32 (INTTB20)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM20 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
15
14
13
12
11
10
9
8






EIM211
EIM210
DM21
IL212
IL211
IL210
R/W
0
0
Must be written as 11.
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM21 = 0
Interrupt Number 33 (INTTB21)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM21 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
23
22
21
20
19
18
17
16






EIM221
EIM220
DM22
IL222
IL221
IL220
R/W
0
0
Must be written as 11.
0
DMA
trigger
0: Disable
1: Enable
31
30
29
28
27






EIM231
EIM230
DM23
0
0
0
When DM22 = 0
Interrupt Number 34 (INTTB30)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM22 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
26
25
24
IL232
IL231
IL230
R/W
0
0
Must be written as 11.
TMP1941AF-267
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM23 = 0
Interrupt Number 35 (INTTB31)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM23 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
2003-03-27
TMP1941AF
Interrupt Controller (7 of 12)
Mnemonic Name Address
IMCAL
IMCAH
Interrupt
Mode
Control
Register
AL
Interrupt
Mode
Control
Register
AH
FFFF
E028H
FFFF
E02AH
7
6
5
4
3
2
1
0






EIM281
EIM280
DM28
IL282
IL281
IL280
R/W
0
0
Must be written as 11.
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM28 = 0
Interrupt Number 40 (INTTBOF0)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM28 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
15
14
13
12
11
10
9
8






EIM291
EIM290
DM29
IL292
IL291
IL290
R/W
0
0
Must be written as 11.
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM29 = 0
Interrupt Number 41 (INTTBOF1)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM29 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
23
22
21
20
19
18
17
16






EIM2A1
EIM2A0
DM2A
IL2A2
IL2A1
IL2A0
R/W
0
0
Must be written as 11.
0
DMA
trigger
0: Disable
1: Enable
31
30
29
28
27






EIM2B1
EIM2B0
DM2B
0
0
0
When DM2A = 0
Interrupt Number 42 (INTTBOF2)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM2A = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
26
25
24
IL2B2
IL2B1
IL2B0
R/W
0
0
Must be written as 11.
TMP1941AF-268
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM2B = 0
Interrupt Number 43 (INTTBOF3)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM2B = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
2003-03-27
TMP1941AF
Interrupt Controller (8 of 12)
Mnemonic Name Address
IMCCL
IMCCH
Interrupt
Mode
Control
Register
CL
Interrupt
Mode
Control
Register
CH
FFFF
E030H
FFFF
E032H
7
6
5
4
3
2
1
0






EIM301
EIM300
DM30
IL302
IL301
IL300
R/W
0
0
Must be written as 11.
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM30 = 0
Interrupt Number 48 (INTRX0)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM30 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
15
14
13
12
11
10
9
8






EIM311
EIM310
DM31
IL312
IL311
IL310
R/W
0
0
Must be written as 11.
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM31= 0
Interrupt Number 49 (INTTX0)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM31= 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
23
22
21
20
19
18
17
16






EIM321
EIM320
DM32
IL322
IL321
IL320
R/W
0
0
Must be written as 11.
0
DMA
trigger
0: Disable
1: Enable
31
30
29
28
27






EIM331
EIM330
DM33
0
0
0
When DM32 = 0
Interrupt Number 50 (INTRX1)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM32 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
26
25
24
IL332
IL331
IL330
R/W
0
0
Must be written as 11.
TMP1941AF-269
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM33 = 0
Interrupt Number 51 (INTTX1)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM33= 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
2003-03-27
TMP1941AF
Interrupt Controller (9 of 12)
Mnemonic Name Address
IMCDL
IMCDH
Interrupt
Mode
Control
Register
DL
Interrupt
Mode
Control
Register
DH
7
6
5
4
3
2
1
0






EIM341
EIM340
DM34
IL342
IL341
IL340
R/W
0
0
Must be written as 11.
0
DMA
trigger
0: Disable
1: Enable
FFFF
E034H
FFFF
E036H
13
12
0
0
When DM34 = 0
Interrupt Number 52 (INTS2)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM34 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
11
10
9
0
15
14






8
23
22
21
20
19
18
17
16






EIM361
EIM360
DM36
IL362
IL361
IL360
R/W
0
0
Must be written as 00.
0
Must be
written as
0.
0
0
Must be written as 000.
0
R/W
0
0
Must be written as 11.
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM36 = 0
Interrupt Number 54 (INTRX3)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM36 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
31
30
29
28
27
26
25
24






EIM371
EIM370
DM37
IL372
IL371
IL370
R/W
0
0
Must be written as 11.
TMP1941AF-270
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM37 = 0
Interrupt Number 55 (INTTX3)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM37 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
2003-03-27
TMP1941AF
Interrupt Controller (10 of 12)
Mnemonic Name Address
IMCEL
IMCEH
Interrupt
Mode
Control
Register
EL
Interrupt
Mode
Control
Register
EH
FFFF
E038H
FFFF
E03AH
7
6
5
4
3
2
1
0






EIM381
EIM380
DM38
IL382
IL381
IL380
R/W
0
0
Must be written as 11.
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM38 = 0
Interrupt Number 56 (INTRX4)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM38 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
15
14
13
12
11
10
9
8






EIM391
EIM390
DM39
IL392
IL391
IL390
R/W
0
0
Must be written as 11.
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM39 = 0
Interrupt Number 57 (INTTX4)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM39 = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
23
22
21
20
19
18
17
16






EIM3A1
EIM3A0
DM3A
IL3A2
IL3A1
IL3A0
R/W
0
0
Must be written as 01.
0
DMA
trigger
0: Disable
1: Enable
31
30
29
28
27






EIM3B1
EIM3B0
DM3B
0
0
0
When DM3A = 0
Interrupt Number 58 (INTRTC)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM3A = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
26
25
24
IL3B2
IL3B1
IL3B0
R/W
0
0
Must be written as 11.
TMP1941AF-271
0
DMA
trigger
0: Disable
1: Enable
0
0
When DM3B = 0
Interrupt Number 59 (INTAD)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM3B = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
0
2003-03-27
TMP1941AF
Interrupt Controller (11 of 12)
Mnemonic Name Address
IMCFL
IMCFH
Interrupt
Mode
Control
Register
FL
Interrupt
Mode
Control
Register
FH
FFFF
E03CH
FFFF
E03EH
7
6
5
4
3
2
1
0






EIM3C1
EIM3C0
DM3C
IL3C2
IL3C1
IL3C0
R/W
0
0
Must be written as 10.
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM3C = 0
Interrupt Number 60 (INTDMA0)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM3C = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
15
14
13
12
11
10
9
8






EIM3D1
EIM3D0
DM3D
IL3D2
IL3D1
IL3D0
R/W
0
0
Must be written as 10.
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM3D = 0
Interrupt Number 61 (INTDMA1)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM3D = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
23
22
21
20
19
18
17
16






EIM3E1
EIM3E0
DM3E
IL3E2
IL3E1
IL3E0
R/W
0
0
Must be written as 10.
0
DMA
trigger
0: Disable
1: Enable
31
30
29
28
27






EIM3F1
EIM3F0
DM3F
0
0
0
When DM3E = 0
Interrupt Number 62 (INTDMA2)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM3E = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
26
25
24
IL3F2
IL3F1
IL3F0
R/W
0
0
Must be written as 10.
TMP1941AF-272
0
DMA
trigger
0: Disable
1: Enable
0
0
0
When DM3F = 0
Interrupt Number 63 (INTDMA3)
000: Interrupt disabled.
001–111: Priority level (1–7)
When DM3F = 1
DMAC channel select
000–011: Ch. number (0–3)
100–111: Don’t use.
2003-03-27
TMP1941AF
Interrupt Controller (12 of 12)
Mnemonic Name Address
7
6
5
4
IVRL
3
2
1
0




0
0
0
0
11
10
9
R
0
0
0
0
Interrupt vector for the source of the current interrupt
15
14
13
12
8
IVRH
R/W
IVR
Interrupt
Vector
Register
IVRL
R
0
0
0
0
23
22
21
20
0
0
19
18
FFFF
E040H
0
0
Interrupt vector for the
source of the current
interrupt
15
16
IVRH
R/W
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
0
0
0
0
IVRH
R/W
0
INTCLR
Interrupt
Request
Clear
Register
FFFF
E060H
0
0
0
7
6
5
4
3
2
1
0






EICLR5
EICLR4
EICLR3
EICLR2
EICLR1
EICLR0



W



IVRL[9:4] value for an interrupt to be cleared
TMP1941AF-273
2003-03-27
TMP1941AF
19.3 Chip Select/Wait Controller
Chip Select/Wait Controller (1 of 4)
Mnemonic Name Address
7
6
5
4
3
2
1
0
1
1
1
1
11
10
9
8
MA0
R/W
1
1
1
1
Bits 9–0 specify the address bits (A23–A14) to be masked.
0: The corresponding address bit is not masked.
1: The corresponding address bit is masked.
15
14
13
12
MA0
R/W
BMA0
Base/
Mask
Address
Register
FFFF
E400H
0
Must be
written as
0.
23
0
Must be
written as
0.
22
0
Must be
written as
0.
21
0
Must be
written as
0.
0
Must be
written as
0.
20
19
0
Must be
written as
0.
18
0
Address mask
0: Not masked
1: Masked
0
17
16
0
0
25
24
BA0
R/W
0
0
31
30
0
0
0
0
A23–A16 of the starting address for CS0
29
28
27
26
BA0
R/W
0
0
0
0
0
0
A31–A24 of the starting address for CS0
0
0
7
6
5
4
3
2
1
0
1
1
1
1
11
10
9
8
MA1
R/W
1
1
1
1
Bits 9–0 specify the address bits (A23–A14) to be masked.
0: The corresponding address bit is not masked.
1: The corresponding address bit is masked.
15
14
13
12
MA1
R/W
BMA1
Base/
Mask
Address
Register
FFFF
E404H
0
Must be
written as
0.
23
0
Must be
written as
0.
22
0
Must be
written as
0.
21
0
Must be
written as
0.
0
Must be
written as
0.
20
19
0
Must be
written as
0.
18
0
Address mask
0: Not masked
1: Masked
0
17
16
0
0
25
24
0
0
BA1
R/W
0
0
31
30
0
0
0
0
A23–A16 of the starting address for CS1
29
28
27
26
BA1
R/W
0
0
0
0
0
0
A31–A24 of the starting address for CS1
TMP1941AF-274
2003-03-27
TMP1941AF
Chip Select/Wait Controller (2 of 4)
Mnemonic Name Address
7
6
5
4
3
2
1
0
1
1
1
1
11
10
9
8
MA2
R/W
1
1
1
1
Bits 8–0 specify the address bits (A23–A15) to be masked
0: The corresponding address bit is not masked.
1: The corresponding address bit is masked.
15
14
13
12
MA2
R/W
BMA2
Base/
Mask
Address
Register
FFFF
E408H
0
Must be
written as
0.
23
0
Must be
written as
0.
22
0
Must be
written as
0.
21
0
Must be
written as
0.
0
Must be
written as
0.
20
19
0
Must be
written as
0.
18
0
Must be
written as
0.
0
Address
mask
0: Not
masked
1: Masked
17
16
0
0
25
24
BA2
R/W
0
0
31
30
0
0
0
0
A23–A16 of the starting address for CS2
29
28
27
26
BA2
R/W
0
0
0
0
0
0
A31–A24 of the starting address for CS2
0
0
7
6
5
4
3
2
1
0
1
1
1
1
11
10
9
8
MA3
R/W
1
1
1
1
Bits 8–0 specify the address bits (A23–A15) to be masked
0: The corresponding address bit is not masked.
1: The corresponding address bit is masked.
15
14
13
12
MA3
R/W
BMA3
Base/
Mask
Address
Register
FFFF
E40CH
0
Must be
written as
0.
23
0
Must be
written as
0.
22
0
Must be
written as
0.
21
0
Must be
written as
0.
0
Must be
written as
0.
20
19
0
Must be
written as
0.
18
0
Must be
written as
0.
0
Address
mask
0: Not
masked
1: Masked
17
16
0
0
25
24
0
0
BA3
R/W
0
0
31
30
0
0
0
0
A23–A16 of the starting address for CS3
29
28
27
26
BA3
R/W
0
0
0
0
0
0
A31–A24 of the starting address for CS3
TMP1941AF-275
2003-03-27
TMP1941AF
Chip Select/Wait Controller (3 of 4)
Mnemonic Name Address
7
6
B0OM
W
0
0
Chip select output
waveform
00: ROM/SRAM
Don’t use any other
value.
5
4



B0BUS
0
Data bus
width
0: 16-bit
1: 8-bit
3
2
1
0
B0W
W
0
1
0
1
Number of wait-state cycles
0000: No wait state,
0001: 1 wait state
0010: 2 wait states,
0011: 3 wait states
0100: 4 wait states,
0101: 5 wait states
0110: 6 wait states,
0111: 7 wait states
1111: (1+N) wait states, as determined by the WAIT
pin
Don’t use any other value.
15
14
13
12
11
10












B0E
W
0
CS0 enable



0: Disable
1: Enable
B01CS
Chip
Select/
Wait
Control
Register
FFFF
E480H
23
22
B1OM
W
0
0
Chip select output
waveform
00: ROM/SRAM
Don’t use any other
value.
21
20



B1BUS
0
Data bus
width
0: 16-bit
1: 8-bit
19
8
B0RCV
W
0
0
Number of dummy cycles
(Read recovery time)
00: 2 dummy cycles
01: 1 dummy cycle
10: No dummy cycle
11: Don’t use.
18
17
16
B1W
W
0
1
0
1
Number of wait-state cycles
0000: No wait state,
0001: 1 wait state
0010: 2 wait states,
0011: 3 wait states
0100: 4 wait states,
0110: 5 wait states
0110: 6 wait states,
0111: 7 wait states
1111: (1+N) wait states, as determined by the WAIT
pin
Don’t use any other value.
31
30
29
28
27
26












B1E
W
0
CS1 enable



0: Disable
1: Enable
TMP1941AF-276
9
25
24
B1RCV
W
0
0
Number of dummy cycles
(Read recovery time)
00: 2 dummy cycles
01: 1 dummy cycle
10: No dummy cycle
11: Don’t use.
2003-03-27
TMP1941AF
Chip Select/Wait Controller (4 of 4)
Mnemonic Name Address
7
6
B2OM
W
0
0
Chip select output
waveform
00: ROM/SRAM
Don’t use any other
value.
5
4



B2BUS
0
Data bus
width
0: 16-bit
1: 8-bit
3
2
1
0
B2W
W
0
1
0
Number of wait-state cycles
0000: No wait state,
0001: 1 wait state
0010: 2 wait states,
0011: 3 wait states
0100: 4 wait states,
0101: 5 wait states
0110: 6 wait states,
0111: 7 wait states
1
1111: (1+N) wait states, as determined by the WAIT
pin
Don’t use any other value.
B23CS
Chip
Select/
Wait
Control
Register
15
14
13
12












23
22
21
20
B3OM

W

0
0
Chip select output
waveform
00: ROM/SRAM
Don’t use any other
value.



B3BUS
FFFF
E484H
0
Data bus
width
0: 16-bit
1: 8-bit
11
10
19
29
28
27
26









B3E
W
0
CS3 enable



0: Disable
1: Enable
BEXCS
Chip
Select/
Wait
Control
Register
FFFF
E488H
0
0
Chip select output
waveform
00: ROM/SRAM
Don’t use any other
value.
5
4



BEXBUS
0
Data bus
width
0: 16-bit
1: 8-bit
3
16
25
24
B3RCV
W
0
0
Number of dummy cycles
(Read recovery time)
00: 2 dummy cycles
01: 1 dummy cycle
10: No dummy cycle
11: Don’t use.
2
1
0
0
1
BEXW
W
0
1
Sets the number of wait cycles
0000–0111: 0–7 wait states
1111: (1+N) wait states, as determined by the WAIT
pin
Don’t use any other value.
15
14
13
12
11
10


















TMP1941AF-277
17
W
0
1
0
1
Number of wait-state cycles
0000: No wait state,
0001: 1 wait state
0010: 2 wait states,
0011: 3 wait states
0100: 4 wait states,
0101: 5 wait states
0110: 6 wait states,
0111: 7 wait states
1111: (1+N) wait states, as determined by the WAIT
pin
Don’t use any other value.
30
6
0
0
Number of dummy cycles
(Read recovery time)
00: 2 dummy cycles
01: 1 dummy cycle
10: No dummy cycle
11: Don’t use.
B3W



BEXOM
W
8
B2RCV
W
18
31
7
9
B2E
B2M
W
W
1
0
CS2 enable CS2 space
select
0: Disable
1: Enable
0: Whole
4-Gbyte
space
1: CS
space
9
8
BEXRCV
W
0
0
Number of dummy cycles
(Read recovery time)
00: 2 dummy cycles
01: 1 dummy cycle
10: No dummy cycle
11: Don’t use.
2003-03-27
TMP1941AF
19.4 Clock Generator (CG)
Clock Generator (1 of 2)
Mnemonic Name Address
SYSCR0
System
Clock
Control
Register 0
FFFF
EE00H
7
6
5
4
3
2
1
0
XEN
XTEN
RXEN
RXTEN
RSYSCK
WUEF
PRCK1
PRCK0
1
High-speed
oscillator
0
Low-speed
oscillator
1
High-speed
oscillator
after exiting
STOP mode
R/W
0
0
Low-speed Clock select
oscillator
after exiting
after exiting STOP mode
STOP mode
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
0: Highspeed
1: Lowspeed
0
0
0
Prescaler clock select
Oscillator
warm-up
00: fperiph/4
period
(WUP) timer 01: fperiph/2
10: fperiph
On writes:
11: Reserved
0: Don’tcare
1: Start
WUP
On reads:
0: Expired
1: Not
expired



SYSCR1
SYSCR2
SYSCR3
System
Clock
Control
Register 1
System
Clock
Control
Register 2
System
Clock
Control
Register 3



FFFF
EE01H
FFFF
EE02H
DRVOSCH
R/W
0
High-speed
oscillator
drive
capability
0: High
1: Low
DRVOSCL
R/W
0
Low-speed
oscillator
drive
capability
0: High
1: Low



SCOSEL
R/W
0
SCOUT
output
select
FFFF
EE03H
SYSCK
0
System
clock (fsys)
select
ADCCLK
ADC
Conversion
Clock
Register



DFOSC
0
High-speed
oscillator
frequency
divide factor



0: Divide-by2
1: Divide-by1
WUPT1
WUPT0
R/W
R/W
1
0
Oscillator warm-up time
STBY1
STBY0
R/W
R/W
1
1
Standby mode select
00: Reserved
01: 28/input frequency
10: 214/input frequency
11: 216/input frequency
00: Reserved
01: STOP mode
10: SLEEP mode
11: IDLE mode



ALESEL
R/W
1
ALE output
width select












0: fsys × 0.5
1: fsys × 1.5



FFFF
EE04H
TMP1941AF-278



GEAR1
GEAR0
R/W
1
1
High-speed clock (fc) gear
select
00: fc
01: fc/2
10: fc/4
11: fc/8
0: Highspeed
0: fgear
(fgear)
1: fc
1: Lowspeed (fs)
0: fs
1: fsys



FPSEL
R/W
0
fperiph
select



DRVE
R/W
0
1: Pins are
driven in
STOP
mode.
0: Pins are
not driven
in STOP
mode.
LUPFG
LUPTM
R/W
0
0
PLL lock
PLL lock
0: Locked
time select
1: Unlocked 0: 216/input
frequency
1: 212/input
frequency
ADCCK1
ADCCK0
R/W
R/W
0
0
ADC conversion clock
(fadc) select
00: fsys/2
01: fsys/4
10: fsys/8
11: Don’t use.
2003-03-27
TMP1941AF
Clock Generator (2 of 2)
Mnemonic Name Address
IMCGA0
IMCGA1
IMCGA2
IMCGA3
IMCGB0
Interrupt
CG Control
Register
A0
Interrupt
CG Control
Register
A1
Interrupt
CG Control
Register
A2
Interrupt
CG Control
Register
A3
Interrupt
CG Control
Register
B0
IMCGB1
Interrupt
CG Control
Register
B1
IMCGB2
Interrupt
CG Control
Register
B2
IMCGB3
Interrupt
CG Control
Register
B3
7
6
5
4
3
2
1






EMCG01
EMCG00









FFFF
EE10H






FFFF
EE11H






FFFF
EE12H






FFFF
EE13H






FFFF
EE14H
FFFF
EE15H
FFFF
EE16H
R/W
1
0
Wake-up INT0 sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
EMCG11
EMCG10
R/W
1
0
Wake-up INT1 sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
EMCG21
EMCG20
R/W
1
0
Wake-up INT2 sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
0
INT0EN
R/W
0
INT0
enable
0: Disable
1: Enable









INT1EN
R/W
0
INT1
enable
0: Disable
1: Enable









INT2EN
R/W
0
INT2
enable
0: Disable
1: Enable
EMCG31
EMCG30


1
0
Wake-up INT3 sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge



EMCG41
EMCG40


1
0
Wake-up INT4 sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge











0
INT3
enable
0: Disable
1: Enable








0
INT4
enable
0: Disable
1: Enable










1
0
Must be written as 10.











0
Must be
written as
0.










1
0
Must be written as 10.











0
Must be
written as
0.















INTRTCEN
R/W
0
INTRTC
enable
FFFF
EE17H
EMCG71
EMCG72
R/W
1
0
Must be written as 11.
0:Disable
1: Enable



EICRCG
Interrupt
Request
Clear
Register







FFFF
EE20H
TMP1941AF-279




ICRCG2
ICRCG1
ICRCG0

W

0
0
0
Clear interrupt request
(Only when relevant interrupts are
programmed to be used to exit
STOP/SLEEP mode.)
000: INT0 100: INT4
001: INT1 101: Reserved
010: INT2 110: Reserved
011: INT3 111: INTRTC
2003-03-27
TMP1941AF
19.5 DMA Controller (DMAC)
DMA Controller (1 of 16)
Mnemonic Name Address
7
6
5
4
3
2
1
0
SAC0
DIO
DAC1
DAC0
TrSiz1
TrSiz0
DPS1
DPS0
0
Transfer size
0x: 32 bits
10: 16 bits
11: 8 bits
0
R/W
0
Source
address
count (bits 8
& 7)
00: Incremented
01: Decremented
1x: Fixed
0
Destination
(I/O)
0: Memory
1: I/O
0
0
Destination address
count
00: Incremented
01: Decremented
1x: Fixed
0
Device port size
0x: 32 bits
10: 16 bits
11: 8 bits
0
15
14
13
12
11
10
9
8

ExR
PosE
Lev
SReq
RelEn
SIO
SAC1
R/W
0
Must be
written as
0.
CCR0
DMA
Channel
Control
Register 0
FFFF
E200H
0
External
request
mode
1: External
transfer
request
0: Internal
transfer
request
0
Must be
written as
0.
0
Must be
written as
1.
0
Snoop
request
0: Disabled
1: Enabled
0
0
Bus release Source (I/O)
request
0: Memory
enable
1: I/O
0: Disabled
1: Enabled
0
Source
address
count (bits 8
& 7)
00: Incremented
01: Decremented
1x: Fixed
23
22
21
20
19
18
17
16
NIEn
AbIEn




Big

R/W
1
Normal
completion
interrupt
enable
0: Disabled
1: Enabled
1
Abnormal
termination
interrupt
enable
0: Disabled
1: Enabled
1
Must be
written as
0.
0
Must be
written as
0.
0
Must be
written as
0.
0
Must be
written as
0.
1
Must be
written as
0.
31
30
29
28
27
26
25
Str
W
0
1: Channel
0 start


0


0


0


0


0


0
TMP1941AF-280
0
Must be
written as
0.
24

W
0
Must be
written as
0.
2003-03-27
TMP1941AF
DMA Controller (2 of 16)
Mnemonic Name Address
7
6
5
4
3
2
1
0













0
0
0
0
0
R/W
0
Must be
written as 0.
CSR0
DMA
Channel
Status
Register 0
FFFF
E204H
0
Must be
written
as 0.
0
Must be
written
as 0.
15
14
13
12
11
10
9
8
















0
0
0
0
0
0
0
0








23
22
21
20
19
18
17
16
NC
AbC

BES
BED
Conf




0
0
24
R/W
0
0
R
0
0
0
0
1: Normal
1: Abnormal Must be
1: Bus error 1: Bus error 1: Configuration
completion termination written as 0.
(source)
(destination)
error
status flag status flag
31
30
29
28
27
26
25
Act







R







0
0
0
0
0
0
0
0
1: Channel
0 active
TMP1941AF-281
2003-03-27
TMP1941AF
DMA Controller (3 of 16)
Mnemonic Name Address
7
6
5
4
3
2
1
0
SAddr7
SAddr6
SAddr5
SAddr4
SAddr3
SAddr2
SAddr1
SAddr0
R/W
Undefined
15
14
13
12
11
10
9
8
SAddr15
SAddr14
SAddr13
SAddr12
SAddr11
SAddr10
SAddr9
SAddr8
R/W
SAR0
DMA
Source
Address
Register 0
Undefined
FFFF
E208H
23
22
21
20
19
18
17
16
SAddr23
SAddr22
SAddr21
SAddr20
SAddr19
SAddr18
SAddr17
SAddr16
R/W
Undefined
31
30
29
28
27
26
25
24
SAddr31
SAddr30
SAddr29
SAddr28
SAddr27
SAddr26
SAddr25
SAddr24
R/W
Undefined
7
6
5
4
3
2
1
0
DAddr7
DAddr6
DAddr5
DAddr4
DAddr3
DAddr2
DAddr1
DAddr0
R/W
Undefined
DAR0
DMA
Destination
Address
Register 0
FFFF
E20CH
15
14
13
12
11
10
9
8
DAddr15
DAddr14
DAddr13
DAddr12
DAddr11
DAddr10
DAddr9
DAddr8
R/W
Undefined
23
22
21
20
19
18
17
16
DAddr23
DAddr22
DAddr21
DAddr20
DAddr19
DAddr18
DAddr17
DAddr16
R/W
Undefined
31
30
29
28
27
26
25
24
DAddr31
DAddr30
DAddr29
DAddr28
DAddr27
DAddr26
DAddr25
DAddr24
R/W
Undefined
7
6
5
4
3
2
1
0
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
R/W
Undefined
BCR0
DMA
Byte Count
Register 0
FFFF
E210H
15
14
13
12
11
10
9
8
BC15
BC14
BC13
BC12
BC11
BC10
BC9
BC8
R/W
Undefined
23
22
21
20
19
18
17
16
BC23
BC22
BC21
BC20
BC19
BC18
BC17
BC16
R/W
Undefined
31
30
29
28
27
26
25
24








0
0
0
0

0
0
0
TMP1941AF-282
0
2003-03-27
TMP1941AF
DMA Controller (4 of 16)
Mnemonic Name Address
DTCR0
DMA
Transfer
Control
Register 0
FFFF
E218H
7
6
5
4
3
2
1
0


0


0
DACM2
DACM1
DACM0
SACM2
SACM1
SACM0
15
14
13
12
11
10
9
8








R/W
0
0
0
Bit position at which destination
addresses are counted
000: Bit 0
001: Bit 4
010: Bit 8
011: Bit 12
100: Bit 16
101: Reserved
110: Reserved
111: Reserved
0
0
0
Bit position at which source addresses
are counted
000: Bit 0
001: Bit 4
010: Bit 8
011: Bit 12
100: Bit 16
101: Reserved
110: Reserved
111: Reserved
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16








0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24








0
0
0
0
0
0
0
0
TMP1941AF-283
2003-03-27
TMP1941AF
DMA Controller (5 of 16)
Mnemonic Name Address
7
6
5
4
3
2
1
0
SAC0
DIO
DAC1
DAC0
TrSiz1
TrSiz0
DPS1
DPS0
0
0
0
0
0
0
0
0
R/W
Source
address
count (bits 8
& 7)
00: Incremented
01: Decremented
1x: Fixed
Destination
(I/O)
0: Memory
1: I/O
Destination address count Transfer size
00: Incremented
0x: 32 bits
01: Decremented
10: 16 bits
1x: Fixed
11: 8 bits
Device port size
0x: 32 bits
10: 16 bits
11: 8 bits
15
14
13
12
11
10
9
8

ExR
PosE
Lev
SReq
RelEn
SIO
SAC1
0
0
0
0
0
0
R/W
CCR1
DMA
Channel
Control
Register 1
FFFF
E220H
Must be
External
written as 0. request
mode
1: External
0: Internal
0
Must be
Must be
Snoop
written as 0. written as 1. request
0: Disabled
1: Enabled
0
Bus release Source (I/O)
request
0: Memory
enable
1: I/O
0: Disabled
1: Enabled
Source
address
count (bits 8
& 7)
00: Inc
01: Dec
1x: Fixed
23
22
21
20
19
18
17
16
NIEn
AbIEn




Big

0
0
1
0
R/W
1
Normal
completion
interrupt
enable
0: Disabled
1: Enabled
1
Abnormal
termination
interrupt
enable
0: Disabled
1: Enabled
1
0
Must be
Must be
Must be
Must be
Must be
Must be
written as 0. written as 0. written as 0. written as 0. written as 0. written as 0.
31
30
29
28
27
26
25
24
Str







W
0

0

0

0

0

0

0
W
0
1: Channel 1
start
Must be
written as 0.
TMP1941AF-284
2003-03-27
TMP1941AF
DMA Controller (6 of 16)
Mnemonic Name Address
7
6
5
4
3
2
1
0













0
0
0
0
0
R/W
0
0
0
Must be written Must be
Must be
as 0.
written as written as
0.
0.
CSR1
DMA
Channel
Status
Register 1
FFFF
E224H
15
14
13
12
11
10
9
8
















0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
NC
AbC

BES
BED
Conf




0
0
24
R/W
0
0
R
0
0
0
0
1: Normal
1: Abnormal Must be
1: Bus error 1: Bus error 1: Configuration
termination termination written as 0.
(source)
(destination)
error
status
status
flag
flag
31
30
29
28
27
26
25
Act







R







0
1: Channel 1
active
0
0
0
0
0
0
0
TMP1941AF-285
2003-03-27
TMP1941AF
DMA Controller (7 of 16)
Mnemonic Name Address
7
6
5
4
3
2
1
0
SAddr7
SAddr6
SAddr5
SAddr4
SAddr3
SAddr2
SAddr1
SAddr0
R/W
Undefined
15
14
13
12
11
10
9
8
SAddr15
SAddr14
SAddr13
SAddr12
SAddr11
SAddr10
SAddr9
SAddr8
R/W
SAR1
DMA
Source
Address
Register 1
FFFF
E228H
Undefined
23
22
21
20
19
18
17
16
SAddr23
SAddr22
SAddr21
SAddr20
SAddr19
SAddr18
SAddr17
SAddr16
R/W
Undefined
31
30
29
28
27
26
25
24
SAddr31
SAddr30
SAddr29
SAddr28
SAddr27
SAddr26
SAddr25
SAddr24
R/W
Undefined
7
6
5
4
3
2
1
0
DAddr7
DAddr6
DAddr5
DAddr4
DAddr3
DAddr2
DAddr1
DAddr0
R/W
Undefined
DAR1
DMA
Destination
Address
Register 1
15
14
13
12
11
10
9
8
DAddr15
DAddr14
DAddr13
DAddr12
DAddr11
DAddr10
DAddr9
DAddr8
R/W
Undefined
FFFF
E22CH
23
22
21
20
19
18
17
16
DAddr23
DAddr22
DAddr21
DAddr20
DAddr19
DAddr18
DAddr17
DAddr16
R/W
Undefined
31
30
29
28
27
26
25
24
DAddr31
DAddr30
DAddr29
DAddr28
DAddr27
DAddr26
DAddr25
DAddr24
R/W
Undefined
7
6
5
4
3
2
1
0
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
R/W
Undefined
BCR1
DMA
Byte Count
Register 1
15
14
13
12
11
10
9
8
BC15
BC14
BC13
BC12
BC11
BC10
BC9
BC8
R/W
Undefined
FFFF
E230H
23
22
21
20
19
18
17
16
BC23
BC22
BC21
BC20
BC19
BC18
BC17
BC16
R/W
Undefined
31
30
29
28
27
26
25
24








0
0
0
0

0
0
0
TMP1941AF-286
0
2003-03-27
TMP1941AF
DMA Controller (8 of 16)
Mnemonic Name Address
DTCR1
DMA
Transfer
Control
Register 1
FFFF
E238H
7
6
5
4
3
2
1
0


0


0
DACM2
DACM1
DACM0
SACM2
SACM1
SACM0
15
14
13
12
11
10
9
8








0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16








R/W
0
0
0
Bit position at which destination
addresses are counted
000: Bit 0
001: Bit 4
010: Bit 8
011: Bit 12
100: Bit 16
101: Reserved
110: Reserved
111: Reserved
0
0
0
Bit position at which source addresses
are counted
000: Bit 0
001: Bit 4
010: Bit 8
011: Bit 12
100: Bit 16
101: Reserved
110: Reserved
111: Reserved


0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24








0
0
0
0

0
0
0
TMP1941AF-287
0
2003-03-27
TMP1941AF
DMA Controller (9 of 16)
Mnemonic Name Address
7
6
5
4
3
2
1
0
SAC0
DIO
DAC1
DAC0
TrSiz1
TrSiz0
DPS1
DPS0
0
0
0
0
0
0
0
0
Source
address
count (bits
8 & 7)
00: Incremented
01: Decremented
1x: Fixed
Destination
(I/O)
0: Memory
1: I/O
R/W
Destination address
count
00: Incremented
01: Decremented
1x: Fixed
Transfer size
0x: 32 bits
10: 16 bits
11: 8 bits
Device port size
0x: 32 bits
10: 16 bits
11: 8 bits
15
14
13
12
11
10
9
8

ExR
PosE
Lev
SReq
RelEn
SIO
SAC1
0
0
0
0
R/W
Must be
written as
0.
CCR2
DMA
Channel
Control
Register 2
FFFF
E240H
External
request
mode
1: External
transfer
request
0: Internal
transfer
request
Must be
written as
0.
Must be
written as
1.
0
0
0
0
Snoop
request
0: Disabled
1: Enabled
Bus
release
request
enable
0: Disabled
1: Enabled
Source
(I/O)
0: Memory
1: I/O
Source
address
count (bits
8 & 7)
00: Incremented
01: Decremented
1x: Fixed
23
22
21
20
19
18
17
16
NIEn
AbIEn




Big

R/W
1
Normal
completion
interrupt
enable
0: Disabled
1: Enabled
1
Abnormal
termination
interrupt
enable
0: Disabled
1: Enabled
1
Must be
written as
0.
0
Must be
written as
0.
31
30
29
28
27
26
25
24
Str
W













W
0
1: Channel
2 start
0
0
0
0
0
0
TMP1941AF-288
0
Must be
written as
0.
0
Must be
written as
0.
1
Must be
written as
0.
0
Must be
written as
0.
0
Must be
written as
0.
2003-03-27
TMP1941AF
DMA Controller (10 of 16)
Mnemonic Name Address
CSR2
DMA
Channel
Status
Register 2
FFFF
E244H
7
6
5
4
3
2


0


0


0


0


0

15
14
13
12
11
10
9
8


0


0


0


0


0


0


0


0
23
22
21
20
19
18
17
16


0


0
AbC

BES
R/W
0
0
0
0
1: Normal
1: Abnormal Must be
1: Bus
completion termination written as 0.
error
status flag status flag
(source)
NC
0
Must be
written as 0.
BED
Conf
R
0
0
1: Bus error 1: Configuration
(destination)
error
1

R/W
0
Must be
written
as 0.
0

0
Must be
written
as 0.
31
30
29
28
27
26
25
24
Act
R
0
1: Channel
2 active


0


0


0


0


0


0


0
TMP1941AF-289
2003-03-27
TMP1941AF
DMA Controller (11 of 16)
Mnemonic Name Address
7
6
5
4
3
2
1
0
SAddr7
SAddr6
SAddr5
SAddr4
SAddr3
SAddr2
SAddr1
SAddr0
R/W
Undefined
15
14
13
12
11
10
9
8
SAddr15
SAddr14
SAddr13
SAddr12
SAddr11
SAddr10
SAddr9
SAddr8
R/W
SAR2
DMA
Source
Address
Register 2
Undefined
FFFF
E248H
23
22
21
20
19
18
17
16
SAddr23
SAddr22
SAddr21
SAddr20
SAddr19
SAddr18
SAddr17
SAddr16
R/W
Undefined
31
30
29
28
27
26
25
24
SAddr31
SAddr30
SAddr29
SAddr28
SAddr27
SAddr26
SAddr25
SAddr24
R/W
Undefined
7
6
5
4
3
2
1
0
DAddr7
DAddr6
DAddr5
DAddr4
DAddr3
DAddr2
DAddr1
DAddr0
R/W
Undefined
DAR2
DMA
Destination
Address
Register 2
FFFF
E24CH
15
14
13
12
11
10
9
8
DAddr15
DAddr14
DAddr13
DAddr12
DAddr11
DAddr10
DAddr9
DAddr8
R/W
Undefined
23
22
21
20
19
18
17
16
DAddr23
DAddr22
DAddr21
DAddr20
DAddr19
DAddr18
DAddr17
DAddr16
R/W
Undefined
31
30
29
28
27
26
25
24
DAddr31
DAddr30
DAddr29
DAddr28
DAddr27
DAddr26
DAddr25
DAddr24
R/W
Undefined
7
6
5
4
3
2
1
0
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
R/W
Undefined
BCR2
DMA
Byte Count
Register 2
FFFF
E250H
15
14
13
12
11
10
9
8
BC15
BC14
BC13
BC12
BC11
BC10
BC9
BC8
R/W
Undefined
23
22
21
20
19
18
17
16
BC23
BC22
BC21
BC20
BC19
BC18
BC17
BC16
R/W
Undefined
31
30
29
28
27
26
25
24








0
0
0
0

0
0
0
TMP1941AF-290
0
2003-03-27
TMP1941AF
DMA Controller (12 of 16)
Mnemonic Name Address
DTCR2
DMA
Transfer
Control
Register 2
FFFF
E258H
7
6
5
4
3
2
1
0


0


0
DACM2
DACM1
DACM0
SACM2
SACM1
SACM0
15
14
13
12
11
10
9
8








0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16








R/W
0
0
0
Bit position at which destination
addresses are counted
000: Bit 0
001: Bit 4
010: Bit 8
011: Bit 12
100: Bit 16
101: Reserved
110: Reserved
111: Reserved
0
0
0
Bit position at which source addresses
are counted
000: Bit 0
001: Bit 4
010: Bit 8
011: Bit 12
100: Bit 16
101: Reserved
110: Reserved
111: Reserved


0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24








0
0
0
0

0
0
0
TMP1941AF-291
0
2003-03-27
TMP1941AF
DMA Controller (13 of 16)
Mnemonic Name Address
FFFF
E260H
7
6
5
4
3
2
1
0
SAC0
DIO
DAC1
DAC0
TrSiz1
TrSiz0
DPS1
DPS0
0
0
0
0
0
0
0
0
Source
address
count (bits
8 & 7)
00: Incremented
01: Decremented
1x: Fixed
Destination
(I/O)
0: Memory
1: I/O
R/W
Destination address
count
00: Incremented
01: Decremented
1x: Fixed
Transfer size
0x: 32 bits
10: 16 bits
11: 8 bits
Device port size
0x: 32 bits
10: 16 bits
11: 8 bits
15
14
13
12
11
10
9
8

ExR
PosE
Lev
SReq
RelEn
SIO
SAC1
0
0
0
0
R/W
Must be
written as
0.
CCR3
DMA
Channel
Control
Register 3
External
request
mode
1: External
transfer
request
0: Internal
transfer
request
Must be
written as
0.
Must be
written as
1.
0
0
0
0
Snoop
request
0: Disabled
1: Enabled
Bus
release
request
enable
0: Disabled
1: Enabled
Source
(I/O)
0: Memory
1: I/O
Source
address
count (bits
8 & 7)
00: Incremented
01: Decremented
1x: Fixed
23
22
21
20
19
18
17
16
NIEn
AbIEn




Big

R/W
1
Normal
completion
interrupt
enable
0: Disabled
1: Enabled
1
Abnormal
termination
interrupt
enable
0: Disabled
1: Enabled
1
Must be
written as
0.
0
Must be
written as
0.
31
30
29
28
27
26
25
24
Str
W













W
0
1: Channel
3 start
0
0
0
0
0
0
TMP1941AF-292
0
Must be
written as
0.
0
Must be
written as
0.
1
Must be
written as
0.
0
Must be
written as
0.
0
Must be
written as
0.
2003-03-27
TMP1941AF
DMA Controller (14 of 16)
Mnemonic Name Address
CSR3
DMA
Channel
Status
Register 3
FFFF
E264H
7
6
5
4
3
2


0


0


0


0


0

15
14
13
12
11
10
9
8


0


0


0


0


0


0


0


0
23
22
21
20
19
18
17
16


0


0
0
Must be
written as 0.
AbC

BES
BED
Conf
R/W
R
0
0
0
0
0
0
1: Normal
1: Abnormal Must be
1: Bus error 1: Bus error 1: Configuration
termination termination written as 0.
(source)
(destination)
error
status flag
status flag
NC
1
0


R/W
0
0
Must be
Must be
written as written
0.
as 0.
31
30
29
28
27
26
25
24
Act
R
0
1: Channel
3 active


0


0


0


0


0


0


0
TMP1941AF-293
2003-03-27
TMP1941AF
DMA Controller (15 of 16)
Mnemonic Name Address
7
6
5
4
3
2
1
0
SAddr7
SAddr6
SAddr5
SAddr4
SAddr3
SAddr2
SAddr1
SAddr0
R/W
Undefined
15
14
13
12
11
10
9
8
SAddr15
SAddr14
SAddr13
SAddr12
SAddr11
SAddr10
SAddr9
SAddr8
R/W
SAR3
DMA
Source
Address
Register 3
Undefined
FFFF
E268H
23
22
21
20
19
18
17
16
SAddr23
SAddr22
SAddr21
SAddr20
SAddr19
SAddr18
SAddr17
SAddr16
R/W
Undefined
31
30
29
28
27
26
25
24
SAddr31
SAddr30
SAddr29
SAddr28
SAddr27
SAddr26
SAddr25
SAddr24
R/W
Undefined
7
6
5
4
3
2
1
0
DAddr7
DAddr6
DAddr5
DAddr4
DAddr3
DAddr2
DAddr1
DAddr0
R/W
Undefined
DAR3
DMA
Destination
Address
Register 3
FFFF
E26CH
15
14
13
12
11
10
9
8
DAddr15
DAddr14
DAddr13
DAddr12
DAddr11
DAddr10
DAddr9
DAddr8
R/W
Undefined
23
22
21
20
19
18
17
16
DAddr23
DAddr22
DAddr21
DAddr20
DAddr19
DAddr18
DAddr17
DAddr16
R/W
Undefined
31
30
29
28
27
26
25
24
DAddr31
DAddr30
DAddr29
DAddr28
DAddr27
DAddr26
DAddr25
DAddr24
R/W
Undefined
7
6
5
4
3
2
1
0
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
R/W
Undefined
BCR3
DMA
Byte Count
Register 3
FFFF
E270H
15
14
13
12
11
10
9
8
BC15
BC14
BC13
BC12
BC11
BC10
BC9
BC8
R/W
Undefined
23
22
21
20
19
18
17
16
BC23
BC22
BC21
BC20
BC19
BC18
BC17
BC16
R/W
Undefined
31
30
29
28
27
26
25
24








0
0
0
0

0
0
0
TMP1941AF-294
0
2003-03-27
TMP1941AF
DMA Controller (16 of 16)
Mnemonic Name Address
DTCR3
DMA
Transfer
Control
Register 3
FFFF
E278H
7
6
5
4
3
2
1
0


0


0
DACM2
DACM1
DACM0
SACM2
SACM1
SACM0
15
14
13
12
11
10
9
8








0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16








R/W
0
0
0
Bit position at which destination
addresses are counted
000: Bit 0
001: Bit 4
010: Bit 8
011: Bit 12
100: Bit 16
101: Reserved
110: Reserved
111: Reserved
0
0
0
Bit position at which source addresses
are counted
000: Bit 0
001: Bit 4
010: Bit 8
011: Bit 12
100: Bit 16
101: Reserved
110: Reserved
111: Reserved


0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24








0
0
0
0

0
DCR
DMA
Control
Register
FFFF
E280H
0
0
0
7
6
5
4
3
2
1
0


0


0


0


0


0


0


0


0
15
14
13
12
11
10
9
8


0


0


0


0


0


0


0


0
23
22
21
20
19
18
17
16


0


0


0


0


0


0


0


0
31
30
29
28
27
26
25
24
Rst
W
0
1: DMAC
software
reset


0


0


0


0


0


0


0
7
6
5
4
3
2
1
0
DOT7
DOT6
DOT5
DOT4
DOT3
DOT2
DOT1
DOT0
R/W
Undefined
DHR
DMA
Data
Holding
Register
FFFF
E28CH
15
14
13
12
11
10
9
8
DOT15
DOT14
DOT13
DOT12
DOT11
DOT10
DOT9
DOT8
R/W
Undefined
23
22
21
20
19
18
17
16
DOT23
DOT22
DOT21
DOT20
DOT19
DOT18
DOT17
DOT16
R/W
Undefined
31
30
29
28
27
26
25
24
DOT31
DOT30
DOT29
DOT28
DOT27
DOT26
DOT25
DOT24
R/W
Undefined
TMP1941AF-295
2003-03-27
TMP1941AF
19.6 8-Bit Timers (TMRAs)
Mnemonic Name Address
TA01RUN
TA23RUN
TMRA01
Run
Register
TMRA23
Run
Register
FFFF
F100H
FFFF
F108H
7
6
5
4
3
TA0RDE
R/W






I2TA01
0
Double
Buffering
0: Disable
1: Enable



TA2RDE
R/W






0
Double
Buffering
0: Disable
1: Enable



TA01M0
PWM01
PWM00
TA01M1
0
IDLE
0: Off
1: On
I2TA23
0
IDLE
0: Off
1: On
TA1CLK1
2
1
0
TA01PRUN
TA1RUN
R/W
0
Prescalar
Run/Stop
Control
0: Stop
1: Run
0
0
Run/Stop Control
0: Stop & clear
1: Run
TA23PRUN
TA3RUN
R/W
0
Prescalar
Run/Stop
Control
0: Stop
1: Run
TA1CLK0
TA0RUN
TA2RUN
0
0
Run/Stop Control
0: Stop & clear
1: Run
TA0CLK1
TA0CLK0
R/W
TA01MOD
TMRA01
Mode
Register
FFFF
F104H
0
0
Operating mode
00: 8-bit interval timer
01: 16-bit interval timer
10: 8-bit PPG
11: 8-bit PWM
TA23M1
TA23M0
0
PWM period
00: Reserved
6
01: 2 -1
10: 27-1
11: 28-1
PWM21
0
0
0
TMRA1 clock source
00: TA0TRG
01: φT1
10: φT16
11: φT256
PWM20
TA3CLK1
TA3CLK0
0
0
TMRA0 clock source
00: TA0IN input
01: φT1
10: φT4
11: φT16
TA2CLK1
TA2CLK0
R/W
TA23MOD
TA1FFCR
TA3FFCR
TMRA23
Mode
Register
TMRA01
Timer FlipFlop
Control
Register
TMRA23
Timer FlipFlop
Control
Register
FFFF
F10CH
0
0
Operating mode
00: 8-bit interval timer
01: 16-bit interval timer
10: 8-bit PPG
11: 8-bit PWM
0
PWM period
00: Reserved
6
01: 2 -1
10: 27-1
11: 28-1
0
























FFFF
F105H
FFFF
F10DH
TMP1941AF-296
0
0
TMRA3 clock source
00: TA2TRG
01: φT1
10: φT16
11: φT256
0
0
TMRA2 clock source
00: TA2IN input pin
01: φT1
10: φT4
11: φT16
TAFF1C1
TAFF1C0
TAFF1IE
R/W
1
1
0
00: Toggles TA1FF.
TA1FF
(software toggle)
toggle
01: Sets TA1FF to 1.
enable
10: Clears TA1FF to 0.
0: Disable
11: Don’t-care
1: Enable
This field is always read
as 11.
TAFF3C1
TAFF3C0
TAFF3IE
R/W
1
1
0
00: Toggles TA3FF
TA3FF
(software toggle).
toggle
01: Sets TA3FF to 1
enable
10: Clears TA3FF to 0
0: Disable
11: Don’t care
1: Enable
This field is always read
as 11.
TAFF1IS
0
TA1FF
toggle
trigger
0: TMRA0
1: TMRA1
TAFF3IS
0
TA3FF
trigger
0: TMRA2
1: TMRA3
2003-03-27
TMP1941AF
19.7 16-Bit Timer/Event Counters (TMRBs)
16-Bit Timer Control (1 of 2)
Mnemonic Name Address
7
6
5
4
3
TB0RDE







I2TB0


















TB0CP0
W*
1
Software
capture
0: Capture
1: Don’t
care
TB0CPM1
R/W
TB0RUN
TMRB0
Run
Register
FFFF
F180H
0
Double
Buffering
0: Disable
1: Enable
0
Must be
written as
0.

TB1RDE
R/W
TB1RUN
TMRB1
Run
Register
FFFF
F190H
0
Double
Buffering
0: Disable
1: Enable
0
Must be
written as
0.

TB2RDE
R/W
TB2RUN
TMRB2
Run
Register
FFFF
F1A0H
0
Double
Buffering
0: Disable
1: Enable
0
Must be
written as
0.

TB3RDE
R/W
TB3RUN
TMRB3
Run
Register
FFFF
F1B0H
0
Double
Buffering
0: Disable
1: Enable
0
Must be
written as
0.


R/W
TB0MOD
TMRB0
Mode
Register
FFFF
F182H
0
0
Must be written as 00.


R/W
TB1MOD
TMRB1
Mode
Register
FFFF
F192H
0
0
Must be written as 00.


R/W
TB2MOD
TMRB2
Mode
Register
FFFF
F1A2H
0
0
Must be written as 00.


R/W
TB3MOD
TMRB3
Mode
Register
FFFF
F1B2H
0
0
Must be written as 00.
TB1CP0
W*
1
Software
capture
0: Capture
1: Don’t
care
TB2CP0
W*
1
Software
capture
0: Capture
1: Don’t
care
TB3CP0
W*
1
Software
capture
0: Capture
1: Don’t
care
0
IDLE
0: Off
1: On
I2TB1
0
IDLE
0: Off
1: On
I2TB2
0
IDLE
0: Off
1: On
I2TB3
0
IDLE
0: Off
1: On
2
TB0RUN
R/W
0
Run/Stop
Control
0: Stop &
clear
1: Run
TB1PRUN
R/W
0
Prescalar
Run/Stop
Control
0: Stop
1: Run



TB1RUN
R/W
0
Run/Stop
Control
0: Stop &
clear
1: Run
TB2PRUN
R/W
0
Prescalar
Run/Stop
Control
0: Stop
1: Run



TB2RUN
R/W
0
Run/Stop
Control
0: Stop &
clear
1: Run
TB3PRUN
R/W
0
Prescalar
Run/Stop
Control
0: Stop
1: Run



TB3RUN
R/W
0
Run/Stop
Control
0: Stop &
clear
1: Run
TB0CPM0
TB1CPM0
0
0
Capture triggers
00: Disabled
01: TB1IN0↑TB1IN1↑
10: TB1IN0↑TB1IN0↓
11: TA1OUT↑TA1OUT↓
TB2CPM1
TB2CPM0
0
0
Capture triggers
00: Disabled
01: TB2IN0↑TB2IN1↑
10: TB2IN0↑TB2IN0↓
11: TA1OUT↑TA1OUT↓
TB3CPM1
TB3CPM0
0
0
Capture triggers
00: Disabled
01: Disabled
10: Disabled
11: TA1OUT↑TA1OUT↓
TMP1941AF-297
0



0
0
Capture triggers
00: Disabled
01: TB0IN0↑TB0IN1↑
10: TB0IN0↑TB0IN0↓
11: TA1OUT↑TA1OUT↓
TB1CPM1
1
TB0PRUN
R/W
0
Prescalar
Run/Stop
Control
0: Stop
1: Run
TB0CLE
R/W
0
UC0 clear
control
0: Disable
1: Enable
TB1CLE
R/W
0
UC1 clear
control
0: Disable
1: Enable
TB2CLE
R/W
0
UC2 clear
control
0: Disable
1: Enable
TB3CLE
R/W
0
UC3 clear
control
0: Disable
1: Enable
TB0CLK1
TB0CLK0
0
0
TMRB0 clock source
00: TB0IN0 input
01: φT1
10: φT4
11: φT16
TB1CLK1
TB1CLK0
0
0
TMRB1 clock source
00: TB1IN0 input
01: φT1
10: φT4
11: φT16
TB2CLK1
TB2CLK0
0
0
TMRB2 clock source
00: TB2IN0 input
01: φT1
10: φT4
11: φT16
TB3CLK1
TB3CLK0
0
0
TMRB3 clock source
00: TB3IN0 input
01: φT1
10: φT4
11: φT16
2003-03-27
TMP1941AF
16-Bit Timer Control (2 of 2)
Mnemonic Name Address
TB0FFCR
TMRB0
Timer FlipFlop
Control
Register
7
6
5


TB0C1T1
W*
1
1
Must be written as 11.
FFFF
F183H
* This field is always
read as 11.


W*
TB1FFCR
TMRB1
Timer FlipFlop
Control
Register
1
1
Must be written as 11.
FFFF
F193H
* This field is always
read as 11.


W*
TB2FFCR
TMRB2
Timer FlipFlop
Control
Register
1
1
Must be written as 11.
FFFF
F1A3H
* This field is always
read as 11.


W*
TB3FFCR
TMRB3
Timer FlipFlop
Control
Register
1
1
Must be written as 11.
FFFF
F1B3H
* This field is always
read as 11.
4
3
TB0C0T1
TB0E1T1
R/W
0
0
0
TB0FF0 toggle-trigger
0: Trigger disabled
1: Trigger enabled
UC0
→TB0CP1
UC0 →
TB0CP0
UC0 =
TB0RG1
TB1C1T1
TB1C0T1
TB1E1T1
R/W
0
0
0
TB1FF0 toggle-trigger
0: Trigger disabled
1: Trigger enabled
UC1 →
TB1CP1
UC1 →
TB1CP0
UC1 =
TB1RG1
TB2C1T1
TB2C0T1
TB2E1T1
R/W
0
0
0
TB2FF0 toggle-trigger
0: Trigger disabled
1: Trigger enabled
UC2 →
TB2CP1
UC2 →
TB2CP0
UC2 =
TB2RG1
TB3C1T1
TB3C0T1
TB3E1T1
R/W
0
0
0
TB3FF0 toggle-trigger
0: Trigger disabled
1: Trigger enabled
UC3 →
TB3CP1
UC3 →
TB3CP0
TMP1941AF-298
UC3 =
TB3RG1
2
TB0E0T1
0
UC0 =
TB0RG0
TB1E0T1
0
UC1 =
TB1RG0
TB2E0T1
0
UC2 =
TB2RG0
TB3E0T1
0
UC3 =
TB3RG0
1
0
TB0FF0C1 TB0FF0C0
W*
1
1
TB0FF0 control
00: Toggle
01: Set
10: Clear
11: Don’t care
* This field is always
read as 11.
TB1FF0C1 TB1FF0C0
W*
1
1
TB1FF0 control
00: Toggle
01: Set
10: Clear
11: Don’t care
* This field is always
read as 11.
TB2FF0C1 TB2FF0C0
W*
1
1
TB2FF0 control
00: Toggle
01: Set
10: Clear
11: Don’t care
* This field is always
read as 11.
TB3FF0C1 TB3FF0C0
W*
1
1
TB3FF0 control
00: Toggle
01: Set
10: Clear
11: Don’t care
* This field is always
read as 11.
2003-03-27
TMP1941AF
19.8 Serial I/O (SIO)
SIO0
Mnemonic Name Address
SC0CR
SC0MOD0
BR0CR
BR0ADD
SC0MOD1
Serial
Channel 0
Control
Register
FFFF
F201H
Serial
Channel 0
Mode
Register 0
FFFF
F202H
Baud Rate
Generator 0
Control
Register
FFFF
F203H
7
RB8
R
0
Bit 8 of a
received
character
TB8
FFFF
F204H
Serial
Channel 0
Mode
Register 1
FFFF
F205H
5
PE
R/W
0
0
Parity type Parity
0: Odd
0: Disabled
1: Even
1: Enabled
CTSE
RXE
4
3
2
OERR
PERR
FERR
R (Cleared when read)
0
0
0
1: Error has occurred.
Overrun
Parity
Framing
WU
SM1
1
0
SCLKS
IOC
R/W
0
0:SCLK0↑
1:SCLK0↓
SM0
0
0: Baud rate
generator
1: SCLK0
input
SC1
SC0
R/W
0
Bit 8 of a
transmitted
character
0
Handshake
control
0: Disables
CTS
operation
1: Enables
CTS
operation

BR0ADDE
0
Receive
control
0: Disables
receiver
1: Enables
receiver
BR0CK1
0
Wake-up
function
0: Disabled
1: Enabled
0
0
Serial transfer mode
00: I/O Interface mode
01: 7-bit UART mode
10: 8-bit UART mode
11: 9-bit UART mode
BR0CK0
0
0
Serial clock (for UART)
00: TA0TRG (timer)
01: Baud rate generator
10: Internal fsys/2 clock
11: External clock
(SCLK0 input)
BR0S3
BR0S2
BR0S1
0
0
0
BR0S0
R/W
0
Must be
written as
0.
Baud Rate
Generator 0
Control
Register
6
EVEN



I2S0
R/W
0
IDLE
0: Off
1: On
0
N+
(16–K)/16
function
0: Disabled
1: Enabled



FDPX0
R/W
0
Synchronous
0: Halfduplex
1: Fullduplex
0
00: φT0
01: φT2
10: φT8
11: φT32
0
Clock divisor value N






BR0K3









TMP1941AF-299
0
BR0K2
BR0K1
BR0K0
R/W
0
0
0
Value of K in N+(16–K)/16






0



2003-03-27
TMP1941AF
SIO1
Mnemonic Name Address
SC1CR
Serial
Channel 1
Control
Register
FFFF
F209H
7
RB8
R
0
Bit 8 of a
received
character
6
5
EVEN
PE
R/W
0
0
Parity type Parity
0: Odd
0: Disabled
1: Even
1: Enabled
TB8
CTSE
RXE
4
3
2
OERR
PERR
FERR
R (Cleared when read)
0
0
0
1: Error has occurred.
Overrun
Parity
WU
SM1
Framing
1
0
SCLKS
IOC
R/W
0
0
0: SCLK1↑ 0: Baud rate
1: SCLK1↓
generator
1: SCLK1
input
SM0
SC1
SC0
R/W
SC1MOD0
Serial
Channel 1
Mode
Register 0
FFFF
F20AH
0
Bit 8 of a
transmitted
character
0
Handshake
control
0: Disables
CTS
operation
1: Enables
CTS
operation
0
Receive
control
0: Disables
receiver
1: Enables
receiver
0
Wake-up
function
0: Disabled
1: Enabled

BR1ADDE
BR1CK1
BR1CK0
0
0
Serial transfer mode
00: I/O Interface mode
01: 7-bit UART mode
10: 8-bit UART mode
11: 9-bit UART mode
0
0
Serial clock (for UART)
00: TA0TRG (timer)
01: Baud rate generator
10: Internal fsys/2 clock
11: External clock
(SCLK1 input)
BR1S3
BR1S2
BR1S1
BR1S0
0
0
0
0
R/W
BR1CR
BR1ADD
Baud Rate
Generator 1
Control
Register
FFFF
F20BH
Baud Rate
Generator 1
Control
Register
FFFF
F20CH
0
Must be
written as
0.
0
N+
(16–K)/16
function
0: Disabled
1: Enabled



I2S0
SC1MOD1
FFFF
F20DH
0
IDLE
0: Off
1: On
0
Clock divisor value N









BRK1K3
FDPX0









R/W
Serial
Channel 1
Mode
Register 1
0
00: φT0
01: φT2
10: φT8
11: φT32
0
Synchronous
0: Halfduplex
1: Fullduplex
TMP1941AF-300
BRK1K2
BRK1K1
BRK1K0
R/W
0
0
0
Value of K in N+(16–K)/16






0



2003-03-27
TMP1941AF
SIO3
Mnemonic Name Address
SC3CR
Serial
Channel 3
Control
Register
7
6
5
4
3
2
1
0
RB8
EVEN
PE
OERR
PERR
FERR


0
0
0
Parity type
0: Odd
1: Even
Parity
0: Disabled
1: Enabled
CTSE
RXE
R
FFFF
F281H
0
Bit 8 of a
received
character
TB8
R/W
R (Cleared when read)
0
R/W
0
WU
0
Must be written as 00.
1: Error has occurred.
Overrun
0
Parity
Framing
SM1
SM0
0
0
SC1
SC0
0
0
R/W
SC3MOD0
Serial
Channel 3
Mode
Register 0
0
FFFF
F282H
Bit 8 of a
transmitted
character

0
Must be
written as
0.
BR3ADDE
0
0
Receive
control
0: Disables
receiver
1: Enables
receiver
Wake-up
function
0: Disabled
1: Enabled
BR3CK1
BR3CK0
Serial transfer mode
00: Reserved
01: 7-bit UART mode
10: 8-bit UART mode
11: 9-bit UART mode
Serial clock (for UART)
00: TA0TRG (timer)
01: Baud rate generator
10: Internal fsys/2 clock
11: Don’t care
BR3S3
BR3S2
BR3S1
BR3S0
0
0
0
0
R/W
BR3CR
BR3ADD
SC3MOD1
Baud Rate
Generator 3
Control
Register
FFFF
F283H
Baud Rate
Generator 3
Control
Register
FFFF
F284H
Serial
Channel 3
Mode
Register 1
0
FFFF
F285H
Must be
written as
0.
0
N+
(16–K)/16
function
0: Disabled
1: Enabled
0
0
00: φT0
01: φT2
10: φT8
11: φT32
Clock divisor value N
















BR3K3
BR3K2
BR3K1
BR3K0
0
0
R/W
0
0
Value of K in N+(16–K)/16
I2S0







R/W







0







4
3
2
IDLE
0: Off
1: On
SIO4
Mnemonic Name Address
SC4CR
Serial
Channel 4
Control
Register
FFFF
F289H
7
RB8
R
0
Bit 8 of a
received
character
TB8
6
5
EVEN
PE
R/W
0
0
Parity type Parity
0: Odd
0: Disabled
1: Even
1: Enabled
CTSE
RXE
OERR
PERR
FERR
R (Cleared when read)
0
0
0
1: Error has occurred.
Overrun
WU
Parity
Framing
SM1
SM0
1
0


R/W
0
0
Must be written as 00.
SC1
SC0
R/W
SC4MOD0
Serial
Channel 4
Mode
Register 0
FFFF
F28AH
0
Bit 8 of a
transmitted
character

0
Must be
written as
0.
BR4ADDE
0
Receive
control
0: Disables
receiver
1: Enables
receiver
0
Wake-up
function
0: Disabled
1: Enabled
BR4CK1
BR4CK0
0
0
Serial transfer mode
00: Reserved
01: 7-bit UART mode
10: 8-bit UART mode
11: 9-bit UART mode
0
0
Serial clock (for UART)
00: TA0TRG (timer)
01: Baud rate generator
10: Internal fsys/2 clock
11: Don’t care
BR4S3
BR4S2
BR4S1
BR4S0
0
0
0
0
R/W
Baud Rate
Generator 4
Control
Register
FFFF
F28BH
BR4ADD
Baud Rate
Generator 4
Control
Register
FFFF
F28CH
SC4MOD1
Serial
Channel 4
Mode
Register 1
BR4CR
FFFF
F28DH
0
Must be
written as
0.



I2S0
R/W
0
IDLE
0: Off
1: On
0
N+
(16–K)/16
function
0: Disabled
1: Enabled
0
00: φT0
01: φT2
10: φT8
11: φT32
0
Clock divisor value N









BR4K3












TMP1941AF-301
BR4K2
BR4K1
BR4K0
R/W
0
0
0
Value of K in N+(16–K)/16






0



2003-03-27
TMP1941AF
19.9 Serial Bus Interface (SBI)
Mnemonic Name Address
7
BC2
6
BC1
5
BC0
4
3


W
R/W
0
0
0
0
Number of bits per transfer
ACK clock
(when ACK = 0)
pulse
000: 8, 001: 1, 010: 2
0: No ACK
011: 3, 100: 4, 101: 5
1: ACK
110: 6, 111: 7
SIOS
SIOINH
SIOM1
SIOM0
W
0
0
0
0
FFFF
Start
Abort
Transfer mode
F240H
transfer
transfer
00: Transmit mode
(SIO Mode) 0: Stop
0: Continue 01: Reserved
1: Start
1: Abort
10: Transmit/Receive
mode
11: Receive mode
Serial Bus
Interface
Control
Register 1
SBI0DBR
SBI Data
Buffer
Register
FFFF
F241H
DB7
DB6
DB5
SA6
SA5
SA4



DB4
DB3
R (receive) / W (transmit)
Undefined
SA3
1
0/
SCK0
SCK2
SCK1
SWRMON
W
W
R/W
0
0
1
Internal SCL output clock frequency
(on writes) / Software reset monitor
000: 4, 001: 5, 010: 6
011: 7, 100: 8, 101: 9
110: 10, 111: Reserved
SCK2
SCK1
SCK0
W
R/W
0
0
1
Serial clock frequency (on writes) /
Software reset monitor
000: 3, 001: 4, 010: 5
011: 6, 100: 7, 101: 8
110: 9, 111: External clock

ACK
FFFF
F240H
(I2C Bus
Mode)
SBI0CR1
2
DB2
DB1
DB0
SA2
SA1
SA0
ALS
0
0
0
0
Address
recognition
0:
Recognize
1: Does not
recognize
W
0
I2C0AR
I2C bus
Address
Register
FFFF
F242H
0
0
0
When the SBI is addressed as a slave, this field specifies a 7-bit I2C-bus address to which the
SBI responds.
MST
TRX
BB
PIN
SBIM1
SBIM0
0
0
SWRST1
SWRST0
0
0
W
0
Master/
slave
FFFF
F243H
(I2C Bus
Mode)
SBI0CR2 on
writes
SBI0SR
on reads
MST
TRX
0
START/
STOP
generation
BB
1
INTSBI
interrupt
clear
PIN
Master/
slave
0
Transmit/
receive
0
I2C Bus
status
1
INTS2
interrupt
status












FFFF
F243H
(SIO Mode)
SBI0BR0
Serial Bus
Interface
Control
Register 0
SBI0BR1
Serial Bus
Interface
Control
Register 1
FFFF
F244H
FFFF
F245H
Operating mode
00: Port mode
01: SIO mode
10: I2C Bus mode
11: Reserved
AL
Software reset
A write of 10 followed by
a write of 01
AAS
AD0
LRB
R
0
Serial Bus
Interface
Control 2
/Status
Register
0
Transmit/
receive



P4EN
R/W
0
Internal
clock
0: Off
1: On
I2SBI0
R/W
0
IDLE
0: Off
1: On



0
0
0
0
Arbitration
lost
0: 
1: Detected
Addressed
as slave
0: 
1: Detected
Address 0
(general
call)
0: 
1: Detected
Last
received bit
0: 0
1: 1
SEF


0
0




Serial
transfer
status
0:
Terminated
1: In
progress
Shift
operation
status
0:
Terminated
1: In
progress
SIOF
R






























TMP1941AF-302

W
0
Must be
written as
0.



2003-03-27
TMP1941AF
19.10 A/D Converter (ADC)
Mnemonic Name Address
7
6
5
4
3
2
1
0
EOCF
ADBF


ITM0
REPEAT
SCAN
ADS
R
ADMOD0
A/D Mode
Control
Register 0
FFFF
F310H
0
End-ofconversion
flag
0: Before
conversion
or
conversion
in progress
1:
Conversion
completed
0
A/D
conversion
busy flag
0: Idle
1:
Conversion
in progress
VREFON
I2AD
R/W
ADMOD1
ADREG04L
ADREG04H
ADREG15L
A/D Mode
Control
Register 1
0
VREF
control
0: Off
1: On
FFFF
F300H
A/D
Conversion
Result
Reg 0/4 High
FFFF
F301H



ADTRGE
A/D
Conversion
Result
Reg 1/5 Low
FFFF
F302H
0
External
conversion
trigger
0: Disable
1: Enable
ADREG37L
AD Result
Reg 3/7 low
FFFF
F306H
ADREG37H
A/D
Conversion
Result
Reg 3/7 High
FFFF
F307H
000
001
010
011
SCAN=0
AN0
AN1
AN2
AN3
100
101
110
111
AN4
AN5
AN6
AN7
0
SCAN=1
AN0
AN0 →AN1
AN0 → AN1 → AN2
AN0 → AN1 → AN2 →
AN3
AN4
AN4 → AN5
AN4 → AN5 → AN6
AN6 → AN7


ADR0RF
R
Undefined





0
ADR07
ADR06
ADR05
ADR04
ADR03
ADR02




ADR1RF
R
ADR08
R
Undefined
ADR10
R
Undefined
ADR18











0
ADR17
ADR16
ADR15
ADR14
ADR13
ADR12




ADR2RF
R
R
Undefined
ADR20
R
Undefined
ADR29
FFFF
F305H
0
0
Analog input channel select


ADR21
A/D
Conversion
ADREG26H
Result
Reg 2/6 High
ADCH0


ADR19
FFFF
F304H
ADCH1
R/W


ADR11
A/D
Conversion
Result
Reg 2/6 Low
ADCH2


ADR00
ADR09
FFFF
F303H
ADCCLK



0
1: A/D
conversion
start
R
ADR01
A/D
Conversion
Result
Reg 0/4 Low
A/D
Conversion
Clock Select
Register
R/W
0
0
0
Interrupt
1:
1: Channel
timing in
Continuous scan
fixedconversion conversion
channel
continuous
conversion
mode
0
Must be
written as
0.
FFFF
F311H
A/D
Conversion
ADREG15H
Result
Reg 1/5 High
ADREG26L
0
IDLE
0: Off
1: On
0
Must be
written as
0.
ADR28











0
ADR27
ADR26
ADR25
ADR24
ADR23
ADR22









ADR3RF
R
0
ADR35
ADR34
ADR33
ADR32
ADCCK1
R
Undefined
ADR31
ADR30
R
Undefined
ADR39
ADR38






ADR37
ADR36
R
Undefined


















FFFF
EE04H
ADCCK0
R/W
0
0
A/D conversion clock
00: fsys/2
01: fsys/4
10: fsys/8
11: Reserved
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19.11 Watchdog Timer (WDT)
Mnemonic Name Address
WDMOD
WDT
Mode
Register
WDCR
WDT
Control
Register
FFFF
F090H
7
WDTE
R/W
1
1: WDT
enable
6
5
4
3
2
WDTP1
WDTP0






I2WDT
R/W
0
0
00: 216/fsys
01: 218/ fsys
10: 220/ fsys
11: 222/ fsys
0
IDLE
0: Off
1: On
1
0
RESCR
R/W
0
1: System
reset

0
Must be
written as
0.

W

B1H: WDT disable code; 4EH: WDT clear-count code
FFFF
F091H
19.12 Real-Time Clock (RTC)
Mnemonic Name Address
RTCCR
RTC
Control
Register
FFFF
F0A0H
RTCREG
RTC
Accumulator
Register
FFFF
F0A4H
7

R/W
0
Must be
written as
0.
RUI7
6
5
4









RUI6
RUI5
RUI4
3
2
1
0
RTCRCLR
RTCSEL1
RTCSEL0
R/W
R/W
0
0
0
14
0: Clears
00: 2 /fs
13
Accumulator. 01: 2 /fs
10: 212/fs
11: 211/fs
RTCRUN
R/W
0
0: Stop and
clear the
counter.
1: Begin
counting.
RUI3
RUI2
RUI1
RUI0
0
0
0
0
R
0
0
0
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20. I/O Port Equivalent-Circuit Diagrams
•
How to read circuit diagrams
The circuit diagrams in this chapter are drawn using the same gate symbols as for the 74HCxx Series
standard CMOS logic ICs.
The signal named STOP has a unique function. This signal goes active-high if the CPU sets the HALT
bit when the STBY[1:0] field in the SYSCR2 register is programmed to 01 (i.e., STOP mode) and the
Drive Enable (DRVE) bit in the same register is cleared. If the DRVE bit is set, the STOP signal remains
inactive (at logic 0).
•
The input protection circuit has a resistor in the range of several tens to several hundreds of ohms.
■ AD0–AD7, AD8–AD15, A8–A15, P44, P71, P73–P76, P80–P87, P91–P92, P94–P95, PA0–PA5
Vcc
Output Data
P-ch
Output Enable
STOP
N-ch
Input/Output
Input Data
Input Enable
■ A16–A23, A0–A7, RD , WR
Vcc
Output Data
Output
STOP
■ HWR , WAIT , BUSRQ , BUSAK , R / W , P37, P40–43
Vcc
Output Data
P-ch
Output Enable
STOP
N-ch
Vcc
Programmable
Pullup Resistor
Input/Output
Input Data
Input Enable
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■ Port 5 (AN0–AN7)
Analog Input
Channel Select
Analog Input
Input
Input Data
Input Enable
■ P77 (INT0)
Vcc
Output Data
Output Enable
STOP
Input/Output
Input Data
Schmitt-Trigger
■ P70, P72, P90, P93, PA6–PA7
Vcc
Output Data
P-ch
Open-Drain
Output Enable
N-ch
Output Enable
STOP
Input Data
Input/Output
Input Enable
■ P96 (XT1), P97 (XT2)
Clock
Input Enable
Oscillator Circuit
Input Data
P97(XT2)
Output Data
Output Enable
Input Enable
Input Data
P96(XT1)
Output Data
Output Enable
STOP
Low-Frequency
Oscillator Enable
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■ NMI , AM0–AM1, PLLOFF
NMI
PLLOFF
Input
Schmitt-Trigger
■ ALE
Vcc
Internal ALE
P-ch
Output
N-ch
Output Enable
■ RESET
Vcc
Input
Reset
Schmitt-Trigger
WDTOUT
Reset Enable
■ X1, X2
Oscillator Circuit
X2
High-Frequency
Oscillator Enable
X1
Clock
■ VREFH, VREFL
VREFON
P-ch
Ladder Resistors
VREFH
VREFL
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21. Notations, Precautions and Restrictions
21.1 Notations and Terms
(1) I/O register fields are often referred to as <register_mnemonic>.<field_name> for the interest of
brevity. For example, TA01RUN.TA0RUN means the TA0RUN bit in the TA01RUN register.
(2) fc, fs, fsys, state
fosc:
Clock supplied from the X1 and X2 pins
fpll:
Clock generated by the on-chip PLL
fc:
Clock selected by the PLLOFF pin
fs:
Clock supplied from the XT1 and XT2 pins
fgear: Clock selected by the SYSCR1.GEAR[1:0] bits
fsys:
Clock selected by the SYSCR1.SYSCK bit
The fsys cycle is referred to as a state.
In addition, the clock selected by the SYSCR1.FPSEL bit and the prescalar clock source selected by
the SYSCR0.PRCK[1:0] bits are referred to as fperiph and φT0 respectively.
21.2 Precautions and Restrictions
(1) Processor Revision Identifier
The Process Revision Identifier (PRId) register in the TX19 core of the TMP1941AF contains
0x0000_2C90.
(2) AM0– AM1 Pins
The BW0 and BW1 pins must be connected to the DVcc pin to ensure that their signal levels do not
fluctuate during chip operation.
(3) Oscillator Warm-Up Counter
If an external crystal is utilized, an interrupt signal programmed to bring the TMP1941AF out of
STOP mode triggers the on-chip warm-up counter. The system clock is not supplied to the on-chip logic
until the warm-up counter expires.
(4) Programmable Pullup Resistors
When port pins are configured as input ports, the integrated pullup resistors can be enabled and
disabled under software control. The pullup resistors are not programmable when port pins are
configured as output ports.
The relevant port registers must be programmed by using store instructions.
(5) External Bus Mastership
The pin states while the bus is granted to an external device are described in Chapter 7, I/O Ports.
(6) Watchdog Timer (WDT)
Upon reset, the WDT is enabled. If the watchdog timer function is not required, it must be disabled
after reset. When relevant pins are configured as bus arbitration signals, the I/O peripherals including
the WDT can operate during external bus mastership.
(7) A/D Converter (ADC)
The ladder resistor network between the VREFH and VREFL pins can be disconnected under
software control. This helps to reduce power dissipation, for example, in STOP mode.
(8) Undefined Bits in I/O Registers
Undefined I/O register bits are read as undefined states. Therefore, software must be coded without
relying on the states of any undefined bits.
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(9) Usage Restrictions
Overflow Exception #1
Problem:
When an overflow exception is taken, the EPC register might contain an incorrect return address, pointing
to the instruction immediately following the one that caused an overflow.
The restart location in the EPC register should be the address of the arithmetic instruction that caused the
exception, rather than the following instruction.
Detects an overflow and writes to EPC.
n
Arithmetic Instruction (e.g., ADD)
n+4
Next Instruction
Instruction Pipeline
F
D
E
M
W
F
D
E
M
W
Detects an interrupt. Writes to EPC.
EPC Register
n
n+4
In the above example, the processor writes address n to the EPC register upon detection of an overflow.
However, executing the next instruction generates an interrupt at the same time, causing the processor to
rewrite the EPC register with address n+4 in the next cycle.
•
Problem-Causing Situation:
A) Software uses the ADD, ADDI or SUB instruction in the 32-bit ISA.
B) The ADD, ADDI or SUB instruction causes an overflow.
C) Another exception is requested simultaneously with the overflow.
This problem occurs when all of these conditions are true.
Workarounds:
•
Before returning from the overflow exception handler, determine whether the instruction
pointed to by the EPC register caused an overflow.
•
Make sure that two arithmetic instructions will not appear consecutively.
•
Disable interrupts prior to arithmetic instructions.
You should always use one of these workarounds to avoid this problem.
Note:
Toshiba’s compiler uses no instructions that could cause an overflow. Therefore, since
condition c) above never becomes true, this problem does not occur.
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Overflow Exception #2
Problem:
If an overflow exception caused a jump to the exception handler and the first instruction in that exception
handler caused another exception, the EPC register should point to the address of the first instruction in the
exception handler. However, the EPC register might contain the address that caused the overflow
exception.
•
Problem-Causing Situation:
When, with the instruction pipeline full, an overflow exception was taken at the following
sequence of instructions and then the first instruction in the overflow exception handler causes
another exception
ADD, ADDI or SUB
<= # Instruction that causes an overflow
Jump or branch instruction <= # Instruction with a delay slot
Delay slot
Note:
Toshiba’s compiler uses no instructions that could cause an overflow. Therefore, this
problem does not occur.
Workaround:
Don’t place a jump or branch instruction immediately following an instruction that could cause an
overflow (ADD, ADDI or SUB).
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When Using Multiple DMAC Channels (External Bus Interface Unit)
Problem:
Switching between DMA channels might cause an external chip select (CS) signal to be incorrectly driven
active for one cycle. RD, WR, ALE and other external bus control signals are not driven active.
DMAC Bus Mastership
e.g., DMAC Ch. 1 Internal Select Signal
e.g., DMAC Ch. 2 Internal Select Signal
DMAC Ch. 3 Internal Select Signal
CS from External Bus I/F Unit
In cases where the DMAC continually assumes bus mastership, switching from one channel to another
causes channel 3 to be selected for one cycle as shown above. If the destination address for channel 3
references an external address space and a chip select is programmed for that address space, the external
bus interface unit drives the chip select signal off chip even though no bus cycle has been started.
•
Problem-Causing Situation:
A) The system hardware uses two or more DMAC channels.
B) The system hardware uses one or more external CS channels.
C) While a DMA request for one channel is being serviced, a next DMA request has been
received on another channel and left pending. Or, two or more channels have received DMA
requests simultaneously.
D) The destination address for channel 3 points to an external address space. (Upon reset, the
content of the destination address register is undefined. Therefore, even when channel 3 is not
used, its destination address register might be pointing to an external address space.)
This problem occurs when all of these conditions are true.
Workaround:
The system hardware must be designed not to operate with CS alone.
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LWL and LWR Instructions
Problem:
The LWL or LWR instruction might provide incorrect results.
•
Problem-Causing Situation #1:
a. The destination of a load instruction (LB, LBU, LH, LHU, LW, LWL or LWR) is identical to
that of the LWL or LWR instruction.
b. The instruction pipeline is full. (The load instruction and the LWL or LWR instruction will
be executed consecutively.)
c.
The DMAC is programmed for data cache snooping. Once the load instruction is executed,
the DMAC initiates a DMA transaction. After it has been serviced, the LWLor LWR
instruction is executed.
This problem occurs when all of these conditions are true.
•
Problem-Causing Situation #2:
a. The destination of a load instruction (LB, LBU, LH, LHU, LW, LWL or LWR) is identical to
that of the LWL or LWR instruction.
b. The Doze or Halt bit in the Config register is set to 1 immediately before the load
instruction.
c.
The instruction pipeline is full. (The load instruction and the LWL or LWR instruction will
be executed consecutively.)
d. After the load instruction is executed, the processor is put in the STOP, SLEEP or IDLE
mode.
e.
Note:
After an interrupt signaling brings the processor out of the STOP, SLEEP or IDLE mode, the
LWL or LWR instruction is executed.
This applies to the case in which an interrupt signaling does not generate an interrupt
upon exit from STOP, SLEEP or IDLE mode. In other words, either the IEc bit in the
Status register is cleared (interrupts disabled), or if the IEc bit is set, the priority level
of the incoming interrupt signaling is lower than the mask level programmed in the
CMask field in the Status register. (Exit from STOP, SLEEP or IDLE mode can be
accomplished even with such settings.)
This problem occurs when all of these conditions are true.
Workarounds:
To use the LWL or LWR instruction,
1) Place a NOP between a load instruction and the LWL or LWR instruction, or
2) Disable the data cache snooping of the DMAC before the LWL or LWR instruction is executed.
Also, don’t put the processor in STOP, SLEEP or IDLE mode before the LWL or LWR
instruction is executed.
TMP1941AF-312
2003-03-27
TMP1941AF
Overflow Exception When a DSU Probe Is Used
Problem:
It looks as if an overflow exception caused a jump to the reset and nonmaskable exception vector address
(0xBFC0_0000).
•
Problem-Causing Situation:
When an overflow exception occurs, with the processor connected to a DSU probe
Note:
Toshiba’s compiler uses no instructions that could cause an overflow. Therefore, this
problem does not occur.
Workaround:
Don’t place a jump or branch instruction immediately following an instruction that could cause an
overflow (ADD, ADDI or SUB).
IDLE (Doze) Mode
Problem:
A deadlock might occur when returning to normal operating mode from IDLE (Doze) mode.
•
Problem-Causing Situation:
When the DMAC initiates a DMA transaction with snooping enabled after the Doze bit in the
Config register is set and before the CPU clock stops.
Workaround:
If snooping is enabled, stop the DMAC before putting the processor in IDLE (Doze) mode.
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2003-03-27
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TMP1941AF-314
2003-03-27