TOSHIBA TMP91C630F

TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L1 Series
TMP91C630
Preface
Thank you very much for making use of Toshiba microcomputer LSIs.
Before use this LSI, refer the section, “Points of Note and Restrictions”.
TMP91C630
CMOS 16-Bit Microcontrollers
TMP91C630F
1.
Outline and Features
TMP91C630 is a high-speed 16-bit microcontroller designed for the control of various mid- to
large-scale equipment. 2 Kbytes of boot ROM is built-in. The standard name of this microcontroller
is TMP91C630F-7770 with ROM code (7770).
The package of TMP91C630 is 100-pin flat type. The features are shown below.
(1) High-speed 16-bit CPU (900/L1 CPU)
x
Instruction mnemonics are upward-compatible with TLCS-90/900
x
16 Mbytes of linear address space
x
General-purpose registers and register banks
x
16-bit multiplication and division instructions; bit transfer and arithmetic instructions
x
Micro DMA: Four-channels (444 ns/2 bytes at 36 MHz)
(2) Minimum instruction execution time: 111 ns (at 36 MHz)
(3) Built-in RAM: 6 Kbytes
Built-in ROM: None
Built-in Boot ROM: 2 Kbytes
(4) External memory expansion
x
Expandable up to 16 Mbytes (shared program/data area)
x
Can simultaneously support 8-/16-bit width external data bus
‚‚‚ Dynamic data bus sizing
(5) 8-bit timers: 6 channels
(6) 16-bit timer/event counter: 1 channel
(7) Serial bus interface: 2 channels
(8) 10-bit AD converter: 8 channels
(9) Watchdog timer
030619EBP1
xThe information contained herein is subject to change without notice.
xThe information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of TOSHIBA or others.
xTOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
xThe TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made
at the customer’s own risk.
xThe products described in this document are subject to the foreign exchange and foreign trade laws.
xTOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law
and regulations.
xFor a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality
and Reliability Assurance/Handling Precautions.
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TMP91C630
(10) Chip Select/Wait controller: 4 blocks
(11) Interrupts: 35 interrupts
x
9 CPU interrupts: Software interrupt instruction and illegal instruction
x
19 internal interrupts: 7 priority levels are selectable.
x
7 external interrupts: 7 priority levels are selectable.
(Level mode, rising edge mode and falling edge mode are selectable.)
(12) Input/output ports: 53 pins
(13) Standby function
Three halt modes: Idle2 (programmable), Idle1, Stop
(14) Operating voltage
x
VCC
2.7 V to 3.6 V (fc max
36 MHz)
(15) Package
x
100-pin QFP: P-LQFP100-1414-0.50F
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TMP91C630
DVCC [4]
DVSS [4]
ADTRG (AN3/PA3)
AN0~AN7 (PA0~PA7)
VREFH
VREFL
AVCC
AVSS
CPU (TLCS-900L1)
10-bit 8-ch
AD
converter
Port A
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
W A
B C
D E
H L
IX
IY
IZ
SP
BOOT
AM0/AM1
RESET
OSC
Clock gear
32 bits
F
SR
PC
RD
X1
X2
EMU0
EMU1
Port 1
(P10~P17) D8~D15
Port 2
(P20~P27) A16~A23
WR
PZ2 ( HWR )
PZ3
Port Z
Watchdog timer
(WDT)
TXD0 (P80)
RXD0 (P81)
SCLK0/ CTS0 (P82)
STS0 (P83)
TXD1 (P84)
RXD1 (P85)
SCK1/ CTS1 (P86)
STS1 (P87)
Data bus
D0~D7
Address bus
A0~A7
A8~A15
Serial I/O
(channel 0)
Port 5
BUSRQ (P53)
BUSAK (P54)
Serial I/O
(channel 1)
Port 8
WAIT (P55)
TA0IN/INT1 (P70)
8-bit timer
(TMRA0)
TA1OUT (P71)
8-bit timer
(TMRA1)
CS/WAIT
controller
(4 blocks)
6-KB RAM
8-bit timer
(TMRA3)
TA4IN/INT3 (P73)
8-bit timer
(TMRA4)
TA5OUT (P74)
8-bit timer
(TMRA5)
INT4 (P75)
CS1 (P61)
CS2 (P62)
CS3 (P63)
8-bit timer
(TMRA2)
TA3OUT/INT2 (P72)
CS0 (P60)
Interrupt
controller
16-bit timer
(TMRB0)
NMI
INT0 (P56)
TB0IN0 (P93)
TB0IN1 (P94)
TB0OUT0 (P95)
TB0OUT1 (P96)
2-KB boot ROM
Port 9
INT5 (P90)
Port 7
Figure 1.1 TMP91C630 Block Diagram
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TMP91C630
2.
Pin Assignment and Pin Functions
The Pin Assignment and Pin Functions of the TMP91C630F are showed in Figure 2.1.1.
2.1
Pin Assignment Diagram
Figure 2.1.1 shows the pin assignment of the TMP91C630F.
Pin
Pin Name
No.
No.
63
62
61
60
59
58
57
56
55
54
53
52
51
DVCC
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
D5
D4
D3
D2
D1
D0
P96/TB0OUT1
P95/TB0OUT0
P94/TB0IN1
P93/TB0IN0
P90/INT5
P75/INT4
P74/TA5OUT
P73/TA4IN/INT3
P72/TA3OUT/INT2
P71/TA1OUT
P70/TA0IN/INT1
AM1
X1
DVSS
X2
DVCC
AM0
P63/ CS3
25
24
23
22
21
20
19
18
17
16
15
14
P62/ CS2
P61/ CS1
P60/ CS0
EMU1
EMU0
P87/ STS1
P86/SCLK1/ CTS1
P85/RXD1
P84/TXD1
P83/ STS0
P82/SCLK0/ CTS0
P81/RXD0
P27/A23
P26/A22
P25/A21
P24/A20
P23/A19
P22/A18
P21/A17
P20/A16
A15
A14
A13
A12
64
65
66
67
68
69
70
71
72
73
74
75
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
RD
WR
DVCC
PZ2/ HWR
DVSS
PA0/AN0
PA1/AN1
PA2/AN2
PA3/AN3/ ADTRG
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7 100
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
76
49
77
48
78
47
79
46
80
45
81
44
82
43
83
42
84
41
85
TMP91C630F
40
86
39
87
38
88
37
89
Top view
36
90
35
91
34
92
P-LQFP100-1414-0.50F
33
93
32
94
31
95
30
96
29
97
28
98
27
99
26
100
1
VREFH
VREFL
AVSS
AVCC
NMI
DVSS
P53/ BUSRQ
DVCC
P54/ BUSAK
P55/ WAIT
P56/INT0
PZ3
P80/TXD0
Pin Name
Pin
2
3
4
5
6
7
BOOT
DVSS
P17/D15
P16/D14
P15/D13
P14/D12
P13/D11
P12/D10
P11/D9
P10/D8
D7
D6
RESET
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
1
2
3
4
5
6
7
8
9
10
11
12
13
Figure 2.1.1 Pin Assignment Diagram (100-Pin LQFP)
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2.2
Pin Names and Functions
The names of the Input/Output pins and their functions are described below.
Table 2.2.1 to Table 2.2.3 show Pin name and functions.
Table 2.2.1 Pin Names and Functions (1/3)
Pin Names
Number
of Pins
I/O
Functions
D0 to D7
8
I/O
Data (lower): Bits 0 to 7 of data bus
P10 to P17
8
I/O
Port 1: I/O port that allows I/O to be selected at the bit level
(When used to the external 8-bit bus)
Data (upper): Bits 8 to15 of data bus
P20 to P27
A16 to A23
8
Output
Output
Port 2: Output port
Address: Bits 16 to 23 of address bus
A8 to A15
8
Output
Address: Bits 8 to 15 of address bus
A0 to A7
8
Output
Address: Bits 0 to 7 of address bus
RD
1
Output
Read: Strobe signal for reading external memory
WR
1
Output
Write: Strobe signal for writing data to pins D0 to D7
P53
1
I/O
Input
1
I/O
Output
1
I/O
Input
Port 55: I/O port (with pull-up resistor)
Wait: Pin used to request CPU bus wait. ((1 N) waits mode)
P56
INT0
1
I/O
Input
Port 56: I/O port (with pull-up resistor)
Interrupt request pin0: Interrupt request pin with programmable level/rising
edge/falling edge
P60
1
Output
Output
Port 60: Output port
Chip select 0: Outputs 0 when address is within specified address area.
1
Output
Output
Port 61: Output port
Chip select 1: Outputs 0 when address is within specified address area.
1
Output
Output
Port 62: Output port
Chip select 2: Outputs 0 when address is within specified address area.
1
Output
Output
Port 63: Output port
Chip select 3: Outputs 0 when address is within specified address area.
P70
TA0IN
INT1
1
I/O
Input
Input
P71
TA1OUT
1
I/O
Output
Port 71: I/O port
8-bit TMRA0 or 8-bit TMRA1 output
P72
TA3OUT
INT2
1
I/O
Output
Input
Port 72: I/O port
8-bit TMRA2 or 8-bit TMRA3 output
Interrupt request pin 2: Interrupt request pin with programmable level/rising
edge/falling edge
I/O
D8 to D15
BUSRQ
P54
BUSAK
P55
WAIT
CS0
P61
CS1
P62
CS2
P63
CS3
Port 53: I/O port (with pull-up resistor)
Bus request: Signal used to request bus release (high-impedance).
Port 54: I/O port (with pull-up resistor)
Bus acknowledge: Signal used to acknowledge bus release
(high-impedance).
Port 70: I/O port
8-bit TMRA0 input
Interrupt request pin 1: Interrupt request pin with programmable level/rising
edge/falling edge
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TMP91C630
Table 2.2.2 Pin Names and Functions (2/3)
Pin Names
Number
of Pins
I/O
Functions
Port 73: I/O port
8-bit TMRA4 input
Interrupt request pin 3: Interrupt request pin with programmable level/rising
edge/falling edge.
P73
TA4IN
INT3
1
I/O
Input
Input
P74
TA5OUT
1
I/O
Output
P75
INT4
1
I/O
Input
P80
TXD0
1
I/O
Output
P81
RXD0
1
I/O
Input
Port 81: I/O port (with pull-up resistor)
Serial receive data 0
P82
SCLK0
1
I/O
Input
I/O
Port 82: I/O port (with pull-up resistor)
Serial clock I/O 0
Serial data send enable 0 (Clear to send)
1
I/O
P84
TXD1
1
I/O
Output
P85
RXD1
1
I/O
Input
Port 85: I/O port (with pull-up resistor)
Serial receive data 1
P86
SCLK1
1
I/O
Input
I/O
Port 86: I/O port (with pull-up resistor)
Serial clock I/O 1
Serial data send enable 1 (Clear to send)
1
I/O
P90
INT5
1
I/O
Input
Port 90: I/O port
Interrupt request pin 5: Interrupt request pin with programmable level/rising
edge/falling edge
P93
TB0IN0
1
I/O
Input
Port 93: I/O port
Timer B0 input 0
P94
TB0IN1
1
I/O
Input
Port 94: I/O port
Timer B0 input 1
P95
TB0OUT0
1
I/O
Output
Port 95: I/O port
Timer B0 output 0
P96
TB0OUT1
1
I/O
Output
Port 96: I/O port
Timer B0 output 1
PA0 to PA7
AN0 to AN7
8
Input
Input
Input
1
I/O
Output
1
I/O
CTS0
P83
STS0
CTS1
P87
STS1
ADTRG
PZ2
HWR
PZ3
Port 74: I/O port
8-bit TMRA4 or 8-bit TMRA5 output
Port 75: I/O port
Interrupt request pin 4: Interrupt request pin with programmable
Port 80: I/O port (with pull-up resistor)
Serial send data 0: Programmable open-drain output pin
Port 83: I/O port (with pull-up resistor)
Serial data request signal 0
Port 84: I/O port (with pull-up resistor)
Serial send data 0: Programmable open-drain output pin
Port 87: I/O port (with pull-up resistor)
Serial data request signal 1
Port A0 to A7: Pins used to input port.
Analog input 0 to 7: Pins used to input to AD converter.
AD trigger: Signal used to request AD start (PA3).
Port Z2: I/O port (with pull-up resistor)
High write: Strobe signal for writing data to pins D8 to D15
Port Z3: I/O port (with pull-up resistor)
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TMP91C630
Table 2.2.3 Pin Names and Functions (3/3)
Number
of Pins
I/O
BOOT
1
Input
This pin sets boot mode (with pull-up resistor)
NMI
1
Input
Non-maskable interrupt request pin: Interrupt request pin with programmable
falling edge level or with both edge levels programmable
AM0 to AM1
2
Input
Operation mode:
AM1 0 and AM0
Pin Names
Functions
AM1
RESET
1
Input
0 and AM0
1: External 16-bit bus is fixed
or external 8-/16-bit buses are mixed.
0: External 8-bit bus is fixed.
Reset: Initializes TMP91C630 (with pull-up resistor)
VREFH
1
Input
Pin for reference voltage input to AD converter (H)
VREFL
1
Input
Pin for reference voltage input to AD converter (L)
AVCC
1
I/O
AVSS
1
X1/X2
2
Oscillator connection pins
DVCC
4
Power supply pins
DVSS
4
EMU0
1
Output
Open pin
EMU1
1
Output
Open pin
Power supply pin for AD converter
GND supply pin for AD converter
GND pins (0 V)
Note 1: An external DMA controller cannot access the device’s built-in memory or built-in I/O devices using
the BUSRQ and BUSAK signals.
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TMP91C630
3.
Operation
This section describes the basic components, functions and operation of the TMP91C630.
Notes and restrictions which apply to the various items described here are outlined in section 7.
Precautions and restrictions at the end of this databook.
3.1
CPU
The TMP91C630 incorporates a high-performance 16-bit CPU (the 900/L1 CPU). For a
description of this CPU’s operation, please refer to the section of this databook which describes
the TLCS-900/L1 CPU.
The following sub-sections describe functions peculiar to the CPU used in the TMP91C630;
these functions are not covered in the section devoted to the TLCS-900/L1 CPU.
3.1.1
Reset
When resetting the TMP91C630 microcontroller, ensure that the power supply voltage is
within the operating voltage range, and that the internal high-frequency oscillator has
stabilized. Then set the RESET input to Low level at least for 10 system clocks (ten states:
8.89 Ps at 36 MHz). Thus, when turn on the switch, be set to the power supply voltage is
within the operating voltage range, and that the internal high-frequency oscillator has
stabilized. Then hold the RESET input to Low level at least for 10 system clocks.
Clock gear is initialized 1/16 mode by Reset operation. It means that the system clock
mode fSYS is set to fc/32 ( fc/16 u 1/2).
When the reset has been accepted, the CPU performs the following:
x Sets the program counter (PC) as follows in accordance with the reset vector stored
at address FFFF00H to FFFF02H:
PC<0:7>
PC<8:15>
PC<16:23>
m
m
m
Data in location FFFF00H
Data in location FFFF01H
Data in location FFFF02H
x
Sets the stack pointer (XSP) to 100H.
x
Sets bits <IFF0:IFF2> of the status register (SR) to 111 (thereby setting the
interrupt level mask register to level 7).
x
Sets the <MAX> bit of the status register to 1 (MAX mode).
(Note: As this product does not support MIN mode, do not program a 0 to the
<MAX> bit.)
x
Clears bits <RFP0:RFP2> of the status register to 000 (thereby selecting register
bank 0).
When the reset is cleared, the CPU starts executing instructions according to the
program counter settings. CPU internal registers not mentioned above do not change
when the reset is cleared.
When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows.
x
Initializes the internal I/O registers.
x
Sets the port pins, including the pins that also act as internal I/O, to
general-purpose input or output port mode.
Note: The CPU internal register (except to PC, SR and XSP) and internal RAM data do not
change by resetting.
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Note:
HWR
Pull-up (Internal)
High-Z
Data-out
Data-in
Sampling
(PZ2 input mode)
Sampling
Data-in
(After reset released, startting 2 waits read cycle)
0FFFF00H
Read
WR
D0 to D15
RD
D0 to D15
CS2
CS0, CS1, CS3
A23 to A0
RESET
fFPH
TMP91C630
Figure 3.1.1 shows the timing of a reset for the TMP91C630.
Write
Figure 3.1.1 TMP91C630 Reset Timing Example
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TMP91C630
3.2
Outline of Operation Modes
There are multi-chip and multi-boot modes. Which mode is selected depends on the device’s
pin state after a reset.
x
Multi-chip mode: The device normally operations in this mode. After a reset, the device starts
executing the external memory program.
x
Multi-boot mode: This mode is used to rewrite the external flash memory by serial transfer
(UART).
After a reset, internal boot program starts up, executing a on-board rewrite
program.
Table 3.2.1 Operation Mode Setup Table
Operation Mode
Mode Setup Input Pin
RESET
BOOT
Multi-chip mode
H
Multi-boot mode
L
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3.3
Memory Map
Figure 3.3.1 is a memory map of the TMP91C630.
Multi-chip mode
000000H
000100H
Multi-boot mode
000000H
Internal I/O
(4 Kbytes)
Internal I/O
(4 Kbytes)
000100H
001000H
Direct area (n)
001000H
Internal RAM
(6 Kbytes)
Internal RAM
(6 Kbytes)
002800H
002800H
External memory
01F800H
Internal boot ROM
(2 Kbytes)
01FFFFH
External memory
16-Mbyte area
(r32)
(r32)
(r32)
(r32 d8/16)
(r32 r8/16)
(nnn)
External memory
FFFF00H
FFFFFFH
FFF800H
FFFEFFH
FFFF00H
FFFFFFH
Vector table
(256 bytes)
(
Internal boot ROM
(2 Kbytes)
Vector table
(256 bytes)
Internal area)
Figure 3.3.1 TMP91C630 Memory Map
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3.4
Triple Clock Function and Standby Function
The TMP91C630 system clock block contains
(1) Clock gearing system
(2) Standby controller
(3) Noise reducing circuit
It can be used for low-power, low-noise systems. The system clock operating mode (single
clock mode) is shown in Figure 3.4.1.
Reset
(fOSCH/32)
IDLE2 mode
(I/O operate)
IDLE1 mode
( only oscillator operate)
Instruction
Interrupt
Instruction
Interrupt
Release reset
NORMAL mode
(fOSCH/gear value/2)
Instruction
Interrupt
STOP mode
(Stops all circuits)
Clock mode transition figure
Figure 3.4.1 System Clock Block Diagram
The clock frequency input from the X1 and X2 pins is called fc. In case of TMP91C630, fc
fFPH. The system clock fSYS is defined as the divided clock of fFPH, and one cycle of fSYS is
regarded to as one state.
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3.4.1
Block Diagram of System Clock
SYSCR2<WUPTM1:0>
SYSCR0
Warming up timer (High-frequency oscillator)
IT
<PRCK1:0>
IT0
fc/16
fFPH
y2 y4
fFPH
y2
fc
fSYS
fc/2
fc/4
fc/8
fc/16
X1
High-frequency
X2
oscillator
y2
fOSCH
y4
y8 y16
SYSCR1<GEAR2:0>
Clock gear
fSYS
CPU
TMRA01 to TMRA45
IT0
ROM
Prescaler
RAM
Interrupt
controller
TMRB0
Prescaler
WDT
I/O ports
SIO0, SIO1
Prescaler
Figure 3.4.2 Block Diagram of System Clock
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SFRs
SYSCR0
(00E0H)
Bit symbol
7
6
5
4
3
2
1
0
PRCK1
PRCK0
0
0
Read/Write
After reset
Function
R/W
1
Always
write 1
0
Always
write 0
1
Always
write 1
0
Always
write 0
0
Always
write 0
0
Always
write 0
Select prescaler clock
00: fFPH
01: Reserved
10: fc/16
11: Reserved
7
SYSCR1
(00E1H)
6
5
4
Bit symbol
2
1
0
GEAR2
GEAR1
GEAR0
0
0
Read/Write
R/W
After reset
0
Always
write 0
Function
7
SYSCR2
(00E2H)
3
1
Select gear value of high frequency (fc)
000: fc
001: fc/2
010: fc/4
011: fc/8
100: fc/16
101: (Reserved)
110: (Reserved)
111: (Reserved)
6
5
4
3
2
Bit symbol
WUPTM1
WUPTM0
HALTM1
HALTM0
DRVE
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
1
After reset
Function
0
Always
write 0
Warm-up timer
00: Reserved
01: 28/Input frequency
10: 214
11: 216
HALT mode
00: Reserved
01: STOP mode
10: IDLE1 mode
11: IDLE2 mode
1
0
0
1: Drive the
pin during
STOP
mode
Figure 3.4.3 SFR for System Clock
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TMP91C630
EMCCR0
(00E3H)
7
6
5
4
3
2
1
Bit symbol
PROTECT
EXTIN
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
Function
EMCCR1
(00E4H)
0
Protect flag
0: OFF
1: ON
0
Always
write 0
1
Always
write 1
0
Always
write 0
0
Always
write 0
0
1: External
clock
1
Always
write 1
0
1
Always
write 1
Bit symbol
Read/Write
After reset
Writing 1FH turns protections off.
Writing any value except 1FH turns protection on.
Function
Figure 3.4.4 SFR for Noise-Reducing
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TMP91C630
3.4.2
System Clock Controller
The system clock controller generates the system clock signal (fSYS) for the CPU core and
internal I/O. It contains a clock gear circuit for high-frequency (fc) operation. The register
SYSCR1<GEAR0:2> sets the high-frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4,
fc/8 or fc/16). These functions can reduce the power consumption of the equipment in which
the device is installed.
The initialization<GEAR0:2>
(fc/16 u 1/2) after a reset.
100 will cause the system clock (fSYS) to be set to fc/32
For example, fSYS is set to 1.125 MHz when the 36 MHz oscillator is connected to the X1
and X2 pins.
Clock gear controller
The fFPH is set according to the contents of the clock gear select register SYSCR1
<GEAR0:2> to either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower
value of fFPH reduces power consumption.
Example: Changing to a high-frequency gear
SYSCR1
EQU
00E1H
LD
(SYSCR1), XXXX0000B
;
Changes fSYS to fc/2.
X: Don’t care
(Changing to high-frequency clock gear)
To change the clock gear, write the appropriate value to the SYSCR1<GEAR0:2>
register. The value of fFPH will not change until a period of time equal to the warm-up
time has elapsed from the point at which the register is written to.
There is a possibility that the instruction immediately following the instruction
which changes the clock gear will be executed before the new clock setting comes into
effect. To ensure that this does not happen, insert a dummy instruction (to execute a
Write cycle) as follows.
Example:
SYSCR1
EQU
00E1H
LD
(SYSCR1), XXXX0001B
; Changes fSYS to fc/4.
LD
(DUMMY), 00H
; Dummy instruction
Instruction to be executed after clock gear has changed.
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TMP91C630
3.4.3
Prescaler Clock Controller
For the internal I/O (TMRA01 to TMRA45, TMRB0 and SIO0, SIO1) there is a prescaler
which can divide the clock.
The IT clock input to the prescaler is either the clock fFPH divided by 2 or the clock fc/16
divided by 2. The setting of the SYSCR0 <PRCK0:1> register determines which clock signal
is input.
The IT0 clock input to the prescaler is either the clock fFPH divided by 4 or the clock fc/16
divided by 4. The setting of the SYSCR0 <PRCK0:1> register determines which clock signal
is input.
3.4.4
Noise Reduction Circuits
Noise reduction circuits are built in, allowing implementation of the following features.
(1) Single drive for high-frequency oscillator
(2) Protection of register contents
The above functions are performed by making the appropriate settings in the EMCCR0
and EMCCR1 registers.
(1) Single drive for high-frequency oscillator
(Purpose)
Not need twin-drive and protect mistake-operation by inputted noise to X2 pin when
the external-oscillator is used.
(Block diagram)
fOSCH
X1 pin
Enable oscillation (STOP EMCCR0<EXTIN>)
X2 pin
(Setting method)
When a 1 is written to the EMCCR0<EXTIN>, the oscillator is disabled and is
operated as a buffer. The X2 pin always outputs a 1.
<EXTIN> is initialized to 0 by a reset.
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(2) Runaway provision with protection register
(Purpose)
Provision against runaway of program caused by noise mixing etc.
If specified SFR (clock and memory control register) is changed in runaway state,
memory access is impossibility.
By setting protection register, write operation to specified SFR (clock register and
memory control register) can be prohibited.
Specified SFR list
1. CS/WAIT controller
B0CS, B1CS, B2CS, B3CS, BEXCS,
MSAR0, MSAR1, MSAR2, MSAR3,
MAMR0, MAMR1, MAMR2, MAMR3
2. Clock gear (write enable only EMCCR1)
SYSCR0, SYSCR1, SYSCR2, EMCCR0
(Block diagram)
Protect register
EMCCR0<PROTECT>
Write except “1FH” to EMCCR1
Write “1FH” to EMCCR1
S
R
Q
Write signal to
SFR
Write signal to specified SFR
Write signal to other SFR
(Setting method)
If writing except “1FH” code to EMCCR1 register, it become protect ON. By this
operation, write operation to specified SFR is disabling.
If writing “1FH” code to EMCCR1 register, it become protect OFF. State of protect
can be confirmed by reading EMCCR0<PROTECT>.
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3.4.5
Standby Controller
(1) HALT modes
When the HALT instruction is executed, the operating mode switches to IDLE2,
IDLE1 or STOP mode, depending on the contents of the SYSCR2<HALTM1:0>
register.
The subsequent actions performed in each mode are as follows:
a.
IDLE2: The CPU only is halted.
In IDLE2 mode internal I/O operations can be performed by setting the
following registers.
Table 3.4.1 shows the registers of setting operation during IDLE2 mode.
Table 3.4.1 The Registers of Setting Operation during IDLE2 Mode
Internal I/O
SFR
TMRA01
TA01RUN<I2TA01>
TMRA23
TA23RUN<I2TA23>
TMRA45
TA45RUN<I2TA45>
TMRB0
TB0RUN<I2TB0>
SIO0
SC0MOD1<I2S0>
SIO1
SC1MOD1<I2S0>
AD converter
ADMOD1<I2AD>
WDT
WDMOD<I2WDT>
b.
IDLE1: Only the oscillator to operate.
c.
STOP: All internal circuits stop operating.
The operation of each different HALT mode is described in Table 3.4.2.
Table 3.4.2 I/O Operation during HALT Modes
HALT Mode
IDLE2
IDLE1
STOP
SYSCR2 <HALTM1:0>
11
10
01
CPU
I/O ports
Stop
Maintain same state as when HALT instruction was executed.
See Table 3.4.5
TMRA, TMRB
Block
SIO
AD converter
Can be selected
Stopped
WDT
Interrupt controller
Operational
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(2) How to clear a HALT mode
The Halt state can be cleared by a reset or by an interrupt request. The combination
of the value in <IFF0:2> of the interrupt mask register and the current HALT mode
determine in which ways the HALT mode may be cleared. The details associated with
each type of Halt state clearance are shown in Table 3.4.3.
x
Clearance by interrupt request
Whether or not the HALT mode is cleared and subsequent operation depends on the
status of the generated interrupt. If the interrupt request level set before execution of
the HALT instruction is greater than or equal to the value in the interrupt mask
register, the following sequence takes place: the HALT mode is cleared, the interrupt is
then processed, and the CPU then resumes execution starting from the instruction
following the HALT instruction. If the interrupt request level set before execution of
the HALT instruction is less than the value in the interrupt mask register, the HALT
mode is not cleared. (If a non-maskable interrupt is generated, the Halt mode is cleared
and the interrupt processed, regardless of the value in the interrupt mask register.)
However, for INT0 to INT4 only, even if the interrupt request level set before
execution of the HALT instruction is less than the value in the interrupt mask register,
the HALT mode is cleared. In this case, the interrupt is not processed and the CPU
resumes execution starting from the instruction following the HALT instruction. The
interrupt request flag remains set to 1.
x
Clearance by reset
Any Halt state can be cleared by a reset.
When STOP mode is cleared by a RESET signal, sufficient time (at least 3 ms) must
be allowed after the reset for the operation of the oscillator to stabilize.
When a HALT mode is cleared by resetting, the contents of the internal RAM remain
the same as they were before execution of the HALT instruction. However, all other
settings are re-initialized. (Clearance by an interrupt affects neither the RAM contents
nor any other settings – the state which existed before the HALT instruction was
executed is retained.)
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TMP91C630
Table 3.4.3 Source of Halt State Clearance and Halt Clearance Operation
Interrupt Enabled
Interrupt Disabled
(Interrupt Level) t (Interrupt Mask) (Interrupt Level) < (Interrupt Mask)
Status of Received Interrupt
Interrupt
Source of halt state clearance
HALT Mode
IDLE2
IDLE1 STOP
NMI
i
i
INTWDT
i
u
*1
IDLE2
IDLE1 STOP
u
*1
ż
ż
i
i
ż
*1
INT0 to INT4 (Note)
i
i
INT5
i
u
u
u
u
u
INTTA0 to INTTA5
i
u
u
u
u
u
INTTB00, INTTB01, INTTBOF0
i
u
u
u
u
u
INTRX0, INTTX0
i
u
u
u
u
u
INTRX1, INTTX1
i
u
u
u
u
u
INTAD
i
u
u
u
u
u
RESET
Reset initializes the LSI
i: After clearing the HALT mode, CPU starts interrupt processing.
ż: After clearing the HALT mode, CPU resumes executing starting from instruction following the HALT
instruction.
u: Cannot be used to clear the HALT mode.
: The priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level.
There is not this combination type.
*1: The HALT mode is cleared when the warm-up time has elapsed.
Note: When the HALT mode is cleared by INT0 to INT4 interrupt of the level mode in the interrupt enabled
status, hold the level until starting interrupt processing. Changing level before holding level, interrupt
processing is correctly started.
Example: Clearing IDLE1 mode
An INT0 interrupt clears the Halt state when the device is in IDLE1 mode.
Address
8203H
8206H
8209H
820BH
820EH
LD
LD
EI
LD
HALT
(IIMC0), 00H
(INTE0AD), 06H
5
(SYSCR2), 28H
; Selects INT0 interrupt rising edge.
; Sets INT0 interrupt level to 6.
; Sets interrupt level to 5 for CPU.
; Sets HALT mode to IDLE1 mode.
; Halts CPU.
INT0
INT0 interrupt routine
RETI
820FH
LD
XX, XX
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TMP91C630
(3) Operation
a.
IDLE2 mode
In IDLE2 mode only specific internal I/O operations, as designated by the
IDLE2 setting register, can take place. Instruction execution by the CPU stops.
Figure 3.4.5 illustrates an example of the timing for clearance of the IDLE2
mode Halt state by an interrupt.
X1
A0 to A23
D0 to D15
Data
Data
RD
WR
Clearing interrupt
IDLE2 mode
Figure 3.4.5 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt
b.
IDLE1 mode
In IDLE1 mode, only the internal oscillator continue to operate. The system
clock in the MCU stops.
In the Halt state, the interrupt request is sampled asynchronously with the
system clock; however, clearance of the Halt state (i.e. restart of operation) is
synchronous with it.
Figure 3.4.6 illustrates the timing for clearance of the IDLE1 mode Halt state
by an interrupt.
X1
A0 to A23
D0 to D15
Data
Data
RD
WR
Clearing interrupt
IDLE1 mode
Figure 3.4.6 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt
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TMP91C630
c.
STOP mode
When STOP mode is selected, all internal circuits stop, including the internal
oscillator. pin status in STOP mode depends on the settings in the
SYSCR2<DRVE> register. Table 3.4.5 summarizes the state of these pins in STOP
mode.
After STOP mode has been cleared system clock output starts when the
warm-up time has elapsed, in order to allow oscillation to stabilize. See the
sample warm-up times in Table 3.4.4.
Figure 3.4.7 illustrates the timing for clearance of the STOP mode Halt state by
an interrupt.
Warm-up time
X1
A0 to A23
D0 to D15
Data
Data
RD
WR
interrupt for
release
STOP
mode
Figure 3.4.7 Timing Chart for STOP Mode Halt State Cleared by Interrupt
Table 3.4.4 Sample Warm-up Times After Clearance of STOP Mode
at fOSCH 36 MHz
SYSCR2<WUPTM1:0>
01 (2 )
8
10 (2 )
14
11 (2 )
7.1 Ps
0.455 ms
1.820 ms
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TMP91C630
Table 3.4.5 Pin States in STOP Mode
Pin Names
I/O
D0 to D7
Input/output mode
P10 to P17 (D8 to D15)
<DRVE>
0
<DRVE>
Input mode
Output mode
Input/output mode
Output
Output pin
Output
Output
Input
Output
Input
Output
Output
Input
Output
Input
Output
Input
Output
PA0 to PA7
Output pin
Input mode
Output mode
Input mode
Output mode
Output mode
Input mode
Output mode
Input mode
Output mode
Input mode
Output mode
Input mode
NMI
Input pin
Input
Input
P20 to P27 (A16 to A23),
A0 to A15
RD , WR
PZ2, PZ3
P53 to P56
P60 to P63
P70 to P75
P80 to P87
P90, P93 to P96
1
RESET
Input
Input
Input
AM0, AM1
Input
Input
Input
X1
Input
X2
Output
High level output
High level output
:
As for input mode/input pin, input gate is closed.
Output mode/output pin is at high impedance.
Input: Input gate is in operation. Fix input voltage to L or H.
Output: Output state
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TMP91C630
3.5
Interrupts
Interrupts are controlled by the CPU interrupt mask register SR<IFF2:0> and by the built-in
interrupt controller.
The TMP91C630 has a total of 35 interrupts divided into the following five types:
x
Interrupts generated by CPU: 9 sources
(Software interrupts, Illegal instruction interrupt)
x
Interrupts on external pins ( NMI and INT0 to INT5): 7 sources
x
Internal I/O interrupts: 19 sources
A (fixed) individual interrupt vector number is assigned to each interrupt.
One of seven (variable) priority level can be assigned to each maskable interrupt.
The priority level of non-maskable interrupts are fixed at 7 as the highest level.
When an interrupt is generated, the interrupt controller sends the piority of that interrupt to
the CPU. If multiple interrupts are generated simultaneously, the interrupt controller sends
the interrupt with the highest priority to the CPU. (The highest priority is level 7 using for
non-maskable interrupts.)
The CPU compares the priority level of the interrupt with the value of the CPU interrupt
mask register <IFF2:0>. If the priority level of the interrupt is higher than the value of the
interrupt mask register, the CPU accepts the interrupt.
The interrupt mask register <IFF2:0> value can be updated using the value of the EI
instruction (EI num sets <IFF2:0> data to num).
For example, specifying “EI 3” enables the maskable interrupts which priority level set in the
interrupt controller is 3 or higher, and also non-maskable interrupts.
Operationally, the DI instruction (<IFF2:0>
7) is identical to the EI 7 instruction. DI
instruction is used to disable maskable interrupts because of the priority level of maskable
interrupts is 0 to 6. The EI instruction is vaild immediately after execution.
In addition to the above general-purpose interrupt processing mode, TLCS-900/L1 has a
micro DMA interrupt processing mode as well. The CPU can transfer the data (1/2/4 bytes)
automatically in micro DMA mode, therefore this mode is used for speed-up interrupt
processing, such as transferring data to the internal or external peripheral I/O. Moreover,
TMP91C630 has software start function for micro DMA processing request by the software not
by the hardware interrupt.
Figure 3.5.1 shows the overall interrupt processing flow.
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Interrupt processing
Interrupt appointed
by micro DMA
start vector?
No
Interrupt vector calue “V” read
Interrupt request F/F clear
General-purpose
interrupt
processing
Yes
Clear interrupt request flag
Data transfer by micro DMA
Count m Count 1
PUSH
PC
PUSH
SR
SR<IFF2:0> mLevel of
accepted
interrupt 1
INTNEST m INTNEST 1
Count
0
Micro DMA processing
Yes
Clear vector register
generating micro DMA transfer
end interrupt
(INTTC0 to INTTC3)
No
PC m (FFFF00H V)
Interrupt processing program
RETI instruction
POP
SR
POP
PC
INTNEST m INTNEST 1
End
Figure 3.5.1 Interrupt and Micro DMA Processing Sequence
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3.5.1
General-Purpose Interrupt Processing
When the CPU accepts an interrupt, it usually performs the following sequence of
operations. That is also the same as TLCS-900/L and TLCS-900/H.
(1) The CPU reads the interrupt vector from the interrupt controller.
If the same level interrupts occur simultaneously, the interrupt controller generates an
interrupt vector in accordance with the default priority and clears the interrupt
request.
(The default priority is already fixed for each interrupt: the smaller vector value has
the higher priority level.)
(2) The CPU pushes the value of program counter (PC) and status register (SR) onto the
stack area (indicated by XSP).
(3) The CPU sets the value which is the priority level of the accepted interrupt plus 1(1)
to the interrupt mask register <IFF2:0>. However, if the priority level of the accepted
interrupt is 7, the register’s value is set to 7.
(4) The CPU increases the interrupt nesting counter INTNEST by 1(1).
(5) The CPU jumps to the address indicated by the data at address “FFFF00H interrupt
vector” and starts the interrupt processing routine.
The above processing time is 18-states (1.0 Ps at 36 MHz) as the best case (16 bits
data-bus width and 0-waits).
When the CPU compled the interrupt processing, use the RETI instruction to return
to the main routine. RETI restores the contents of program counter (PC) and status
register (SR) from the stack and decreases the interrupt nesting counter INTNEST by
1(1).
Non-maskable interrupts cannot be disabled by a user program. Maskable
interrupts, however, can be enabled or disabled by a user program. A program can set
the priority level for each interrupt source. (A priority level setting of 0 or 7 will disable
an interrupt request.)
If an interrupt request which has a priority level equal to or greater than the value of
the CPU interrupt mask register <IFF2:0> comes out, the CPU accepts its interrupt.
Then, the CPU interrupt mask register <IFF2:0> is set to the value of the priority level
for the accepted interrupt plus 1(1).
Therefore, if an interrupt is generated with a higher level than the current interrupt
during its processing, the CPU accepts the later interrupt and goes to the nesting
status of interrupt processing.
Moreover, if the CPU receives another interrupt request while performing the said
(1) to (5) processing steps of the current interrupt, the latest interrupt request is
sampled immediately after execution of the first instruction of the current interrupt
processing routine. Specifying DI as the start instruction disables maskable interrupt
nesting.
A reset initializes the interrupt mask register <IFF2:0> to 111, disabling all
maskable interrupts.
Table 3.5.1 shows the TMP91C630 interrupt vectors and micro DMA start vectors.
The address FFFF00H to FFFFFFH (256 bytes) is assigned for the interrupt vector
area.
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Table 3.5.1 TMP91C630 Interrupt Vectors and Micro DMA Start Vectors
Default
Priority
Type
Interrupt Source or Source of Micro DMA
Vector Value
Request
Vector
Reference
Address
Micro DMA
Start Vector
1
Reset or [SWI0] instruction
0000H
FFFF00H
2
[SWI1] instruction
0004H
FFFF04H
3
Illegal instruction or [SWI2] instruction
0008H
FFFF08H
4
[SWI3] instruction
000CH
FFFF0CH
5
[SWI4] instruction
0010H
FFFF10H
[SWI5] instruction
0014H
FFFF14H
7
[SWI6] instruction
0018H
FFFF18H
8
[SWI7] instruction
001CH
FFFF1CH
9
NMI : NMI pin input
0020H
FFFF20H
10
INTWD: Watchdog timer
0024H
FFFF24H
Micro DMA
11
INT0: INT0 pin input
0028H
FFFF28H
0AH
12
INT1: INT1 pin input
002CH
FFFF2CH
0BH
13
INT2: INT2 pin input
0030H
FFFF30H
0CH
14
INT3: INT3 pin input
0034H
FFFF34H
0DH
15
INT4: INT4 pin input
0038H
FFFF38H
0EH
16
INT5: INT5 pin input
003CH
FFFF3CH
0FH
17
(Reserved)
0040H
FFFF40H
10H
18
(Reserved)
0044H
FFFF44H
11H
19
(Reserved)
0048H
FFFF48F
12H
20
INTTA0: 8-bit timer 0
004CH
FFFF4CH
13H
21
INTTA1: 8-bit timer 1
0050H
FFFF50H
14H
22
INTTA2: 8-bit timer 2
0054H
FFFF54H
15H
23
INTTA3: 8-bit timer 3
0058H
FFFF58H
16H
24
INTTA4: 8-bit timer 4
005CH
FFFF5CH
17H
25
INTTA5: 8-bit timer 5
0060H
FFFF60H
18H
26
(Reserved)
0064H
FFFF64H
19H
27
(Reserved)
0068H
FFFF68H
1AH
INTTB00: 16-bit timer 0 (TB0RG0)
006CH
FFFF6CH
1BH
6
Non-mask
able
28
29
Maskable
INTTB01: 16-bit timer 0 (TB0RG1)
0070H
FFFF70H
1CH
30
(Reserved)
0074H
FFFF74H
1DH
31
(Reserved)
0078H
FFFF78H
1EH
32
INTTBOF0: 16-bit timer 0 (Overflow)
007CH
FFFF7CH
1FH
33
(Reserved)
0080H
FFFF80H
20H
34
INTRX0: Serial receive (Channel 0)
0084H
FFFF84H
21H
35
INTTX0: Serial transmission (Channel 0)
0088H
FFFF88H
22H
36
INTRX1: Serial receive (Channel 1)
008CH
FFFF8CH
23H
37
INTTX1: Serial transmission (Channel 1)
0090H
FFFF90H
24H
38
(Reserved)
0094H
FFFF94H
25H
39
(Reserved)
0098H
FFFF98H
26H
40
INTAD: AD conversion end
009CH
FFFF9CH
27H
41
INTTC0: Micro DMA end (Channel 0)
00A0H
FFFFA0H
28H
42
INTTC1: Micro DMA end (Channel 1)
00A4H
FFFFA4H
29H
43
INTTC2: Micro DMA end (Channel 2)
00A8H
FFFFA8H
2AH
44
INTTC3: Micro DMA end (Channel 3)
00ACH
FFFFACH
2BH
(Reserved)
00B0H
to
00FCH
FFFFB0H
to
FFFFFCH
to
to
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TMP91C630
3.5.2
Micro DMA Processing
In addition to general-purpose interrupt processing, the TMP91C630 supprots a micro
DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the
highest priority level (level 6) among maskable interrupts, regardless of the priority level of
the particular interrupt source. Micro. The micro DMA has 4 channels and is possible
continuous transmission by specifing the say later burst mode.
Because the micro DMA function has been implemented with the cooperative operation
of CPU, when CPU goes to a stand-by mode by HALT instruction, the requirement of micro
DMA will be ignored (pending).
(1) Micro DMA operation
When an interrupt request specified by the micro DMA start vector register is
generated, the micro DMA triggers a micro DMA request to the CPU at interrupt
priority level 6 and starts processing the request in spite of any interrupt source’s level.
The micro DMA is ignored on <IFF2:0> “7”
The 4 micro DMA channels allow micro DMA processing to be set for up to 4 types of
interrupts at any one time. When micro DMA is accepted, the interrupt request
flip-flop assigned to that channel is cleared.
The data are automatically transferred once(1/2/4 bytes) from the transfer source
address to the transfer destination address set in the control register, and the transfer
counter is decreased by 1(1).
If the decreased result is 0, the micro DMA transfer end interrupt (INTTC0 to
INTTC3) passes from the CPU to the interrupt controller. In addition, the micro DMA
start vector register DMAnV is cleared to 0, the next micro DMA is disabled and micro
DMA processing completes. If the decreased result is other than 0, the micro DMA
processing completes if it isn’t specified the say later burst mode. In this case, the
micro DMA transfer end interrupt (INTTC0 to INTTC3) aren’t generated.
If an interrupt request is triggered for the interrupt source in use during the interval
between the clearing of the micro DMA start vector and the next setting,
general-purpose interrupt processing executes at the interrupt level set. Therefore, if
only using the interrupt for starting the micro DMA (not using the interrupts as a
general-purpose interrupt: level 1 to 6), first set the interrupts level to 0 (interrupt
requests disabled).
If using micro DMA and general-purpose interrupts together, first set the level of the
interrupt used to start micro DMA processing lower than all the other interrupt levels.
In this case, the cause of general interrupt is limited to the edge interrupt.
The priority of the micro DMA transfer end interrupt (INTTC0 to INTTC3) is defined
by the interrupt level and the default priority as the same as the other maskable
interrupt.
If a micro DMA request is set for more than one channel at the same time, the
priority is not based on the interrupt priority level but on the channel number. The
smaller channel number has the higher priority (Channel 0 (high) > channel 3 (low)).
While the register for setting the transfer source/transfer destination addresses is a
32-bit control register, this register can only effectively output 24-bit addresses.
Accordingly, micro DMA can access 16 Mbytes (the upper eight bits of the 32 bits are
not valid).
Three micro DMA transfer modes are supported: 1-byte transfer, 2-byte (one-word)
transfer, and 4-byte transfer. After a transfer in any mode, the transfer
source/destination addresses are increased, decreased, or remain unchanged.
91C630-29
2003-07-22
TMP91C630
This simplifies the transfer of data from I/O to memory, from memory to I/O, and
from I/O to I/O. For details of the transfer modes, see (4) Transfer Mode Register. As
the transfer counter is a 16-bit counter, micro DMA processing can be set for up to
65536 times per interrupt source. (The micro DMA processing count is maximized
when the transfer counter initial value is set to 0000H.)
Micro DMA processing can be started by the 23 interrupts shown in the micro DMA
start vectors of Figure 3.5.1 and by the micro DMA soft start, making a total of 24
interrupts.
Figure 3.5.2 shows the word transfer micro DMA cycle in transfer destination
address INC mode (except for Counter mode, the same as for other modes).
(The conditions for this cycle are based on an external 16-bit bus, 0 waits, trandfer
source/transfer destination addresses both even-numberd values).
1 state
DM1
(Note 1)
DM2
DM3
DM4
DM5
(Note 2)
DM6
DM7
DM8
X1
A0 to A23
Trasfer source address
Trasger destination
address
RD
WR / HWR
D0 to D15
Input
Output
Figure 3.5.2 Timing for Micro DMA Cycle
States 1 to 3: Instruction fetch cycle (gets next address code).
If 3 bytes and more instruction codes are inserted in the instruction queue
buffer, this cycle becomes a dummy cycle.
States 4 to 5: Micro DMA read cycle
State 6: Dummy cycle (the address bus remains unchanged from state 5)
States 7 to 8: Micro DMA write cycle
Note 1: If the source address area is an 8-bit bus, it is increased by two states.
If the source address area is a 16-bit bus and the address starts from an odd number, it is
increased by two states.
Note 2: If the destination address area is an 8-bit bus, it is increased by two states.
If the destination address area is a 16-bit bus and the address starts from an odd number,
it is increased by two states.
91C630-30
2003-07-22
TMP91C630
(2) Soft start function
In addition to starting the micro DMA function by interrupts, TMP91C815 includes
a micro DMA software start function that starts micro DMA on the generation of the
write cycle to the DMAR register.
Writing 1 to each bit of DMAR register causes micro DMA once. At the end of
transfer, the corresponding bit of the DMAR register is automatically cleared to 0.
Only one-channel can be set once for micro DMA. (Do not write 1 to plural bits.)
When writing again 1 to the DMAR register, check whether the bit is 0 before
writing 1.
When a burst is specified by DMAB register, data is continuously transferred until
the value in the micro DMA transfer counter is 0 after start up of the micro DMA.
Symbol
Name
Address
DMAR
DMA
software
request
register
7
6
5
4
3
2
1
DMAR3
DMAR2
0
DMA request
89H
DMAR1
DMAR0
R/W
(no RMW)
0
0
0
0
(3) Transfer control registers
The transfer source address and the transfer destination address are set in the
following registers. Data setting for these registers is done by an “LDC cr, r”
instruction.
Channel 0
DMAS0
DMA source address register 0: only use LSB 24 bits
DMAD0
DMA destination address register 0: only use LSB 24 bits
DMAC0
DMA counter register 0: 1 to 65536
DMAM0
DMA mode register 0
Channel 3
DMAS3
DMA source address register 3
DMAD3
DMA destination address register 3
DMAC3
DMA counter register 3
DMAM3
DMA mode register 3
8 bits
16 bits
32 bits
91C630-31
2003-07-22
TMP91C630
(4) Detailed description of the transfer mode register
8 bits
DMAM0 to
DMAM3
0
0
0
Mode
Number of
Transfer Bytes
000
(fixed)
000
00
001
010
011
100
101
Byte transfer
Note: When setting a value in this register, clear 0 to the upper 3
bits.
Mode Description
Minimum
Number of
Execution Time
Execution States
at fc 36 MHz
Transfer destination address INC mode
..............I/O to memory
8 states
444 ns
(DMADn) m (DMASn)
DMACn m DMACn 1
If DMACn 0, then INTTCn is generated.
12 states
667 ns
01
Word transfer
10
4-byte transfer
00
Byte transfer
Transfer destination address DEC mode
..............I/O to memory
8 states
444 ns
01
Word transfer
10
4-byte transfer
(DMADn) m (DMASn)
DMACn m DMACn 1
If DMACn 0, then INTTCn is generated.
12 states
667 ns
00
Byte transfer
Transfer source address INC mode
..............Memory to I/O
8 states
444ns
01
Word transfer
10
4-byte transfer
(DMADn) m (DMASn)
DMACn m DMACn 1
If DMACn 0, then INTTCn is generated.
12 states
667 ns
00
Byte transfer
8 states
444ns
01
Word transfer
10
4-byte transfer
12 states
667 ns
00
Byte transfer
8 states
444 ns
12 states
667 ns
5 states
278 ns
Transfer source address DEC mode
..............Memory to I/O
(DMADn) m (DMASn)
DMACn m DMACn 1
If DMACn 0, then INTTCn is generated.
Fixed address mode
..............I/O to I/O
(DMADn) m (DMASn)
DMACn m DMACn 1
If DMACn 0, then INTTCn is generated.
01
Word transfer
10
4-byte transfer
00
Counter mode
........ For counting number of times interrupt is generated
DMASn m DMASn 1
DMACn m DMACn 1
If DMACn 0, then INTTCn is generated.
Note 1: “n” is the corresponding micro DMA channels 0 to 3
DMADn /DMASn: Post-increment (increment register value after transfer)
DMADn /DMASn: Post-decrement (decrement register value after transfer)
The I/Os in the table mean fixed address and the memory means increment (INC) or decrement
(DEC) addresses.
Note 2: Execution time is under the condition of:
16-bit bus width (both translation and destination address area)/0 waits/
fc 36 MHz/selected high frequency mode (fc u 1)
Note 3: Do not use an undefined code for the transfer mode register except for the defined codes listed in
the above table.
91C630-32
2003-07-22
TMP91C630
3.5.3
Interrupt Controller Operation
The block diagram in Figure 3.5.3 shows the interrupt circuits. The left-hand side of the
diagram shows the interrupt controller circuit. The right-hand side shows the CPU
interrupt request signal circuit and the halt release circuit.
For each of the 26 interrupt channels there is an interrupt request flag (consisting of a
flip-flop), an interrupt priority setting register and a micro DMA start vector register. The
interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to
zero in the following cases:
x
when reset occurs
x
when the CPU reads the channel vector after accepted its interrupt
x
when executing an instruction that clears the interrupt (write DMA start vector to
INTCLR register)
x
when the CPU receives a micro DMA request (when micro DMA is set)
x
when the micro DMA burst transfer is terminated
An interrupt priority can be set independently for each interrupt source by writing the
priority to the interrupt priority setting register (e.g. INTE0AD or INTE12). 6 interrupt
priorities levels (1 to 6) are provided. Setting an interrupt source’s priority level to 0 (or 7)
disables interrupt requests from that source. The priority of non-maskable interrupts (NMI
pin interrupts and Watchdog timer interrupts) is fixed at 7. If interrupt request with the
same level are generated at the same time, the default priority (the interrupt with the
lowest priority or, in other words, the interrupt with the lowest vector value) is used to
determine which interrupt request is accepted first.
The 3rd and 7th bits of the interrupt priority setting register indicate the state of the
interrupt request flag and thus whether an interrupt request for a given channel has
occurred.
The interrupt controller sends the interrupt request with the highest priority among the
simulateous interrupts and its vector address to the CPU. The CPU compares the priority
value <IFF2:0> in the Status register by the interrupt request signal with the priority
value set; if the latter is higher, the interrupt is accepted. Then the CPU sets a value higher
than the priority value by 1(1) in the CPU SR <IFF2:0>. Interrupt request where the
priority value equals or is higher than the set value are accepted simultaneously during the
previous interrupt routine.
When interrupt processing is completed (after execution of the RETI instruction), the
CPU restores the priority value saved in the stack before the interrupt was generated to
the CPU SR<IFF2:0>.
The interrupt controller also has registers (4 channels) used to store the micro DMA start
vector. Writing the start vector of the interrupt source for the micro DMA processing (see
Table 3.5.1), enables the corresponding interrupt to be processed by micro DMA processing.
The values must be set in the micro DMA parameter register (e.g. DMAS and DMAD) prior
to the micro DMA processing.
91C630-33
2003-07-22
Micro
DMA
counter
zero
interrupt
91C630-34
INTAD
INTTC0
INTTC1
INTTC2
INTTC3
INT1
INT2
INT3
INT4
INT5
INTTA0
INT0
INTWD
NMI
S
R
Q
RESET
D5
D4
D3
D2
D1
D0
INTTC
D Q
CLR
V
V
Soft start
V 9CH
V A0H
V A4H
V A8H
V ACH
DMA0V
DMA1V
DMA2V
DMA3V
S
6 Selector
34
6
20H
24H
V 28H
V 2CH
V 30H
V 34H
V 38H
V 3CH
V 4CH
Interrupt request flag
Dn 3
Decoder
Y1
Y2
Y3
Y4
Y5
Y6
A
B
C
Interrupt vector read
Micro DMA acknowledge
S Q
R
Interrupt
request F/F
CLR
Micro DMA start vector setting register
Reset
Dn 2
Priority setting register
Dn
Dn 1
D
Q
RESET
interrupt
vector read
Interrupt request F/F
Interrupt controller
4
1
7
0
1
2
3
B
A
D2
D3
D4
D5
D6
D7
D0
D1
3 INTRQ2 to 0
2
Interrupt vector
read
Interrupt
vector
generator
4-input OR
26
1
2 Highest A
B
3 priority
interrupt C
4
level select
5
6
7
Micro DMA channel
priority decoder
6
1
Priority encoder
Interrupt
request signal
to CPU
Interrupt
level detect
RESET
if IFF
2
7 then 0
Micro DMA request
Micro DMA channel
specification
INT0, 1, 2, 3, 4
NMI
HALT release
During
IDLE1
During
STOP
Interrupt request
signal
EI 1 to 7
DI
RESET
if INTRQ2 to 0 t IFF
2 to 0 then 1.
3
3
IFF2:0
Interrupt
mask F/F
CPU
TMP91C630
Figure 3.5.3 Block Diagram of Interrupt Controller
2003-07-22
TMP91C630
(1) Interrupt priority setting registers
Name Symbol Address
INTE0
&
INTE0AD
INTAD
enable
INT1
&
INT2
enable
INT3
&
INT4
enable
7
6
5
4
3
2
INTAD
90H
IADC
IADM2
IADM1
R
0
IADM0
R/W
0
I0C
I0M2
91H
I2C
I2M2
0
0
0
I2M0
R/W
0
92H
I4C
I1C
I1M2
R
0
I4M2
R
0
0
0
0
m After reset
I1M1
I1M0
0
R/W
0
0
0
I3M1
I3M0
INT3
I4M1
I4M0
R/W
0
m Bit symbol
m Read/Write
R/W
0
INT4
INTE34
source
I0M0
INT1
I2M1
R
0
m Interrupt
I0M1
R
0
INT2
INTE12
1
INT0
I3C
I3M2
R
0
0
0
R/W
0
0
0
I5M1
I5M0
INT5
INT5
enable
INTE5
I5C
93H
0
INTTA0
&
INTETA01
INTTA1
enable
INTTA2
&
INTETA23
INTTA3
enable
INTTA4
&
INTETA45
INTTA5
enable
INTTA1 (TMRA1)
95H
ITA1C
ITA1M2
R
0
ITA1M1
ITA1M0
R/W
0
ITA3C
ITA3M2
R
0
ITA0C
0
0
0
ITA3M1
ITA5C
ITA5M2
R
0
ITA3M0
0
ITA5M1
Interrupt request flag
0
ITA0M1
ITA0M0
R/W
0
0
0
ITA2C
ITA2M2
0
ITA2M1
ITA2M0
R/W
0
0
0
INTTA4 (TMRA4)
ITA5M0
R/W
0
ITA0M2
R
0
0
INTTA2 (TMRA2)
INTTA5 (TMRA5)
97H
0
R
R/W
0
R/W
INTTA0 (TMRA0)
INTTA3 (TMRA3)
96H
I5M2
R
ITA4C
ITA4M2
R
ITA4M1
ITA4M0
R/W
0
0
0
lxxM2
lxxM1
lxxM0
0
0
0
Disables interrupt requests
0
0
1
Sets interrupt priority level to 1
0
1
0
Sets interrupt priority level to 2
0
1
1
Sets interrupt priority level to 3
1
0
0
Sets interrupt priority level to 4
1
0
1
Sets interrupt priority level to 5
1
1
0
Sets interrupt priority level to 6
1
1
1
Disables interrupt requests
91C630-35
0
0
0
Function (write)
2003-07-22
TMP91C630
Name Symbol Address
7
6
5
4
3
INTTB01 (TMRB0)
Interrupt
enable INTETB0
TMRB0
99H
ITB01C
ITB01M2 ITB01M1
R
Interrupt
enable
INTETBOV
TMRB0V
(over flow)
Interrupt
enable
serial 0
0
ITB00C
ITB00M2
0
0
0
ITX0M2
ITF0M2
9DH
ITX1C
ITX0M0
IRX0C
R/W
0
0
IRX0M2
R
0
ITX1M2
0
0
INTTC0
&
INTETC01
INTTC1
enable
INTTC2
&
INTETC23
INTTC3
enable
ITX1M0
IRX1C
R/W
0
ITC1C
0
0
0
ITC1M0
ITC0C
R/W
0
IRX1M2
ITC3C
0
ITC3M2
0
Interrupt request flag
0
0
IRX1M1
IRX1M0
0
ITC0M2
R
0
0
0
0
ITC0M1
ITC0M0
0
R/W
0
0
0
ITC2M1
ITC2M0
INTTC2
ITC3M1
R
IRX0M0
R/W
INTTC3
A1H
IRX0M1
INTTC0
ITC1M1
R
0
0
R
0
ITC1M2
0
R/W
INTTC1
A0H
ITF0M0
INTRX1
ITX1M1
R
ITF0M1
R/W
INTTX1
INTES1
m After reset
0
INTRX0
ITX0M1
R
source
0
R
ITX0C
m Interrupt
INTTBOF0 (Overflow)
ITF0C
9BH
9CH
0
ITB00M1 ITB00M0 m Bit symbol
m Read/Write
R/W
0
INTTX0
INTES0
1
R
0
(Reserved)
0
Interrupt
enable
serial 1
ITB01M0
R/W
0
2
INTTB00 (TMRB0)
ITC3M0
ITC2C
R/W
0
ITC2M2
R
0
0
0
R/W
0
0
0
lxxM2
lxxM1
lxxM0
0
0
0
Disables interrupt requests
0
0
1
Sets interrupt priority level to 1
0
1
0
Sets interrupt priority level to 2
0
1
1
Sets interrupt priority level to 3
1
0
0
Sets interrupt priority level to 4
1
0
1
Sets interrupt priority level to 5
1
1
0
Sets interrupt priority level to 6
1
1
1
Disables interrupt requests
91C630-36
Function (write)
2003-07-22
TMP91C630
(2) External interrupt control
Name Symbol Address
7
6
5
4
3
2
1
0
I2EDGE
I2LE
I1DGE
I1LE
I0EDGE
I0LE
NMIREE
0
0
0
0
0
0
W
Interrupt
input mode
control 0
IIMC0
8CH
(no RMW) Write 0
INT2EDGE INT2
0: Edge
0: Rising
1: Level
1: Falling
0
INT1EDGE INT1
0: Edge
0: Rising
1: Level
1: Falling
0
INT0EDGE INT0
0: Edge
0: Rising
1: Level
1: Falling
1: Operate
even on
rising/falling
edge of NMI
INT2 level enable
0
Edge detect INT
1
Level INT
INT1 level enable
0
Edge detect INT
1
Level INT
INT0 level enable
0
Edge detect INT
1
Level INT
NMI rising edge enable
0
INT request generation at falling edge
1
INT request generation at rising/falling edge
Name
Interrupt
input
mode
control1
Symbol Address
7
6
5
4
3
2
1
I5EDGE
I5LE
I4EDGE
I4LE
I3EDGE
I3LE
0
0
0
0
0
0
0
W
IIMC1
8DH
(no RMW)
INT5EDGE INT5
0: Edge
0: Rising
1: Level
1: Falling
INT4EDGE INT4
0: Edge
0: Rising
1: Level
1: Falling
INT3EDGE INT3
0: Edge
0: Rising
1: Level
1: Falling
INT5 level enable
0
Edge detect INT
1
Level INT
INT4 level enable
0
Edge detect INT
1
Level INT
INT3 level enable
0
Edge detect INT
1
Level INT
When switching IIMC0 and 1 registers, first every FC registers in port which built-in INT function clear to 0.
91C630-37
2003-07-22
TMP91C630
Setting functions on external interrupt pins
Interrupt Pin
Mode
NMI
Setting Method
Falling edge
<NMIREE>
0
Both falling and Rising edges
<NMIREE>
1
INT0
INT1
INT2
INT3
INT4
INT5
Rising edge
<I0LE>
0, <I0EDGE>
0
Falling edge
<I0LE>
0, <I0EDGE>
1
High level
<I0LE>
1, <I0EDGE>
0
Low level
<I0LE>
1, <I0EDGE>
1
Rising edge
<I1LE>
0, <I1EDGE>
0
Falling edge
<I1LE>
0, <I1EDGE>
1
High level
<I1LE>
1, <I1EDGE>
0
Low level
<I1LE>
1, <I1EDGE>
1
Rising edge
<I2LE>
0, <I2EDGE>
0
Falling edge
<I2LE>
0, <I2EDGE>
1
High level
<I2LE>
1, <I2EDGE>
0
Low level
<I2LE>
1, <I2EDGE>
1
Rising edge
<I3LE>
0, <I3EDGE>
0
Falling edge
<I3LE>
0, <I3EDGE>
1
High level
<I3LE>
1, <I3EDGE>
0
Low level
<I3LE>
1, <I3EDGE>
1
Rising edge
<I4LE>
0, <I4EDGE>
0
Falling edge
<I4LE>
0, <I4EDGE>
1
High level
<I4LE>
1, <I4EDGE>
0
Low level
<I4LE>
1, <I4EDGE>
1
Rising edge
<I5LE>
0, <I5EDGE>
0
Falling edge
<I5LE>
0, <I5EDGE>
1
High level
<I5LE>
1, <I5EDGE>
0
Low level
<I5LE>
1, <I5EDGE>
1
(3) Interrupt request flag clear register
The interrupt request flag is cleared by writing the appropriate micro DMA start
vector, as given in Table 3.5.1, to the register INTCLR.
For example, to clear the interrupt flag INT0, perform the following register
operation after execution of the DI instruction.
INTCLR m 0AH
Name Symbol Address
Interrupt
88H
clear
INTCLR
(no RMW)
control
7
Clears interrupt request flag INT0.
6
5
4
3
2
1
0
CLRV5
CLRV4
CLRV3
CLRV2
CLRV1
CLRV0
0
0
0
0
0
0
W
0
0
Interrupt vector
91C630-38
2003-07-22
TMP91C630
(4) Micro DMA start vector registers
These registers assign micro DMA processing to an sets which source corresponds to
DMA. The interrupt source whose micro DMA start vector value matches the vector
set in one of these registers is designated as the micro DMA start source.
When the micro DMA transfer counter value reaches zero, the micro DMA transfer
end interrupt corresponding to the channel is sent to the interrupt controller, the
micro DMA start vector register is cleared, and the micro DMA start source for the
channel is cleared. Therefore, in order for micro DMA processing to continue, the
micro DMA start vector register must be set again during processing of the micro
DMA transfer end interrupt.
If the same vector is set in the micro DMA start vector registers of more than one
channel, the lowest numbered channel takes priority.
Accordingly, if the same vector is set in the micro DMA start vector registers for two
different channels, the interrupt generated on the lower-numbered channel is
executed until micro DMA transfer is complete. If the micro DMA start vector for this
channel has not been set in the channel’s micro DMA start vector register again, micro
DMA transfer for the higher-numbered channel will be commenced. (This process is
known as micro DMA chaining.)
Name Symbol Address
7
6
5
4
3
2
DMA0V5
DMA0V4
DMA0V3
1
0
DMA0V1
DMA0V0
0
0
DMA1V1
DMA1V0
0
0
DMA2V1
DMA2V0
0
0
DMA3V1
DMA3V0
0
0
DMA0 start vector
DMA0
start
vector
DMA0V
80H
(no RMW)
DMA0V2
R/W
0
0
0
0
DMA1 start vector
DMA1
start
vector
DMA1V
DMA1V5
81H
(no RMW)
DMA1V4
DMA1V3
DMA1V2
R/W
0
0
0
0
DMA2 start vector
DMA2
start
vector
DMA2V
DMA2V5
82H
(no RMW)
DMA2V4
DMA2V3
DMA2V2
R/W
0
0
0
0
DMA3 start vector
DMA3
start
vector
DMA3V
DMA3V5
83H
(no RMW)
DMA3V4
DMA3V3
DMA3V2
R/W
0
0
0
0
(5) Specification of a micro DMA burst
Specifying the micro DMA burst function causes micro DMA transfer, once started,
to continue until the value in the transfer counter register reaches zero. Setting any of
the bits in the register DMAB which correspond to a micro DMA channel (as shown
below) to 1 specifies that any micro DMA transfer on that channel will be a burst
transfer.
Name Symbol Address
DMA
software
request
register
DMAR
DMA
burst
register
DMAB
7
6
5
89H
(no RMW)
4
3
2
1
0
DMAR3
DMAR2
DMAR1
DMAR0
R/W
R/W
R/W
R/W
0
0
0
0
1: DMA software request
DMAB3
DMAB2
8AH
(no RMW)
DMAB1
DMAB0
0
0
R/W
0
91C630-39
0
2003-07-22
TMP91C630
(6) Notes
The instruction execution unit and the bus interface unit in this CPU operate
independently. Therefore if, immediately before an interrupt is generated, the CPU
fetches an instruction which clears the corresponding interrupt request flag (Note), the
CPU may execute this instruction in between accepting the interrupt and reading the
interrupt vector. In this case, the CPU will read the default vector 0008H and jump to
interrupt vector address FFFF08H.
To avoid this, an instruction which clears an interrupt request flag should always be
preceded by a DI instruction.
Thus, before a POP SR instruction is executed, changing the value of the interrupt
mask register <IFF2 to IFF0>, a DI instruction should be used to disable interrupts.
In addition, please note that the following two circuits are exceptional and demand
special attention.
INT0 to 5 level mode
In Level mode INT0 is not an edge-triggered interrupt. Hence, in Level
mode the interrupt request flip-flop for INT0 does not function. The
peripheral interrupt request passes through the S input of the flip-flop
and becomes the Q output. If the interrupt input mode is changed from
Edge mode to Level mode, the interrupt request flag is cleared
automatically.
(For example: in case of INT0)
If the CPU enters the interrupt response sequence as a result of INT0
going from 0 to 1, INT0 must then be held at 1 until the interrupt
response sequence has been completed. If INT0 is set to Level mode
so as to release a HALT state, INT0 must be held at 1 from the time
INT0 changes from 0 to 1 until the HALT state is released. (Hence, it
is necessary to ensure that input noise is not interpreted as a 0,
causing INT0 to revert to 0 before the HALT state has been released.)
When the mode changes from Level mode to Edge mode, interrupt
request flags which were set in Level mode will not be cleared.
Interrupt request flags must be cleared using the following sequence.
DI
LD (IIMC0), 00H; Switches interrupt input mode from Level
mode to Edge mode.
LD (INTCLR), 0AH; Clears interrupt request flag.
EI
INTRX
Note:
The interrupt request flip-flop can only be cleared by a Reset or by
reading the Serial channel receive buffer. It cannot be cleared by an
instruction.
The following instructions or pin input state changes are equivalent to instructions
which clear the interrupt request flag.
INT0 to 5: Instructions which switch to Level mode after an interrupt request has been
generated in Edge mode.
The pin input changes from High to Low after an interrupt request has been
generated in Level mode (H o L).
INTRX: Instructions which read the Receive buffer
91C630-40
2003-07-22
TMP91C630
3.6
Port Functions
The TMP91C630 features 53-bit settings which relate to the various I/O ports.
As well as general-purpose I/O port functionality, the port pins also have I/O functions which
relate to the built-in CPU and internal I/Os. Table 3.6.1 lists the functions of each port pin.
Table 3.6.2 lists I/O registers and their specifications.
Table 3.6.1 Port Functions
Port Name
Pin Name
Number of
Pins
Direction
R
(R: n
with programmable pull-up resistor)
Direction
Setting Unit
Pin Name for Internal
Function
Port 1
P10 to P17
8
I/O
Bit
D8 to D15
Port 2
P20 to P27
8
Output
(Fixed)
A16 to A23
Port 5
P53
P54
P55
P56
1
1
1
1
I/O
I/O
I/O
I/O
n
n
n
n
Bit
Bit
Bit
Bit
INT0
BUSRQ
BUSAK
WAIT
P60
1
Output
(Fixed)
CS0
P61
P62
P63
1
1
1
Output
Output
Output
(Fixed)
(Fixed)
(Fixed)
CS1
Port 7
P70
P71
P72
P73
P74
P75
1
1
1
1
1
1
I/O
I/O
I/O
I/O
I/O
I/O
Bit
Bit
Bit
Bit
Bit
Bit
TA0IN/INT1
TA1OUT
TA3OUT/INT2
TA4IN/INT3
TA5OUT
INT4
Port 8
P80
P81
P82
P83
P84
P85
P86
P87
1
1
1
1
1
1
1
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
n
n
n
n
n
n
n
n
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
TXD0
RXD0
SCLK0/ CTS0
P90
P93
P94
P95
P96
1
1
1
1
1
I/O
I/O
I/O
I/O
I/O
Bit
Bit
Bit
Bit
Bit
INT5
TB0IN0
TB0IN1
TB0OUT0
TB0OUT1
Port 6
Port 9
Port A
PA0 to PA7
7
Input
(Fixed)
Port Z
PZ2
PZ3
1
1
I/O
I/O
n
n
Bit
Bit
91C630-41
CS2
CS3
STS0
TXD1
RXD1
SCLK1/ CTS1
STS1
AN0 to AN7, ADTRG (PA3)
HWR
2003-07-22
TMP91C630
Table 3.6.2 (a) I/O Registers and Their Specifications
Port
Port 1
Port 2
Port Z
Name
P10 toP17
P20 to P27
PZ2
PZ3
Port 5
P53
P54
P55
P56
Port 6
Port 7
X: Don’t care
I/O Registers
Specification
Pn
PnCR
PnFC
Input port
u
0
0
Output port
u
1
0
D8 to D15 bus
u
1
Output port
u
A16 to A23 output
u
Input port (without PU)
0
0
0
Input port (with PU)
1
0
0
Output port
u
1
0
HWR output
u
1
1
Input port (without PU)
0
0
Input port (with PU)
1
0
Output port
u
1
Input port (without PU)
0
0
0
Input port (with PU)
1
0
0
Output port
u
1
0
BUSRQ Input (without PU)
0
0
1
None
1
0
1
None
BUSRQ Input (with PU)
1
0
1
Input port (without PU)
0
0
0
Input port (with PU)
1
0
0
Output port
u
1
0
BUSAK output
u
1
1
Input port/ WAIT input (without PU)
0
0
Input port/ WAIT input (with PU)
1
0
Output port
u
1
None
Input port/INT0 input (without PU)
0
0
1
Input port/INT0 input (with PU)
1
0
1
1
Output port
u
P60 to P63
Output port
u
P60
CS0 output
u
P61
CS1 output
u
P62
CS2 output
u
1
P63
CS3 output
u
1
P70 to P75
Input port
u
0
Output port
u
1
0
TA0IN input
u
0
None
1
P70
0
0
1
None
1
0
INT1 input
u
0
P71
TA1OUT output
u
1
1
P72
TA3OUT output
u
1
1
INT2 input
u
0
1
P73
TA4IN input
u
0
None
INT3 input
u
0
1
P74
TA5OUT output
u
1
1
P75
INT4 input
u
0
1
91C630-42
2003-07-22
TMP91C630
Table 3.6.2 (b) I/O Registers and Their Specifications
Port
Port 8
Name
P80
P81
P82
P83
P84
P85
P86
P87
Port 9
P90
P93 to P96
Port A
Specification
X: Don’t care
I/O Registers
Pn
PnCR
PnFC
Input port (without PU)
0
0
0
Input port (with PU)
1
0
0
Output port
u
1
0
TXD0 output (Note1)
u
1
1
Input port/RXD0 input (without PU)
0
0
None
Input port/RXD0 input (with PU)
1
0
Output port
u
1
Input port/SCLK0/ CTS0 input (without PU)
0
0
0
Input port/SCLK0/ CTS0 input (with PU)
1
0
0
Output port
u
1
0
SCLK0 output
u
1
1
Input port (without PU)
0
0
0
Input port (with PU)
1
0
0
Output port
u
1
0
STS0 output
u
1
1
Input port (without PU)
0
0
0
Input port (with PU)
1
0
0
Output port
u
1
0
TXD1 output (Note1)
u
1
1
Input port/RXD1 input (without PU)
0
0
None
Input port/RXD1 input (with PU)
1
0
Output port
u
1
Input port/SCLK1/ CTS1 input (without PU)
0
0
0
Input port/SCLK1/ CTS1 input (with PU)
1
0
0
Output port
u
1
0
SCLK1 output
u
1
1
Input port (without PU)
0
0
0
Input port (with PU)
1
0
0
Output port
u
1
0
STS1 output
u
1
1
Input port
u
0
0
Output port
u
1
0
INT5 input
u
0
1
Input port
u
0
Output port
u
1
P93
TB0IN0 input
u
0
P94
TB0IN1 input
u
0
P95
TB0OUT0 output
u
1
1
P96
TB0OUT1 output
u
1
1
PA0 to PA7
Input port
u
(Note 2)
u
ADTRG input (Note 3)
u
AN0 to AN7
PA3
None
None
Note 1: If P80 and P84 are used as open-drain output port, they are need to set registers ODE<ODE84,
ODE80>.
Note 2: When PA0 to PA7 are used as AD converter input channels, a 3-bit field in the AD mode control
register ADMOD1<ADCH2:0> is used to select the channel.
Note 3: When PA3 is used as the ADTRG input, ADMOD1<ADTRGE> is used to enable external trigger
input.
91C630-43
2003-07-22
TMP91C630
After a Reset the port pins listed below function as general-purpose I/O port pins.
A Reset sets I/O pins which can be programmed for either input or output to be input port
pins.
Setting the port pins for internal function use must be done in software.
Note about bus release and programmable pull-up I/O port pins
When the bus is released (e.g. when BUSAK 0), the output buffers for D0 to D15, A0 to A23,
and the control signals ( RD , WR , HWR and CS0 to CS3 ) are off and are set to
High-impedance.
However, the output of built-in programmable pull-up resistors are kept before the bus is
released. These programmable pull-up resistors can be selected ON/OFF by programmable
when they are used as the input ports.
When they are used as output ports, they cannot be turned ON/OFF in software.
Table 3.6.3 shows the pin states after the bus has been released.
Table 3.6.3 Pin States (after Bus Release)
Pin Names
Pin State (after Bus Release)
Used as Port
D0 to D7
P10 to P17
(D8 to D15)
High-Impedance (High-Z)
Unchanged
(e.g. not set to High-impedance (High-Z))
RD
WR
Unchanged
(e.g. not set to High-impedance (High-Z))
n
n
n
n
The output buffer is set to OFF.
The programmable pull-up resistor is set to ON
irrespective of the output latch.
n
n
PZ2 ( HWR )
P60 ( CS0 )
P61 ( CS1 )
P62 ( CS2 )
P63 ( CS3 )
n
First all bits are set High, then they are set to
High-Impedance (High-Z).
A0 to A15
P20 to P27
(A16 to A23)
Used for Function
91C630-44
2003-07-22
TMP91C630
Figure 3.6.1 shows an example external interface circuit when the bus release function is
used.
When the bus is released, neither the internal memory nor the internal I/O can be accessed.
However, the internal I/O continues to operate. As a result, the watchdog timer also continues
to run. Therefore, the bus release time must be taken into account and care must be taken when
setting the detection time for the WDT.
RD
WR
PZ2 ( HWR )
System control bus
P60 ( CS0 )
P61 ( CS1 )
P62 ( CS2 )
P63 ( CS3 )
P20 (A16)
to
P27 (A23)
Address bus (A23 to A16)
Figure 3.6.1 Interface Circuit Example (Using Bus Release Function)
The above circuit is necessary to set the signal level when the bus is released.
A reset sets ( RD ) and ( WR ), P60 ( CS0 ), P61 ( CS1 ), P62 ( CS2 ), P63 ( CS3 ) to output, and PZ2
( HWR ) and P54 ( BUSAK ) to input with pull-up resistor.
91C630-45
2003-07-22
TMP91C630
3.6.1
Port 1 (P10 to P17)
Port 1 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or
output using the control register P1CR. Resetting, the control register P1CR to 0 and sets
Port 1 to input mode.
In addition to functioning as a general-purpose I/O port, Port 1 can also function as an
address data bus (D8 to D15).
In case of AM1 0, and AM0 1 (outside 16-bit data bus), port 1 always functions as the
data bus (D8 to D15) irrespective of the setting in P1CR control register.
Reset
Direction control
(on bit basis)
P1CR write
Internal data bus
Output latch
Port 1
P10 to P17
(D8 to D15)
Output buffer
P1 write
P1 read
Figure 3.6.2 Port 1
Port 1 Register
Bit symbol
P1
(0001H) Read/Write
7
6
5
4
3
2
1
0
P17
P16
P15
P14
P13
P12
P11
P10
R/W
After reset
Data from external port (Output latch register is cleared to 0.)
Port 1 Control Register
Bit symbol
P1CR
(0004H) Read/Write
After reset
7
6
5
4
3
2
1
0
P17C
P16C
P15C
P14C
P13C
P12C
P11C
P10C
0
0
0
0
0
0
0
0
W
Function
Note:
0: In
1: Out
Read-modify-write is prohibited for P1CR.
Port 1 I/O setting
0
Input
1
Output
Figure 3.6.3 Register for Port 1
91C630-46
2003-07-22
TMP91C630
3.6.2
Port 2 (P20 to P27)
Port 2 is an 8-bit output port. In addition to functioning as a output port, Port 2 can also
function as an address bus (A16 to A23).
Each bit can be set individually for address bus using the function register P2FC.
Resetting sets all bits of the function register P2FC to 1 and sets Port 2 to address bus.
Reset
S
Function control
Internal data bus
(on bits basis)
P2FC write
Output
latch
B
Selector
S
A
Output buffer
P2 write
Port 2
P20 to P27
(A16 to A23)
P2 read
Internal A16 to A23
Figure 3.6.4 Port 2
Port 2 Register
Bit symbol
P2
(0006H) Read/Write
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
R/W
After reset
Output latch register is set to 1
Port 2 Function Register
7
6
5
4
3
2
1
0
Bit symbol
P27F
P26F
P25F
P24F
P23F
P22F
P21F
P20F
After reset
1
1
1
1
1
1
1
1
P2FC
(0009H) Read/Write
Function
Note:
W
0: Port
1: Address bus (A23 to A16)
Read-modify-write is prohibited for P2FC.
Figure 3.6.5 Register for Port 2
91C630-47
2003-07-22
TMP91C630
Port 5 (P53 to P56)
Port 5 is an 4-bit general-purpose I/O port. I/O is set using control register P5CR and
P5FC. Resetting resets all bits of the output latch P5 to 1, the control register P5CR and
the function register P5FC to 0 and sets P52 to P56 to input mode with pull-up register.
In addition to functioning as a general-purpose I/O port, Port 5 also functions as I/O for
the CPU’s control/status signal.
Reset
Direction control
(on bit basis)
P5CR write
Function control
Internal data bus
3.6.3
(on bit basis)
P5FC write
P-ch
(Programmable pull-up)
S
Output
latch
P53 ( BUSRQ )
P5 write
P5 read
Internal BUSRQ
Figure 3.6.6 Port 53
91C630-48
2003-07-22
TMP91C630
Reset
Direction control
(on bit basis)
P5CR write
(on bit basis)
P5FC write
P-ch
(Programmable pull-up)
S
S
Output
latch
A
B
Selector
Internal data bus
Function control
P54 ( BUSAK )
Output buffer
P5 write
BUSAK
P5 read
Figure 3.6.7 Port 54
Reset
Direction control
(on bit basis)
P-ch
(Programmable pull-up)
Internal data bus
P5CR write
S
Output
latch
P55 ( WAIT )
Output buffer
P5 write
P5 read
Internal WAIT
Figure 3.6.8 Port 55
91C630-49
2003-07-22
TMP91C630
Reset
Direction control
(on bit basis)
Internal data bus
P5CR write
Function control
(on bit basis)
P5FC write
P-ch
(Programmable pull-up)
S
Output latch
P56 (INT0)
P5 write
Output buffer
S
B
Selector
P5 write
INT0
A
Level or edge
&
rising edge or falling edge
IIMC0<I0LE, I0EDGE>
Figure 3.6.9 Port 56
91C630-50
2003-07-22
TMP91C630
Port 5 Register
7
Bit symbol
P5
(000DH) Read/Write
6
5
4
3
P56
P55
P54
P53
2
1
0
2
1
0
1
0
R/W
Data from external port
(Output latch register is set to 1)
After reset
Function
0: Pull-up resistor OFF
1: Pull-up resistor ON
Port 5 Control Register
7
Bit symbol
P5CR
(0010H) Read/Write
6
5
4
3
P56C
P55C
P54C
P53C
0
0
0
0
W
After reset
Function
0: In
1: Out
I/O setting
0
Input
1
Output
Port 5 Function Register
7
Bit symbol
P5FC
(0011H) Read/Write
After reset
Function
6
5
P56F
4
3
P54F
P53F
W
2
W
0
0
0: Port
1: INT0
input
0: Port
1: BUSAK
0
0: Port
1: BUSRQ
Note 1: Read-modify-write are prohibited for registers P5CR and P5FC.
Note 2: When port 5 is used in the input mode, P5 register controls the built-in pull-up resistor.
Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up
resistor may be depended on the states of the input pin.
Note 3: When P55 pin is used as a WAIT pin, clear P5CR<P55C> to 0 and Chip select/WAIT control
register <BnW2:0> to 010.
Figure 3.6.10 Register for Port 5
91C630-51
2003-07-22
TMP91C630
Port 6 (P60 to P63)
Port 6 is a 4-bit output port. When reset, the P62 output latch is cleared to 0 while the
P60, P61 and P63 output latches are set to 1.
In addition to functioning as an output port, this port can output standard chip select
signals ( CS0 to CS3 ). These settings are made by using the P6FC register. When reset, the
P6FC register has all of its bits cleared to 0, so that the port is set for output mode.
Internal data bus
Reset
Funtion
control
(on bit basis)
P6FC write
S
S
Output
lacth
A
B Selector
Output buffer
P60 ( CS0 ),
P61 ( CS1 ),
P63 ( CS3 )
P6 write
P6 read
CS0 , CS1 , CS3
Figure 3.6.11 Port 60, 61 and 63
Reset
Function control
(on bit basis)
P6FC write
S
R
Output
latch
A
B
Selector
Internal data bus
3.6.4
P62 ( CS2 )
Output buffer
P6 write
CS2
P6 read
Figure 3.6.12 Port 62
91C630-52
2003-07-22
TMP91C630
Port 6 Register
7
6
5
4
Bit symbol
P6
(0012H) Read/Write
After reset
3
2
1
0
P63
P62
P61
P60
R/W
Output latch Output latch
Output latch register is
register is
register is
set to 1.
set to 1.
clear to 0.
Port 6 Function Register
7
6
5
4
Bit symbol
P6FC
(0015H) Read/Write
3
2
1
0
P63F
P62F
P61F
P60F
0
0
0
0
W
After reset
Function
Note:
0: Port
1: CS
Read-modify-write is prohibited for the registers P6FC.
0
1
Port (P60)
0
1
Port (P61)
0
1
Port (P62)
0
1
Port (P63)
CS0
CS1
CS2
CS3
Figure 3.6.13 Register for Port 6
91C630-53
2003-07-22
TMP91C630
3.6.5
Port 7 (P70 to P75)
Port 7 is a 6-bit general-purpose I/O port. Each bit can be set individually for input or
output. Resetting sets Port 7 to be an input port. In addition to functioning as a
general-purpose I/O port, the individual port pins can also have the following functions:
port pins 70 and 73 can function as the inputs TA0IN and TA4IN to the 8-bit timer, and
port pins 71, 72 and 74 can function as the 8-bit timer outputs TA1OUT, TA3OUT and
TA5OUT. For each of the output pins, timer output can be enabled by writing a 1 to the
corresponding bit in the Port 7 function register (P7FC).
Resetting clears all bits of the registers P7CR and P7FC to 0, and sets all bits to be input
port pins.
Reset
Direction control
(on bit basis)
P7CR write
Function control
(on bit basis)
Internal data bus
P7FC write
S
Output latch
S B
P7 write
P70 (TA0IN/INT1)
P73 (TA4IN/INT3)
P75 (INT4)
Selector
INT1
P7 read
A
INT3
INT4
Level or edge
and
rising edge or falling edge
TA0IN
IIMC0<I1LE, I1EDGE>
IIMC1<I3LE, I3EDGE>
IIMC1<I4LE, I4EDGE>
TA4IN
Figure 3.6.14 Ports 70, 73 and 75
91C630-54
2003-07-22
TMP91C630
Reset
Direction control
(on bit basis)
P7CR write
Function control
(on bit basis)
Internal data bus
P7FC write
S
Output latch
A S
Selector
Timer F/F out
P7 write
B
TA1OUT: 8-bit TMRA1
TA5OUT: 8-bit TMRA5
P71 (TA1OUT)
P74 (TA5OUT)
B
Selector
P7 read
S A
Figure 3.6.15 Ports 71 and 74
Reset
Direction control
(on bit basis)
P7CR write
Function control
(on bit basis)
P7FC write
Internal data bus
Function control
(on bit basis)
P7FC write
S
Output latch
Timer F/F out
P7 write
(TA3OUT: 8-bit TMRA3)
A S
Selector
P72 (TA3OUT/INT2)
B
B
Selector
P7 read
S A
INT2
Edge or level
&
Rising edge or falling edge
IIMC0<I2LE, I2EDGE>
Figure 3.6.16 Port 72
91C630-55
2003-07-22
TMP91C630
Port 7 Register
7
6
P7
Bit symbol
(0013H)
Read/Write
5
4
3
2
1
0
P75
P74
P73
P72
P71
P70
R/W
After reset
Data from external port (Output register is set to 1)
Port 7 Control Register
7
6
P7CR
Bit symbol
(0016H)
Read/Write
5
4
3
2
1
0
P75C
P74C
P73C
P72C
P71C
P70C
0
0
0
0
0
0
W
After reset
Port 7 I/O setting
0
Input
1
Output
Port 7 Function Register
7
Bit symbol
P7FC
(0017H) Read/Write
After reset
Function
6
5
4
3
2
1
0
P72F2
P75F
P74F
P73F
P72F1
P71F
P70F
W
W
0
0
0: Port
1: INT2
input
0: Port
1: INT4
input
W
0
0
0: Port
0: Port
1: TA5OUT 1: INT3
input
W
0
W
0
0
0: Port
0: Port
0: Port
1: TA3OUT 1: TA1OUT 1: INT1
input
Note: Read-modify-write are prohibited for the registers
P7CR and P7FC.
Setting P71 as 8-bit timer output 1
P7FC<P71F>
P7CR<P71C>
1
1
Setting P72 as 8-bit timer output 3
P7FC<P72F1>
P7CR<P72C>
1
1
Setting P74 as 8-bit timer output 5
P7FC<P74F>
P7CR<P74C>
1
1
Figure 3.6.17 Port 7 Registers
91C630-56
2003-07-22
TMP91C630
Port 8 (P80 to P87)
x
Port pins 80 to 87
Port pins 80 to 87 constitute a 8-bit general-purpose I/O port. Each bit can be set
individually for input or output. Resetting sets P80 to P87 to be an input port. It also sets
all bits of the output latch register to 1.
In addition to functioning as general-purpose I/O port pins, P80 to P87 can also function
as the I/O for serial channel 0. These function can be enabled for I/O by writing a 1 to the
corresponding bit of the Port 8 Function Register (P8FC).
Resetting clears all bits of the registers P8CR and P8FC to 0 and sets all bits to be input
port pins. (with pull-up resistors).
(1) Port pins 80 (TXD0) and 84 (TXD1)
As well as functioning as I/O port pins, port pins 80 and 84 can also function as serial
channel TXD output pins.
These port pins feature a programmable open-drain function.
Reset
Direction control
(Each bit can be
set individually.)
P8CR write
Internal data bus
3.6.6
P-ch
Function control
(Each bit can be
set individually.)
(Programmable pull-up)
P8FC write
S
Output latch
A
S
Selector
P8 write
TXD0 or TXD1
B
S
B
Open-drain
possible
ODE<ODE80, 84>
Output buffer
P80 (TXD0)
P84 (TXD1)
Selector
P8 read
A
Figure 3.6.18 Port Pins 80 and 84
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TMP91C630
(2) Port pins 81 (RXD0) and 85 (RXD1)
Port pins 81 and 85 are I/O port pins and can also be used as RXD input pin for the
serial channels.
Reset
P-ch
Internal data bus
Direction control
(Each bit can be
set individually.)
(Programmable pull-up)
P8CR write
S
Output latch
Output buffer
S
P8 write
P81 (RXD0)
P85 (RXD1)
B
Selector
P8 read
A
RXD0 or RXD1
Figure 3.6.19 Port pins 81 and 85
(3) Port pins 82 ( CTS0 /SCLK0) and 86 ( CTS1 /SCLK1)
Port pins 82 and 86 are I/O port pins and can also be used as the CTS input pins or
SCLK I/O pins for the serial channels.
Reset
Direction control
(Each bit can be
set individually.)
P-ch
Internal data bus
P8CR write
(Programmable pull-up)
Function control
(Each bit can be
set individually.)
P8FC write
S
Output latch
P8 write
A
S
Selector
P82 (SCLK0/ CTS0 )
P86 (SCLK1/ CTS1 )
B
SCLK0
SCLK1
S B
Selector
P8 read
A
SCLK0, CTS0 input
SCLK1, CTS1 input
Figure 3.6.20 Ports 82 and 86
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2003-07-22
TMP91C630
(4) Port pins 83 ( STS0 ) and 87 ( STS1 )
Port pins 83 and 87 are I/O port pins and can also be used as STS output pin for the
received data request signal.
Reset
Direction control
(on bit basis)
P8CR write
Internal data bus
Function control
(on bit basis)
P8FC write
S
Output latch
P8 write
S
A
Y
Selector
B
P-ch
(Programmable pull-up)
P83 ( STS0 )
P87 ( STS1 )
STS0 or STS1
P8 read
S
B
Selector
Y
A
Figure 3.6.21 Port Pins 83 and 87
91C630-59
2003-07-22
TMP91C630
Port 8 Register
Bit symbol
7
6
5
4
3
2
1
0
P87
P86
P85
P84
P83
P82
P81
P80
P8
Read/Write
(0018H)
After reset
R/W
Data from external port (Output latch register is set to 1)
Function
0: Pull-up resistor OFF
1: Pull-up resistor ON
Port 8 Control Register
Bit symbol
P8CR
(001AH) Read/Write
After reset
7
6
5
4
3
2
1
0
P87C
P86C
P85C
P84C
P83C
P82C
P81C
P80C
0
0
0
0
0
0
0
0
W
Function
0: In 1: Out
Port 8 I/O setting
0
Input
1
Output
Port 8 Function Register
Bit symbol
P8FC
(001BH) Read/Write
After reset
Function
7
6
4
3
2
P87F
P86F
P84F
P83F
P82F
P80F
W
W
W
W
W
W
0
0
0
0
0
0: Port
1: STS1
output
5
0: Port
1: SCLK1
output
0: Port
1: TXD1
output
0: Port
1: STS0
output
Note 1: Read-modify-write are prohibited for the registers
P8CR and P8FC.
Note 2: Writing 1 to bit 0 of the ODE register sets the TXD0,
1 pin to be open-drain.
No register is provided for switching between the I/O
port and RXD input functions of the P81/RXD0,
P85/RXD1 pin. Hence, when Port 8 is used as an
input port, the serial data input signals received on
those pins are also input to the SIO.
0: Port
1: SCLK0
output
1
0
0
0: Port
1: TXD0
input
To set P80 and P84 for TXD0 and TXD1 outputs
P8FC<P80F><P84F>
1
P8CR<P80C><P84C>
1
To set P82 and P86 for SCLK0 and SCLK1 outputs
P8FC<P82F><P86F>
P8CR<P82C><P86C>
1
1
To set P83 and P87 for STS0 and STS1 outputs
P8FC<P83F><P87F>
1
P8CR<P83C><P87C>
1
Figure 3.6.22 Port 8 Register
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TMP91C630
Port 9 (P90, P93 to P96)
Port 9 is an 5-bit general-purpose I/O port. Each bit can be set individually for input or
output, Resetting sets port 9 to be an input port, It also sets all bits in the output latch
register P9 to 1. In addtion to functioning as a general-purpose I/O port, the various pins of
Port 9 can also function as the clock input for the 16-bit timer flipflop putput, on as input
INT5. These functions cn be enabled by writing a 1 to the corresponding bits in the Port 9
function registers (P9FC).
(1) P90
Reset
Direction control
(on bit basis)
P9CR write
Internal data bus
3.6.7
S
Output latch
P90 (INT5)
P9 write
S
B
Selector
Y
A
P9 read
Level or edge
and
rising edge or falling edge
INT5
P9FC<P90F>
IIMC1<I5LE/I5EDGE>
Figure 3.6.23 Port 90
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2003-07-22
TMP91C630
(2) P93 to P96
Reset
Direction control
(on bit basis)
P9CR write
S
Output latch
P93 (TB0IN0)
P94 (TB0IN1)
S
P9 write
B
Selector
P9 read
A
Internal data bus
TB0IN0
TB0IN1
Reset
Direction control
(on bit basis)
P9CR write
Function control
(on bit basis)
P9FC write
S
Output latch
A
P9 write
Timer F/F OUT
S
Selector
B
P95 (TB0OUT0)
P96 (TB0OUT1)
TB0OUT0: 16-bit TMRB0
TB0OUT1: 16-bit TMRB0
B
Selector
P9 read
S A
Figure 3.6.24 Port Pins P93 to P96
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2003-07-22
TMP91C630
Port 9 Register
7
Bit symbol
6
5
4
3
P96
P95
P94
P93
Read/Write
P9
(0019H) After reset
2
1
0
P90
R/W
R/W
Data from
external port
(Output latch
register is set
to 1)
Data from external port
(Output latch register is set to 1)
Port 9 Control Register
7
6
5
4
3
Bit symbol
P96C
P95C
P94C
P93C
After reset
0
0
0
0
P9CR
(001CH) Read/Write
2
1
0
P90C
W
W
Function
0
0: In 1: Out
Port 9 I/O setting
0
Input
1
Output
Port 9 Function Register
7
Bit symbol
P9FC
(001DH) Read/Write
After reset
Function
6
5
P96F
P95F
4
3
2
1
P90F
0
W
W
W
0
0
0
0: Port
0: Port
1: TB0OUT1 1: TB0OUT0
0: Port
1: INT5
input
To set P95 for TB0OUT0 output
1
P9FC<P95F>
1
P9CR<P95C>
To set P96 for TB0OUT1 output
1
P9FC<P96F>
1
P9CR<P96C>
Note:
Read-modify-write are prohibited for the registers
P9CR and P9FC.
Figure 3.6.25 Port 9 Registers
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TMP91C630
3.6.8
Port A (PA0 to PA7)
Internal data bus
Port A is an 8-bit input port and can also be used as the analog input pins for the internal
AD converter.
PA0 to PA7
( ADTRG , AN0
to AN7)
Port A read
Conversion
result
register
AD
converter
Channel
selector
AD read
ADTRG
(for PA3 only)
Figure 3.6.26 Port A
Port A Register
Bit symbol
PA
(001EH) Read/Write
After reset
Note:
7
6
5
4
3
2
1
0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
R
Data from external port
The input channel selection of AD converter and the permission of ADTRG input are set by AD converter mode
register ADMOD1.
Figure 3.6.27 Port A Register
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TMP91C630
Port Z (PZ2, PZ3)
Port Z is a 2-bit general-purpose I/O port. I/O is set using control register PZCR and
PZFC. Resetting clears all bits of the output latch PZ to 1, the control register PZCR and
the function register PZFC to 0 and sets PZ2 and PZ3 to input mode with pull-up register.
In addition to functioning as a general-purpose I/O port. Port Z also functions as I/O for
the CPU’s control/status signal.
Reset
Direction control
(on bit basis)
PZCR write
(on bit basis)
PZFC write
P-ch
(Programmable pull-up)
S
S
Output
latch
A
Selector
Internal data bus
Function control
B
PZ2 ( HWR )
Output buffer
PZ write
HWR
PZ read
Figure 3.6.28 Port Z2
Reset
Direction control
(on bit basis)
Internal data bus
3.6.9
P-ch
(Purogrammable pull-up)
PZCR write
S
Output latch
PZ write
PZ3
S
Output buffer
B
Selector
PZ read
A
Figure 3.6.29 Port Z3
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TMP91C630
Port Z Register
7
6
5
4
Bit symbol
PZ
(007DH) Read/Write
3
2
PZ3
PZ2
1
0
1
0
1
0
R/W
Data from external port
(Note)
After reset
Function
0: Pull-up resistor OFF
1: Pull-up resistor ON
Note: Output latch register is set to 1.
Port Z Control Register
7
6
3
2
Bit symbol
5
4
PZ3
PZ2
After reset
0
PZCR
(007EH) Read/Write
W
0
Function
0: In 1: Out
Setting Port Z as I/O
0
Input
1
Output
Port Z Control Register
7
6
5
4
3
Bit symbol
2
PZ2F
PZFC
(007FH) Read/Write
W
After reset
0
Function
0: Port
1: HWR
Figure 3.6.30 Port Z Registers
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2003-07-22
TMP91C630
3.7
Chip Select/Wait Controller
On the TMP91C630, four user-specifiable address areas (CS0 to CS3) can be set. The data bus
width and the number of waits can be set independently for each address area (CS0 to CS3 plus
any other).
The pins CS0 to CS3 (which can also function as port pins P60 to P63) are the respective
output pins for the areas CS0 to CS3. When the CPU specifies an address in one of these areas,
the corresponding CS0 to CS3 pin outputs the chip select signal for the specified address area
(in ROM or SRAM). However, in order for the chip select signal to be output, the Port 6 function
register P6FC must be set. External connection of ROM and SRAM is supported.
The areas CS0 to CS3 are defined by the values in the memory start address registers
MSAR0 to MSAR3 and the memory address mask registers MAMR0 to MAMR3.
The chip select/wait control registers B0CS to B3CS and BEXCS should be used to specify the
master enable/disable status the data bus width and the number of waits for each address area.
The input pin which controls these states is the bus wait request pin ( WAIT ).
3.7.1
Specifying an Address Area
The address areas CS0 to CS3 are specified using the memory start address registers
(MSAR0 to MSAR3) and the memory address mask registers (MAMR0 to MAMR3).
During each bus cycle, a compare operation is performed to determine whether or not the
address specified on the bus corresponds to a location in one of the areas CS0 to CS3. If the
result of the comparison is a match, it indicates that the corresponding CS area is to be
accessed. If so, the corresponding CS0 to CS3 pin outputs the chip select signal and the
bus cycle proceeds according to the settings in the corresponding B0CS to B3CS chip
select/wait control register. See 3.7.2, chip select/wait control registers.
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2003-07-22
TMP91C630
(1) Memory start address registers
Figure 3.7.1 shows the memory start address registers. The memory start address
registers MSAR0 to MSAR3 determine the start addresses for the memory areas CS0
to CS3 respectively. The eight most significant bits (A23 to A16) of the start address
should be set in <S23 to S16>. The 16 least significant bits of the start address (A15 to
A0) are fixed to 0. Thus the start address can only be set to lie on a 64-Kbyte boundary,
starting from 000000H. Figure 3.7.2 shows the relationship between the value set in
the start address register and the start address.
Memory Start Address Registers (for Areas CS0 to CS3)
MSAR0 (00C8H)/
MSAR1 (00CAH)
Bit symbol
MSAR2 (00CCH)/
MSAR3 (00CEH)
After reset
7
6
5
4
3
2
1
0
S23
S22
S21
S20
S19
S18
S17
S16
1
1
1
1
1
1
1
1
Read/Write
R/W
Function
Determines A23 to A16 of start address.
Sets start addresses for areas CS0 to CS3.
Figure 3.7.1 Memory Start Address Register
Start address
Address
000000H
64 Kbytes
Value in start address register (MSAR0 to MSAR3)
000000H ..................... 00H
010000H ..................... 01H
020000H ..................... 02H
030000H ..................... 03H
040000H ..................... 04H
050000H ..................... 05H
060000H ..................... 06H
to
to
FF0000H ..................... FFH
FFFFFFH
Figure 3.7.2 Relationship between Start Address and Start Address Register Value
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2003-07-22
TMP91C630
(2) Memory address mask registers
Figure 3.7.3 shows the memory address mask registers. The size of each of the areas
CS0 to CS3 can be set by specifying a mask in the corresponding memory address mask
register (MAMR0 to MAMR3). Each bit in a memory address mask register (MAMR0
to MAMR3) which is set to 1 masks the corresponding bit of the start address which
has been set in the corresponding memory start address register (MSAR0 to MSAR3).
The compare operation used to determine whether or not a bus address is in one of the
areas CS0 to CS3 only compares address bits for which a 0 has been set in the
corresponding bit position in the corresponding memory address mask register.
Also, the address bits which each memory address mask register can mask vary from
register to register; hence, the possible size settings for the areas CS0 to CS3 differ
accordingly.
Memory Address Mask Register (for CS0 Area)
7
6
5
4
3
2
1
0
Bit symbol
V20
V19
V18
V17
V16
V15
V14 to 9
V8
After reset
1
1
1
1
1
1
1
1
MAMR0
(00C9H) Read/Write
R/W
Function
Sets size of CS0 area 0: used for address compare
Range of possible settings for CS0 area size: 256 bytes to 2 Mbytes.
Memory Address Mask Register (CS1)
MAMR1 Bit symbol
(00CBH) Read/Write
After reset
7
6
5
4
3
2
1
0
V21
V20
V19
V18
V17
V16
V15 to 9
V8
1
1
1
1
1
1
1
1
R/W
Function
Sets size of CS0 area 0: used for address compare
Range of possible settings for CS1 area size: 256 bytes to 4 Mbytes.
Memory Address Mask Register (CS2 and CS3)
MAMR2 (00CDH)/ Bit symbol
MAMR3 (00CFH) Read/Write
After reset
Function
7
6
5
4
3
2
1
0
V22
V21
V20
V19
V18
V17
V16
V15
1
1
1
1
1
1
1
1
R/W
Sets size of CS2 or CS3 area 0: used for address compare
Range of possible settings for CS2 and CS3 area sizes: 32 Kbytes to 8 Mbytes.
Figure 3.7.3 Memory Address Mask Registers
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(3) Setting memory start addresses and address areas
Figure 3.7.4 shows an example in which CS0 is specified to be a 64-Kbyte address
area starting at 010000H.
First, MSAR0<S23:16>, the eight most significant bits of the start address register
and which correspond to the memory start address, are set to 01H. Next, based on the
desired CS0 area size, the difference between the start address and the end address
(01FFFFH) is calculated. Bits 20 to 8 of this result constitute the mask value for the
desired CS0 area size. Setting this value in MAMR0<V20:8> (bits 20 to 8 of the
memory address mask register) sets the desired area size for CS0. In this example 07H
is set in MAMR0, specifying an area size of 64 Kbytes.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
F
1
1
1
1
F
1
1
1
1
F
1
1
H
F
Memory
end
address
CS0 area
size
(64 Kbytes)
S23 S22 S21 S20 S19 S18 S17 S16
MSAR0
0
0
0
0
0
0
0
0
Memory
start
address
1
1
H
V20 V19 V18 V17 V16 V15
MAMR0 0
0
0
0
0
0
0
0
0
1
V14 to V9
1
1
1
1
V8
1
1
1
7
1
1
1
1
1
1
1
H
1
Memory address
mask register
setting
Setting of 07H specifies a 64-Kbyte area.
Figure 3.7.4 Example Showing How to Set the CS0 Area
A reset sets MSAR0 to MSAR3 and MAMR0 to MAMR3 to FFH. In addition,
B0CS<B0E>, B1CS<B1E> and B3CS<B3E> are reset to 0, disabling the CS0, CS1 and
CS3 areas. However, since a reset resets B2CS<B2M> to 0 and sets B2CS<B2E> to 1,
CS2 is enabled with the address range 002800H to 01F7FFH, 020000H to FFFFFFH.
When addresses outside the areas specified as CS0 to CS3 are accessed, the bus width
and number of waits specified in BEXCS are used. (See 3.7.2, Chip Select/Wait Control
Registers.)
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2003-07-22
TMP91C630
(4) Address area size specification
Table 3.7.1 shows the valid area sizes for each CS area and indicates which method
can be used to make the size setting. A ' indicates that it is not possible to set the area
size in question using the memory start address register and memory address mask
register. If an area size for a CS area marked ' in the table is to be set, the start
address must either be set to 000000H or to a value that is greater than 000000H by an
integer multiple of the desired area size.
If the CS2 area is set to 16 Mbytes or if two or more areas overlap, the
lowest-numbered CS area has highest priority (e.g. CS0 has a higher priority than any
other area).
Example: To set the area size for CS0 to 128 Kbytes:
a.
Valid start addresses
000000H
020000H
040000H
128 Kbytes
128 Kbytes
Any of these addresses may be set as the start address.
128 Kbytes
060000H
b.
Invalid start addresses
000000H
010000H
030000H
This is not an integer multiple of the desired area size
setting. Hence, none of these addresses can be set as the
start address.
64 Kbytes
128 Kbytes
128 Kbytes
050000H
Table 3.7.1 Valid Area Sizes for Each CS Area
Size (bytes)
CS area
CS0
CS1
CS2
CS3
256
512
32 K
64 K
128 K
256 K
512 K
1M
2M
ż
ż
ż
ż
ż
ż
ż
ż
ż
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
ż
ż
91C630-71
4M
8M
2003-07-22
TMP91C630
3.7.2
Chip Select/Wait Control Registers
Figure 3.7.5 lists the chip select/wait control registers.
The master enable/disable, chip select output waveform, data bus width and number of
wait states for each address area (CS0 to CS3 plus any other) are set in the respective chip
select/wait control registers, B0CS to B3CS or BEXCS.
Chip Select/Wait Control Register
7
B0CS
(00C0H)
Bit symbol
B0E
Read/Write
W
After reset
0
Read-modify
Function
-write
instructions
are
prohibited.
B1CS
(00C1H)
B1E
Read/Write
W
B2CS
(00C2H)
3
2
1
0
B0BUS
B0W2
B0W1
B0W0
0
0
0
B1OM1
1
0: Disable
1: Enable
Bit symbol
B3E
Read/Write
W
Read-modify After reset
Functions
-write
instructions
are
prohibited.
0
0
Chip select output
waveform selection
00: For ROM/SRAM
01:
10:
Don’t care
11:
B2M
B2OM1
0: 16 bits
1: 8 bits
B1BUS
B1W1
B1W0
0
0
0
Number of waits
000: 2 waits
001: 1 wait
010: (1 N) waits
011: 0 waits
B2BUS
0
0: Disable
1: Enable
0
CS2 area
selection
0: 16-Mbyte
area
1: CS area
0
0
Chip select output
waveform selection
00: For ROM/SRAM
01:
10:
Don’t care
11:
B3OM1
B3OM0
B2W1
B2W0
0
0
0
0
Data bus
width
Number of waits
000: 2 waits
001: 1 wait
010: (1 N) waits
011: 0 waits
0: 16 bits
1: 8 bits
B3BUS
0
0
Chip select output
waveform selection
00: For ROM/SRAM
01:
10:
Don’t care
11:
B3W2
B3W1
B3W0
0
0
0
0
Data bus
width
Number of waits
000: 2 waits
001: 1 wait
010: (1 N) waits
011: 0 waits
0: 16 bits
1: 8 bits
BEXBUS
BEXW2
0
CS area disable
1
CS area enable
CS2 area selection
1
16-Mbyte area
BEXW1
BEXW0
0
0
0
Data bus
width
Number of waits
000: 2 waits
001: 1 wait
010: (1 N) waits
011: 0 waits
0: 16 bits
1: 8 bits
Master enable bit
1xx: Reserved
W
Functions
0
1xx: Reserved
W
After reset
0
1xx: Reserved
B2W2
Read/Write
Read-modify
-write
instructions
are
prohibited.
1xx: Reserved
B1W2
0
Data bus
width
0: 16 bits
1: 8 bits
B2OM0
Bit symbol
BEXCS
(00C7H)
Number of waits
000: 2 waits
001: 1 wait
010: (1 N) waits
011: 0 waits
W
After reset
B3CS
(00C3H)
Data bus
width
B1OM0
Read/Write
Read-modify
Functions
-write
instructions
are
prohibited.
0
W
0
B2E
4
B0OM0
W
0: Disable
1: Enable
Bit symbol
5
B0OM1
0
0
Chip select output
waveform selection
00: For ROM/SRAM
01:
10:
Don’t care
11:
0: Disable
1: Enable
Bit symbol
Read-modify After reset
-write
Function
instructions
are
prohibited.
6
Chip select output
waveform selection
Number of address area waits
(See 3.7.2 (3) Wait Control.)
00 For ROM/SRAM
01
10 Don’t care
11
Specified address area
1xx: Reserved
Data bus width selection
0
16-bit data bus
1
8-bit data bus
Figure 3.7.5 Chip Select/Wait Control Registers
91C630-72
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TMP91C630
(1) Master enable bits
Bit 7 (<B0E>, <B1E>, <B2E> or <B3E>) of a chip select/wait control register is the
master bit which is used to enable or disable settings for the corresponding address
area. Writing 1 to this bit enables the settings. A Reset disables <B0E>, <B1E> and
<B3E> (i.e sets them to 0) and enables <B2E> (i.e. sets it to 1). Hence after a Reset only
the CS2 area is enabled.
(2) Data bus width selection
Bit 3 (<B0BUS>, <B1BUS>, <B2BUS>, <B3BUS> or <BEXBUS>) of a chip
select/wait control register specifies the width of the data bus. This bit should be set to
0 when memory is to be accessed using a 16-bit data bus, and to 1 when an 8-bit data
bus is to be used.
This process of changing the data bus width according to the address being accessed
is known as dynamic bus sizing. For details of this bus operation see Figure 3.7.2.
Table 3.7.2 Dynamic Bus Sizing
Operand Data Operand Start Memory Data
Bus Width
Address
Bus Width
8 bits
2n 0
(Even number)
2n 1
(Odd number)
16 bits
2n 0
(Even number)
2n 1
(Odd number)
2n 0
(Even number)
D15 to D8
D7 to D0
2n 0
xxxxx
16 bits
2n 0
xxxxx
b7 to b0
8 bits
2n 1
xxxxx
b7 to b0
16 bits
2n 1
b7 to b0
xxxxx
8 bits
2n 0
xxxxx
b7 to b0
b7 to b0
2n 1
xxxxx
b15 to b8
16 bits
2n 0
b15 to b8
b7 to b0
8 bits
2n 1
xxxxx
b7 to b0
2n 2
xxxxx
b15 to b8
2n 1
b7 to b0
xxxxx
2n 2
xxxxx
b15 to b8
2n 0
xxxxx
b7 to b0
2n 1
xxxxx
b15 to b8
8 bits
16 bits
2n 1
(Odd number)
CPU Data
8 bits
16 bits
32 bits
CPU Address
8 bits
16 bits
2n 2
xxxxx
b23 to b16
2n 3
xxxxx
b31 to b24
2n 0
b15 to b8
b7 to b0
2n 2
b31 to b24
b23 to b16
2n 1
xxxxx
b7 to b0
2n 2
xxxxx
b15 to b8
2n 3
xxxxx
b23 to b16
2n 4
xxxxx
b31 to b24
2n 1
b7 to b0
xxxxx
2n 2
b23 to b16
b15 to b8
2n 4
xxxxx
b31 to b24
Input data in bit positions marked xxxxx is ignored during a read. During a write,
the bus lines corresponding to these bit positions go high-impedance and the write
strobe signal for the bus remains inactive.
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TMP91C630
(3) Wait control
Bits 0 to 2 (<B0W0:2>, <B1W0:2>, <B2W0:2>, <B3W0:2> or <BEXW0:2>) of a chip
select/wait control register specify the number of waits that are to be inserted when
the corresponding memory area is accessed.
The following types of wait operation can be specified using these bits. Bit settings
other than those listed in the table should not be made.
Table 3.7.3 Wait Operation Settings
<BxW2:0>
No. of Waits
000
2 waits
Inserts a wait of two states, irrespective of the WAIT pin state.
001
1 wait
Inserts a wait of one state, irrespective of the WAIT pin state.
010
(1 N) waits
011
0 waits
1xx
Reserved
Wait Operation
Inserts one wait state, then continuously samples the state of the
WAIT pin. While the WAIT pin remains Low, the wait continues; the
bus cycle is prolonged until the pin goes High.
Ends the bus cycle without a wait, regardless of the WAIT pin state.
Do not set.
A Reset sets these bits to 000 (2 waits).
(4) Bus width and wait control for an area other than CS0 to CS3
The chip select/wait control register BEXCS controls the bus width and number of
waits when memory locations which are not in one of the four user-specified address
areas (CS0 to CS3) are accessed. The BEXCS register settings are always enabled for
areas other than CS0 to CS3.
(5) Selecting 16-Mbyte area/specified address area
Setting B2CS<B2M> (bit 6 of the chip select/wait control register for CS2) to 0
designates the 16-Mbyte area 002800H to 01F7FFH, 020000H to FFFFFFH as the CS2
area. Setting B2CS<B2M> to 1 designates the address area specified by the start
address register MSAR2 and the address mask register MAMR2 as CS2 (i.e. if
B2CS<B2M> 1, CS2 is specified in the same manner as CS0, CS1 and CS3 are).
A Reset clears this bit to 0, specifying CS2 as a 16-Mbyte address area.
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TMP91C630
(6) Procedure for setting chip select/wait control
When using the chip select/wait control function, set the registers in the following
order:
a.
Set the memory start address registers MSAR0 to MSAR3.
Set the start addresses for CS0 to CS3.
b.
Set the memory address mask registers MAMR0 to MAMR3.
Set the sizes of CS0 to CS3.
c.
Set the chip select/wait control registers B0CS to B3CS.
Set the chip select output waveform, data bus width, number of waits and
master enable/disable status for CS0 to CS3 .
The CS0 to CS3 pins can also function as pins P60 to P63. To output a chip
select signal using one of these pins, set the corresponding bit in the Port 6
function register P6FC to 1.
If a CS0 to CS3 address is specified which is actually an internal I/O, RAM or
ROM area address, the CPU accesses the internal address area and no chip select
signal is output on any of the CS0 to CS3 pins.
Setting example:
In this example CS0 is set to be the 64-Kbyte area 010000H to 01FFFFH. The bus
width is set to 16 bits and the number of waits is clear to 0.
MSAR0
01H ........... Start address: 010000H
MAMR0
07H .......... Address area: 64 Kbytes
B0CS
83H............... ROM/SRAM, 16-bit data bus, zero waits, CS0 area settings
enabled
91C630-75
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TMP91C630
3.7.3
Connecting External Memory
Figure 3.7.6 shows an example of how to connect external memory to the TMP91C630.
In this example the ROM is connected using a 16-bit bus. The RAM and I/O are
connected using an 8-bit bus.
TMP91C630
CS0
CS1
Address bus
CS2
A0
to
A23
CS
CS
Upper byte
ROM
OE
CS
Lower byte
ROM
OE
CS
8-bit
RAM
OE WE
8-bit
I/O
OE WE
D8
to
D15
D0
to
D7
RD
WR
Figure 3.7.6 Example of External Memory Connection
(ROM uses 16-bit bus; RAM and I/O use 8-bit bus.)
A reset clears all bits of the Port 4 control register P6CR and the Port 6 function register
P6FC to 0 and disables output of the CS signal. To output the CS signal, the appropriate bit
must be set to 1.
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TMP91C630
3.8
8-Bit Timers (TMRA)
The TMP91C630 features six built-in 8-bit timers.
These timers are paired into three modules: TMRA01, TMRA23 and TMRA45. Each module
consists of two channels and can operate in any of the following four operating modes.
x
8-bit interval timer mode
x
16-bit interval timer mode
x
8-bit programmable square wave pulse generation output mode (PPG variable duty cycle
with variable period)
x
8-bit pulse width modulation output mode (PWM variable duty cycle with constant
period)
Figure 3.8.1 to 3.8.3 show block diagrams for TMRA01, TMRA23 and TMRA45.
Each channel consists of an 8-bit up-counter, an 8-bit comparator and an 8-bit timer register.
In addition, a timer flip-flop and a prescaler are provided for each pair of channels.
The operation mode and timer flip-flops are controlled by five control SFRs (special-function
registers).
Each of the three modules (TMRA01, TMRA23 and TMRA45) can be operated independently.
All modules operate in the same manner; hence only the operation of TMRA01 is explained
here.
Table 3.8.1 Registers and Pins for Each Module
Module
External
pin
TMRA01
TMRA23
TMRA45
Input pin for external
clock
TA0IN
(shared with P70)
No
TA4IN
(shared with P73)
Output pin for timer
flip-flop
TA1OUT
(shared with P71)
TA3OUT
(shared with P72)
TA5OUT
(shared with P74)
TA01RUN (0100H)
TA23RUN (0108H)
TA45RUN (0110H)
TA0REG (0102H)
TA1REG (0103H)
TA2REG (010AH)
TA3REG (010BH)
TA4REG (0112H)
TA5REG (0113H)
TA01MOD (0104H)
TA23MOD (010CH)
TA45MOD (0114H)
TA1FFCR (0105H)
TA3FFCR (010DH)
TA5FFCR (0115H)
Timer run register
Timer register
SFR
(address) Timer mode register
Timer flip-flop control
register
91C630-77
2003-07-22
Prescaler
IT4
91C630-78
TA01RUN
<TA0RDE>
IT256
Internal bus
Register buffer 0
8-bit timer register
TA0REG
8-bit up-counter
(CP0)
TMRA0
match output:
TA0TRG
TA01MOD
<TA01M1:0>
TA0TRG
TMRA0
interrupt output:
INTTA0
Match
detect
8-bit up-counter
(UC1)
TA01RUN<TA1RUN>
Internal bus
8-bit timer register
TA1REG
TA1FFCR
Timer
flip-flop
TA1FF
Timer flip-flop
output: TA1OUT
TMRA1
interrupt output: INTTA1
Match
8-bit comparator detect
(CP1)
TA01MOD
<TA1CLK1:0>
IT1
IT16
IT256
Selector
Run/clear TA01RUN
<TA01PRUN>
2n1
Overflow
TA01MOD
<PWM01:00>
8-bit up-counter
(UC0)
TA01RUN<TA0RUN>
IT16
8 16 32 64 128 256 512
Selector
4
TA01MOD
<TA0CLK1:0>
External input
clock: TA0IN IT1
IT4
IT16
IT1
2
3.8.1
Prescaler
clock: IT0
TMP91C630
Block Diagrams
Figure 3.8.1 TMRA01 Block Diagram
2003-07-22
Prescaler
clock: IT0
IT4
91C630-79
TA23RUN
<TA2RDE>
Internal bus
Register buffer 2
8-bit timer register
TA2REG
8-bit up-counter
(UC3)
TA23RUN<TA3RUN>
TMRA2
match output:
TA2TRG
Internal bus
8-bit timer
register TA3REG
TA3FFCR
Timer
flip-flop
TA3FF
Timer flip-flop
output: TA3OUT
TMRA3
interrupt output: INTTA3
Match
8-bit comparator detect
register (CP3)
TA23MOD
<TA3CLK1:0>
IT1
IT16
IT256
TA23MOD
<TA23M1:0>
TA2TRG
TMRA2
interrupt output:
INTTA2
Match
8-bit comparator detect
(CP2)
TA23MOD
<PWM21:20>
2n 1
Overflow
8-bit up-counter
(UC2)
Selector
Run/clear TA23RUN
<TA23PRUN>
IT256
TA23RUN<TA2RUN>
IT16
8 16 32 64 128 256 512
TA23MOD
<TA2CLK1:0>
IT1
IT4
IT16
4
Selector
IT1
2
Prescaler
TMP91C630
Figure 3.8.2 TMRA23 Block Diagram
2003-07-22
External input
clock: TA4IN
Prescaler
clock: IT0
IT4
91C630-80
TA45RUN
<TA4RDE>
IT256
Internal bus
Register buffer 4
8-bit timer
register TA4REG
8-bit comparator
(CP4)
Selector
8-bit up-counter
(UC5)
TA45RUN<TA5RUN>
TMRA4
match output:
TA4TRG
Internal bus
8-bit timer register
TA5REG
TA5FFCR
Timer
flip-flop
TA5FF
Timer flip-flop
output: TA5OUT
TMRA5
interrupt output: INTTA5
Match
8-bit comparator detect
(CP5)
TA45MOD
<TA5CLK1:0>
IT1
IT16
IT256
TA45MOD
<TA45M1:0>
TA4TRG
TMRA4
interrupt output:
INTTA4
Match
detect
2n1
Overflow
TA45MOD
<PWM41:40>
8-bit up-counter
(UC4)
TA45RUN<TA4RUN>
IT16
Prescaler
Run/clear TA45RUN
8 16 32 64 128 256 512
<TA45PRUN>
TA45MOD
<TA4CLK1:0>
IT1
IT4
IT16
4
Selector
IT1
2
TMP91C630
Figure 3.8.3 TMRA45 Block Diagram
2003-07-22
TMP91C630
3.8.2
Operation of Each Circuit
(1) Prescalers
The 9-bit prescaler in TMRA01 generates the clock source of TMRA01.
The clock IT0 is divided by 4 and input to this prescaler. IT0 can be either fFPH or
fc/16 and is selected using the prescaler clock selection register SYSCR0<PRCK1:0>.
The prescaler’s operation can be controlled using TA01RUN<TA0PRUN> in the
timer control register. Setting <TA0PRUN> to 1 starts the count; setting <TA0PRUN>
to 0 clears the prescaler to zero and stops operation. Table 3.8.2 shows the various
prescaler output clock resolutions.
Table 3.8.2 Prescaler output clock resolution
at fc
Prescaler
Clock Selection
<PRCK1:0>
(fFPH)
Gear Value
<GEAR2:0>
IT1
IT4
3
5
IT16
IT256
7
11
000 (fc)
fc/2 (0.22 Ps) fc/2 (0.9 Ps)
fc/2 (3.6 Ps)
fc/2 (57 Ps)
001 (fc/2)
fc/24 (0.4 Ps)
fc/28 (7.1 Ps)
fc/212 (114 Ps)
010 (fc/4)
011 (fc/8)
10
(fc/16 clock)
36 MHz
Prescaler Output Clock Resolution
5
fc/2 (0.9 Ps)
6
fc/2 (1.8 Ps)
7
fc/26 (1.8 Ps)
7
fc/2 (3.6 Ps)
8
fc/2 (7.1 Ps)
9
9
fc/213 (228 Ps)
10
fc/214 (455 Ps)
11
fc/2 (14 Ps)
fc/2 (28 Ps)
100 (fc/16)
fc/2 (3.6 Ps)
fc/2 (14 Ps)
fc/2 (57 Ps)
fc/215 (910 Ps)
XXX
fc/27 (3.6 Ps)
fc/29 (14 Ps)
fc/211 (57 Ps)
fc/215 (910 Ps)
xxx: Don’t care
(2) Up-counters (UC0 and UC1)
These are 8-bit binary counters which count up the input clock pulses for the clock
specified by TA01MOD.
The input clock for UC0 is selectable and can be either the external clock input via
the TA0IN pin or one of the three internal clocks IT1, IT4 or IT16. The clock setting is
specified by the value set in TA01MOD<TA01CLK1:0>.
The input clock for UC1 depends on the operation mode. In 16-bit timer mode, the
overflow output from UC0 is used as the input clock. In any mode other than 16-bit
timer mode, the input clock is selectable and can either be one of the internal clocks
IT1, IT16 or IT256, or the comparator output (the match detection signal) from
TMRA0.
For each interval timer the timer operation control register bits
TA01RUN<TA0RUN> and TA01RUN<TA1RUN> can be used to stop and clear the
up-counters and to control their count. A reset clears both up-counters, stopping the
timers.
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TMP91C630
(3) Timer registers (TA0REG and TA1REG)
These are 8-bit registers which can be used to set a time interval. When the value set
in the timer register TA0REG or TA1REG matches the value in the corresponding
up-counter, the comparator match detect signal goes active. If the value set in the
timer register is 00H, the signal goes active when the up-counter overflows.
The TA0REG are double buffer structure, each of which makes a pair with register
buffer.
The setting of the bit TA01RUN<TA0RDE> determines whether TA0REG’s double
buffer structure is enabled or disabled. It is disabled if <TA0RDE> 0 and enabled if
<TA0RDE> 1.
When the double buffer is enabled, data is transferred from the register buffer to the
timer register when a 2n 1 overflow occurs in PWM mode, or at the start of the PPG
cycle in PPG mode. Hence the double buffer cannot be used in timer mode.
A reset initializes <TA0RDE> to 0, disabling the double buffer. To use the double
buffer, write data to the timer register, set <TA0RDE> to 1, and write the following
data to the register buffer. Figure 3.8.4 shows the configuration of TA0REG.
Up-counter
Comparator (CP0)
Selector
Timer registers 0 (TA0REG)
B
Y
Shift trigger
Matching detection in PPG cycle
2n 1 overflow of PWM
A
Write to TA0REG
Register buffers 0
S
Write
Internal data bus
TA01RUN<TA0RDE>
Figure 3.8.4 Configuration of TA0REG
Note: The same memory address is allocated to the timer register and the register buffer. When
<TA0RDE> 0, the same value is written to the register buffer and the timer register; when
<TA0RDE> 1, only the register buffer is written to.
The address of each timer register is as follows.
TA0REG: 000102H
TA1REG: 000103H
TA2REG: 00010AH
TA3REG: 00010BH
TA4REG: 000112H
TA5REG: 000113H
All these registers are write-only and cannot be read.
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2003-07-22
TMP91C630
(4) Comparator (CP0 and CP1)
The comparator compares the value in an up-counter with the value set in a timer
register. If they match, the up-counter is cleared to zero and an interrupt signal
(INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer
flip-flop is inverted at the same time.
(5) Timer flip-flop (TA1FF)
The timer flip-flop (TA1FF) is a flip-flop inverted by the match detect signal (8-bit
comparator output) of each interval timer.
Whether inversion is enabled or disabled is determined by the setting of the bit
TA1FFCR<TAFF1IE> in the timer flip-flop control register.
A reset clears the value of TA1FF to 0. Writing 01 or 10 to TA1FFCR<TAFF1C1:0>
sets TA1FF to 0 or 1. Writing 00 to these bits inverts the value of TA1FF (this is known
as software inversion).
The TA1FF signal is output via the TA1OUT pin (which can also be used as P71).
When this pin is used as the timer output, the timer flip-flop should be set beforehand
using the Port 7 function register P7FC.
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TMP91C630
3.8.3
SFRs
TMRA01 Run Register
7
TA01RUN Bit symbol
(0100H)
Read/Write
5
4
3
2
1
0
I2TA01
TA01PRUN
TA1RUN
TA0RUN
0
0
0
0
R/W
After reset
Function
6
TA0RDE
R/W
0
Timer Run/Stop control
0: Stop & clear
1: Run (Count up)
IDLE2
0: Stop
1: Operate
Double
buffer
0: Disable
1: Enable
TA0REG double buffer control
Timer run/stop control
0
Disable
0
Stop & clear
1
Enable
1
Run (Count up)
I2TA01: Operation in IDLE2 mode
TA01PRUN: Run prescaler
TA1RUN: Run TMRA1
TA0RUN: Run TMRA0
Note:
The values of bits 4 to 6 of TA01RUN are undefined when read.
TMRA23 Run Register
7
TA23RUN Bit symbol
(0108H)
Read/Write
5
4
3
2
1
0
I2TA23
TA23PRUN
TA3RUN
TA2RUN
0
0
0
0
R/W
After reset
Function
6
TA2RDE
R/W
0
Timer Run/Stop control
0: Stop & clear
1: Run (Count up)
IDLE2
0: Stop
1: Operate
Double
buffer
0: Disable
1: Enable
TA2REG double buffer control
Timer run/stop control
0
Disable
0
Stop & clear
1
Enable
1
Run (Count up)
I2TA23: Operation in IDLE2 mode
TA23PRUN: Run prescaler
TA3RUN: Run TMRA3
TA2RUN: Run TMRA2
Note:
The values of bits 4 to 6 of TA23RUN are undefined when read.
Figure 3.8.5 TMRA Registers
91C630-84
2003-07-22
TMP91C630
TMRA45 Run Register
7
TA45RUN Bit symbol
(0110H)
Read/Write
5
4
3
2
1
0
I2TA45
TA45PRUN
TA5RUN
TA4RUN
0
0
0
0
R/W
After reset
Function
6
TA4RDE
R/W
0
TA4REG double buffer control
0
Disable
1
Timer Run/Stop control
0: Stop & clear
1: Run (Count up)
IDLE2
0: Stop
1: Operate
Double
buffer
0: Disable
1: Enable
Timer run/stop control
0
Stop & clear
1
Enable
Run (Count up)
I2TA45: Operation during IDLE2 mode
TA45PRUN: Run for prescaler
TA5RUN: Run TMRA5
TA4RUN: Run TMRA4
Note:
The values of bits 4 to 6 of TA45RUN are undefined when read.
Figure 3.8.6 TMRA Registers
91C630-85
2003-07-22
TMP91C630
TMRA01 Mode Register
TA01MOD Bit symbol
(0104H)
Read/Write
After reset
Function
7
6
5
4
3
2
1
0
TA01M1
TA01M0
PWM01
PWM00
TA1CLK1
TA1CLK0
TA0CLK1
TA0CLK0
0
0
0
0
0
0
0
0
R/W
Operation mode
00: 8-bit timer mode
01: 16-bit timer mode
10: 8-bit PPG mode
11: 8-bit PWM mode
PWM cycle
00: Reserved
01: 26 1
10: 27 1
11: 28 1
Source clock for TMRA1
00: TA0TRG
01: IT1
10: IT16
11: IT256
Source clock for TMRA0
00: TA0IN pin
01: IT1
10: IT4
11: IT16
TMRA0 source clock selection
00
TA0IN (external input)
01
IT1 (prescaler)
10
IT4 (prescaler)
11
IT16 (prescaler)
TMRA1 source clock selection
00
TA01MOD
<TA01M1:0> z 01
Comparator output from
TMRA0
01
IT1
10
IT16
11
IT256
TA01MOD
<TA01M1:0> 01
Overflow output from
TMRA0
(16-bit timer mode)
PWM cycle selection
00
Reserved
01
(26 1) u clock source
10
(27 1) u clock source
11
(28 1) u clock source
TMRA01 operation mode selection
00
Two 8-bit timers
01
16-bit timer
10
8-bit PPG
11
8-bit PWM (TMRA0), 8-bit timer (TMRA1)
Figure 3.8.7 TMRA Registers
91C630-86
2003-07-22
TMP91C630
TMRA23 Mode Register
TA23MOD Bit symbol
(010CH)
Read/Write
After reset
Function
7
6
5
4
3
2
1
0
TA23M1
TA23M0
PWM21
PWM20
TA3CLK1
TA3CLK0
TA2CLK1
TA2CLK0
0
0
0
0
0
0
0
0
R/W
Operation mode
00: 8-bit timer mode
01: 16-bit timer mode
10: 8-bit PPG mode
11: 8-bit PWM mode
PWM cycle
00: Reserved
01: 26 1
10: 27 1
11: 28 1
TMRA3 clock for TMRA3
00: TA2TRG
01: IT1
10: IT16
11: IT256
TMRA2 clock for TMRA2
00: Reserved
01: IT1
10: IT4
11: IT16
TMRA2 source clock selection
00
Reserved
01
IT1 (prescaler)
10
IT4 (prescaler)
11
IT16 (prescaler)
TMRA3 source clock selection
00
TA23MOD
<TA23M1:0> z 01
Comparator output from
TMRA2
01
IT1
10
IT16
11
IT256
TA23MOD
<TA23M1:0> 01
Overflow output from
TMRA2
(16-bit timer mode)
PWM cycle selection
00
Reserved
01
(26 1) u clock source
10
(27 1) u clock source
11
(28 1) u clock source
TMRA23 operation mode selection
00
Two 8-bit timers
01
16-bit timer
10
8-bit PPG
11
8-bit PWM (TMRA0), 8-bit timer (TMRA3)
Figure 3.8.8 TMRA Registers
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TMRA45 Mode Register
TA45MOD Bit symbol
(0114H)
Read/Write
After reset
Function
7
6
5
4
3
2
1
0
TA45M1
TA45M0
PWM41
PWM40
TA5CLK1
TA5CLK0
TA4CLK1
TA4CLK0
0
0
0
0
R/W
Operation mode
00: 8-bit timer mode
01: 16-bit timer mode
10: 8-bit PPG mode
11: 8-bit PWM mode
PWM cycle
00: reserved
01: 26 1
10: 27 1
11: 28 1
0
0
Source clock for TMRA5
00: TA4TRG
01: IT1
10: IT16
11: IT256
0
0
Source clock for TMRA4
00: TA4IN pin
01: IT1
10: IT4
11: IT16
Source clock for TMRA4
00
TA4IN (external input)
01
IT1 (prescaler)
10
IT4 (prescaler)
11
IT16 (prescaler)
Soruce clock for TMRA5
00
TA45MOD
<TA45M1:0> z 01
Comparator output from
TMRA4
01
IT1
10
IT16
11
IT256
TA45MOD
<TA45M1:0> 01
Overflow output from
TMRA4
(16-bit timer mode)
PWM cycle
00
Reserved
01
(26 1) u clock source
10
(27 1) u clock source
11
(28 1) u clock source
Operation mode for TMRA45
00
Two 8-bit timers
01
16-bit timer
10
8-bit PPG
11
8-bit PWM (TMRA4), 8-bit timer (TMRA5)
Figure 3.8.9 TMRA Registers
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TMRA1 Flip-flop Control Register
7
TA1FFCR
(0105H)
6
5
4
Bit symbol
3
2
1
0
TAFF1C1
TAFF1C0
TAFF1IE
TAFF1IS
Read/Write
R/W
After reset
1
Read-modify Function
-write
instruction is
prohibited.
R/W
1
00: Invert TA1FF
01: Set TA1FF
10: Clear TA1FF
11: Don’t care
0
TA1FF
control for
inversion
0: Disable
1: Enable
0
TA1FF
inversion
select
0: TMRA0
1: TMRA1
Inverse signal for timer flip-flop 1 (TA1FF)
(Don’t care except in 8-bit timer mode)
0
Inversion by TMRA0
1
Inversion by TMRA1
Inversion of TA1FF
0
Disabled
1
Enabled
Control of TA1FF
00
Inverts the value of TA1FF
01
Sets TA1FF to 1
10
Clears TA1FF to 0
11
Don’t care
Figure 3.8.10 TMRA Registers
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TMRA3 Flip-flop Control Register
7
TA3FFCR
(010DH)
6
5
4
Bit symbol
3
2
1
0
TAFF3C1
TAFF3C0
TAFF3IE
TAFF3IS
Read/Write
R/W
After reset
R/W
1
Read-modify Function
-write
instruction is
prohibited.
1
00: Invert TA3FF
01: Set TA3FF
10: Clear TA3FF
11: Don’t care
0
TA3FF
control for
inversion
0: Disable
1: Enable
0
TA3FF
inversion
select
0: TMRA2
1: TMRA3
Inverse signal for timer flip-flop 3 (TA3FF)
(Don’t care except in 8-bit timer mode)
0
Inversion by TMRA2
1
Inversion by TMRA3
Inversion of TA3FF
0
Disabled
1
Enabled
Control of TA3FF
00
Inverts the value of TA3FF
01
Sets TA3FF to 1
10
Clears TA3FF to 0
11
Don’t care
Figure 3.8.11 TMRA Register
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TMRA5 Flip-flop Control Register
7
TA5FFCR
(0115H)
6
5
4
Bit symbol
3
2
1
0
TAFF5C1
TAFF5C0
TAFF5IE
TAFF5IS
Read/Write
R/W
After reset
R/W
1
Read-modify Function
-write
instruction is
prohibited.
1
00: Invert TA5FF
01: Set TA5FF
10: Clear TA5FF
11: Don’t care
0
0
TA5FF
control for
inversion
TA5FF
inversion
select
0: Disable
1: Enable
0: TMRA4
1: TMRA5
Inverse signal for timer flip-flop 5 (TA5FF)
(Don’t care except in 8-bit timer mode)
0
Inversion by TMRA4
1
Inversion by TMRA5
Inversion of TA5FF
0
Disabled
1
Enabled
Control of TA5FF
00
Inverts the value of TA5FF
01
Sets TA5FF to 1
10
Clears TA5FF to 0
11
Don’t care
Figure 3.8.12 TMRA Registers
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3.8.4
Operation in Each Mode
(1) 8-bit timer mode
Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers.
a.
Generating interrupts at a fixed interval (using TMRA1)
To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop
TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and
TA1REG register, respectively. Then, enable the interrupt INTTA1 and start
TMRA1 counting.
Example: To generate an INTTA1 interrupt every 8.8 Ps at fc
as follows:
36 MHz, set each register
* Clock state
System clock: High frequency (fc)
Clock gear: 1 (fc)
Prescaler clock: fFPH
MSB
TA01RUN
TA01MOD
m
m
7
–
0
TA1REG
INTETA01
TA01RUN
m
m
m
0
X
–
6
X
0
5
X
X
4
X
X
3
0
2
1
1
0
X
LSB
0
X
0
1
X
1
0
X
0
1
X
1
0
1
0
1
0
Stop TMRA1 and clear it to 0.
Select 8-bit timer mode and select IT1
(0.22 Ps at fc 36 MHz) as the input clock.
Set TA1REG to 8.8 Ps y IT1 40 28H
Enable INTTA1 and set it to Level 5.
Start TMRA1 counting.
X: Don’t care, : No change
Select the input clock using Table 3.8.4
Note : The input clocks for TMRA0 and TMRA1 differ as follows:
TMRA0: Uses TA0IN input and can be selected from IT1, IT4 or IT16
TMRA1: Match output of TMRA0 and can be selected from IT1, IT16, IT256
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b.
Generating a 50% duty ratio square wave pulse
The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its
status output via the timer output pin (TA1OUT).
Example: To output a 1.32 Ps square wave pulse from the TA1OUT pin at fc 36 MHz, use the
following procedure to make the appropriate register settings. This example uses
TMRA1; however, either TMRA0 or TMRA1 may be used.
* Clock state
System clock: High frequency (fc)
Clock gear: 1 (fc)
Prescaler clock: fFPH
TA01RUN
TA01MOD
m
m
7
0
6
X
0
5
X
X
4
X
X
3
0
2
1
1
0
X
0
X
TA1REG
TA1FFCR
m
m
0
X
0
X
0
X
0
X
0
1
0
0
1
1
1
1
P7CR
P7FC
TA01RUN
m
m
m
X
X
X
X
X
X
X
1
1
1
1
Stop TMRA1 and clear it to 0.
Select 8-bit timer mode and select IT1 (0.22 Ps at fc 36
MHz) as the input clock.
Set the timer register to 1.32 Ps y IT1 y 2 3
Clear TA1FF to 0 and set it to invert on the match detect
signal from TMRA1.
Set P71 to function as the TA1OUT pin.
Start TMRA1 counting.
X: Don’t care, : No change
IT1
TA01RUN
<TA1RUN>
Bit 7 to 2
Up-counter
Bit 1
Bit 0
0
1
2
3
1
0
2
3
0
1
2
3
0
Comparator
timing
Comparator output
(match detect)
INTTA1
UC1 clear
TA1FF
TA1OUT
0.67Ps at fc
36 MHz
Figure 3.8.13 Square Wave Output Timing Chart (50% duty)
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c.
Making TMRA1 count up on the match signal from the TMRA0 comparator
Select 8-bit timer mode and set the comparator output from TMRA0 to be the input
clock to TMRA1.
Comparaot output
(TMRA0 match)
TMRA0 up-counter
(when TA0REG 5)
TMRA1 up-counter
(when TA1REG 2)
1
2
3
4
5
1
2
1
3
2
4
5
1
2
3
1
TMRA1 match output
Figure 3.8.14 TMRA1 Count Up on Signal from TMRA0
(2) 16-bit timer mode
A 16-bit interval timer is configured by pairing the two 8-bit timers TMRA0 and
TMRA1.
To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together,
set TA01MOD <TA01M1:0> to 01.
In 16-bit timer mode, the overflow output from TMRA0 is used as the input clock for
TMRA1, regardless of the value set in TA01MOD<TA1CLK1:0>. Table 3.8.4 shows the
relationship between the timer (interrupt) cycle and the input clock selection.
Setting example: To generate an INTTA1 interrupt every 0.225 seconds at fc
timer registers TA0REG and TA1REG as follows:
36 MHz, set the
* Clock state
System clock: High frequency (fc)
Clock gear: 1 (fc)
Prescaler clock: fFPH
If IT16 (3.6 Ps at 36 MHz) is used as the input clock for counting, set the following value in
the registers: 0.225 s y 3.6 Ps 62500 F424H; i.e. set TA1REG to F4H and TA0REG to 24H.
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The comparator match signal is output from TMRA0 each time the up-counter UC0
matches TA0REG, where the up-counter UC0 is not be cleared.
In the case of the TMRA1 comparator, the match detect signal is output on each
comparator pulse on which the values in the up-counter UC1 and TA1REG match.
When the match detect signal is output simultaneously from both the comparators
TMRA0 and TMRA1, the up-counters UC0 and UC1 are cleared to 0 and the interrupt
INTTA1 is generated. Also, if inversion is enabled, the value of the timer flip-flop
TA1FF is inverted.
Example: When TA1REG
Value of up-counter
(UC1, UC0)
TMRA0 comparator
match detect signal
0000H
04H and TA0REG
0080H
0180H
80H
0280H
0380H
0480H
Interrupt INTTA1
Timer output TA1OUT
Inversion
Figure 3.8.15 Timer Output by 16-Bit Timer Mode
(3) 8-bit PPG (Programmable Pulse Generation) output mode
Square wave pulses can be generated at any frequency and duty ratio by TMRA0.
The output pulses may be active-Low or active-High. In this mode TMRA1 cannot be
used.
TMRA0 outputs pulses on the TA1OUT pin (which can also be used as P71).
tH
tL
t
TA0REG and UC0 match
(Interrupt INTTA0)
TA1REG and UC0 match
(Interruput INTTA1)
TA1OUT
TA0REG
TA1REG
Figure 3.8.16 8-Bit PPG Output Waveforms
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In this mode a programmable square wave is generated by inverting the timer
output each time the 8-bit up-counter (UC0) matches the value in one of the timer
registers TA0REG or TA1REG.
The value set in TA0REG must be smaller than the value set in TA1REG.
Although the up-counter for TMRA1 (UC1) is not used in this mode, TA01RUN
<TA1RUN> should be set to 1 so that UC1 is set for counting.
Figure 3.8.17 shows a block diagram representing this mode.
TA1OUT
TA01RUN<TA0RUN>
Selector
IT1
IT4
IT16
8-bit up-counter
(UC 0)
TA1FF
TA1FFCR<TAFF1IE>
Inversion
TA01MOD<TA0CLK1:0>
INTTA0
Comparator
Selector
Comparator
INTTA1
TA0REG
Shift trigger
TA0REG-WR
TA1REG
Register buffer
TA01RUN<TA0RDE>
Internal data bus
Figure 3.8.17 Block Diagram of 8-Bit PPG Output Mode
If the TA0REG double buffer is enabled in this mode, the value of the register buffer
will be shifted into TA0REG each time TA1REG matches UC0.
Use of the double buffer facilitates the handling of low-duty waves (when duty is
varied).
Match with TA0REG
and up-counter
(Up-counter
Q1)
(Up-countner
Q2)
Match with TA1REG
TA0REG
(Value to be compared)
Register buffer
Shift from register buffer
Q2
Q1
Q2
Q3
TA0REG (register buffer)
write
Figure 3.8.18 Operation of Register Buffer
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Example: To generate 1/4-duty 113.636kHz pulses (at fc
36 MHz):
8.8 Ps
* Clock state
System clock: High frequency (fc)
Clock gear: 1 (fc)
Prescaler clock: fFPH
Calculate the value which should be set in the timer register.
To obtain a frequency of 113.636 kHz, the pulse cycle t should be:
t 1/113.636 kHz 8.8 Ps
IT1 0.22 Ps (at 36 MHz);
8.8 Ps y 0.22 Ps 40
Therefore set TA1REG 40 28H.
The duty is to be set to 1/4: t u 1/4 8.8 Ps u 1/4
2.2 Ps y 0.22 Ps 10
Therefore, set TA0REG 10 0AH.
TA01RUN
TA01MOD
TA0REG
TA1REG
TA1FFCR
m
m
m
m
m
7
0
1
0
0
X
6
X
0
0
0
X
5
X
X
0
1
X
4
X
X
0
0
X
3
X
1
1
0
2
0
X
0
0
1
1
0
0
1
0
1
0
0
1
0
0
X
P7CR
P7FC
TA01RUN
m
m
m
X
X
1
X
X
X
X
X
1
1
1
1
1
2.2 Ps
Stop TMRA0 and TMRA01 and clear it to 0.
Set the 8-bit PPG mode, and select IT1 as input clock.
Write 0AH
Write 28H
Set TA1FF, enabling both inversion.
10 generates a negative logic pulse.
Set P71 as the TA1OUT pin.
Start TMRA0 and TMRA1 counting.
X: Don’t care, : No change
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(4) 8-bit PWM output mode
This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum
resolution of 8 bits can be output.
When TMRA0 is used the PWM pulse is output on the TA1OUT pin (which is also
used as P71). TMRA1 can also be used as an 8-bit timer.
The timer output is inverted when the up-counter (UC0) matches the value set in the
timer register TA0REG or when 2n 1 counter overflow occurs (n 6, 7 or 8 as specified
by TA01MOD<PWM01:00>). The up-counter UC0 is cleared when 2n 1 counter
overflow occurs.
The following conditions must be satisfied before this PWM mode can be used.
Value set in TA0REG < value set for 2n 1 counter overflow
Value set in TA0REG z 0
TA0REG and
UC0 match
2n 1
overflow
(INTTA0 interrupt)
TA1OUT
tPWM
(PWM cycle)
Figure 3.8.19 8-Bit PWM Waveforms
Figure 3.8.20 shows a block diagram representing this mode.
TA01RUN<TA0RUN>
IT1
IT4
IT16
8-bit up counter
(UC 0)
Selector
Clear
TAFF1
2n 1
overflow
control
TA01MOD<TA0CLK1:0>
TA1OUT
TA1FFCR
<TAFF1IE>
Invert
TA01MOD
<PWM01:00>
Overflow
Comparator
INTTA0
TA0REG
Selector
TA0REG-WR
Shift trigger
Register buffer
TA01RUN<TA0RDE>
Internal data bus
Figure 3.8.20 Block Diagram of 8-Bit PWM Mode
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In this mode the value of the register buffer will be shifted into TA0REG if 2n 1
overflow is detected when the TA0REG double buffer is enabled.
Use of the double buffer facilitates the handling of low duty ratio waves.
Match with TA0REG
Up-counter
Q1
Up-counter
Q2
2n 1 overflow
TA0REG
(value to be compared)
Q1
Register buffer
Q2
Shift into TA0REG
Q2
Q3
TA0REG (register buffer)
write
Figure 3.8.21 Register Buffer Operation
Example: To output the following PWM waves on the TA1OUT pin at fc
36 MHz:
15.84 Ps
27.94 Ps
* Clock state
System clock: High frequency (fc)
Clock gear: 1 (fc)
Prescaler clock: fFPH
To achieve a 27.94 Ps PWM cycle by setting IT1 to 0.22 Ps (at fc
27.94 Ps y 0.22 Ps 127
2n 1 127
Therefore n should be set to 7.
Since the low-level period is 15.84 Ps when IT1 0.22 Ps,
set the following value for TA0REG:
15.84 Ps y 0.22 Ps 72 48H
MSB
6
X
1
5
X
1
4
X
0
3
X
2
X
1
0
LSB
0
0
1
TA01RUN
TA01MOD
m
m
7
1
TA0REG
TA1FFCR
m
m
0
X
1
X
0
X
0
X
1
1
0
0
0
1
0
X
P7CR
P7FC
TA01RUN
m
m
m
X
X
1
X
X
X
X
X
1
1
1
1
1
36 MHz):
Stop TMRA0 and clear it to 0.
Select 8-bit PWM mode (cycle: 27 1) and select IT1 as
the input clock.
Write 48H.
Clear TA1FF to 0, enable the inversion.
Set P71 and the TA1OUT pin.
Start TMRA0 counting.
X: Don’t care, : No change
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Table 3.8.3 PWM Cycle
at fc
Select Prescaler
Clock
<PRCK1:0>
00
(fFPH)
10
(fc/16 clcok)
36 MHz
PWM Cycle
Gear Value
<GEAR2:0>
6
7
2 1
8
2 1
2 1
IT1
IT4
IT16
IT1
IT4
IT16
IT1
IT4
IT16
000 (fc)
12.6 Ps
56.7 Ps
66.6 Ps
25.4 Ps
114 Ps
457 Ps
51 Ps
001 (fc/2)
25.2 Ps
113 Ps
447 Ps
50.8 Ps
229 Ps
901 Ps
102 Ps
459 Ps 1811 Ps
010 (fc/4)
56.7 Ps
227 Ps
895 Ps
114 Ps
457 Ps 1803 Ps
230 Ps
918 Ps 3621 Ps
011 (fc/8)
113 Ps
447 Ps 1789 Ps
229 Ps
902 Ps 3607 Ps
459 Ps 1811 Ps 7242 Ps
100 (fc/16)
227 Ps
895 Ps 3585 Ps
457 Ps 1803 Ps 7226 Ps
918 Ps 3621 Ps 14510 Ps
XXX
227 Ps
895 Ps 3585 Ps
457 Ps 1803 Ps 7226 Ps
918 Ps 3621 Ps 14510 Ps
230 Ps
918 Ps
XXX: Don’t care
(5) Settings for each mode
Table 3.8.4 shows the SFR settings for each mode.
Table 3.8.4 Timer Mode Setting Registers
Register Name
TA01MOD
TA1FFCR
<Bit Symbol>
<TA01M1:0>
<PWM01:00>
<TA1CLK1:0> <TA0CLK1:0>
TAFF1IS
Function
Timer Mode
PWM Cycle
Upper Timer
Input Clock
Lower Timer
Input Clock
Timer F/F Invert
Signal Select
8-bit timer u 2 channels
00
Lower timer match,
IT1, IT16, IT256
(00, 01, 10, 11)
External clock,
IT1, IT4, IT16
(00, 01, 10, 11)
0: Lower timer output
1: Upper timer output
16-bit timer mode
01
External clock,
IT1, IT4, IT16
(00, 01, 10, 11)
8-bit PPG u 1 channel
10
External clock,
IT1, IT4, IT16
(00, 01, 10, 11)
8-bit PWM u 1 channel
11
26 1, 27 1, 28 1
(01, 10, 11)
External clock,
IT1, IT4, IT16
(00, 01, 10, 11)
8-bit timer u 1 channel
11
IT1, IT16 , IT256
(01, 10, 11)
Output disabled
: Don’t care
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3.9
16-Bit Timer/Event Counters (TMRB)
The TMP91C630 incorporates multifunctional 16-bit timer/event counter (TMRB0) which
has the following operation modes:
x
16-bit interval timer mode
x
16-bit event counter mode
x
16-bit programmable pulse generation (PPG) mode
The timer/event counter channel consists of a 16-bit up-counter, two 16-bit timer registers
(one of them with a double-buffer structure), two 16-bit capture registers, two comparators, a
capture input controller, a timer flip-flop and a control circuit.
The timer/event counter is controlled by an 11-byte control SFR.
This chapter consists of the following items:
Table 3.9.1 Differences Between TMRB0
Channel
TMRB0
Spec
External
pins
External clock/Capture trigger
input pins
TB0IN0 (also used as P93)
Timer flip-flop output pins
TB0OUT0 (also used as P95)
Timer run register
TB0RUN (0180H)
Timer mode register
TB0MOD (0182H)
TB0IN1 (also used as P94)
TB0OUT1 (also used as P96)
Timer flip-flop control register
TB0FFCR (0183H)
TB0RG0L (0188H)
SFR
(address)
TB0RG0H (0189H)
Timer register
TB0RG1L (018AH)
TB0RG1H (018BH)
TB0CP0L (018CH)
Capture register
TB0CP0H (018DH)
TB0CP1L (018EH)
TB0CP1H (018FH)
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(from TMRA01)
TB0IN0
TB0IN1
Prescaler clock: IT0
IT4
8
91C630-102
TB0RUN
<TB0RDE>
Count
clock
Internal data bus
Register buffer 0
16-bit timer register
TB0RG0H/L
16-bit comparator
(CP0)
TB0MOD<TB0CLK1:0>
IT16
Selector
TB0MOD
<TB0CP0I>
Match
detection
INT output
Internal data bus
16-bit time register
TB0RG1H/L
TB0FF1
TB0FF0
Match detection
Timer
flip-flop
control
Timer
flip-flop
Register 0 Register 1
INTTB00 INTTB01
16-bit comparator
(CP1)
TB0RUN<TB0RUN>
TB0MOD<TB0CLE>
Capture register 1
TB0CP1H/L
16-bit up-counter
(UC0)
Capture register 0
TB0CP0H/L
Run/
clear TB0RUN
<TB0PRUN>
IT16
16 32
Capture,
external INT
input control
4
TB0MOD IT1
<TB0CPM1:0> IT4
IT1
2
Internal data bus
Over flow INT
INTTBOF0
TB0OUT1
TB0OUT0
Timer flip-flop
output
3.9.1
Internal data bus
TMP91C630
Block Diagrams
Figure 3.9.1 Block Diagram of TMRB0
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TMP91C630
3.9.2
Operation of Each Block
(1) Prescaler
The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock (IT0)
is divided clock (divided by 4) from selected clock by the register SYSCR0<PRCK1:0> of
clock-gear.
This prescaler can be started or stopped using TB0RUN<TB0RUN>. Counting starts
when <TB0RUN> is set to 1; the prescaler is cleared to zero and stops operation when
<TB0RUN> is clear to 0.
Table 3.9.2 Prescaler Clock Resolution
at fc
Prescaler Clock Resolution
Prescaler Clock Selection Clock Gear Value
<PRCK1:0>
<GEAR2:0>
00
(fFPH)
10
(fc/16 clock)
36 MHz
IT1
IT4
IT16
000 (fc)
fc/23 (0.2 Ps)
fc/25 (0.9 Ps)
fc/27 (3.6 Ps)
001 (fc/2)
fc/24 (0.4 Ps)
fc/26 (1.8 Ps)
fc/28 (7.1 Ps)
010 (fc/4)
011 (fc/8)
5
fc/2 (0.9 Ps)
6
fc/2 (1.8 Ps)
7
7
fc/29 (14 Ps)
8
fc/210 (28 Ps)
9
fc/2 (3.6 Ps)
fc/2 (7.1 Ps)
100 (fc/16)
fc/2 (3.6 Ps)
fc/2 (14 Ps)
fc/211 (57 Ps)
XXX
fc/27 (3.6 Ps)
fc/29 (14 Ps)
fc/211 (57 Ps)
xxx: Don’t care
(2) Up-counter (UC0)
UC0 is a 16-bit binary counter which counts up pulses input from the clock specified
by TB0MOD<TB0CLK1:0>.
Any one of the prescaler internal clocks IT1, IT4 and IT16 or an external clock input
via the TB0IN0 pin can be selected as the input clock. Counting or stopping & clearing
of the counter is controlled by TB0RUN<TB0RUN>.
When clearing is enabled, the up-counter UC0 will be cleared to zero each time its
value matches the value in the timer register TB0RG1H/L. Clearing can be enabled or
disabled using TB0MOD<TB0CLE>.
If clearing is disabled, the counter operates as a free-running counter.
A timer overflow interrupt (INTTBOF0) is generated when UC0 overflow occurs.
91C630-103
2003-07-22
TMP91C630
(3) Timer registers (TB0RG0H/L and TB0RG1H/L)
These two 16-bit registers are used to set the interval time. When the value in the
up-counter UC0 matches the value set in this timer register, the comparator match
detect signal will go active.
Setting data for timer register is executed using 2 byte data transfer instruction or
using 1 byte date transfer instruction twice for lower 8 bits and upper 8 bits in order.
The TB0RG0 timer register has a double-buffer structure, which is paired with
register buffer. The value set in TB0RUN<TB0RDE> determines whether the
double-buffer structure is enabled or disabled: it is disabled when <TB0RDE> 0, and
enabled when <TB0RDE> 1.
When the double buffer is enabled, data is transferred from the register buffer to the
timer register when the values in the up-counter (UC0) and the timer register TB0RG1
match.
After a reset, TB0RG0 and TB0RG1 are undefined. If the 16-bit timer is to be used
after a reset, data should be written to it beforehand.
On a reset TB0RUN<TB0RDE> is initialized to 0, disabling the double buffer. To use
the double buffer, write data to the timer register, set <TB0RDE> to 1, then write data
to the register buffer as shown below.
TB0RG0 and the register buffer both have the same memory addresses (000188H
and 000189H) allocated to them. If <TB0RDE> 0, the value is written to both the
timer register and the register buffer. If <TB0RDE> 1, the value is written to the
register buffer only.
The addresses of the timer registers are as follows:
TMRB0
TB0RG0
TB0RG1
Upper 8 bits
Lower 8 bits
Upper 8 bits
Lower 8 bits
000189H
000188H
00018BH
00018AH
The timer registers are write-only registers and thus cannot be read.
(4) Capture registers (TB0CP0H/L and TB0CP1H/L)
These 16-bit registers are used to latch the values in the up-counter UC0.
Data in the capture registers should be read using a 2-byte data load instruction or
two 1-byte data load instructions. The least significant byte is read first, followed by
the most significant byte.
The addresses of the capture registers are as follows:
TMRB0
TB0CP0
TB0CP1
Upper 8 bits
Lower 8 bits
Upper 8 bits
Lower 8 bits
00018DH
00018CH
00018FH
00018EH
The capture registers are read-only registers and thus cannot be written to.
91C630-104
2003-07-22
TMP91C630
(5) Capture input control
This circuit controls the timing to latch the value of up-counter UC0 into TB0CP0
and TB0CP1. The latch timing for the capture register is determined by TB0MOD
<TB0CPM1:0>.
In addition, the value in the up-counter can be loaded into a capture register by
software. Whenever 0 is written to TB0MOD<TB0CP0I>, the current value in the
up-counter is loaded into capture register TB0CP0. It is necessary to keep the prescaler
in run mode (i.e. TB0RUN<TB0PRUN> must be held at a value of 1).
(6) Comparators (CP0 and CP1)
CP0 and CP1 are 16-bit comparators which compare the value in the up-counter
UC0 with the value set in TB0RG0 or TB0RG1 respectively, in order to detect a match.
If a match is detected, the comparator generates an interrupt (INTTB00 or INTTB01
respectively).
(7) Timer flip-flops (TB0FF0 and TB0FF1)
These flip-flops are inverted by the match detect signals from the comparators and
the latch signals to the capture registers. Inversion can be enabled and disabled for
each element using TB0FFCR<TB0C1T1, TB0C0T1, TB0E1T1 and TB0E0T1>. After a
reset the value of TB0FF0 is undefined. If 00 is written to TB0FFCR<TB0FF0C1:0> or
<TB0FF1C1:0>, TB0FF0 will be inverted. If 01 is written to the capture registers, the
value of TB0FF0 will be set to 1. If 10 is written to the capture registers, the value of
TB0FF0 will be cleared to 0. The values of TB0FF0 and TB0FF1 can be output via the
timer output pins TB0OUT0 (which is shared with P95) and TB0OUT1 (which is
shared with P96). Timer output should be specified using the Port 9 function register.
91C630-105
2003-07-22
TMP91C630
3.9.3
SFRs
TMRB0 Run Register
TB0RUN Bit symbol
(0180H)
Read/Write
After reset
Function
7
6
3
2
TB0RDE
I2TB0
TB0PRUN
TB0RUN
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Double
buffer
0: Disable
1: Enable
5
4
Write 0
IDLE2
0: Stop
1: Operate
1
0
Timer Run/Stop control
0: Stop & clear
1: Run (Count up)
Count operation
0
Stop and clear
1
Count
I2TB0: Operation during IDLE2 mode
TB0PRUN: Operation of prescaler
TB0RUN: Operation of TMRB0
Note:
The 1, 4 and 5 of TB0RUN are read as undefined value.
Figure 3.9.2 The Registers for TMRB0
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TMP91C630
TMRB0 Run Register
TB0MOD Bit symbol
(0182H)
Read/Write
After reset
Function
7
6
5
4
3
2
1
0
TB0CT1
TB0ET1
TB0CP0I
TB0CPM1
TB0CPM0
TB0CLE
TB0CLK1
TB0CLK0
0
0
0
0
R/W
0
W*
0
1
R/W
Execute
software
capture
Capture timing
00: Disable
01: TB0IN0 n TB0IN1 n
0: Execute 10: TB0IN0 n TB0IN0 p
Invert when Invert when
1: Don’t care 11: TA1OUT n TA1OUT p
the UC
the UC
value
value is
captured to matches the
value in
TB0CP1.
TB0RG1.
TB0FF1 inversion
0: Disable trigger
1: Enable trigger
0
Control
up-counter
0: Disable
clearing
1: Enable
clearing
TMRB0 source clock
00: TB0IN0 pin
01: IT1
10: IT4
11: IT16
TMRB0 source clock
00
TB0IN0 pin
01
IT1
10
IT4
11
IT16
Up-counter clear control
0
Disable
1
TB0RG1 clearing on match with TB0RG1.
Capture timing
Capture control
00
Disable
01
TB0CP0 at TB0IN0 rising
TB0CP1 at TB0IN1 rising
10
TB0CP0 at TB0IN0 rising
TB0CP1 at TB0IN0 falling
11
TB0CP0 at TA1OUT rising
TB0CP1 at TA1OUT falling
Software capture
0
The value in the up-counter is captured to TB0CP0.
1
Don’t care
Figure 3.9.3 TMRB0 Registers
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TMP91C630
TMRB0 Flip-flop Control Register
TB0FFCR Bit symbol
(0183H)
Read/Write
After reset
Function
7
6
5
4
3
2
1
0
TB0FF1C1
TB0FF1C0
TB0C1T1
TB0C0T1
TB0E1T1
TB0E0T1
TB0FF0C1
TB0FF0C0
0
0
0
1
W*
1
R/W
1
Control TB0FF1
00: Invert
01: Set
10: Clear
11: Don’t care
* Always read as 11
W*
0
1
TB0FF0 inversion trigger
0: Disable trigger
1: Enable trigger
Control TB0FF0
00: Invert
01: Set
10: Clear
Invert when
Invert when
Invert when
Invert when
the UC value the UC value the UC value the UC value 11: Don’t care
is loaded into is loaded into matches the matches the * Always read as 11
TB0CP1.
TB0CP0.
value in
TB0RG1.
value in
TB0RG0.
TB0FF0 control
00
Invert
01
Set to 1
10
Clear to 0
11
Don’t care
Inverted when the UC value matches the value in TB0RG0.
0
Disable trigger
1
Enable trigger
Inverted when the UC value matches the value in TB0RG1.
0
Disable trigger
1
Enable trigger
Inverted when the UC value is loaded into TB0CP0.
0
Disable trigger
1
Enable trigger
Inverted when the UC value is loaded into TB0CP1.
0
Disable trigger
1
Enable trigger
Figure 3.9.4 TMRB0 Registers
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2003-07-22
TMP91C630
3.9.4
Operation in Each Mode
(1) 16-bit interval timer mode
Generating interrupts at fixed intervals
In this example, the interrupt INTTB01 is set to be generated at fixed intervals. The
interval time is set in the timer register TB0RG1.
TB0RUN
INTETB01
m
m
7
0
X
6
0
1
5
X
0
4
X
0
TB0FFCR
TB0MOD
m
m
1
0
1
0
0
1
0
0
TB0RG1
m
TB0RUN
m
*
*
0
*
*
0
*
*
X
3
X
0
0
(**
* *
* *
X –
2
0
0
1
X
0
0
0
0
0 1 1
1 * *
01, 10, 11)
* * *
* * *
1 X 1
Stop TMRB0.
Enable INTTB01 and set interrupt level 4. Disable
INTTB00.
Disable the trigger.
Select internal clock for input and
disable the capture function.
Set the interval time (16 bits).
Start TMRB0.
X: Don’t care, : No change
(2) 16-bit event counter mode
As described above, in 16-bit timer mode, if the external clock (TB0IN0 pin input) is
selected as the input clock, the timer can be used as an event counter. To read the
value of the counter, first perform software capture once, then read the captured value.
TB0RUN
P9CR
INTETB01
m
m
m
TB0FFCR
TB0MOD
TB0RG1
m
m
m
TB0RUN
m
7
0
X
X
6
0
1
5
X
0
4
X
0
3
0
X
2
0
X
0
1
X
X
0
0
0
0
1
0
*
*
0
1
0
*
*
0
0
1
*
*
X
0
0
*
*
X
0
0
*
*
0
1
*
*
1
1
0
*
*
X
1
0
*
*
1
Stop TMRB0.
Set P93 input mode
Enable INTTB01 and set interrupt level 4. Disable
INTTB00.
Disable the trigger.
Select TB0IN0 as the input clock.
Set the number of counts (16 bits).
Start TMRB0.
X: Don’t care, : No change
When the timer is used as an event counter, set the prescaler in run mode
(i.e. with TB0RUN<TB0PRUN> 1).
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TMP91C630
(3) 16-bit programmable pulse generation (PPG) output mode
Square wave pulses can be generated at any frequency and duty ratio. The output
pulse may be either Low-active or High-active.
The PPG mode is obtained by inversion of the timer flip-flop TB0FF0 that is to be
enabled by the match of the up-counter UC0 with timer register TB0RG0 or TB0RG1
and to be output to TB0OUT0. In this mode the following conditions must be satisfied.
(Value set in TB0RG0) < (Value set in TB0RG1)
Match with TB0RG0
(INTTB00 inerrupt)
Match with TB0RG1
(INTTB01 interrupt)
TB0OUT0 pin
Figure 3.9.5 Programmable pulse generation (PPG) output waveforms
When the TB0RG0 double buffer is enabled in this mode, the value of register buffer
0 will be shifted into TB0RG0 at match with TB0RG1. This feature facilitates the
handling of low-duty waves.
Match with TB0RG0
Up-counter
Q1
Up-counter
Match with TB0RG1
TB0RG0
(value to be compared)
Register buffer
Q2
Shift into theTB0RG1
Q1
Q2
Q2
Q3
Write into the TB0RG0
Figure 3.9.6 Operation of Register Buffer
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2003-07-22
TMP91C630
The following block diagram illustrates this mode.
TB0RUN<TB0RUN>
TB0OUT0 (PPG output)
Selector
TB0IN0
IT1
IT4
IT16
16-bit up-counter
UC0
Match
16-bit comparator
Clear
F/F
(TB0FF0)
16-bit comparator
TB0RG0
Selector
TB0RG0-WR
Register buffer 0
TB0RG1
TB0RUN<TB0RDE>
Internal data bus
Figure 3.9.7 Block Diagram of 16-Bit Mode
The following example shows how to set 16-bit PPG output mode:
m
7
0
*
*
*
*
1
6
0
*
*
*
*
0
5
X
*
*
*
*
X
4
X
*
*
*
*
X
3
*
*
*
*
2
0
*
*
*
*
0
1
X
*
*
*
*
X
0
0
*
*
*
*
0
TB0FFCR
m
X
X
0
0
1
1
1
0
TB0MOD
m
0
0
1
0
P9CR
P9FC
TB0RUN
m
m
m
X
X
1
0
1
1
X
TB0RUN
TB0RG0
m
m
TB0RG1
m
TB0RUN
0
(**
X X
X 1 * *
01, 10, 11)
X X X X 1 X 1
Disable the TB0RG0 double buffer and stop TMRB0.
Set the duty ratio (16 bits).
Set the frequency (16 bits).
Enable the TB0RG0 double buffer.
(The duty and frequency are changed on an INTTB01
interrupt.)
Set the mode to invert TB0FF0 at the match with
TB0RG0/TB0RG1. Set TB0FF0 to 0.
Select the internal clock as the input clock and disable
the capture function.
Set P95 to function as TB0OUT0.
Start TMRB0.
X: Don’t care, : No change
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2003-07-22
TMP91C630
3.10 Serial Channels
TMP91C630 includes two serial I/O channels. Either UART mode (asynchronous
transmission) or I/O interface mode (synchronous transmission) can be selected.
x
I/O interface mode
Mode 0: For transmitting and receiving I/O data using the
synchronizing signal SCLK for extending I/O.
Mode 1: 7-bit data
x
UART mode
Mode 2: 8-bit data
Mode 3: 9-bit data
In Mode 1 and Mode 2 a parity bit can be added. Mode 3 has a wake-up function for making
the master controller start slave controllers via a serial link (a multi-controller system).
Figure 3.10.4 and 3 are block diagrams.
Table 3.10.1 Channels 0 and 1
Channel 0
Pin name
Channel 1
TXD1 (P84)
RXD1 (P85)
CTS1 /SCLK1 (P86)
STS1 (P87)
TXD0 (P80)
RXD0 (P81)
CTS0 /SCLK0 (P82)
STS0 (P83)
x Mode 0 (I/O Interface mode)
Bit0
1
2
3
4
5
6
7
Transfer direction
x Mode 1 (7-bit UART mode)
No parity
Start
Bit0
1
2
3
4
5
6
Stop
Parity
Start
Bit0
1
2
3
4
5
6
Parity Stop
x Mode 2 (8-bit UART mode)
No parity
Start
Bit0
1
2
3
4
5
6
7
Stop
Parity
Start
Bit0
1
2
3
4
5
6
7
Parity Stop
x Mode 3 (9-bit UART mode)
Start
Bit0
1
2
3
4
5
6
7
8
Start
Bit0
1
2
3
4
5
6
7
Bit8
Bit8
Bit8
Stop
Stop (Wake-up)
1 denoted.an address (select code).
0 denoted data.
Figure 3.10.1 Data Formats
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2003-07-22
TMP91C630
STS0 and STS1 pins are built in port P83 and P87. STS0 and STS1 are the request
signal for the next data send to the CPU. P8CR sets port as output mode, P8FC sets
STS using mode, and bit 0 of SC0MOD1 (SC1MOD1) register sets L level. Then STS is
enable to start to transfer the data.
When SCLK signal is exactly falling edge, STS is disable.
And when it is ended to transfer 8-bits data, the STS can be setted to enable and
request the next data
In SCLK output mode, the STS function can’t be used.
RESIO
S
IOBUS
D
WR
STS output
Q
CK
SCLK
IPH
S
D
CK
Q
D
Q
CK
SCLK input
SCLK
TXD
STS
STS is H level, when SCLK is falling edge timing.
REG WR by programing
91C630-113
2003-07-22
TMP91C630
3.10.1
Block Diagrams
Figure 3.10.2 is a block diagram representing serial channel 0.
Prescaler
2 4 8 16 32 64
IT0
IT2 IT8 IT32
Serial clock generation circuit
BR0CR
<BR0CK1:0>
TA0TRG
(from TMRA0)
BR0CR
<BR0ADDE>
Baud rate
generator
SC0MOD0
<SC1:0>
Selector
fSYS
y2
SCLK0
Shared
with P82
SCLK0
Shared
with P82
Selector
UART
mode
Selector
Selector
IT0
IT2
IT8
IT32
BR0ADD
<BR0K3:0>
Prescaler
BR0CR
<BR0S3:0>
SIOCLK
SC0MOD0
<SM1:0>
I/O
interface mode
SC0CR
<IOC>
I/O interface mode
Receive
counter
(UART only y 16)
INT request
INTRX0
INTTX0
SC0MOD0
<WU>
Serial channel
interrupt
control
RXDCLK
SC0MOD0
<RXE>
Transmision
counter
(UART only y 16)
TXDCLK
Receive
control
Transmission
control
SC0CR
<PE> <EVEN>
SC0MOD0
<CTSE>
Parity control
RXD0
Shared
with P81
CTS0
Shared
with P82
Receive buffer 1 (shift register)
RB8
Receive buffer 2 (SC0BUF)
Error flag
TB8
Transmission buffer
SC0CR
<OERR><PERR><FERR>
TXD0
Shared
with P80
Internal data bus
Figure 3.10.2 Block Diagram of the Serial Channel 0
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2003-07-22
TMP91C630
Prescaler
2 4 8 16 32 64
IT0
IT2 IT8 IT32
Serial clock generation circuit
BR1CR
<BR1CK1:0>
TA0TRG
(from TMRA0)
BR1CR
<BR1ADDE>
Baud rate
generator
SC1MOD0
<SC1:0>
Selector
fSYS
y2
SCLK1
Shared
with P86
SCLK1
Shared
with P86
Selector
UART
mode
Selector
Selector
IT0
IT2
IT8
IT32
BR1ADD
<BR1K3:0>
Prescaler
BR1CR
<BR1S3:0>
SIOCLK
SC1MOD0
<SM1:0>
I/O
interface mode
SC1CR
<IOC>
I/O interface mode
Receive
counter
(UART only y 16)
INT request
INTRX1
INTTX1
SC1MOD0
<WU>
Serial channel
interrupt
control
RXDCLK
SC1MOD0
<RXE>
Transmision
counter
(UART only y 16)
TXDCLK
Receive
control
Transmission
control
SC1CR
<PE> <EVEN>
SC1MOD0
<CTSE>
Parity control
RXD1
Shared
with P85
CTS1
Shared
with P86
Receive buffer 1 (shift register)
RB8
Receive buffer 2 (SC1BUF)
Error flag
TB8
Transmission buffer
SC1CR
<OERR><PERR><FERR>
TXD1
Shared
with P84
Internal data bus
Figure 3.10.3 Block Diagram of the Serial Channel 1
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3.10.2
Operation of Each Circuit
(1) Prescaler, prescaler clock select
There is a 6-bit prescaler for waking serial clock. The clock selected using
SYSCR0<PRCK1:0> is divided by 4 and input to the prescaler as IT0. The prescaler
can be run by selecting the baud rate generator as the waking serial clock.
Table 3.10.2 shows prescaler clock resolution into the baud rate generator.
Table 3.10.2 Prescaler Clock Resolution to Baud Rate Generator
Select Prescaler Clock
<PRCK1:0>
00
(fFPH)
Gear Value
<GEAR2:0>
Prescaler Output Clock Resolution
IT0
IT2
IT8
IT32
000 (fc)
fc/22
fc/24
fc/26
fc/28
001 (fc/2)
fc/23
fc/25
fc/27
fc/29
010 (fc/4)
fc/24
fc/26
fc/28
fc/210
011 (fc/8)
5
fc/2
7
fc/2
9
fc/2
fc/211
100 (fc/16)
fc/26
fc/28
fc/210
fc/212
XXX
fc/28
fc/210
fc/212
10
(fc/16 clock)
X: Don’t care, : Cannot be used
The baud rate generator selects between 4 clock inputs: IT0, IT2, IT8, and IT32
among the prescaler outputs.
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2003-07-22
TMP91C630
(2) Baud rate generator
The baud rate generator is a circuit which generates transmission and receiving
clocks which determine the transfer rate of the serial channels.
The input clock to the baud rate generator, IT0, IT2, IT8 or IT32, is generated by
the 6-bit prescaler which is shared by the timers. One of these input clocks is selected
using the BR0CR<BR0CK1:0> field in the baud rate generator control register.
The baud rate generator includes a frequency divider, which divides the frequency by
1 or N (16 K )
16
to 16 values, determining the transfer rate.
The transfer rate is determined by the settings of BR0CR<BR0ADDE, BR0S3:0> and
BR0ADD<BR0K3:0>.
x
In UART mode
When BR0CR<BR0ADDE>
0
The settings BR0ADD<BR0K3:0> are ignored. The baud rate generator divides
the selected prescaler clock by N, which is set in BR0CK <BR0S3:0>. (N 1, 2, 3
‚‚‚ 16)
When BR0CR<BR0ADDE>
1
The N (16 – K)/16 division function is enabled. The baud rate generator
divides the selected prescaler clock by N (16 – K)/16 using the value of N set in
BR0CR<BR0S3:0> (N 2, 3 ‚‚‚ 15) and the value of K set in BR0ADD<BR0K3:0>
(K 1, 2, 3 ‚‚‚ 15)
Note: If N 1 or N 16, the N (16 K)/16 division function is disabled. Clear
BR0CR<BR0ADDE> to 0.
x
In I/O interface mode
The N (16 – K)/16 division function is not available in I/O interface mode. Clear
BR0CR<BR0ADDE> to 0 before dividing by N.
The method for calculating the transfer rate when the baud rate generator is used is
explained below.
x
In UART mode
Baud rate
x
In I/O interface mode
Baud rate
x
Input clock of baud rate generator
y 16
Frequency divider for baud rate generator
Input clock of baud rate generator
y2
Frequency divider for baud rate generator
Integer divider (N divider)
For example, when the source clock frequency (fc) 12.288 MHz, the input clock
frequency
IT2 (fc/16), the frequency divider N (BR0CR<BR0S3:0>)
5, and
BR0CR<BR0ADDE> 0, the baud rate in UART mode is as follows:
* Clock state
Baud rate
System clock: High frequency (fc)
Clock gear: 1 (fc)
Prescaler clock: System clock
fc/16
y 16
5
12.288 u 106 y 16 y 5 y 16
9600 (bps)
Note: The N (16 K)/16 division function is disabled and setting BR0ADD
<BR0K3:0> is invalid.
91C630-117
2003-07-22
TMP91C630
x
N (16 K)/16 divider (UART mode only)
Accordingly, when the source clock frequency (fc)
4.8 MHz, the input clock
frequency
IT0, the frequency divider N (BR0CR<BR0S3:0>)
7, K
(BR0ADD<BR0K3:0>) 3, and BR0CR <BR0ADDE> 1, the baud rate in UART mode
is as follows:
* Clock state
System clock: High frequency (fc)
Clock gear: 1 (fc)
Prescaler clock: System clock
fc/4
7 (16 3)/16
Baud rate
y 16
4.8 u 106 y 4 y (7 13/16) y 16
9600 (bps)
Table 3.10.3 and 3.10.4 show examples of UART mode transfer rates.
Additionally, the external clock input is available in the serial clock (Serial channels
0 and 1). The method for calculating the baud rate is explained below:
x
In UART mode
Baud rate
external clock input frequency y 16
It is necessary to satisfy (external clock input cycle) t fc/4
x
In I/O interface mode
Baud rate
external clock input frequency
It is necessary to satisfy (external clock input cycle) t 16/fc
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TMP91C630
Table 3.10.3 Transfer Rate Selection (When Baud Rate Generator is Used and BR0CR<BR0ADDE>
0)
Unit (kbps)
Input Clock
fc [MHz]
Frequency Divider
IT2
IT8
IT32
2
76.800
19.200
4.800
1.200
4
38.400
9.600
2.400
0.600
8
19.200
4.800
1.200
0.300
0
9.600
2.400
0.600
0.150
5
38.400
9.600
2.400
0.600
A
19.200
4.800
1.200
0.300
2
115.200
3
76.800
19.200
4.800
1.200
6
38.400
9.600
2.400
0.600
C
19.200
4.800
1.200
0.300
9.830400
12.288000
IT0
14.745600
Note 1: Transfer rates in I/O interface mode are eight times faster than the values given above.
Note 2: The values in this table are calculated for when fc is selected as the system clock, the clock
gear is set for fc and the system clock is the prescaler clock input.
Table 3.10.4 Selection of Transfer Rate (When TMRA0 with Input Clock IT1 is Used)
Unit (kbps)
fc
TA0REG
12.288 MHz
12 MHz
9.8304 MHz
8 MHz
6.144 MHz
1H
96
76.8
62.5
48
2H
48
38.4
31.25
24
3H
32
4H
24
5H
19.2
8H
12
AH
9.6
10H
6
14H
4.8
31.25
16
19.2
12
9.6
9.6
6
4.8
4.8
3
2.4
Method for calculating the transfer rate (when TMRA0 is used):
Transfer rate
Clock frequency determined by SYSCR0<PRCK1:0>
TA0REG u 8 u 16
(when TMRA0 (input clock IT1) is used)
Note 1: The TMRA0 match detect signal cannot be used as the transfer clock in I/O interface mode.
Note 2: The values in this table are calculated for when fc is selected as the system clock, the clock
gear is set for fc and the system clock is the prescaler clock input.
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TMP91C630
(3) Serial clock generation circuit
This circuit generates the basic clock for transmitting and receiving data.
In I/O interface mode
x
In SCLK output mode with the setting SC0CR<IOC> 0, the basic clock is generated
by dividing the output of the baud rate generator by 2, as described previously.
In SCLK input mode with the setting SC0CR<IOC> 1, the rising edge or falling
edge will be detected according to the setting of the SC0CR<SCLKS> register to
generate the basic clock.
In UART mode
x
The SC0MOD0<SC1:0> setting determines whether the baud rate generator clock,
the internal system clock fSYS, the match detect signal from timer TMRA0 or the
external clock (SCLK0) is used to generate the basic clock SIOCLK.
(4) Receiving counter
The receiving counter is a 4-bit binary counter used in UART mode which counts up
the pulses of the SIOCLK clock. It takes 16 SIOCLK pulses to receive 1 bit of data; each
data bit is sampled three times - on the 7th, 8th and 9th clock cycles.
The value of the data bit is determined from these three samples using the majority
rule.
For example, if the data bit is sampled respectively as 1, 0 and 1 on 7th, 8th and 9th
clock cycles, the received data bit is taken to be 1. A data bit sampled as 0, 0 and 1 is
taken to be 0.
(5) Receiving control
x
In I/O interface mode
In SCLK output mode with the setting SC0CR<IOC>
0, the RXD0 signal is
sampled on the rising edge of the shift clock which is output on the SCLK0 pin.
In SCLK input mode with the setting SC0CR<IOC> 1, the RXD0 signal is sampled
on the rising or falling edge of the SCLK0 input, according to the SC0CR<SCLKS>
setting.
x
In UART mode
The receiving control block has a circuit which detects a start bit using the majority
rule. Received bits are sampled three times; when two or more out of three samples are
0, the bit is recognized as the start bit and the receiving operation commences.
The values of the data bits that are received are also determined using the majority
rule.
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(6) The receiving buffers
To prevent overrun errors, the receiving buffers are arranged in a double-buffer
structure.
Received data is stored one bit at a time in receiving buffer 1 (which is a shift
register). When 7 or 8 bits of data have been stored in receiving buffer 1, the stored
data is transferred to receiving buffer 2 (SC0BUF); this causes an INTRX0 interrupt to
be generated. The CPU only reads receiving buffer 2 (SC0BUF). Even before the CPU
has finished reading the contents of receiving buffer 2 (SC0BUF), more data can be
received and stored in receiving buffer 1. However, if receiving buffer 2 (SC0BUF) has
not been read completely before all the bits of the next data item are received by
receiving buffer 1, an overrun error occurs. If an overrun error occurs, the contents of
receiving buffer 1 will be lost, although the contents of receiving buffer 2 and
SC0CR<RB8> will be preserved.
SC0CR<RB8> is used to store either the parity bit added in 8-bit UART mode or
the most significant bit (MSB) in 9-bit UART mode.
In 9-bit UART mode the wake-up function for the slave controller is enabled by
setting SC0MOD0<WU> to 1; in this mode INTRX0 interrupts occur only when the
value of SC0CR<RB8> is 1.
(7) Transmission counter
The transmission counter is a 4-bit binary counter which is used in UART mode and
which, like the receiving counter, counts the SIOCLK clock pulses; a TXDCLK pulse is
generated every 16 SIOCLK clock pulses.
SIOCLK
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
TXDCLK
Figure 3.10.4 Generation of the Transmission Clock
(8) Transmission controller
x
In I/O interface mode
In SCLK output mode with the setting SC0CR<IOC>
0, the data in the
transmission buffer is output one bit at a time to the TXD0 pin on the rising edge of the
shift clock which is output on the SCLK0 pin.
In SCLK input mode with the setting SC0CR<IOC> 1, the data in the transmission
buffer is output one bit at a time on the TXD0 pin on the rising or falling edge of the
SCLK0 input, according to the SC0CR<SCLKS> setting.
x
In UART mode
When transmission data sent from the CPU is written to the transmission buffer,
transmission starts on the rising edge of the next TXDCLK, generating a transmission
shift clock TXDSFT.
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Handshake function
Serial channels 0 and 1 each have a CTS pin. Use of this pin allows data can be sent
in units of one frame; thus, overrun errors can be avoided. The handshake functions is
enabled or disabled by the SC0MOD0<CTSE> setting.
When the CTS pin foes high on completion of the current data send, data
transmission is halted until the CTS pin foes low again. However, the INTTX0
interrupt is generated, it requests the next data send to the CPU. The next data is
written in the transmission buffer and data sending is halted.
Although there is no RTS pin, a handshake function can easily be configured by
assigning any port to perform the RTS function. The RTS should be output high to
request send data halt after data receive is completed by software in the RXD interrupt
routine.
TMP91C630
TMP91C630
TXD
RXD
CTS
RTS (any port)
Sender
Receiver
Figure 3.10.5 Handshake Function
Timing to writing to the
transmission buffer
CTS
Send is suspended
from (1) and (2).
(1)
13
(2)
14
15
16
1
2
3
14
15
16
1
2
3
SIOCLK
TXDCLK
Start bit
TXD
Bit0
Note 1: If the CTS signal goes high during transmission, no more data will be sent after completion of the
current transmission.
Note 2: Transmission starts on the first falling edge of the TXDCLK clock after the CTS signal has fallen.
Figure 3.10.6 CTS (Clear to Send) Timing
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(9) Transmission buffer
The transmission buffer (SC0BUF) shifts out and sends the transmission data
written from the CPU, in order one bit at a time starting with the least significant bit
(LSB) and finishing with the most significant bit (MSB). When all the bits have been
shifted out, the empty transmission buffer generates an INTTX0 interrupt.
(10) Parity control circuit
When SC0CR<PE> in the serial channel control register is set to 1, it is possible to
transmit and receive data with parity. However, parity can be added only in 7-bit
UART mode or 8-bit UART mode. The SC0CR<EVEN> field in the serial channel
control register allows either even or odd parity to be selected.
In the case of transmission, parity is automatically generated when data is written
to the transmission buffer SC0BUF. The data is transmitted after the parity bit has
been stored in SC0BUF<TB7> in 7-bit UART mode or in SC0MOD0<TB8> in 8-bit
UART mode. SC0CR<PE> and SC0CR<EVEN> must be set before the transmission
data is written to the transmission buffer.
In the case of receiving, data is shifted into receiving buffer 1, and the parity is added
after the data has been transferred to receiving buffer 2 (SC0BUF), and then compared
with SC0BUF<RB7> in 7-bit UART mode or with SC0CR<RB8> in 8-bit UART mode.
If they are not equal, a parity error is generated and the SC0CR<PERR> flag is set.
(11) Error flags
Three error flags are provided to increase the reliability of data reception.
1.
Overrun error <OERR>
If all the bits of the next data item have been received in receiving buffer 1 while
valid data still remains stored in receiving buffer 2 (SC0BUF), an overrun error is
generated.
Following show over run generating process flow example.
(Receiving interrupts routine)
(1) Read receiving buffer
(2) Read error flag
(3) If<OERR>
“1”
Then
A) Set receiving enable write “0” to <RXE>
B) Wait the end of now frame
C) Read receiving buffer
D) Read error flag
E) Set receiving enable write “1” to <RXE>
F) Request transmission again
(4) Other process
2.
Parity error <PERR>
The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is
compared with the parity bit received via the RXD pin. If they are not equal, a
parity error is generated.
3.
Framing error <FERR>
The stop bit for the received data is sampled three times around the center. If
the majority of the samples are 0, a framing error is generated.
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2003-07-22
TMP91C630
(12) Timing generation
a.
In UART mode
Receiving
Mode
9-bit
(Note)
8-bit Parity
(Note)
8-bit, 7-bit Parity, 7-bit
Interrupt timing
Center of last bit
(bit 8)
Center of last bit
(parity bit)
Center of stop bit
Framing error timing
Center of stop bit
Center of stop bit
Center of stop bit
Parity error timing
Overrun error timing
Center of last bit
(parity bit)
Center of last bit
(bit 8)
Center of last bit
(parity bit)
m
Center of stop bit
Note: In 9-bit mode and 8-bit parity mode, interrupts coincide with the ninth bit pulse.
Thus, when servicing the interrupt, it is necessary to allow a 1-bit period to elapse (so
that the stop bit can be transferred) in order to allow proper framing error checking.
Transmitting
Mode
Interrupt timing
b.
9-bit
8-bit Parity
8-bit, 7-bit Parity, 7-bit
Just before stop bit is
transmitted
m
m
I/O interface
Transmission
interrupt
timing
Receiving
interrupt
timing
SCLK output mode
Immediately after rise of last SCLK signal. (See Figure 3.10.19)
SCLK input mode
Immediately after rise of last SCLK signal Rising mode, or
immediately after fall in Falling mode. (See Figure 3.10.20)
SCLK output mode
Timing used to transfer received to data Receive buffer 2 (SC0BUF)
(e.g. immediately after last SCLK). (See Figure 3.10.21)
SCLK input mode
Timing used to transfer received data to Receive buffer 2 (SC0BUF)
(e.g. immediately after last SCLK). (See Figure 3.10.22)
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3.10.3
SC0MOD0
(0202H)
SFRs
Bit symbol
7
6
5
4
3
2
1
0
TB8
CTSE
RXE
WU
SM1
SM0
SC1
SC0
0
0
0
0
0
0
0
0
Hand shake
0: CTS
disable
1: CTS
enable
Receive
function
0: Receive
disable
1: Receive
enable
Read/Write
After reset
Function
R/W
Transfer
data bit 8
Wake up
function
0: Disable
1: Enable
Serial transmission mode
00: I/O interface mode
01: 7-bit UART mode
10: 8-bit UART mode
11: 9-bit UART mode
Serial transmission clock
(UART)
00: TMRA0 trigger
01: Baud rate generator
10: Internal clock fSYS
11: External clcok
(SCLK0 input)
Serial transmission clock source (UART)
00
Timer TMRA0 match detect signal
01
Baud rate generator
10
Internal clock fSYS
11
External clock (SCLK0 input)
Note: The clock selection for the I/O interface mode is
controlled by the serial bontrol register (SC0CR).
Serial transmission mode
00
I/O interface mode
01
10
7-bit mode
UART
11
8-bit mode
9-bit mode
Wake-up function
9-bit UART
0
Interrupt generated when
data is received
1
Interrupt generated only
when RB8 1
Other modes
Don’t care
Receiving function
0
Receive disabled
1
Receive enabled
Handshake function ( CTS pin) enable
0
Disabled (always transferable)
1
Enabled
Transmission data bit 8
Figure 3.10.7 Serial Mode Control Register (Channel 0, SC0MOD0)
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SC1MOD0
(020AH)
Bit symbol
7
6
5
4
3
2
1
0
TB8
CTSE
RXE
WU
SM1
SM0
SC1
SC0
0
0
0
0
0
0
0
0
Hand shake
0: CTS
disable
1: CTS
enable
Receive
function
0: Receive
disable
1: Receive
enable
Read/Write
After reset
Function
R/W
Transfer
data bit 8
Wake up
function
0: Disable
1: Enable
Serial transmission mode
00: I/O interface mode
01: 7-bit UART mode
10: 8-bit UART mode
11: 9-bit UART mode
Serial transmission clock
(UART)
00: TMRA0 trigger
01: Baud rate generator
10: Internal clock fSYS
11: External clcok
(SCLK1 input)
Serial transmission clock source (UART)
00
01
10
11
Timer TMRA0 match detect signal
Baud rate generator
Internal clock fSYS
External clock (SCLK1 input)
Note: The clock selection for the I/O interface mode is
controlled by the serial bontrol register (SC1CR).
Serial transmission mode
00
01
10
11
I/O interface mode
UART
7-bit mode
8-bit mode
9-bit mode
Wake-up function
0
1
9-bit UART
Other modes
Interrupt generated when
data is received
Don’t care
Interrupt generated only
when RB8 1
Receiving function
0
1
Receive disabled
Receive enabled
Handshake function ( CTS pin) enable
0
1
Disabled (always transferable)
Enabled
Transmission data bit 8
Figure 3.10.8 Serial Mode Control Register (Channel 1, SC1MOD0)
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SC0CR
(0201H)
7
6
5
4
3
2
1
0
Bit symbol
RB8
EVEN
PE
OERR
PERR
FERR
SCLKS
IOC
Read/Write
R
After reset
0
0
0
Function
Received
data bit 8
R/W
0
R (cleared to 0 when read)
Parity
0: Odd
Parity
addition
1: Even
0: Disable
1: Enable
0
R/W
0
0
0
0: SCLK0
0: Baud rate
generator
1: SCLK0
pin input
1: Error
1: SCLK0
Overrun
Parity
Framing
I/O interface input clock selection
0
1
Baud rate generator
SCLK0 pin input
Edge selection for SCLK pin
0
1
Transmits and receivers
data on rising edge of SCLK0.
Transmits and receivers
data on falling edge SCLK0.
Framing error flag
Parity error flag
Overrun error flag
Cleared to 0 when read
Parity addition enable
0
1
Disabled
Enabled
Even parity addition/check
0
1
Odd parity
Even parity
Received data 8
Note:
As all error flags are cleared after reading do not test only a single bit with a bit-testing
instruction.
Figure 3.10.9 Serial Control Register (Channel 0, SC0CR)
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SC1CR
(0209H)
7
6
5
4
3
2
1
0
Bit symbol
RB8
EVEN
PE
OERR
PERR
FERR
SCLKS
IOC
Read/Write
R
After reset
0
0
0
Function
Received
data bit 8
R/W
0
R (cleared to 0 when read)
Parity
0: Odd
Parity
addition
1: Even
0: Disable
1: Enable
0
R/W
0
0
0
0: SCLK1
0: Baud rate
generator
1: SCLK1
pin input
1: Error
1: SCLK1
Overrun
Parity
Framing
I/O interface input clock selection
0
1
Baud rate generator
SCLK1 pin input
Edge selection for SCLK pin
0
1
Transmits and receivers
data on rising edge of SCLK1.
Transmits and receivers
data on falling edge SCLK1.
Framing error flag
Parity error flag
Overrun error flag
Cleared to 0 when read
Parity addition enable
0
1
Disabled
Enabled
Even parity addition/check
0
1
Odd parity
Even parity
Received data 8
Note:
As all error flags are cleared after reading do not test only a single bit with a bit-testing
instruction.
Figure 3.10.10 Serial Control Register (Channel 1, SC1CR)
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BR0CR
(0203H)
Bit symbol
7
6
5
4
3
2
1
0
BR0ADDE
BR0CK1
BR0CK0
BR0S3
BR0S2
BR0S1
BR0S0
0
0
0
0
0
0
0
0
Read/Write
R/W
After reset
Function
Write “0”
(16 K)/16 00: IT0
division
01: IT2
0: Disable
10: IT8
1: Enable
11: IT32
(16 K)/16 division enable
0
Disable
1
Enable
7
BR0ADD
(0204H)
Setting of the Divided frequency
Setting the input clock of baud rate generator
00
Internal clock IT0
01
Internal clock IT2
10
Internal clock IT8
11
Internal clock IT32
6
5
4
Bit symbol
3
2
1
0
BR0K3
BR0K2
BR0K1
BR0K0
0
0
0
0
Read/Write
R/W
After reset
Sets frequency divisor K
(divided by N (16 K)/16)
Function
Sets Baud Rate Generator Frequency Divisor
BR0CR<BR0ADDE>
BR0CR
<BR0S3:0>
DR0ADD
<BR0K3:0>
0000
0001 (K 1)
to
1111 (K 15)
0000 (N 16)
or
0001 (N 1)
Disable
1
0000 (N 2)
or
1111 (N 15)
0
1) (UART only)
to
1111 (N 15)
0000 (N 16)
Disable
Divided by
Disable
BR0CR<BR0ADDE>
0001 (N
Divided by N
N 16 K
16
Note 1: The baud rate generator can be set 1 when UART mode and disable (16 K)/16 division
function. Don’t use in I/O interface mode.
Note 2: Set BR0CR<BR0ADDE> to 1 after setting K (K
K)/16 division function is used.
1 to 15) to BR0ADD<BR0K3:0> when (16
Note 3: (16 K)/16 division function is possible to use in only UART mode.
Clear BR0CR<BR0ADDE> to 0 and disable N (16 K)/16 division function in I/O interface
mode.
Figure 3.10.11 Baud Rate Generator Control (Channel 0, BR0CR and BR0ADD)
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BR1CR
(020BH)
Bit symbol
7
6
5
4
3
2
1
0
BR1ADDE
BR1CK1
BR1CK0
BR1S3
BR1S2
BR1S1
BR1S0
0
0
0
0
0
0
0
0
Read/Write
R/W
After reset
Function
Write “0”
(16 K)/16 00: IT0
division
01: IT2
0: Disable
10: IT8
1: Enable
11: IT32
(16 K)/16 division enable
0
Disable
1
Enable
7
BR1ADD
(020CH)
Setting of the divided frequency
Setting the input clock of baud rate generator
00
Internal clock IT0
01
Internal clock IT2
10
Internal clock IT8
11
Internal clock IT32
6
5
4
Bit symbol
3
2
1
0
BR1K3
BR1K2
BR1K1
BR1K0
0
0
0
0
Read/Write
R/W
After reset
Sets frequency divisor K
(divided by N (16 K)/16)
Function
Sets Baud Rate Generator Frequency Divisor
BR0CR<BR1ADDE>
BR1CR
<BR1S3:0>
DR1ADD
<BR1K3:0>
0000
0001 (K 1)
to
1111 (K 15)
0000 (N 16)
or
0001 (N 1)
Disable
1
0000 (N 2)
or
1111 (N 15)
0
1) (UART only)
to
1111 (N 15)
0000 (N 16)
Disable
Divided by
Disable
BR1CR<BR1ADDE>
0001 (N
Divided by N
N 16 K
16
Note 1: The baud rate generator can be set 1 when UART mode and disable (16 K)/16 division
function. Don’t use in I/O interface mode.
Note 2: Set BR1CR<BR1ADDE> to 1 after setting K (K
(16 K)/16 division function is used.
1 to 15) to BR1ADD<BR1K3 to 0> when Note 3: (16 K)/16 division function is possible to use in only UART mode.
Clear BR1CR<BR1ADDE> to 0 and disable (16 K)/16 division function in I/O interface
mode.
Figure 3.10.12 Baud Rate Generator Control (Channel 1, BR1CR and BR1ADD)
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SC0BUF
(0200H)
7
6
5
4
3
2
1
0
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
7
6
5
4
3
2
1
0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
Note:
(Transmission)
(Receiving)
Read-modify-write instruction is prohibited for SC0BUF.
Figure 3.10.13 Serial Transmission/Receiving Buffer Registers (Channel 0 and SC0BUF)
SC0MOD1
(0205H)
7
6
Bit symbol
I2S0
FDPX0
STSEN0
Read/Write
R/W
R/W
W
After reset
0
0
Function
5
4
3
2
1
1
STS0
0: Enable
1: Disable
Duplex
0: Half
1: Full
IDLE2
0: Stop
1: Run
0
Figure 3.10.14 Serial Mode Control Register 1 (Channel 0 and SC0MOD1)
SC1BUF
(0208H)
7
6
5
4
3
2
1
0
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
7
6
5
4
3
2
1
0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
Note:
(Transmission)
(Receiving)
Read-modify-write instruction is prohibited for SC1BUF.
Figure 3.10.15 Serial Transmission/Receiving Buffer Registers (Channel 1 and SC1BUF)
SC1MOD1
(020DH)
7
6
Bit symbol
I2S1
FDPX1
STSEN1
Read/Write
R/W
R/W
W
After reset
0
0
Function
IDLE2
0: Stop
1: Run
5
4
3
2
1
0
1
STS1
0: Enable
1: Disable
Duplex
0: Half
1: Full
Figure 3.10.16 Serial Mode Control Register 1 (Channel 1 and SC1MOD1)
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3.10.4
Operation in Each Mode
(1) Mode 0 (I/O interface mode)
This mode allows an increase in the number of I/O pins available for transmitting
data to or receiving data from an external shift register.
This mode includes the SCLK output mode to output synchronous clock SCLK and
SCLK input external synchronous clock SCLK.
Output extension
TMP91C630
TXD
Input extension
Shift register
SI
SCLK
SCK
Port
RCK
A
TMP91C630
B
C
D
E
F
G
H
RXD
SCLK
Port
Shift register
QH
CLOCK
S/ L
A
B
C
D
E
F
G
H
TC74HC165 or equivalent
TC74HC595 or equivalent
Figure 3.10.17 SCLK Output Mode Connection Example
Output extension
TMP91C630
TXD
Input extension
Shift register
SI
SCLK
SCK
Port
RCK
A
TMP91C630
B
C
D
E
F
G
H
RXD
SCLK
Port
QH
CLOCK
S/ L
A
B
C
D
E
F
G
H
TC74HC165 or equivalent
TC74HC595 or equivalent
External clock
Shift register
External clock
Figure 3.10.18 Example of SCLK Input Mode Connection
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a.
Transmission
In SCLK output mode 8-bit data and a synchronous clock are output on the
TXD0 and SCLK0 pins respectively each time the CPU writes the data to the
transmission buffer.
When all the data has been output, INTES0<ITX0C> is set to 1, causing an
INTTX0 interrupt to be generated.
Timing to write
transmisison data
SCLK0 output
TXD0
Bit0
Bit1
Bit6
Bit7
<ITX0C> (INTTX0
interrupt request)
Figure 3.10.19 Transmitting Operation in I/O Interface Mode (SCLK0 Output Mode)
(Channel 0)
In SCLK input mode, 8-bit data is output on the TXD0 pin when the SCLK0
input becomes active after the data has been written to the transmission buffer by
the CPU.
When all the data has been output, INTES0<ITX0C> is set to 1, causing an
INTTX0 interrupt to be generated.
SCLK0 input
(<SCLKS> 0: Rising edge mode)
SCLK0 input
(<SCLKS> 1: Falling edge mode)
Bit0
TXD0
Bit1
Bit5
Bit6
Bit7
ITX0C (INTTX0 intterrupt reqest)
Figure 3.10.20 Transmitting Operation in I/O Interface Mode (SCLK0 Input Mode)
(Channel 0)
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b.
Receiving
In SCLK output mode the synchronous clock is output on the SCLK0 pin and
the data is shifted to receiving buffer 1. This is initiated when the receive
interrupt flag INTES0<IRX0C> is cleared as the received data is read. When 8-bit
data is received, the data is transferred to receiving buffer 2 (SC0BUF) following
the timing shown below and INTES0<IRX0C> is set to 1 again, causing an
INTRX0 interrupt to be generated.
Setting SC0MOD0<RXE>to 1 initiates SCLK0 output.
IRX0C(INTRX0
intterrupt request)
SCLK0 output
RXD0
Bit0
Bit1
Bit6
Bit7
Figure 3.10.21 Receiving Operation in I/O Interface Mode (SCLK0 Output Mode)
(Channel 0)
In SCLK input mode the data is shifted to receiving buffer 1 when the SCLK
input goes active. The SCLK input goes active when the receive interrupt flag
INTES0<IRX0C> is cleared as the received data is read. When 8-bit data is
received, the data is shifted to receiving buffer 2 (SC0BUF) following the timing
shown below and INTES0<IRX0C> is set to 1 again, causing an INTRX0 interrupt
to be generated.
SCLK0 input
(<SCLKS> 0: Rising edge mode)
SCLK0 input
(<SCLKS> 1: Falling edge mode)
Bit0
RXD0
Bit1
Bit5
Bit6
Bit7
IRX0C (INTRX0 interrupt request)
Figure 3.10.22 Receiving Operation in I/O Interface Mode (SCLK0 Input Mode)
(Channel 0)
Note: The system must be put in the receive enable state (SC0MOD0<RXE>
be received.
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1) before data can
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TMP91C630
c.
Transmission and receiving (full duplex mode)
When full duplex mode is used, set the receive interrupt level to 0 and set
enable the level of transmit interrupt. Ensure that the program which transmits
the interrupt reads the receiving buffer before setting the next transmit data.
The following is an example of this:
Example: Channel 0, SCLK output
Baud rate 9600 bps
fc 14.7456 MHz
System clock: High frequency (fc)
Clock gear: 1 (fc)
Prescaler clock: fFPH
Main routine
7
0
6
0
5
0
4
1
3
0
2
0
1
1
0
0
0
0
1
0
SC0MOD1 1
SC0CR
X
0
1
0
X
0
0
0
0
0
X
0
0
X
1
0
0
X
X
0
0
0
1
0
0
0
BR0CR
0
0
*
1
1
*
1
0
*
0
0
*
0
0
*
1
0
*
1
0
*
Baud rate 9600 bps
Enable receiving
Set the transmit data and start.
INTTX0 interrupt routine
Acc m SC0BUF
SC0BUF * * * *
*
*
*
*
Read the receiving buffer.
Set the next transmit data.
INTES0
P8CR
P8FC
SC0MOD0
SC0MOD0
SC0BUF
0
0
*
Set the INTTX0 level to 1.
Set the INTRX0 level to 0.
Set P80, P81 and P82 to function as the TXD0, RXD0
and SCLK0 pins respectively.
Select I/O interface mode.
Select Full duplex mode.
Sclk_out, transmit on negative edge, receive on
positive edge
X: Don’t care, : No change
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(2) Mode 1 (7-bit UART mode)
7-bit UART mode is selected by setting the serial channel mode register
SC0MOD0<SM1:0> field to 01.
In this mode a parity bit can be added. Use of a parity bit is enabled or disabled by
the setting of the serial channel control register SC0CR<PE> bit; whether even parity
or odd parity will be used is determined by the SC0CR<EVEN> setting when
SC0CR<PE> is set to 1 (enabled).
Setting example: When transmitting data of the following format, the control registers
should be set as described below. This explanation applies to channel
0.
Start
Bit0
1
2
3
4
5
6
Even
parity Stop
Transmission direction (transmission rate: 2400 bps at fc
12.288 MHz)
* Clock state
System clock: High frequency (fc)
Clock gear: 1 (fc)
Prescaler clock: System clock
P8CR
P8FC
SC0MOD0
SC0CR
BR0CR
INTES0
SC0BUF
m
m
m
m
m
m
m
7
0
X
0
X
*
6
0
1
0
1
*
5
X
0
1
1
0
*
4
0
X
0
0
*
3
0
X
0
*
2
1
X
1
*
1
X
0
0
0
*
0
1
1
1
0
1
*
Set P80 to function as the TXD0 pin.
Select 7-bit UART mode.
Add even parity.
Set the transfer rate to 2400 bps.
Enable the INTTX0 interrupt and set it to Interrupt Level 4.
Set data for transmission.
X: Don’t care, : No change
(3) Mode 2 (8-bit UART mode)
8-bit UART mode is selected by setting SC0MOD0<SM1:0> to 10. In this mode a
parity bit can be added (use of a parity bit is enabled or disabled by the setting of
SC0CR<PE>); whether even parity or odd parity will be used is determined by the
SC0CR<EVEN> setting when SC0CR<PE> is set to 1 (enabled).
Setting example: When receiving data of the following format, the control registers
should be set as described below.
Start
Bit0
1
2
3
4
5
6
7
Transmission direction (transmission rate: 9600 bps at fc
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12.288 MHz)
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TMP91C630
* Clock state
System clock: High frequency (fc)
Clock gear: 1 (fc)
Prescaler clock: System clock
Main settings
P8CR
SC0MOD0
SC0CR
BR0CR
INTES0
m
m
m
m
m
7
0
X
0
6
0
0
0
5
1
1
0
4
0
X
1
3
1
X
0
X
2
0
X
1
1
1
0
0
0
0
0
0
1
0
1
0
Set P81 (RXD0) to input port.
Enable receiving in 8-bit UART mode.
Add even parity.
Set the transfer rate to 9600 bps.
Enable the INTTX0 interrupt and set it to interrupt level 4.
Interrupt processing
Acc
m SC0CR AND 00011100
if Acc
z 0 then ERROR
Acc
m SC0BUF
Check for errors.
Read the received data.
X: Don’t care, : No change
(4) Mode 3 (9-bit UART mode)
9-bit UART mode is selected by setting SC0MOD0<SM1:0> to 11. In this mode parity
bit cannot be added.
In the case of transmission the MSB (9th bit) is written to SC0MOD0<TB8>. In the
case of receiving it is stored in SC0CR<RB8>. When the buffer is written and read, the
MSB is read or written first, before the rest of the SC0BUF data.
Wake-up function
In 9-bit UART mode, the wake-up function for slave controllers is enabled by setting
SC0MOD0<WU> to 1. The interrupt INTRX0 can only be generated when <RB8> 1.
TXD
RXD
Master
Note:
TXD
RXD
Slave 1
TXD
RXD
Slave 2
TXD
RXD
Slave 3
The TXD pin of each slave controller must be in open-drain output mode.
Figure 3.10.23 Serial Link Using Wake-up Function
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Protocol
a.
Select 9-bit UART mode on the master and slave controllers.
b.
Set the SC0MOD0<WU> bit on each slave controller to 1 to enable data receiving.
c.
The master controller transmits data one frame at a time. Each frame includes an 8-bit
select code which identifies a slave controller. The MSB (bit 8) of the data (<TB8>) is
set to 1.
Start
Bit 0
1
2
3
4
5
6
7
Select code of slave controller
8
Stop
1
d.
Each slave controller receives the above frame. Each controller checks the above select
code against its own select code. The controller whose code matches clears its WU bit to
0.
e.
The master controller transmits data to the specified slave controller (the controller
whose SC0MOD0<WU> bit has been cleared to 0). The MSB (bit 8) of the data (<TB8>)
is cleared to 0.
Start
Bit 0
1
2
3
4
5
Data
f.
6
7
Bit 8
Stop
0
The other slave controllers (whose <WU> bits remain at 1) ignore the received data
because their MSBs (bit 8 or <RB8>) are cleared to 0, disabling INTRX0 interrupts.
The slave controller whose WU bit 0 can also transmit to the master controller. In
this way it can signal the master controller that the data transmission from the master
controller has been completed.
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Setting example:
To link two slave controllers serially with the master controller
using the internal clock fSYS as the transfer clock.
TXD
RXD
TXD
Master
RXD
TXD
RXD
Slave 1
Slave 2
Select code
00000001
Select code
00001010
Since serial channels 0 and 1 operate in exactly the same way, channel 0 only is used
for the purposes of this explanation.
x
Setting the master controller
Main
P8CR
P8FC
INTES0
7 6 5
m m X
m X 1 0
4
0
3
X
2
1
1
0
X
0
0
1
1
1
SC0MOD0 m 1 0 1 0 1 1 1 0
SC0BUF
m 0 0 0 0 0 0 0 1
Set P81 and P80 to function as the RXD0 and TXD0 pins
respectively.
Enable the INTTX0 interrupt and set it to interrupt level 4.
Enable the INTRX0 interrupt and set it to interrupt level 5.
Set fSYS as the transmission clock for 9-bit UART mode.
Set the select code for slave controller 1.
INTTX0 interrupt
SC0MOD0 m 0 SC0BUF
m * * * * * * * *
x
Clear TB8 to 0.
Set data for transmission.
Setting the slave controller
Main
P8CR
P8FC
ODE
INTES0
SC0MOD0
m
m
m
m
m
7
X
X
0
6
X
1
0
5
X
X
0
1
4
1
1
3
X
X
1
2
X
1
1
1
0
X
X
1
1
0
1
1
1
0
0
Select P81 and P80 to function as the RXD0 and TXD0 pins
respectively (open-drain output).
Enable INTRX0 and INTTX0.
Set <WU> to 1 in 9-bit UART transmission mode using fSYS as
the transfer clock.
INTRX0 interrupt
Acc m SC0BUF
if Acc select code
then SC0MOD0 m 0 Clear <WU> to 0.
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3.11 Analog/Digital Converter
The TMP91C630 incorporates a 10-bit successive approximation-type analog/digital
converter (AD converter) with 8-channel analog input.
Figure 3.11.1 is a block diagram of the AD converter. The 8-channel analog input pins (AN0 to
AN7) are shared with the input-only port Port A and can thus be used as an input port.
Note: When IDLE2, IDLE1 or STOP mode is selected, so as to reduce the power, with some timings
the system may enter a standby mode even though the internal comparator is still enabled.
Therefore be sure to check that AD converter operations are halted before a HALT instruction
is executed.
Internal data bus
AD mode control register 1 ADMOD1
<ADTRGE>
<ADCH2:0><VREFON>
AD mode control register 0 ADMOD0
<EOCF><ADBF><ITM0><REPEAT><SCAN><ADS>
Scan
Repeat
Channel select
control circuit
Interrupt
ADTRG
Busy
End
Start
Analog input
AD converter control
circuit
AN7 (PA7)
INTAD
interrupt
AN6 (PA6)
AN4 (PA4)
AN3/ ADTRG (PA3)
AN2 (PA2)
AN1 (PA1)
Multiplexer
AN5 (PA5)
AD conversion result
Sample and
hold
AN0 (PA0)
register
ADREG04L to ADREG37L
ADREG04H to ADREG37H
Comparator
VREFH
DA converter
VREFL
Figure 3.11.1 Block Diagram of AD Converter
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3.11.1
Analog/Digital Converter Registers
The AD converter is controlled by the two AD mode control registers: ADMOD0 and
ADMOD1. The eight AD conversion data upper and lower registers (ADREG04H/L,
ADREG15H/L, ADREG26H/L and ADREG37H/L) store the results of AD conversion.
Figure 3.11.2 to Figure 3.12.5 shows the registers related to the AD converter.
AD Mode Control Register 0
ADMOD0
(02B0H)
Bit symbol
7
6
5
4
3
2
1
0
EOCF
ADBF
ITM0
REPEAT
SCAN
ADS
0
0
0
0
Read/Write
After reset
Function
R
0
R/W
AD conversion AD conversion Note:
end flag
busy flag
Always fixed
0: Conversion 0: Conversion to 0
in progress
Note:
Always fixed
to 0
stopped
1: Conversion 1: Conversion
complete
in progress
0
Repeat mode
Interrupt
specification in specification
conversion
0: Single
channel fixed
conversion
repeat mode
1: Repeat
0: Every
conversion
conversion
mode
1: Every fourth
conversion
0
0
AD conversion
start
Scan mode
specification
0: Conversion 0: Don’t care
channel
1: Start
fixed mode
conversion
1: Conversion
Always 0
channel
when read
scan mode
AD conversion start
0
Don’t care
1
Start AD conversion
Note:
Always read as 0.
AD scan mode setting
0
AD conversion channel fixed mode
1
AD conversion channel scan mode
AD repeat mode setting
0
AD single conversion mode
1
AD repeat conversion mode
Specify AD conversion interrupt for channel rixed repeat
conversion mode
Channel fixed repeat conversion mode
<SCAN> 0, <REPEAT> 1
0
Generates interrupt every conversion.
1
Generates interrupt every fourth conversion.
AD conversion busy flag
0
AD conversion stopped
1
AD conversion in progress
AD conversion end flag
0
Before or during AD conversion
1
AD conversion complete
Figure 3.11.2 AD Converter Related Register
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AD Mode Control Register 1
ADMOD1
(02B1H)
7
6
Bit symbol
VREFON
I2AD
Read/Write
R/W
R/W
After reset
0
0
VREF
application
control
IDLE2
0: Stop
1: Operate
Function
5
4
3
2
1
0
ADTRGE
ADCH2
ADCH1
ADCH0
0
0
0
0
R/W
AD external Analog input channel selection
trigger start
control
0: Disable
1: Enable
0: Off
1: On
Analog input channel selection
<SCAN>
0
<ADCH2,
Channel
ADCH1, ADCH0>
fixed
000
AN0
1
Channel
scanned
AN0
001
AN1
AN0 o AN1
010
AN2
AN0 o AN1 o AN2
011
AN3
AN0 o AN1 o AN2 o AN3
100
AN4
AN4
101
AN5
AN4 o AN5
110
AN6
AN4 o AN5 o AN6
111
AN7
AN4 o AN5 o AN6 o AN7
AD conversion start control by external trigger
( ADTRG input)
0
1
Disabled
Enabled
IDLE2 control
0
1
Stopped
In operation
Control of application of reference voltage to AD
converter
0
1
Off
On
Before starting conversion (before writing 1 to
ADMOD0 <ADS>), set the <VREFON> bit to 1.
Figure 3.11.3 AD Converter Related Register
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AD Conversion Data Low Register 0/4
ADREG04L Bit symbol
(02A0H)
Read/Write
7
6
ADR01
ADR00
4
3
2
1
0
ADR0RF
R
After reset
Function
5
R
Undefined
0
AD
conversion
data storage
flag
Stores lower 2 bits of AD
conversion result
1:Conversion
result
stored
AD Conversion Data Upper Register 0/4
ADREG04H Bit symbol
(02A1H)
Read/Write
7
6
5
4
3
2
1
0
ADR09
ADR08
ADR07
ADR06
ADR05
ADR04
ADR03
ADR02
R
After reset
Undefined
Function
Stores upper eight bits AD conversion result.
AD Conversion Data Lower Register 1/5
ADREG15L Bit symbol
(02A2H)
Read/Write
7
6
ADR11
ADR10
4
3
2
1
0
ADR1RF
R
After reset
Function
5
R
Undefined
0
Stores lower 2 bits of AD
conversion result
AD
conversion
result flag
1:Conversion
result
stored
AD Conversion Data Upper Register 1/5
ADREG15H Bit symbol
(02A3H)
Read/Write
7
6
5
4
3
2
1
0
ADR19
ADR18
ADR17
ADR16
ADR15
ADR14
ADR13
ADR12
R
After reset
Undefined
Function
Stores upper eight bits AD conversion result.
9
8
7
6
5
4
3
2
1
0
Channel x
conversion result
ADREGxH
7
6
ADREGxL
5
4
3
2
1
0
7
6
5
4
3
2
1
0
x Bits 5 to 1 are always read as 1.
x Bit 0 is the AD conversion data storage flag <ADRxRF>. When the
AD conversion result is stored, the flag is set to 1. When either of the
registers (ADREGxH, ADREGxL) is read, the flag is cleared to 0.
Figure 3.11.4 AD Converter Related Registers
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AD Conversion Result Lower Register 2/6
ADREG26L Bit symbol
(02A4H)
Read/Write
7
6
ADR21
ADR20
4
3
2
1
0
ADR2RF
R
After reset
Function
5
R
Undefined
0
Stores lower 2 bits of AD
conversion result.
AD
conversion
data storage
flag
1:Conversion
result
stored
AD Conversion Data Upper Register 2/6
ADREG26H Bit symbol
(02A5H)
Read/Write
7
6
5
4
3
2
1
0
ADR29
ADR28
ADR27
ADR26
ADR25
ADR24
ADR23
ADR22
R
After reset
Undefined
Function
Stores upper eight bits of AD conversion result.
AD Conversion Data Lower Register 3/7
ADREG37H Bit symbol
(02A6H)
Read/Write
7
6
ADR31
ADR30
3
2
1
0
ADR3RF
R
Undefined
0
Stores lower 2 bits of AD
conversion result
AD data
storage
1:Conversion
result
stored
7
ADREG37H Bit symbol
(02A7H)
Read/Write
4
R
After reset
Function
5
ADR39
AD Conversion Result Upper Register 3/7
6
5
4
3
ADR38
ADR37
ADR36
ADR35
2
1
0
ADR34
ADR33
ADR32
R
After reset
Undefined
Function
Stores upper eight bits of AD conversion result.
9
8
7
6
5
4
3
2
1
0
Channel x
conversion result
ADREGxH
7
6
ADREGxL
5
4
3
2
1
0
7
6
5
4
3
2
1
0
x Bits 5 to 1 are always read as 1.
x Bit 0 is the AD conversion data storage flag <ADRxRF>. When the
AD conversion result is stored, the flag is set to 1. When either of the
registers (ADREGxH, ADREGxL) is read, the flag is cleared to 0.
Figure 3.11.5 AD Converter Related Registers
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3.11.2
Description of Operation
(1) Analog reference voltage
A high-level analog reference voltage is applied to the VREFH pin; a low-level analog
reference voltage is applied to the VREFL pin. To perform AD conversion, the reference
voltage, the difference between VREFH and VREFL, is divided by 1024 using string
resistance. The result of the division is then compared with the analog input voltage.
To turn off the switch between VREFH and VREFL, program a 0 to
ADMOD1<VREFON> in AD mode control register 1. To start AD conversion in the
OFF state, first write a 1 to ADMOD1<VREFON>, wait for 3 Ps until the internal
reference voltage stabilizes (this is not related to fc), then set ADMOD0<ADS> to 1.
(2) Analog input channel selection
The analog input channel selection varies depends on the operation mode of the AD
converter.
x
In analog input channel fixed mode (ADMOD0<SCAN> 0)
Setting ADMOD1<ADCH2:0> selects one of the input pins AN0 to AN7 as the
input channel.
x
In analog input channel scan mode (ADMOD0<SCAN> 1)
Setting ADMOD1<ADCH2:0> selects one of the four scan modes.
Table 3.11.1 illustrates analog input channel selection in each operation mode.
On a reset, ADMOD0<SCAN> is set to 0 and ADMOD1<ADCH2:0> is initialized to
000. Thus pin AN0 is selected as the fixed input channel. Pins not used as analog input
channels can be used as standard input port pins.
Table 3.11.1 Analog Input Channel Selection
<ADCH2:0>
Channel Fixed
<SCAN> 0
Channel Scan
<SCAN> 1
000
AN0
AN0
001
AN1
AN0 o AN1
010
AN2
AN0 o AN1 o AN2
011
AN3
AN0 o AN1 o AN2 o AN3
100
AN4
AN4
101
AN5
AN4 o AN5
110
AN6
AN4 o AN5 o AN6
111
AN7
AN4 o AN5 o AN6 o AN7
(3) Starting AD conversion
To start AD conversion, write a 1 to ADMOD0<ADS> in AD mode control register 0
or ADMOD1<ADTRGE> in AD mode control register 1, pull the ADTRG pin input
from high to low. When AD conversion starts, the AD conversion busy flag
ADMOD0<ADBF> will be set to 1, indicating that AD conversion is in progress.
Writing a 1 to ADMOD0<ADS> during AD conversion restarts conversion. At that
time, to determine whether the AD conversion results have been preserved, check the
value of the conversion data storage flag ADREGxxL<ADRxRF>.
During AD conversion, a falling edge input on the ADTRG pin will be ignored.
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(4) AD conversion modes and the AD conversion end interrupt
The four AD conversion modes are:
x
Channel fixed single conversion mode
x
Channel scan single conversion mode
x
Chanel fixed repeat conversion mode
x
Channel scan repeat conversion mode
The ADMOD0<REPET> and ADMOD0<SCAN> settings in AD mode control
register 0 determine the AD mode setting.
Completion of AD coversion triggers an INTAD AD conversion end interrupt request.
Also, ADMOD0<EOCF> will be set to 1 to indicate that AD conversion has been
completed.
a.
Channel fixed single conversion mode
Setting ADMOD0<REPET> and ADMOD0<SCAN> to 00 selects conversion
channel fixed single conversion mode.
In this mode data on one specified channel is converted once only. When the
conversion has been completed, the ADMOD0<EOCF> flag is set to 1,
ADMOD0<ADBF> is cleared to 0, and an INTAD interrupt request is generated.
b.
Channel scan single conversion mode
Setting ADMOD0<REPET> and ADMOD0<SCAN> to 01 selects conversion
channel scan single conversion mode.
In this mode data on the specified scan channels is converted once only. When
scan conversion has been completed, ADMOD0<EOCF> is set to 1,
ADMOD0<ADBF> is cleared to 0, and an INTAD interrupt request is generated.
c.
Channel fixed repeat conversion mode
Setting ADMOD0<REPET> and ADMOD0<SCAN> to 10 selects conversion
channel fixed repeat conversion mode.
In this mode data on one specified channel is converted repeatedly. When
conversion has been completed, ADMOD0<EOCF> is set to 1 and
ADMOD0<ADBF> is not cleared to 0 but held at 1. INTAD interrupt request
generation timing is determined by the setting of ADMOD0<ITM0>.
Setting <ITM0> to 0 generates an interrupt request every time an AD
conversion is completed.
Setting <ITM0> to 1 generates an interrupt request on completion of every
fourth conversion.
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d.
Channel scan repeat conversion mode
Setting ADMOD0<REPET> and ADMOD0<SCAN> to 11 selects conversion
channel scan repeat conversion mode.
In this mode data on the specified scan channels is converted repeatedly. When
each scan conversion has been completed, ADMOD0<EOCF> is set to 1 and an
INTAD interrupt request is generated. ADMOD0<ADBF> is not cleared to 0 but
held at 1.
To stop conversion in a repeat conversion mode (i.e. in cases c and d), write a 0
to ADMOD0<REPET>. After the current conversion has been completed, the
repeat conversion mode terminates and ADMOD0<ADBF> is cleared to 0.
Switching to a halt state (IDLE2 mode with ADMOD1<I2AD> cleared to 0,
IDLE1 mode or STOP mode) immediately stops operation of the AD converter
even when AD conversion is still in progress. In repeat conversion modes (i.e. in
cases c and d), when the halt is released, conversion restarts from the beginning.
In single conversion modes (i.e. in cases a and b), conversion does not restart when
the halt is released (the converter remains stopped).
Table 3.11.2 shows the relationship between the AD conversion modes and interrupt
requests.
Table 3.11.2 Relationship Between AD Conversion Modes and Interrupt Requests
Mode
ADMOD0
Interrupt Request Generation
<ITM0>
<REPEAT>
<SCAN>
Channel fixed single
conversion mode
After completion of conversion
X
0
0
Channel scan single
conversion mode
After completion of scan conversion
X
0
1
1
0
1
1
Channel fixed repeat
conversion mode
Every conversion
0
Every forth conversion
1
Channel scan repeat
conversion mode
After completion of every scan
conversion
X
X: Don’t care
(5) AD conversion time
84 states (4.66 Ps at fFPH
channel.
36 MHz) are required for the AD conversion of one
(6) Storing and reading the results of AD conversion
The AD conversion data upper and lower registers (ADREG04H/L to ADREG37H/L)
store the results of AD conversion. (ADREG04H/L to ADRG37H/L are read-only
registers.)
In channel fixed repeat conversion mode (ADMOD0<ITM0> “1”), the conversion
results are stored successively in registers ADREG04H/L to ADRG37H/L. In other
modes the AN0 and AN4, AN1 and AN5, AN2 and AN6, AN3 and AN7 conversion
results are stored in ADREG04H/L, ADREG15H/L, ADREG26H/L and ADREG37H/L
respectively.
Table 3.11.3 shows the correspondence between the analog input channels and the
registers which are used to hold the results of AD conversion.
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Table 3.11.3 Correspondence Between Analog Input Channels and AD Conversion Result Registers
AD Conversion Result Register
Analog Input Channel
(Port A)
Conversion Modes
Other than at Right
AN0
Channel Fixed Repeat
Conversion Mode
(Every 4 th conversion)
ADREG04H/L
ADREG04H/L
AN4
AN1
ADREG15H/L
ADREG15H/L
AN5
AN2
ADREG26H/L
ADREG26H/L
ADREG37H/L
ADREG37H/L
AN6
AN3
AN7
<ADRxRF>, bit 0 of the AD conversion data lower register, is used as the AD
conversion data storage flag. The storage flag indicates whether the AD conversion
result register has been read or not. When a conversion result is stored in the AD
conversion result register, the flag is set to 1. When either of the AD conversion result
registers (ADREGxH or ADREGxL) is read, the flag is cleared to 0.
Reading the AD conversion result also clears the AD conversion end flag ADMOD0
<EOCF> to 0.
Setting example:
a.
Convert the analog input voltage on the AN3 pin and write the result, to memory
address 0800H using the AD interrupt (INTAD) processing routine.
Main routine:
7 6 5 4 3 2 1 0
INTE0AD
ADMOD1
ADMOD0
m X 1 0 0 m 1 1 X X 0 0 1 1
m X X 0 0 0 0 0 1
Enable INTAD and set it to interrupt level 4.
Set pin AN3 to be the analog input channel.
Start conversion in Channel fixed single conversion mode.
Interrupt routine processing example:
b.
WA
m ADREG37
WA
>>6
(0800H)
m WA
Read value of ADREG37L and ADREG37H into 16-bit
general-purpose register WA.
Shift contents read into WA six times to right and zero-fill upper
bits.
Write contents of WA to memory address 0800H.
This example repeatedly converts the analog input voltages on the three pins AN0,
AN1 and AN2, using channel scan repeat conversion mode.
INTE0AD
ADMOD1
ADMOD0
m X 0 0 0 m 1 1 X X 0 0 1 0
m X X 0 0 0 1 1 1
Disable INTAD.
Set pins AN0 to AN2 to be the analog input channels.
Start conversion in Channel scan repeat conversion mode.
X: Don’t care, : No change
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3.12 Watchdog Timer (Runaway Detection Timer)
The TMP91C630 features a watchdog timer for detecting runaway.
The watchdog timer (WDT) is used to return the CPU to normal state when it detects that the
CPU has started to malfunction (runaway) due to causes such as noise. When the watchdog
timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of
the malfunction.
Connecting the watchdog timer output to the reset pin internally forces a reset.
3.12.1
Configuration
Figure 3.12.1 is a block diagram of he watchdog timer (WDT).
WDMOD<RESCR>
RESET
Reset control
Internal reset
INTWD interrupt
WDMOD
<WDTP1:0>
Selector
21
215 217 219 2
fSYS
(fFPH/2)
Binary counter
Q
(22 stages)
R
S
Reset
Internal reset
Write
4EH
Write
B1H
WDMOD<WDTE>
WDT control register WDCR
Internal data bus
Figure 3.12.1 Block Diagram of Watchdog Timer
Note:
The watchdog timer cannot operate by disturbance noise in some case.
Take care when design the device.
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The watchdog timer consists of a 22-stage binary counter which uses the system clock
(fSYS) as the input clock. The binary counter can output fSYS/215, fSYS/217, fSYS/219 and
fSYS/221. Selecting one of the outputs using WDMOD<WDTP1:0> generates a Watchdog
interrupt and outputs watchdog timer out when an overflow occurs.
WDT counter
Overflow
n
0
WDT interrupt
Clear write code
WDT clear
(Soft ware)
Figure 3.12.2 Normal Mode
The runaway detection result can also be connected to the reset pin internally.
In this case, the reset time will be between 22 and 29 states as shown in Figure 3.12.3.
Overflow
WDT counter
n
WDT interrupt
Internal reset
22 to 29 states
(19.6 to 25.8 Ps at fOSCH 36 MHz, fFPH
2.25 MHz)
Figure 3.12.3 Reset Mode
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3.12.2
Control Registers
The watchdog timer WDT is controlled by two control registers WDMOD and WDCR.
(1) Watchdog timer mode register (WDMOD)
a.
Setting the detection time for the watchdog timer in <WDTP1:0>
This 2-bit register is used for setting the watchdog timer interrupt time used
when detecting runaway. On a reset this register is initialized to WDMOD
<WDTP1:0> 00.
The detection times for WDT are shown in Figure 3.12.4.
b.
Watchdog timer enable/disable control register <WDTE>
On a reset WDMOD<WDTE> is initialized to 1, enabling the watchdog timer.
To disable the watchdog timer, it is necessary to set this bit to 0 and to write the
disable code (B1H) to the watchdog timer control register WDCR. This makes it
difficult for the watchdog timer to be disabled by runaway.
However, it is possible to return the watchdog timer from the disabled state to
the enabled state merely by setting <WDTE> to 1.
c.
Watchdog timer out reset connection <RESCR>
This register is used to connect the output of the watchdog timer with the
RESET terminal internally. Since WDMOD<RESCR>is initialized to 0 on a reset,
a reset by the watchdog timer will not be performed.
(2) Watchdog timer control register (WDCR)
This register is used to disable and clear the binary counter for the watchdog timer.
x
Disable control
The watchdog timer can be disabled by clearing WDMOD<WDTE> to 0 and then
writing the disable code (B1H) to the WDCR register.
WDMOD
WDCR
x
m0 0 0 0
m1 0 1 1 0 0 0 1
Clear WDMOD<WDTE> to 0.
Write the disable code (B1H).
Enable control
Set WDMOD<WDTE> to 1.
x
Watchdog timer clear control
To clear the binary counter and cause counting to resume, write the clear code (4EH)
to the WDCR register.
WDCR
m0 1 0 0 1 1 1 0
Write the clear code (4EH).
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WDMOD Bit symbol
(0300H) Read/Write
7
6
5
4
3
2
1
WDTE
WDTP1
WDTP0
I2WDT
RESCR
R/W
R/W
R/W
After reset
Function
1
R/W
0
0
0
R/W
0
Always
write 0
WDT control Select detecting time
1: Enable
00: 215/fSYS
01: 217/fSYS
10: 219/fSYS
11: 221/fSYS
0
0
Always
write 0
IDLE2
0: Stop
1: Operate
R/W
0
0
1: Internally
connects
WDL out
to the
reset pin
Always
write 0
Watchdog timer out control
0
1
Connects WDT out to a reset
IDLE2 control
0
Stop
1
Operation
Watchdog timer detection time
fc
36 MHz
Watchdog Timer Detection Time
SYSCR1
Gear Value
<GEAR2:0>
WDMOD<WDTP1:0>
00
01
10
11
000 (fc)
1.82 ms
7.28 ms
29.1 ms
001 (fc/2)
3.64 ms
14.56 ms
58.2 ms
116.5 ms
233.0 ms
010 (fc/4)
7.28 ms
29.12 ms
116.4 ms
466.0 ms
011 (fc/8)
14.56 ms
58.24 ms
232.8 ms
932.0 ms
100 (fc/16)
29.12 ms
116.48 ms
465.6 ms
1864.0 ms
Watchdog timer enable/disable control
0
Disabled
1
Enabled
Figure 3.12.4 Watchdog Timer Mode Register
7
WDCR
(0301H)
6
5
4
3
Bit symbol
Read/Write
W
1
0
After reset
Function
2
B1H: WDT disable code
4EH: WDT clear code
Disable/clear WDT
B1H
Disable code
4EH
Clear code
Others
Don’t care
Figure 3.12.5 Watchdog Timer Control Register
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3.12.3
Operation
The watchdog timer generates an INTWD interrupt when the detection time set in the
WDMOD<WDTP1:0> has elapsed. The watchdog timer must be zero-cleared in software
before an INTWD interrupt will be generated. If the CPU malfunctions (i.e. if runaway
occurs) due to causes such as noise, but does not execute the instruction used to clear the
binary counter, the binary counter will overflow and an INTWD interrupt will be generated.
The CPU will detect malfunction (runaway) due to the INTWD interrupt and in this case it
is possible to return to the CPU to normal operation by means of an anti-mulfunction
program. By connecting the watchdog timer out pin to a peripheral device’s reset input, the
occurrence of a CPU malfunction can also be relayed to other devices.
The watch dog timer works immediately after reset.
The watchdog timer does not operate in IDLE1 or STOP mode, as the binary counter
continues counting during bus release (When BUSAK goes Low).
When the device is in IDLE2 mode, the operation of WDT depends on the
WDMOD<I2WDT> setting. Ensure that WDMOD<I2WDT> is set before the device enters
IDLE2 mode.
Example: a. Clear the binary counter.
WDCR
m 0 1 0 0 1 1 1 0
Write the clear code (4EH).
b. Set the watchdog timer detection time to 217/fSYS.
WDMOD m 1 0 1 0 0 0
c. Disable the watchdog timer.
WDMOD m 0 0 0 X 0
WDCR m 1 0 1 1 0 0 0 1
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Clear WDTE to 0.
Write the disable code (B1H).
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3.13 Multi-Vector Control
(1) Outline
By rewriting the value of multi-vector control register (MVEC0 and MVEC1), a vector
table is arbitrarily movable.
(2) Control register
The amount of 228 bytes become an interruption vector area from the value set as vector
control register (MVEC0 and MVEC1).
Vector Control Register Composition
7
6
5
MVEC0 Bit symbol
(00AEH) Read/Write
After reset
Function
VEC7
R/W
1
VEC6
R/W
1
VEC5
R/W
1
7
6
5
MVEC1 Bit symbol
(00AFH) Read/Write
After reset
Function
VEC15
R/W
1
VEC14
R/W
1
VEC13
R/W
1
Circuit composition
4
3
VEC4
VEC3
R/W
R/W
1
1
Vector address A15 to A8
4
3
VEC12
VEC11
R/W
R/W
1
1
Vector address A23 to A16
2
1
0
VEC2
R/W
1
VEC1
R/W
1
VEC0
R/W
1
2
1
0
VEC10
R/W
1
VEC9
R/W
1
VEC8
R/W
1
CPU output address AL23 to AL8
AL23 to AL8
CS circuit
form FFFF28H
to FFFFFFH
CS
AL8
Register
(MVEC0)
Register
(MVEC1)
Note:
S
A
Y
<VEC0>
A8
Internal address
A23 to A8
B
AL23
<VEC15>
A23
Write MVEC1 and MVEC0 after Making an Interruption Prohibition State.
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3.14 Multi-Boot Mode
(1) Outline
The TMP91C630 has multi-boot mode available as an on-board programming operation
mode. When in multi-boot mode, the boot ROM is mapped into memory space. This boot
ROM is a mask ROM that contains a program to rewrite the flash memory on-board.
Rewriting is accomplished by connecting the TMP91C630’s SIO and the programming
tool (controller) and then sending commands from the controller to the target board.
The boot program included in the boot ROM only has the function of a loader for
transferring program data from an external source into the device’s internal RAM.
Rewriting can be performed by UART. From 1000H to 105FH in device’s internal RAM is
work area of boot program. Don’t transfer program data in this work area.
Figure 3.14.1 shows an example of how to connect the programming controller and the
target board. (When ROM has 16-bit data bus.)
UART
3 pins
Programming
controller
TXD0 (Output)
RXD0 (Input)
RTS0 (P83) (Output)
TMP91C630
CS2
CS
RD
OE
WR
WE
D0 to D15
Boot/Normal
BOOT
A1 to A16
ROM
DT0 to DT15
AD0 to AD15
Figure 3.14.1 Example for Connecting Units for On-Board Programming
(2) Mode setting
To execute on-board programming, start the TMP91C630 in multi-boot mode. Settings
necessary to start up in multi-boot mode are shown below.
BOOT
L
RESET
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(3) Memory map
Figure 3.14.2 shows memory maps for multi-chip and multi-boot modes. When start up in
multi-boot mode, internal boot ROM is mapped in FFF800H address, the boot program
starts up.
When start up in multi-chip mode, internal boot ROM is mapped in 1F800H address, it
can be made to operate arbitrarily by the user. Program starting address is 1F800H.
Multi-chip mode
000000H
000100H
Multi-boot mode
000000H
Internal I/O
(4 Kbytes)
000100H
001000H
Internal I/O
(4 Kbytes)
Direct area (n)
001000H
Internal RAM
(6 Kbytes)
Internal RAM
(6 Kbytes)
002800H
002800H
External memory
01F800H
Internal boot ROM
(2 Kbytes)
01FFFFH
External memory
16-Mbyte area
(r32)
(r32)
(r32)
(r32 d8/16)
(r32 r8/16)
(nnn)
External memory
FFFF00H
FFFFFFH
Vector table
(256 bytes)
FFF800H
FFFEFFH
FFFF00H
FFFFFFH
(
Internal boot ROM
(2 Kbytes)
Vector table
(256 bytes)
Internal area)
Figure 3.14.2 TMP91C630 Memory Map
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(4) SIO interface specifications
The following shows the SIO communication format in multi-boot mode.
Before on-board programming can be executed, the communication format on the
programming controller side must also be set up in the same way as for the TMP91C630.
Note that although the default baud rate is 9600 bps, it can be changed to other values as
shown in Table 3.14.3.
Serial transfer mode: UART (asynchronous communication) mode, full-duplex
communication
Data length: 8 bits
Parity bit: None
STOP bit: 1 bit
Handshake: Micro-controller (P83) o Programming controller
Baud rate (default): 9600 bps
(5) SIO data transfer format
Table 3.14.1 through Table 3.14.6 show supported frequencies, data transfer format,
baud rate modification commands, operation commands, version management information,
and frequency measurement result with data store location, respectively.
Also refer to the description of boot program operation in the latter pages of this manual
as you read these tables.
Table 3.14.1 Supported Frequencies
16.000 MHz
20.000 MHz
22.579 MHz
25.000 MHz
32.000 MHz
33.868 MHz
36.000 MHz
Table 3.14.2 Transfer Format
Number of Bytes Transfer Data from Controller
Transferred
to TMP91C630
Boot
ROM
RAM
Note:
Baud Rate
Transfer Data from TMP91C630 to
Controller
1st byte
Matching data (5AH)
9600 bps
(Frequency measurement and baud
rate auto set)
2nd byte
9600 bps
OK: Echoback data (5AH)
NG: Nothing transmitted
3rd byte
:
6th byte
9600 bps
Version management information
(See Table 3.14.5)
7th byte
9600 bps
Frequency information (See Table 3.14.6)
8th byte
9th byte
Baud rate modification command
(See Table 3.14.3)
9600 bps
9600 bps
OK: Echoback data
NG: Error code X 3
10th byte
:
n’th -4 byte
User program
Extended Intel Hex format(binary)
Changed new baud rate NG: Operation stop by checksum error
n’th -3 byte
Changed new baud rate OK:SUM(High)
(See (6) (iii) Notes on SUM)
n’th -2 byte
Changed new baud rate OK:SUM(Low)
n’th -1 byte
n’th byte
User program start command (C0H)
(See Table 3.14.4)
Changed new baud rate Changed new baud rate OK: Echoback data (C0H)
NG: Error code X 3
JUMP to user program start address
Error code X 3 means sending an error code three times. Example, when error code is 62H,
TMP91C630 sends 62H three times. About error code, see (6)(ii) Error Code.
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Table 3.14.3 Baud Fate Modification Command
Baud rate (bps)
9600
19200
38400
57600
115200
Modification command
28H
18H
07H
06H
03H
Table 3.14.4 Operation Command
Operation command
Operation
C0H
Start user program
Table 3.14.5 Version Management Information
Version information
ASCII code
FRM1
46H, 52H, 4DH, 31H
Table 3.14.6 Frequency Measurement Result Data
Frequency of resonator
(MHz)
16.000
20.000
22.579
25.000
32.000
33.868
36.000
1000H
(RAM store address)
00H
01H
02H
03H
04H
05H
06H
(6) Description of SIO boot program operation
When you start the TMP91C630 in multi-boot mode, the boot program starts up. The
boot program provides the RAM loader function described below.
RAM loader
The RAM loader transfers the data sent from the controller in extended Intel Hex format
into the internal RAM. When the transfer has terminated normally, the RAM loader
calculates the SUM and sends the result to the controller before it starts executing the user
program. The execution start address is the first address received. This RAM loader
function provides the user’s own way to control on-board programming.
To execute on-board programming in the user program, you need to use the flash memory
command sequence to be connected. (Must be matched to the flash memory addresses in
multi-boot mode).
a.
Operational procedure of RAM loader
1.
Connect the serial cable. Make sure to perform connection before resetting the
microcontroller.
2.
Set the BOOT pin to “Boot” and reset the micro-controller.
3.
The receive data in the 1st byte is the matching data. When the boot program
starts in multi-boot mode, it goes to a state in which it waits for the matching data
to receive. Upon receiving the matching data, it automatically adjusts the serial
channels’ initial baud rate to 9600 bps. The matching data is 5AH.
4.
The 2nd byte is used to echo back 5AH to the controller upon completion of the
automatic baud rate setting in the first byte. If the device fails in automatic baud
rate setting, it goes to an idle state.
5.
The 3rd byte through 6th byte are used to send the version management
information of the boot program in ASCII code. The controller should check that
the correct version of the boot program is used.
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6.
The 7th byte is used to send information of the measured frequency.
The controller should check that the frequency of the resonator is measured
correctly.
7.
The receive data in the 8th byte is the baud rate modification data. The five kinds
of baud rate modification data shown in Table 3.14.3 are available. Even when you
do not change the baud rate, be sure to send the initial baud rate data (28H;9600
bps). Baud rate modification becomes effective after the echoback transmission is
completed.
8.
The 9th byte is used to echo back the received data to the controller when the data
received in the 8th byte is one of the baud rate modification data corresponding to
the device’s operating frequency. Then the baud rate is changed. If the received
baud rate data does not correspond to the device’s operating frequency, the device
goes to an idle state after sending 3 bytes of baud rate modification error code
(62H).
9.
The receive data in the 10th byte through n’th - 4 byte is received as binary data in
Extended Intel Hex format. No received data is echoed back to the controller.
The RAM loader processing routine ignores the received data until it receives the
start mark (3AH for “:”) in extended Intel Hex format. Nor does it send error code
to the controller. After receiving the start mark, the routine receives a range of
data from the data length to checksum and writes the received data to the
specified RAM addresses successively.
After receiving one record of data from start mark to checksum, the routine goes to
a start mark waiting state again.
If a receive error or checksum error of extended hex format occurs, the device goes
to an idle state without returning error code to the controller.
Because the RAM loader processing routine executes a SUM calculation routine
upon detecting the end record, the controller should be placed in a SUM waiting
state after sending the end record to the device.
10. The n’th - 3 byte and the n’th - 2 byte are the SUM value that is sent to the
controller in order of upper byte and lower byte. For details on how to calculate the
SUM, refer to “Notes on SUM” in the latter page of this manual. The SUM
calculation is performed only when no write error, receive error, or extended Intel
Hex format error has been encountered after detecting the end record. Soon after
calculation of SUM, the device sends the SUM data to the controller. The
controller should determine whether writing to the RAM has terminated normally
depending on whether the SUM value is received after sending the end record to
the device.
11. After sending the SUM, the device goes to a state waiting for the user program
start code. If the SUM value is correct, the controller should send the user
program start command to the n’th - 1 byte. The user program start command is
C0H.
12. The n’th byte is used to echo back the user program start code to the controller.
After sending the echoback to the controller, the stack pointer is set to 105FH and
the boot program jumps to the first address that is received as data in extended
Intel Hex format.
13. If the user program start code is wrong or a receive error occurs, the device goes to
an idle state after returning three bytes of error code to the controller.
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b.
Error code
The boot program sends the processing status to the controller using various code.
The error code is listed in the table below.
Table 3.14.7 Error Code
Error code
Meaning of error code
62H
Baud rate modification error occurred.
64H
Operation command error occurred.
A1H
Framing error in received data occurred.
A3H
Overrun error in received data occurred.
*1: When a receive error occurs when receiving the user program, the device does not send the error code to the
controller.
*2: After sending the error code, the device goes to an idle state.
c.
Notes on SUM
1.
Calculation method
SUM consists of byte byte….. byte, the sum of which is returned in word as
the result. Namely, data is read out in byte and sum of which is calculated, with the
result returned in word.
Example:
A1H
B2H
C3H
D4H
2.
If the data to be calculated consists of the four bytes
shown to the left, SUM of the data is:
A1H B2H C3H D4H 02EAH
SUM (HIGH) 02H
SUM (LOW) EAH
Calculation data
The data from which SUM is calculated is the RAM data from the first address
received to the last address received.
The received RAM write data is not the only data to be calculated for SUM. Even
when the received addresses are noncontiguous and there are some unwritten
areas, data in the entire memory area is calculated. The user program should not
contain unwritten gaps.
d.
Notes on extended Intel Hex format (binary)
1.
After receiving the checksum of a record, the device waits for the start mark (3AH
for “:”) of the next record. Therefore, the device ignores all data received between
records during that time unless the data is 3AH.
2.
Make sure that once the controller program has finished sending the checksum of
the end record, it does not send anything and waits for two byes of data to be
received (upper and lower bytes of SUM). This is because after receiving the
checksum of the end record, the boot program calculates the SUM and returns the
calculated SUM in two bytes to the controller.
3.
It becomes the cause of incorrect operation to write to areas out of device’s internal
RAM. Therefore, when an extended record is transmitted, be sure to set a
paragraph address to 0000H.
4.
Always make sure the first record type is an extended record. Because the initial
value of the address pointer is 00H.
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5.
Transmit a user program not by the ASCII code but by binary. However, start
mark “:” is 3AH (ASCII code).
Example: Transmit data in the case of writing in 16 bytes data from address 1060H
Data Record
3A 10 1060 00 0607F100030000F201030000B1F16010 77
Data
Check sum
Record type
Address
Number of data
“:” (Start mark)
3A 00 0000 01 FF
End Record
Check sum
Record type
Address
Number of data
“:” (Start mark)
e.
Error when receiving user program
If the following errors occur in extended Intel Hex format when receiving the user
program, the device goes to an idle state.
f.
x
When the record type is not 00H, 01H, 02H
x
When a checksum error occurs
Error between frequency measurement and baud rate
The boot program measures the resonator frequency when receiving matching data.
If an error is under 3%, the boot program decides on that frequency. Since there is an
overlap between the margin of 3% for 32.000 MHz and 33.868 MHz, the boundary is set
at the intermediate value between the two. The baud rate is set based on the measured
frequency. Each baud rate includes a set error shown in Table 3.14.8. For example, in
the case of 20.000 MHz and 9600 bps, the baud rate is actually set at 9615.38 bps with
an error of 0.2%. To establish communication, the sum of the baud rate set error shown
in Table 3.14.8 and the frequency error need to be under 3%.
Table 3.14.8 Set Error of Each Baud Rate (%)
9600 bps
19200 bps
38400 bps
57600 bps
115200 bps
16.000 MHz
0.2
0.2
0.2
0.6
0.8
20.000 MHz
0.2
0.2
0.2
0.2
22.579 MHz
0
0.7
0
25.000 MHz
0.2
0.5
0.1
0.5
0.5
32.000 MHz
0.1
0.2
0.2
0
0.6
0
0.7
0.2
0.2
33.868 MHz
0.2
0.2
0.2
36.000 MHz
0.2
0.2
0.7
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0.9
0
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TMP91C630
(7) Ports setup of the boot program
Only ports shown in Table 3.14.9 are set up in the boot program. At the time of boot
program use, be careful of the influence on a user system. Do not use CS0 space and P60 in
the system which uses the boot program.
Other ports are not setting up, and are the reset state or the state of boot program
starting.
Table 3.14.9 Ports Setting List
Ports
P60
Function
Input/Output
CS0
Output
High/Low
P61
Port
Output
P62
Port
Output
High
Notes
CS0 space is 20000H to 201FFH
P63
Port
Output
P80
Port
Input
High
P81
RXD0
Input
High
P82
Port
Input
P83
Port
Input
Low
P84
Port
Input
P85
Port
Input
P86
Port
Input
P87
Port
Input
Not open drain port.
This port becomes TXD0 after matching data reception.
This port is set as the output and becomes RTS0 after
matching data reception.
: Un-setting up
(8) Setting method of microcontroller peripherals
Although P83 has the RTS0 function, it is initially in a high impedance state and not set
as RTS0 . To establish serial communication, attach a pull-down resistor to P83.
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4.
Electrical Characteristics
4.1
Absolute Maximum Ratings
Parameter
Rating
Unit
Power supply voltage
Vcc
0.5 to 4.0
V
Input voltage
VIN
0.5 to Vcc 0.5
V
Output current (per pin)
IOL
2
mA
Output current (per pin)
IOH
2
mA
Output current (total)
6IOL
80
mA
Output current (total)
6IOH
80
mA
mW
Power dissipation (Ta
Note:
Symbol
PD
600
Soldering temperature (10 s)
85°C)
TSOLDER
260
°C
Storage temperature
TSTG
65 to 150
°C
Operating temperature
TOPR
40 to 85
°C
The absolute maximum ratings are rated values which must not be exceeded during operation,
even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is
exceeded, a device may break down or its performance may be degraded, causing it to catch fire or
explode resulting in injury to the user. Thus, when designing products which include this device,
ensure that no absolute maximum rating value will ever be exceeded.
4.2
DC Characteristics (1/2)
Parameter
Power supply voltage
(AVCC DVCC)
(AVSS DVSS 0 V)
Symbol
Vcc
Condition
fc
10 MHz to 36 MHz
Min
Typ. (Note)
2.7
Max
Unit
3.6
V
VIL
Vcc
2.7 V to 3.6 V
0.6
The other ports
VIL1
Vcc
2.7 V to 3.6 V
0.3 Vcc
VIL2
Vcc
2.7 V to 3.6 V
AM0, AM1
VIL3
Vcc
2.7 V to 3.6 V
0.3
X1
VIL4
Vcc
2.7 V to 3.6 V
0.2 Vcc
VIH
Vcc
2.7 V to 3.6 V
2.0
VIH1
Vcc
2.7 V to 3.6 V
0.7 Vcc
VIH2
Vcc
2.7 V to 3.6 V
0.75 Vcc
AM0, AM1
VIH3
Vcc
2.7 V to 3.6 V
Vcc 0.3
X1
VIH4
Vcc
2.7 V to 3.6 V
0.8 Vcc
Output low voltage
VOL
IOL
1.6 mA
Output high voltage
VOH
IOH
400 PA
Input low voltage
D0 to D7, P10 to P17 (D8 to D15)
RESET , NMI , BOOT
P56 (INT0), P70 (INT1)
P72 (INT2), P73 (INT3)
P75 (INT4), P90 (INT5)
Input high voltage
D0 to D7, P10 to P17 (D8 to D15)
The other ports
0.3
0.25 Vcc
V
RESET , NMI , BOOT
P56 (INT0), P70 (INT1)
P72 (INT2), P73 (INT3)
P75 (INT4), P90 (INT5)
Note:
Typical measurement Condition is Ta
25°C, Vcc
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Vcc 0.3
0.45
2.4
V
3.0 V unless otherwise noted.
2003-07-22
TMP91C630
DC Characteristics (2/2)
Parameter
Symbol
Min
Typ.
(Note 1)
Max
Condition
Unit
Input leakage current
ILI
0.02
r5
0.0 ” VIN ” Vcc
Output leakage current
ILO
0.05
r10
0.2 ” VIN ” Vcc 0.2
3.6
VIL2 0.2 Vcc,
VIH2 0.8 Vcc
Power down voltage
(at STOP, RAM back-up)
VSTOP
2.0
PA
V
RESET pull-up resistor
RRST
80
400
Vcc
2.7 V to 3.6 V
k:
BOOT pull-up resistor
RBT
80
400
Vcc
2.7 V to 3.6 V
k:
Pin capacitance
CIO
Schmitt width
RESET , NMI , BOOT , INT0 to 5
VTH
0.4
Programmable
pull-up resistor
RKH
80
10
1.0
400
NORMAL (Note 2): (Note 3)
17
25
IDLE2 (Note 3)
4
8
1.5
3.5
0.1
10
IDLE1 (Note 3)
Icc
STOP
Note 1: Typical measurement condition is Ta
25°C, Vcc
fc
1 MHz
pF
Vcc
2.7 V to 3.6 V
V
Vcc
2.7 V to 3.6 V
k:
2.7 V to 3.6 V
36 MHz
mA
2.7 V to 3.6 V
PA
Vcc
fc
Vcc
3.0 V unless otherwise noted.
Note 2: Icc measurement conditions (NORMAL):
All functions operate; output pins are open and input pins are fixed.
Note 3: Power supply current from AVCC pin is included in power supply current (Icc) of DVCC pin.
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4.3 AC Characteristics
(1) Vcc
No.
2.7 to 3.6 V
Parameter
x)
Variable
Symbol
fFPH
Min
Max
Min
100
36 MHz
Unit
Max
1
fFPH period (
tFPH
27.6
27.6
ns
2
A0 to A23 vaild o RD / WR fall
tAC
x 26
1.6
ns
3
RD rise o A0 to A23 hold
tCAR
0.5x 13.8
0.0
ns
4
WR rise o A0 to A23 hold
tCAW
x 13
14.6
ns
5
A0 to A23 valid o D0 to D15 input
tAD
3.5x 40
56.6
ns
6
RD fall o D0 to D15 input
tRD
2.5x 34
35.0
ns
7
RD low width
tRR
2.5x 25
44.0
8
RD rise o D0 to D15 hold
tHR
0
0
ns
9
WR low width
tWW
2.0x 25
30.2
ns
10
D0 to D15 valid o WR rise
tDW
1.5x 35
6.4
ns
11
WR rise o D0 to D15 hold
tWD
x 25
2.6
ns
12
A0 to A23 valid o WAIT input
(1 N) waits mode
tAW
13
RD / WR fall o WAIT hold
tCW
3.5x 60
2.5x 0
ns
36.6
69.0
ns
ns
(1 N) waits mode
14
A0 to A23 valid o Port input
tAPH
15
A0 to A23 valid o Port hold
tAPH2
16
A0 to A23 valid o Port valid
tAPO
3.5x 76
3.5x
20.6
ns
156.6
ns
96.6
3.5x 60
ns
AC Measuring Conditions
x
Output Level: High
0.7 Vcc, Low
0.3 Vcc, CL
x
Input Level:
0.9 Vcc, Low
0.1Vcc
Note:
High
50 pF
Symbol x in the above table means the period of clock fFPH, it’s half period of the system clock fSYS
for CPU core. The period of fFPH depends on the clock gear setting.
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(2) Read cycle
tFPH
fFPH
A0 to A23
CSn
tAW
tCW
WAIT
tAP
tAPH2
Port input
(Note)
tAD
RD
tCAR
tRR
tAC
tRD
tHR
D0 to D15
D0 to D15
Note:
Since the CPU accesses the internal area to read data from a port, the control signals of external
pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be
regarded as depicting internal operation. Please also note that the timing and AC characteristics of
port input/output shown above are typical representation. For details, contact your local Toshiba
sales representative.
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(3) Write cycle
fFPH
A0 to A23
CSn
WAIT
tAPO
Port output
(Note)
WR , HWR
tCAW
tWW
tDW
D0 to D15
D0 to D15
Note:
tWD
Since the CPU accesses the internal area to write data to a port, the control signals of external pins
such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded
as depicting internal operation. Please also note that the timing and AC characteristics of port
input/output shown above are typical representation. For details, contact your local Toshiba sales
representative.
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4.4
AD Conversion Characteristics
AVCC
Parameter
DVCC, AVSS
Symbol
Min
Typ.
Max
Analog reference voltage ()
VREFH
Vcc 0.2 V
Vcc
Vcc
Analog reference voltage ()
VREFL
Vss
VSS
Vss 0.2 V
VAIN
VREFL
Analog input voltage range
Analog current for analog
Reference voltage
<VREFON> 1
<VREFON>
IREF
(VREFL 0V)
0
Error
(not including quantizing errors)
Note 1: 1 LSB
DVSS
Unit
V
VREFH
0.94
1.35
mA
0.02
5.0
PA
r1.0
r4.0
LSB
(VREFH VREFL)/1024 [V]
Note 2: The value of Icc includes the current which flows through the AVCC pin.
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4.5
Serial Channel Timing (I/O Internal Mode)
Note: Symbol x in the below table means the period of clock fFPH, it’s half period of the system clock
fSYS for CPU core. The period of fFPH depends on the clock gear setting.
(1) SCLK input mode
Variable
Parameter
Symbol
Min
Max
36 MHz
(Note)
Min Max
Unit
SCLK period
tSCY
16X
0.44
Ps
Output data o SCLK rising/falling edge*
tOSS
tSCY/2 4X 85
25
ns
SCLK rising/falling edge* o Output data hold
tOHS
tSCY/2 2X 0
276
ns
SCLK rising/falling edge* o Input data hold
tHSR
3X 10
92
SCLK rising/falling edge* o Valid data input
tSRD
Valid data input o SCLK rising/falling edge*
tRDS
*) SCLK rinsing/falling edge:
tSCY 0
0
ns
440
0
ns
ns
The rising edge is used in SCLK rising mode.
The falling edge is used in SCLK falling mode.
Note: at tSCY 16X
(2) SCLK output mode
Min
Max
36 MHz
(Note)
Min Max
8192X
Variable
Parameter
Symbol
Unit
SCLK period (programable)
tSCY
16X
0.44
Ps
Output data oSCLK rising/falling edge*
tOSS
tSCY/2 40
180
ns
SCLK rising/falling edge* o Output data hold
tOHS
tSCY/2 40
180
ns
SCLK rising/falling edge* o Input data hold
tHSR
0
0
SCLK rising/falling edge* o Valid data input
tSRD
Valid data input o SCLK rising/falling edge*
tRDS
*) SCLK rinsing/falling edge:
Note:
at tSCY
tSCY 1X 90
1X 90
ns
324
117
ns
ns
The rising edge is used in SCLK rising mode.
The falling edge is used in SCLK falling mode.
16X
tSCY
SCLK
SCLK
tOSS
Output data
TXD
tOHS
0
1
tSRD
Input data
RXD
0
Valid
tRDS
1
Valid
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3
tHSR
2
3
Valid
Valid
2003-07-22
TMP91C630
4.6
Event Counter (TA0IN, TA4IN, TB0IN0, TB0IN1)
Parameter
Symbol
Variable
Min
Max
36 MHz
Min
Max
Unit
Clock perild
tVCK
8X 100
320
ns
Clock low level width
tVCKL
4X 40
150
ns
Clock high level width
tVCKH
4X 40
150
ns
Note:
Symbol x in the above table means the period of clock fFPH, it’s half period of the system clock
fSYS for CPU core. The period of fFPH depends on the clock gear setting.
4.7
Interrupts
Note:
Symbol x in the above table means the period of clock fFPH, it’s half period of the system
clock fSYS for CPU core. The period of fFPH depends on the clock gear setting.
(1) NMI , INT0 to INT5 interrupts
Parameter
Symbol
Variable
Min
Max
36 MHz
Min
Max
Unit
NMI , INT0 to INT5 low level width
tINTAL
4X 40
150
ns
NMI , INT0 to INT5 high level width
tINTAH
4X 40
150
ns
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4.8
Bus Request/Bus Acknowledge
BUSRQ
(Note 1)
tCBAL
BUSAK
tBAA
tABA
D0 to D15
(Note 2)
A0 to A23,
RD , WR
(Note 2)
CS0 to CS3 ,
HWR
Parameter
Variable
Symbol
fFPH
36 MHz
Min
Max
Min
Max
Unit
Output buffer to BUSAK low
tABA
0
80
0
80
ns
BUSAK high to output buffer on
tBAA
0
80
0
80
ns
Note 1: Even if the BUSRQ signal goes Low, the bus will not be released while the WAIT signal is Low.
The bus will only be released when BUSRQ goes Low while WAIT is High.
Note 2: This line shows only that the output buffer is in the Off state.
It does not indicate that the signal level is fixed.
Just after the bus is released, the signal level set before the bus was released is maintained
dynamically by the external capacitance. Therefore, to fix the signal level using an external
resister during bus release, careful design is necessary, since fixing of the level is delayed.
The internal programmable pull-up/pull-down resistor is switched between the Active and
Non-Active states by the internal signal.
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5.
Table of SFRs
The special function registers (SFRs) include the I/O ports and peripheral control registers
allocated to the 4-Kbyte address space from 000000H to 000FFFH.
(1) I/O port
(2) I/O port control
(3) Interrupt control
(4) Chip select/wait control
(5) Clock gear
(6) 8-bit timer
(7) 16-bit timer
(8) UART/serial channel
(9) AD converter
(10) Watchdog timer
(11) Multi vector control
Table layout
Symbol
Name
Address
7
6
1
0
Bit symbol
Read/Write
Initial value after reset
Remarks
Note:
“Prohibit RMW” in the a table means that you cannot use RMW instructions on these
register.
Example: When setting bit 0 only of the register P1CR, the instruction “SET 0, (0002H)” cannot be
used. The LD (transfer) instruction must be used to write all eight bits.
Read/Write
R/W: Both read and write are possible.
R: Only read is possible.
W: Only write is possible.
W*: Both read and write are possible (when this bit is read as 1)
Prohibit RMW: Read-modify-write instructions are prohibited. (The EX, ADD, ADC, BUS,
SBC, INC, DEC, AND, OR, XOR, STCF, RES, SET, CHG, TEST, RLC, RRC,
RL, RR, SLA, SRA, SLL, SRL, RLD and RRD instruction are
read-modify-write instructions.)
Prohibit RMW*: Read-modify-write is prohibited when controlling the pull-up resistor.
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Table 5.1 Address Map SFRs
[1] Port
Address
0000H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
P1
P1CR
P2
P2FC
P5
Address
0010H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
P5CR
P5FC
P6
P7
P6FC
P7CR
P7FC
P8
P9
P8CR
P8FC
P9CR
P9FC
PA
Address
Name
0020H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH ODE
Address
Name
0070H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH PZ
EH PZCR
FH PZFC
[2] INTC
Address
0080H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Note:
Name
DMA0V
DMA1V
DMA2V
DMA3V
INTCLR
DMAR
DMAB
IIMC0
IIMC1
Address
0090H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
INTE0AD
INTE12
INTE34
INTE5
INTETA01
INTETA23
INTETA45
INTETB0
INTETBOV
INTES0
INTES1
Address
00A0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
INTETC01
INTETC23
MVEC0
MVEC1
Do not access to the unnamed addresses, i.e. addresses to which no register has been allocated.
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[3] CS/WAIT
[4] CGEAR, DFM
Address
00C0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
B0CS
B1CS
B2CS
B3CS
BEXCS
MSAR0
MAMR0
MSAR1
MAMR1
MSAR2
MAMR2
MSAR3
MAMR3
Address
00E0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
SYSCR0
SYSCR1
SYSCR2
EMCCR0
EMCCR1
[5] TMRA
Address
0100H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Note:
Name
TA01RUN
TA0REG
TA1REG
TA01MOD
TA1FFCR
TA23RUN
TA2REG
TA3REG
TA23MOD
TA3FFCR
Address
0110H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
TA45RUN
TA4REG
TA5REG
TA45MOD
TA5FFCR
Do not access to the unnamed addresses, i.e. addresses to which no register has been allocated.
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[6] TMRB0
[7] UART/SIO
Name
Address
0180H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
TB0RUN
TB0MOD
TB0FFCR
TB0RG0L
TB0RG0H
TB0RG1L
TB0RG1H
TB0CP0L
TB0CP0H
TB0CP1L
TB0CP1H
Name
Address
0200H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
SC0BUF
SC0CR
SC0MOD0
BR0CR
BR0ADD
SC0MOD1
SC1BUF
SC1CR
SC1MOD0
BR1CR
BR1ADD
SC1MOD1
[8] 10-bit ADC
Address
02A0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Note:
Name
ADREG04L
ADREG04H
ADREG15L
ADREG15H
ADREG26L
ADREG26H
ADREG37L
ADREG37H
Address
02B0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
ADMOD0
ADMOD1
Do not access to the unnamed addresses i.e. addresses to which no register has been allocated.
[9] WDT
Address
0300H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Note:
Name
WDMOD
WDCR
Do not access to the unnamed addresses, i.e. addresses to which no register has been allocated.
91C630-175
2003-07-22
TMP91C630
(1) I/O port
Symbol
Name
Address
P1
Port 1
01H
7
6
5
4
P17
P16
P15
P14
3
2
1
0
P13
P12
P11
P10
P21
P20
P61
P60
R/W
Data from external port (Output latch register is clear to 0)
P27
P2
Port 2
P26
P25
P24
06H
P23
P22
R/W
Output latch register is set to 1
P56
P5
Port 5
P55
P54
P53
R/W
0DH
Data from external port
(Output latch register is set to 1)
P63
P62
R/W
P6
Port 6
12H
P7
Port 7
13H
Output latch Output latch Output latch register is
register is register is
set to 1.
set to 1.
clear to 0.
P75
P74
P73
P72
P71
P70
R/W
Data from external port (Output latch register is set to 1)
P87
P8
Port 8
P86
P85
P84
18H
P83
P82
P81
P80
R/W
Data from external port (Output latch register is set to 1)
P96
P9
Port 9
Port A
P94
P93
P90
R/W
R/W
Data from external port
(Output latch register is set to 1)
Data from
external
port
(Output
latch
register is
set to 1)
19H
PA7
PA
P95
PA6
PA5
PA4
1EH
PA3
PA2
PA1
PA0
R
Data from external port
PZ3
PZ2
R/W
PZ
Port Z
7DH
Data from external port
(Output latch register is
set to 1)
91C630-176
2003-07-22
TMP91C630
(2) I/O port control (1/2)
Symbol
P1CR
Name
Port 1
control
Address
04H
(Prohibit
RMW)
7
6
5
4
P17C
P16C
P15C
P14C
P5CR
Port 2
function
Port 5
control
09H
(Prohibit
RMW)
0
0
0
0
0: In
P26F
P25F
Port 5
function
1
0
P13C
P12C
P11C
P10C
0
0
0
0
P23F
P22F
P21F
P20F
1
1
1
1
P61F
P60F
1: Out
P24F
W
1
1
1
1
0: Port, 1: Address bus (A23 to A16)
10H
(Prohibit
RMW)
P56C
P55C
0
0
P54C
P53C
0
0
W
0: In
P56F
P5FC
2
W
P27F
P2FC
3
1: Out
P54F
W
11H
0
0: Port
1: INT0
(Prohibit
RMW)
P53F
W
0
0: Port
1: BUSAK
0
0: Port
1: BUSRQ
P63F
P6FC
Port 6
function
W
0
0: Port
1: CS3
(Prohibit
RMW)
P75C
P7CR
Port 7
control
Port 7
function
0
17H
1AH
P8FC
Port 8
control
Port 8
function
P73C
0
0
0: In
W
0
0: Port
1: INT2
(Prohibit
RMW)
P8CR
P74C
0
0: Port
1: CS2
0
0: Port
1: CS1
0
0: Port
1: CS0
P72C
P71C
P70C
0
0
0
P71F
P70F
W
16H
(Prohibit
RMW)
P72F2
P7FC
P62F
15H
P87C
P86C
P75F
W
0
0: Port
1: INT4
P85C
P74F
P73F
W
W
0
0
0: Port
0: Port
1: TA5OUT 1: INT3
P84C
1: Out
P72F1
W
W
W
0
0
0
0: Port
0: Port
0: Port
1: TA3OUT 1: TA1OUT 1: INT1
P83C
P82C
P81C
P80C
0
0
0
0
W
(Prohibit
RMW)
0
P87F
W
1BH
0
(Prohibit 0: Port
RMW) 1: STS1
0
0
0
0: In
P86F
W
0
0: Port
1: SCLK1
P84F
W
0
0: Port
1: TXD1
91C630-177
1: Out
P83F
W
0
0: Port
1: STS0
P82F
W
0
0: Port
1: SCLK0
P80F
W
0
0: Port
1: TXD0
2003-07-22
TMP91C630
I/O port control (2/2)
Symbol
P9CR
P9FC
Name
Port 9
control
Port 9
function
Address
1CH
(Prohibit
RMW)
7
6
P96C
5
P95C
0
0
4
P94C
3
P93C
0
0
2
W
0: In
0
1: Out
0: In 1:Out
P96F
P95F
P90F
1DH
W
W
W
(Prohibit
RMW)
0
0
0: Port
0
0: Port
1: INT5
0: Port
PZ3C
Port Z
control
0
P90C
W
1: TB0OUT1 1: TB0OUT0
PZCR
1
PZ2C
W
7EH
(Prohibit
RMW)
0
0: In
0
1: Out
PZ2F
PZFC
Port Z
function
W
7FH
0
0: Port
1: HWR
(Prohibit
RMW)
ODE
Sirial open
2FH
drain
(Prohibit
RMW)
ODE84
ODE80
W
W
0
0
1: P84ODE
1: P80ODE
91C630-178
2003-07-22
TMP91C630
(3) Interrupt control (1/3)
Symbol
INTE0AD
Name
Interrupt
enable
INT0 &
AD
Address
7
6
5
4
3
2
INTAD
90H
IADC
IADM2
IADM1
R
IADM0
R/W
0
1: INTAD
0
I2C
I2M2
I0C
I0M2
R
Interrupt
enable
INT2/1
91H
0
0
Interrupt request level
Interrupt
enable
INT4/3
92H
I2M0
R/W
0
1: INT2
0
0
1: INT0
0
I4C
I4M2
INTE5
Interrupt
enable
INT5
R
0
1: INT4
I1C
I1M2
0
0
Interrupt request level
Interrupt
INTETA23 enable
TMRA
3/2
Interrupt
INTETA45 enable
TMRA
5/4
INTETB0
INTETBOV
Interrupt
enable
TMRB0
Interrupt
enable
TMRB0
(over flow)
I1M0
R/W
0
1: INT1
0
0
0
Interrupt request level
I3C
I3M2
INT3
I4M1
I4M0
I3M1
R
0
0
Interrupt request level
I3M0
R/W
0
1: INT3
0
0
0
Interrupt request level
I5C
I5M2
INT5
93H
R
95H
ITA1C
INTTA1 (TMRA1)
ITA1M2
ITA1M1
R
0
1: INTTA1
96H
ITA3C
R/W
0
97H
ITA5C
99H
ITB01C
R/W
0
ITB01M0
R/W
0
0
0
Interrupt request level
0
1: INTTA0
0
ITA2M0
R/W
0
1: INTTA2
0
0
0
Interrupt request level
INTTA4 (TMRA4)
ITA4M2
ITA4M1
ITA4C
ITA4M0
R/W
0
1: INTTA4
0
0
0
Interrupt request level
INTTB00 (TMRB0)
ITB00M2
ITB00M1
ITB00C
R
ITB00M0
R/W
0
1: INTTB00
0
0
0
Interrupt request level
INTTBOF0 (TMRB0 overflow)
ITF0M2
ITF0M1
ITF0M0
R
0
1: INTTBOF0
91C630-179
ITA0M0
0
0
Interrupt request level
INTTA2 (TMRA2)
ITA2M2
ITA2M1
ITA2C
ITF0C
9BH
0
0
Interrupt request level
R/W
R
0
0
Interrupt request level
INTTB01 (TMRB0)
ITB01M2 ITB01M1
R
0
1: INTTB01
ITA5M0
I5M0
INTTA0 (TMRA0)
ITA0M2
ITA0M1
ITA0C
R
0
0
Interrupt request level
INTTA5 (TMRA5)
ITA5M2
ITA5M1
R
0
1: INTTA5
ITA3M0
R/W
0
0
R
0
0
Interrupt request level
INTTA3 (TMRA3)
ITA3M2
ITA3M1
R
0
1: INTTA3
ITA1M0
I5M1
R/W
0
1: INT5
Interrupt
INTETA01 enable
TMRA
1/0
I1M1
R
R/W
0
I0M0
0
0
Interrupt request level
INT4
INTE34
I0M1
INT1
I2M1
R
0
R/W
INT2
INTE12
1
INT0
R/W
0
0
0
Interrupt request level
2003-07-22
TMP91C630
Interrupt control (2/3)
Symbol
Name
Address
7
6
5
4
3
2
INTTX0
INTES0
Interrupt
enable
serial 0
9CH
ITX0C
ITX0M2
ITX0M1
R
0
ITX0M0
R/W
0
1: INTTX0
IRX0C
INTES1
9DH
ITX1C
0
0
Interrupt request level
ITX1M2
IRX0M2
0
0
Interrupt
INTETC01
enable
INTTC0/1
0
0
INTETC23
Interrupt
enable
INTTC2/3
ITC1C
ITX1M0
IRX1C
IRX1M2
0
0
0
0
0
1: INTRX1
ITC1M0
R/W
0
ITC3C
ITC0C
ITC0M2
0
0
0
ITC0M0
R/W
0
0
0
ITC2M1
ITC2M0
INTTC2
ITC3M1
ITC3M0
R/W
0
0
ITC0M1
R
0
ITC3M2
R
0
Interrupt request level
INTTC3
A1H
IRX1M0
R/W
INTTC0
ITC1M1
R
0
IRX1M1
R
Interrupt request level
ITC1M2
0
Interrupt request level
INTTC1
A0H
IRX0M0
R/W
1: INTRX0
R/W
1: INTTX1
IRX0M1
INTRX1
ITX1M1
R
0
R
INTTX1
Interrupt
enable
serial 1
1
INTRX0
0
91C630-180
ITC2C
ITC2M2
R
0
0
R/W
0
0
0
2003-07-22
TMP91C630
Interrupt control (3/3)
Symbol
DMA0V
DMA1V
DMA2V
DMA3V
Name
Address
DMA0
start
vector
80H
(Prohibit
RMW)
DMA1
start
vector
81H
(Prohibit
RMW)
DMA2
start
vector
82H
(Prohibit
RMW)
DMA3
start
vector
83H
(Prohibit
RMW)
DMA
burst
request
register
8AH
(Prohibit
RMW)
IIMC1
Interrupt
input
mode
control 1
3
2
1
0
DMA0V3
DMA0V2
DMA0V1
DMA0V0
0
0
0
0
0
0
DMA1V2
DMA1V1
DMA1V0
0
0
0
DMA2V2
DMA2V1
DMA2V0
0
0
0
DMA3V2
DMA3V1
DMA3V0
0
0
0
CLRV2
CLRV1
CLRV0
R/W
DMA1V5
DMA1V4
DMA1V3
R/W
0
0
0
DMA2V5
DMA2V4
DMA2V3
R/W
0
0
0
DMA3V5
DMA3V4
DMA3V3
R/W
0
0
0
DMA3 start vector
89H
(Prohibit
RMW)
IIMC0
4
DMA0V4
DMA2 start vector
DMA
software
request
register
Interrupt
input
mode
control 0
5
DMA0V5
DMA1 start vector
88H
(Prohibit
RMW)
DMAB
6
DMA0 start vector
Interrupt
INTCLR clear
control
DMAR
7
CLRV5
CLRV4
CLRV3
W
Clear interrupt request DMA flag by writing to DMA start vector
DMAR3
DMAR2
DMAR1
DMAR0
R/W
R/W
R/W
R/W
0
0
0
0
1: DMA request in software (Note)
DMAB3
DMAB2
DMAB1
DMAB0
R/W
R/W
R/W
R/W
0
0
0
0
1 : DMA request on burst mode
W
8CH
0
(Prohibit
Always
RMW)
write 0
8DH
(Prohibit
RMW)
I2EDGE
I2LE
I1EDGE
I1LE
I0EDGE
I0LE
NMIREE
W
W
W
W
W
W
W
0
0
0
0
0
0
INT2 edge INT2
0: Edge
0: Rising
1: Level
1: Falling
INT1 edge INT1
0: Edge
0: Rising
1: Level
1: Falling
0
INT0 edge INT0
0: Edge
0: Rising
1: Level
1: Falling
1: Operate
even on
rising/falling
edge of
I5EDGE
I5LE
I4EDGE
I4LE
I3EDGE
I3LE
W
W
W
W
W
W
0
0
0
0
0
INT5
edge
0: Rising
1: Falling
INT5
0: Edge
1: Level
INT4
edge
0: Rising
1: Falling
INT4
0: Edge
1: Level
INT3
edge
0: Rising
1: Falling
NMI
0
INT3
0: Edge
1: Level
Note: Only one-channel can be set once for DMAR register. (Don’t write “1” to plural bits.)
91C630-181
2003-07-22
TMP91C630
(4) Chip select/Wait control (1/2)
Symbol
B0CS
B1CS
B2CS
B3CS
BEXCS
MSAR0
Name
Block 0
CS/WAIT
control
register
Block 1
CS/WAIT
control
register
Block 2
CS/WAIT
control
register
Block 3
CS/WAIT
control
register
External
CS/WAIT
control
register
Memory
start
address
register 0
Memory
MAMR0 address
mask
register 0
MSAR1
Memory
start
address
register 1
Memory
MAMR1 address
mask
register 1
Address
C0H
5
4
3
2
1
0
B0E
7
6
B0OM1
B0OM0
B0BUS
B0W2
B0W1
B0W0
W
W
W
W
W
W
W
0
0
0
00: ROM/SRAM
01:
10: Reserved
11:
0: Disable
(Prohibit 1: Enable
RMW)
C1H
B1OM1
B1OM0
B1BUS
B1W2
B1W1
B1W0
W
W
W
W
W
W
W
0
0
0
0
00: ROM/SRAM
01:
10: Reserved
11:
Data bus
width
0: 16 bits
1: 8 bits
0
0
0
000: 2 waits
001: 1 wait
010: (1 N) waits 1xx: Reserved
011: 0 waits
B2E
B2M
B2OM1
B2OM0
B2BUS
B2W2
B2W1
B2W0
W
W
W
W
W
W
W
W
1
0
0
0
0
0: Disable
(Prohibit 1: Enable
RMW)
C3H
0
0
0
000: 2 waits
001: 1 wait
010: (1 N) waits 1xx: Reserved
011: 0 waits
B1E
0: Disable
(Prohibit 1: Enable
RMW)
C2H
0
Data bus
width
0: 16 bits
1: 8 bits
0: 16-MB 00: ROM/SRAM
space 01:
1: CS area 10: Reserved
11:
Data bus
width
0: 16 bits
1: 8 bits
0
0
0
000: 2 waits
001: 1 wait
010: (1 N) waits 1xx: Reserved
011: 0 waits
B3E
B3OM1
B3OM0
B3BUS
B3W2
B3W1
B3W0
W
W
W
W
W
W
W
0
0
0
0
00: ROM/SRAM
01:
10: Reserved
11:
0: Disable
(Prohibit 1: Enable
RMW)
Data bus
width
0: 16 bits
1: 8 bits
BEXBUS
BEXW2
BEXW1
BEXW0
W
W
W
W
C7H
0
Data bus
width
0: 16 bits
1: 8 bits
(Prohibit
RMW)
S23
S22
S21
S20
C8H
0
0
0
000: 2 waits
001: 1 wait
010: (1 N) waits 1xx: Reserved
011: 0 waits
0
0
0
000: 2 waits
001: 1 wait
010: (1 N) waits 1xx: Reserved
011: 0 waits
S19
S18
S17
S16
1
1
1
1
V16
V15
V14~9
V8
1
1
1
1
R/W
1
1
1
V20
V19
V18
1
Start address A23 to A16
V17
C9H
R/W
1
1
S23
S22
1
1
CS0 area size
0: Enable to address comparision
S21
S20
CAH
S19
S18
S17
S16
1
1
1
1
V17
V16
V15~9
V8
1
1
1
R/W
1
1
1
1
Stat address A23 to A16
V21
V20
V19
V18
CBH
R/W
1
1
1
CS1 area size
1
0: Enable to address comparsion
91C630-182
2003-07-22
TMP91C630
Chip select /Wait control (2/2)
Symbol
Name
Memory
start
MSAR2
address
register 2
Memory
address
MAMR2
mask
register 2
Memory
start
MSAR3
address
register 3
Memory
address
MAMR3
mask
register 3
Address
7
6
5
4
3
2
1
0
S23
S22
S21
S20
S19
S18
S17
S16
1
1
1
1
1
1
1
1
V18
V17
V16
V15
1
1
1
1
R/W
CCH
Start address A23 to A16
V22
V21
V20
V19
R/W
CDH
1
1
1
1
CS2 area size
S23
S22
S21
0: Enable address comparsion
S20
S19
S18
S17
S16
1
1
1
1
V18
V17
V16
V15
1
1
1
1
R/W
CEH
1
1
1
1
Start address A23 to A16
V22
V21
V20
V19
R/W
CFH
1
1
1
CS3 area size
91C630-183
1
0: Enable to address comparsion
2003-07-22
TMP91C630
(5) Clock gear
Symbol
Name
Address
SYSCR0 System
clock
control
register 0
E0H
SYSCR1 System
clock
control
register 1
E1H
7
6
5
4
3
2
1
0
PRCK1
PRCK0
1
0
1
0
0
0
R/W
Always
write 1
Always
write 0
Always
write 1
Always
write 0
0
Always
write 0
0
Always
write 0
GEAR2
0
1
Prscaler clock seleciton
00: fFPH
01: Reserved
10: fc/16
11: Reserved
GEAR1
GEAR0
0
0
R/W
Always
write 0
High-frequency gear value selection
(fc)
000: fc
001: fc/2
010: fc/4
011: fc/8
100: fc/16
101: (Reserved)
110: (Reserved)
111: (Reserved)
SYSCR2 System
clock
control
register 2
E2H
EMCCR0 EMC
control
register 0
E3H
WUPTM1
WUPTM0
HALTM1
HALTM0
DRVE
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
1
0
Always
write 0
Warm-up time
00: Reserved
01: 28/input frequency
10: 214/input frequency
11: 216/input frequency
1: Drive the
pin in
STOP
mode
PROTECT
EXTIN
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
0
Protection
flag
0
Always
write 0
1
Always
write 1
0
Always
write 0
0
Always
wirte 0
0: OFF
1: ON
EMC
EMCCR1 control
register 1
0
HALT mode
00: Reserved
01: STOP mode
10: IDLE1 mode
11: IDLE2 mode
1: fc is
Always
external write 1
clock.
1
Always
write 1
Protection is turned OFF by writing 1FH.
E4H
Protection is turned ON by writing any value except 1FH.
Note: EMCCR1
If protection is on by writing except “1FH” code to EMCCR1 register, write operations to the
following SFRs are not possible.
1. CS/WAIT control
B0CS, B1CS, B2CS, B3CS, BEXCS,
MSAR0, MSAR1, MSAR2, MSAR3,
MAMR0, MAMR1, MAMR2, and MAMR3
2. Clock gear (only EMCCR1 can be written to)
SYSCR0, SYSCR1, SYSCR2 and EMCCR0
91C630-184
2003-07-22
TMP91C630
(6) 8-bit timer (1/3)
(61) TMRA01
Symbol
Name
Address
TMRA01
RUN
100H
TA0REG
TMRA0
register 0
102H
(Prohibit
RMW)
TA1REG
TMRA1
register 1
103H
(Prohibit
RMW)
TMRA01
source
CLK &
MODE
104H
TMRA01
flip-flop
control
105H
TA01RUN
TA01MOD
TA1FFCR
7
TA0RDE
R/W
0
Double
buffer
0: Disable
1: Enable
6
5
4
3
2
1
0
I2TA01 TA01PRUN TA1RUN
TA0RUN
R/W
R/W
R/W
R/W
0
0
0
0
8-bit timer run/stop control
IDLE2
0: Stop & clear
0: Stop
1: Run (Count up)
1: Operate
W
Undefined
W
Undefined
TA01M1 TA01M0
PWM01
PWM00
TA1CLK1 TA1CLK0
R/W
0
0
0
0
0
0
Operation mode
PWM cycle
Source clock for TMRA1
00: 8-bit timer
00: Reserved
00: TA0TRG
01: 16-bit timer
01: 26 1
01: IT1
10: 8-bit PPG
10: 27 1
10: IT16
11: 8-bit PWM
11: 28 1
11: IT256
TAFF1C1 TAFF1C0
R/W
1
1
00: Invert TA1FF
01: Set TA1FF
10: Clear TA1FF
11: Don’t care
91C630-185
TA0CLK1
TA0CLK0
0
0
Source clock for TMRA0
00: TA0IN pin
01: IT1
10: IT4
11: IT16
TAFF1IE
TAFF1IS
R/W
0
0
1: TA1FF 0: TMRA0
invert
1: TMRA1
enable
inversion
2003-07-22
TMP91C630
8-bit timer (2/3)
(62) TMRA23
Symbol
Name
TA23RUN TMRA23
RUN
TA2REG
TMRA2
register 0
TA3REG
TMRA3
register 1
Address
108H
7
TA2RDE
6
5
4
R/W
0
Double
buffer
0: Disable
1: Enable
R/W
0
IDLE2
0: Stop
1: Operate
W
Undefined
10BH
(Prohibit
RMW)
TA23M1
10CH
TA3FFCR TMRA23
flip-flop
control
10DH
2
1
0
TA23PRU TA3RUN
TA2RUN
N
R/W
R/W
R/W
0
0
0
8-bit timer run/stop control
0: Stop & clear
1: Run (Count up)
W
Undefined
10AH
(Prohibit
RMW)
TA23MOD TMRA23
source
CLK &
MODE
3
I2TA23
TA23M0
0
0
Operation mode
00: 8-bit timer
01: 16-bit timer
10: 8-bit PPG
11: 8-bit PWM
PWM21
PWM20
0
PWM cycle
00: Reserved
01: 26 1
10: 27 1
11: 28 1
91C630-186
0
TA3CLK1 TA3CLK0
R/W
0
0
Source clock for TMRA3
00: TA2TRG
01: IT1
10: IT16
11: IT256
TAFF3C1 TAFF3C0
R/W
1
1
00: Invert TA3FF
01: Set TA3FF
10: Clear TA1FF
11: Don’t care
TA2CLK1
TA2CLK0
0
0
Source clock for TMRA2
00: Reserved
01: IT1
10: IT4
11: IT16
TAFF3IE
TAFF3IS
R/W
0
0
1: TA3FF 0: TMRA2
invert
1: TMRA3
enable
inversion
2003-07-22
TMP91C630
8-bit timer (3/3)
(6-3) TMRA45
Symbol
Name
TA45RUN TMRA45
RUN
Address
110H
3
2
1
TA4RDE
7
6
5
4
I2TA45
TA45PRUN
TA5RUN
TA4RUN
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Double
buffer
8-bit timer run/stop control
IDLE2
0: Stop & clear
0: Stop
1: Operate 1: Run (Count up)
0: Disable
1: Enable
TA4REG
TMRA4
register 0
112H
(Prohibit
RMW)
TA5REG
TMRA5
register 1
113H
(Prohibit
RMW)
W
Undefined
W
Undefined
TA45M1
TA45MOD TMRA45
source
CLK &
MODE
114H
TA5FFCR TMRA45
flip-flop
control
115H
0
TA45M0
PWM41
PWM40
TA5CLK1
TA5CLK0
TA4CLK1
TA4CLK0
0
0
R/W
0
Operation mode
00: 8-bit timer
01: 16-bit timer
10: 8-bit PPG
11: 8-bit PWM
0
0
PWM cycle
00: Reserved
01: 26 1
10: 27 1
11: 28 1
0
0
0
Source clock for TMRA5
00: TA4TRG
01: IT1
10: IT16
11: IT256
TAFF5C1
TAFF5C0
Source clock for TMRA4
00: TA4IN pin
01: IT1
10: IT4
11: IT16
TAFF5IE
R/W
1
00: Invert TA5FF
01: SET TA5FF
10: Clear TA5FF
11: Don’t care
91C630-187
TAFF5IS
R/W
1
0
0
1: TA5FF
invert
enable
0: Timer4
1: Timer5
inversion
2003-07-22
TMP91C630
(7) 16-bit timer
(7-1) TMRB0
Symbol
Name
Address
TB0RUN
TMRB0
control
180H
TB0MOD
TMRB0
source
CLK &
MODE
182H
7
TB0RDE
6
5
R/W
0
Double
buffer
0: Disable
1: Enable
TB0CT1
TB0ET1
R/W
0
0
TB0FF1 inversion
trigger
0: TRG disable
1: TRG enable
183H
3
I2TB0
TB0FF1C1 TB0FF1C0
W*
1
1
00: Invert TB0FF1
01: Set
10: Clear
11: Don’t care
Always read as 11
2
TB0PRUN
1
0
TB0RUN
R/W
R/W
R/W
0
0
0
16-bit timer run/stop control
IDLE2
0: Stop & clear
0: Stop
1: Operate 1: Run (Count up)
TB0CP0I
W*
TB0CPM1
TB0CPM0
1
0: Soft
capture
1: Don’t
care
0
0
Capture timing
00: Disable
01: n, n (TB0IN0, TB0IN1)
10: n, p (TB0IN0)
11: n, p (TA1OUT)
TB0C1T1
TB0C0T1 TB0E1T1
R/W
0
0
TB0FF0 invert trigger
0: Trigger disable
1: Trigger enable
Capture to TB0RG1
TB0CP1
matching
TB0FFCR TMRB0
flip-flop
control
4
R/W
0
Always
write 0.
0
TB0RG0L
188H
TMRB0
register 0L (Prohibit
RMW)
W
Undefined
TB0RG0H
189H
TMRB0
register 0H (Prohibit
RMW)
W
Undefined
TB0RG1L
18AH
TMRB0
(Prohibit
register 1L
RMW)
W
Undefined
TB0RG1H
18BH
TMRB0
register 1H (Prohibit
RMW)
W
Undefined
TB0CP0L
Capture
register 0L
18CH
R
Undefined
TB0CP0H
Capture
register 0H
18DH
R
Undefined
TB0CP1L
Capture
register 1L
18EH
R
Undefined
TB0CP1H
Capture
register 1H
18FH
R
Undefined
91C630-188
TB0CLE
R/W
0
1: UC0
clear
enable
TB0E0T1
0
TB0CLK1
TB0CLK0
0
Source clock
0
00: TB0IN0 pin
01: IT1
10: IT4
11: IT16
TB0FF0C1 TB0FF0C0
W*
1
1
00: Invert TB0FF0
01: Set TB0FF0
10: Clear TB0FF0
11: Don’t care
Always read as 11
2003-07-22
TMP91C630
(8) UART/Serial channel control
(8-1) UART/SIO channel 0
Symbol
SC0BUF
Name
Serial
channel 0
buffer
Address
7
6
5
4
3
2
1
0
RB7/TB7
RB6/TB6
RB5/TB5
RB4/TB4
RB3/TB3
RB2/TB2
RB1/TB1
RB0/TB0
SCLKS
IOC
200H
R (receiving)/W (transmission)
Undefined
RB8
SC0CR
Serial
channel 0
control
EVEN
R
201H
0
Receiving
data bit 8
TB8
PE
OERR
R/W
0
Parity
0: Odd
1: Even
CTSE
PERR
FERR
R (cleared to 0 by reading)
0
0
1: Parity
Enable
0
0
1: Error
Over run
Parity
Framing
WU
SM1
SM0
0
0
RXE
R/W
0
0
0:SCLK0n 1: Input
1:SCLK0p SCLK0 pin
SC1
SC0
0
0
R/W
Serial
SC0MOD0 channel 0
mode 0
0
202H
Transfer
data bit 8
0
1: CTS
enable
0: CTS
disable
BR0ADD
0
0
1: Receive 1: Wake-up
enable
enable
0: Receive 0: Wake-up
disable
disable
BR0CK1
BR0CK0
00: TA0TRG
01: Baud rate generator
10: Internal clock fSYS
11: External clock
SCLK0
00: I/O interface
01: UART 7-bit
10: UART 8-bit
11: UART 9-bit
BR0S3
BR0S2
BR0S1
BR0S0
0
0
0
R/W
BR0CR
Baud rate
control
BR0ADD
Serial
channel 0
K setting
register
0
203H
Always
write 0
0
1:(16 K)/16
divided
enable
0
0
00: IT0
01: IT2
10: IT8
11: IT32
Set the frequency divisor N.
(0 to F)
BR0K3
Serial
SC0MOD1 channel 0
mode 1
BR0K2
BR0K1
BR0K0
0
0
R/W
204H
0
0
Set the value of “K”
(1 to F)
205H
I2S0
FDPX0
STSEN0
R/W
R/W
W
0
0
1
STS0
1: Disable
0: Enable
I/O interface
IDLE2
1: Full
0: Stop
duplex
1: Operate
0: Half
duplex
91C630-189
2003-07-22
TMP91C630
(8-2) UART/SIO Channel 1
Symbol
Name
Address
Serial
SC1BUF
channel 1
7
6
5
4
3
2
1
0
RB7/TB7
RB6/TB6
RB5/TB5
RB4/TB4
RB3/TB3
RB2/TB2
RB1/TB1
RB0/TB0
SCLKS
IOC
208H
R (receiving)/W (transmission)
buffer
Undefined
RB8
R
Serial
SC1CR
channel 1
EVEN
209H
0
Receiving
data bit 8
control
TB8
PE
OERR
R/W
0
Parity
0: Odd
1: Even
CTSE
PERR
FERR
R (cleared to 0 by reading)
0
0
0
R/W
0
0
1: Error
Parity
0: Disable
1: Enable
Over run
Parity
Framing
RXE
WU
SM1
SM0
0
0
0
0:SCLK1n 1: Input
1:SCLK1p
SCLK1
pin
SC1
SC0
0
0
R/W
Serial
SC1MOD0 channel 1
0
20AH
mode 0
0
Transmissi 1: CTS
on data bit 8 enable
BR1ADD
0
0
1: Receive 1: Wake-up 00: I/O interface
enable
enable
01: UART 7-bit
10: UART 8-bit
11: UART 9-bit
BR1CK1
BR1CK0
BR1S3
00: TA0TRG
01: Baud rate generator
10: Internal clock fSYS
11: External clock SCLK1
BR1S2
BR1S1
BR1S0
0
0
0
R/W
BR1CR
Baud rate
control
0
20BH
Always
write 0
0
0
0
1: (16 K)/16 00: IT0
divided
01: IT2
enable
Set the frequency divisor N.
0 to F
10: IT8
11: IT32
BR1ADD
Serial
channel 1
K setting
register
mode 1
BR1K2
0
0
BR1K1
BR1K0
0
0
R/W
20CH
Baud rate 0 K
1 to F
Serial
SC1MOD1 channel 1
BR1K3
20DH
I2S1
FDPX1
STSEN1
R/W
R/W
W
0
0
1
STS1
1: Disable
0: Enable
I/O interface
IDLE2
1: Full
0: Stop
duplex
1: Operate
0: Half
duplex
91C630-190
2003-07-22
TMP91C630
(9) AD converter
Symbol
Name
AD
ADMOD0 MODE
register 0
Address
7
6
EOCF
2B0H
ADBF
R
0
0
1: End
1: Busy
5
4
3
2
1
0
ITM0
REPEAT
SCAN
ADS
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Interrupt in
repeat
mode
0: Single
1: Repeat
Always
write 0
Always
write 0
0
0: Fix
1: Scan
0: Don’t care
1: Start
0: Every
conversion
1: Every
fourth
conversion
AD
ADMOD1 MODE
register 1
2B1H
VREFON
I2AD
ADTRGE
R/W
R/W
R/W
0
0
0
External
trigger
start
1: VREF On IDLE2
0: Stop
1: Operation
0: Disable
1: Enable
ADCH2
ADCH1
ADCH0
R/W
0
0
0
Input channel selection
fixed/scan
000: AN0 AN0
001: AN1 AN0 oAN1
010: AN2 AN0 o AN1 o AN2
011: AN3 AN0 o AN1 o AN2 o AN3
100: AN4 AN4
101: AN5 AN4 oAN5
110: AN6 AN4 o AN5 o AN6
111: AN7 AN4 o AN5 o AN6 o AN7
ADREG04L AD result
register
0/4 Low
ADR01
2A0H
ADR09
ADR11
ADR04
ADR03
ADR10
ADR02
ADR1RF
R
ADR18
0
ADR17
ADR16
2A3H
ADR15
ADR14
ADR13
ADR12
R
Undefined
ADR21
2A4H
ADR20
ADR2RF
R
R
Undefined
ADR29
ADR28
0
ADR27
ADR26
2A5H
ADR25
ADR24
ADR23
ADR22
ADR3RF
R
Undefined
ADR31
2A6H
ADR30
R
R
Undefined
ADREG37H AD result
register
3/7 High
ADR05
R
ADR19
ADREG37L AD result
register
3/7 Low
ADR06
Undefined
ADREG26H AD result
register
2/6 High
0
ADR07
R
2A2H
ADREG26L AD result
register
2/6 Low
ADR08
Undefined
ADREG15H AD result
register
1/5 High
R
2A1H
ADREG15L AD result
register
1/5 Low
ADR0RF
R
Undefined
ADREG04H AD result
register
0/4 High
ADR00
ADR39
ADR38
0
ADR37
ADR36
2A7H
ADR35
ADR34
ADR33
ADR32
R
Undefined
Note: 1. ADMOD0<ADS> is always read as “0”.
2. When using ADTRG with ADMOD1<ADTRGE>
“1”, do not set ADMOD1<ADCH2:0>
“011”.
3. When clear ADMOD1<I2AD> to “0”, operation is different by AD conversion mode after released
Halt mode.
91C630-191
2003-07-22
TMP91C630
Watchdog timer control
Symbol
Name
Address
WDT
WDMOD MODE
register
300H
WDCR
301H
7
6
5
4
3
2
1
WDTE
WDTP1
WDTP0
I2WDT
RESCR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
0
0
0
00: 215/fsys
01: 217/fsys
10: 219/fsys
11: 221/fsys
1: WDT
enable
0
0
Always
write 0
Always
write 0
0
1: Internaly Always
IDLE2
connects write 0
0: Stop
WDT out
1: Operate
to the
Reset pin
WDT
control
W
B1H: WDT disable
4EH: WDT clear
(10) Multi vector control
Symbol
Name
Multi
MVEC0 vector
control
Symbol
Name
Multi
MVEC1 vector
control
Note:
Address
00AEH
7
6
5
4
3
2
1
0
VEC7
VEC6
VEC5
VEC4
VEC3
VEC2
VEC1
VEC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
Vector address A15 to A8
Address
00AFH
7
6
5
4
3
2
1
0
VEC15
VEC14
VEC13
VEC12
VEC11
VEC10
VEC9
VEC8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
Vector address A23 to A16
Write MVEC1 and MVEC0 after making an interruption prohibition state.
91C630-192
2003-07-22
TMP91C630
6.
Port Section Equivalent Circuit Diagrams
x Reading the circuit diagrams
The gate symbols used are essentially the same as those used for the standard CMOS logic IC
[74HCXX] Series.
The dedicated signal is described below.
STOP: This signal becomes Active (1) when the Halt mode setting register is set to STOP mode
(i.e. when SYSCR2<HALTM1:0> 0, 1) and the CPU executes the HALT instruction.
When the drive enable bit SYSCR2<DRVE> is set to 1, however, STOP will remains at 0.
x The input protection resistances ranges from several tens of ohms to several hundreds of ohms.
Ŷ
D0 to D7, P10 to P17 (D8 to D15), P71, P74, P93 to P96
VCC
Output data
P-ch
Output enable
Stop
N-ch
I/O
Input data
Input enable
Ŷ
A0 to A15, P20 to P27 (A16 to A23), RD , WR , P60 to P63
VCC
Output data
P-ch
Stop
N-ch
Output
Ŷ
P53 to P55, P81 to P83, P85 to P87, PZ2, PZ3
VCC
Output
P-ch
Output enable
Stop
N-ch
VCC
P-ch
(Programmable pull-up)
I/O
Input data
Input enable
91C630-193
2003-07-22
TMP91C630
Ŷ
PA0 to PA7 (AN0 to AN7)
Analog input
Channel select
Input
Analog input
Input data
Input enable
Ŷ
P56 (INT0)
VCC
Output data
P-ch
Output enable
Stop
N-ch
VCC
P-ch
(Programmable pull-up)
Input data
I/O
Schmitt
Ŷ
P70 (INT1), P72 (INT2), P73 (INT3), P75 (INT4) and P90 (INT5)
VCC
Output data
P-ch
Output enable
Stop
N-ch
I/O
Input data
Schmitt
Ŷ
P80 (TXD0) and P84 (TXD1)
VCC
Output data
P-ch
VCC
Open-drain
output enable
N-ch
P-ch
(Programmable pull-up)
Stop
I/O
Input data
Input enable
Ŷ
NMI
NMI
Input
Schmitt
91C630-194
2003-07-22
TMP91C630
Ŷ
AM0 to AM1
Input data
Ŷ
Input
BOOT
VCC
P-ch
Input
BOOT
Schmitt
Ŷ
RESET
VCC
P-ch
Input
Reset
Schmitt
WDTOUT
Reset enable
Ŷ
X1 and X2
Oscillator
X2
High-frequency
P-ch
N-ch
oscillation enable
X1
Clock
Ŷ
VREFH and VREFL
VREFON
P-ch
VREFH
String
resistance
VREFL
91C630-195
2003-07-22
TMP91C630
7.
Points to Note and Restrictions
(1) Notation
a.
The notation for built-in/I/O registers is as follows register symbol <bit symbol>
e.g.) TA01RUN<TA0RUN> denotes bit TA0RUN of register TA01RUN.
b.
Read-modify-write instructions
An instruction in which the CPU reads data from memory and writes the data to the
same memory location in one instruction.
x
Example 1)
SET 3, (TA01RUN) ‚‚‚ Set bit 3 of TA01RUN.
Example 2)
INC 1, (100H) ‚‚‚ Increment the data at 100H.
Examples of read-modify-write instructions on the TLCS-900
Exchange instruction
EX
(mem), R
Arithmetic operations
ADD (mem), R/# ADC
SUB (mem), R/# SBC
INC #3, (mem) DEC
(mem), R/#
(mem), R/#
#3, (mem)
Logic operations
AND (mem), R/# OR
XOR (mem), R/#
(mem), R/#
Bit manipulation operations
STCF #3/A, (mem) RES #3, (mem)
SET #3, (mem) CHG #3, (mem)
TSET #3, (mem)
Rotate and shift operations
RLC
RL
SLA
SLL
RLD
c.
(mem)
(mem)
(mem)
(mem)
(mem)
RRC
RR
SRA
SRL
RRD
(mem)
(mem)
(mem)
(mem)
(mem)
fOSCH, fc, fFPH, fSYS and one state
The clock frequency input on pin X1 and X2 is called fOSCH. TMP91C630 have not DFM.
Therefore, fc equal fOSCH.
The clock selected by SYSCR1<SYSCK> is called fFPH. The clock frequency give by fFPH
divided by 2 is called fSYS.
One cycle of fSYS is referred to as one state.
91C630-196
2003-07-22
TMP91C630
(2) Points to note
a.
AM0 and AM1 pins
Those pins are connected to the VCC or VSS pin
Do not alter the voltage level of those pins when theTMP91C630 is processing
b.
EMU0and EMU1
Open pins.
c.
Reserved address areas
The TMP91C630 has not any reserved areas.
d.
Warm-up counter
The warm-up counter operates when STOP mode is released, even if the system is using
an external oscillator. As a result a time equivalent to the warm-up time elapses between
input of the release request and output of the system clock.
e.
Programmable pull-up resistance
The programmable pull-up resistor can be turned ON/OFF by a program when the ports
are set for use as input ports. When the ports are set for use as output ports, they cannot be
turned ON/OFF by a program.
The data registers (e.g. P8) are used to turn the pull-up/-down resistors ON/OFF.
Consequently read-modify-write instructions are prohibited.
f.
Bus releasing function
Please refer to the Note about bus release in Section 3.5, Functions of Ports. The pin state
is written when the bus is released.
g.
Watchdog timer
The watchdog timer starts operation immediately after a Reset is released. When the
watchdog timer is not to be used, disable it.
When the bus is released, neither internal memory nor internal I/O can be accessed.
However, the internal I/O continues to operate. Hence the watchdog timer continues to run.
Therefore be careful about the bus releasing time and set the detection timer of watchdog
timer.
h.
AD converter
The string resistor between the VREFH and VREFL pins can be cut by a program so as to
reduce power consumption. When STOP mode is used, disable the resistor using the
program before the HALT instruction is executed.
i.
CPU (micro DMA)
Only the LDC cr, r and LDC r, cr instructions can be used to access the control registers
in the CPU (e.g. the Transfer Source Address Register (DMASn)).
j.
Undefined SFR
The value of an undefined bit in an SFR is undefined when read.
k.
POP SR instruction
Please execute the POP SR instruction during DI condition.
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TMP91C630
8.
Diversity of TMP91C630 and TMP91C829
TMP91C630 is based on TMP91C829, the significant different points of TMP91C630 and
TMP91C829 are shown below. Because power supply is different, the electrical characteristic
specification is changed, please refer to Chapter 4. Electrical characteristics.
The significant different points of TMP91C630 and TMP91C829:
(1) Power Supply
TMP91C630 needs only 3-V power supply.
TMP91C829 needs two power supplies (3 V and 5 V)
(2) Internal RAM
TMP91C630 built in RAM size is 6 Kbytes
TMP91C829 built in RAM size is 8 Kbytes
(3) AD conversion time
TMP91C630 AD conversion time is 84 states
TMP91C829 AD conversion time is 202 states
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2003-07-22
TMP91C630
9.
Package Dimensions
P-LQFP100-1414-0.50F
Unit: mm
91C630-199
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TMP91C630
91C630-200
2003-07-22