WEDC WED3DL3216V7BC

White Electronic Designs
WED3DL3216V
16Mx32 SDRAM
FEATURES
DESCRIPTION
The WED3DL3216V is an 16Mx32 Synchronous DRAM
configured as 4x4Mx32. The SDRAM BGA is constructed
with two 16Mx16 SDRAM die mounted on a multi-layer
laminate substrate and packaged in a 119 lead, 17mm
by 23mm, BGA.
40% Space Savings vs. Monolithic Solution
Reduced System Inductance and Capacitance
3.3V Operating Supply Voltage
Fully Synchronous to Positive Clock Edge
The WED3DL3216V is available in clock speeds
of 133MHz, 125MHz, and 100MHz. The range of
operating frequencies, programmable burst lengths and
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
Clock Frequencies of 100MHz - 133MHz
Burst Operation
• Sequential or Interleave
• Burst Length = Programmable 1, 2, 4, 8
or Full Page
The package and design provides performance
enhancements via a 50% reduction in capacitance vs.
two monolithic devices. The design includes internal
ground and power planes which reduces inductance
on the ground and power pins allowing for improved
decoupling and a reduction in system noise.
• Burst Read and Write
• Multiple Burst Read and Single Write
Data Mask Control Per Byte
Auto and Self Refresh
Automatic and Controlled Precharge Commands
Suspend Mode and Power Down Mode
119 Pin BGA, 17mm x 23mm
PIN CONFIGURATION
(Top view)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
VCCQ
NC
NC
DQC
DQC
VCCQ
DQC
DQC
VCCQ
DQD
DQD
VCCQ
DQD
2
NC
NC
NC
NC
DQC
DQC
DQC
DQC
VCC
DQD
DQD
DQD
DQD
P
R
T
U
DQD
NC
NC
VCCQ
1
NC
A6
NC
NC
2
3
4
BA0
NC
A12
CAS#
BA1
VCC
NC
VSS
VSS
CE#
VSS
RAS#
DQMC NC
CKE
VSS
NC
VCC
VSS
CK
DQMD NC
VSS
WE#
VSS
A1
VSS
NC
A5
NC
3
A0
VCC
A4
NC
4
PIN DESCRIPTION
A0 – A12
BA0-1
5
A10
A11
A9
VSS
VSS
VSS
DQMB
VSS
NC
VSS
DQMA
VSS
VSS
6
A7
NC
A8
NC
DQB
DQB
DQB
DQB
VCC
DQA
DQA
DQA
DQA
7
VCCQ
NC
NC
DQB
DQB
VCCQ
DQB
DQB
VCCQ
DQA
DQA
VCCQ
DQA
A
B
C
D
E
F
G
H
J
K
L
M
N
VSS
NC
A3
NC
5
NC
A2
NC
NC
6
DQA
NC
NC
VCCQ
7
P
R
T
U
Address Bus
Bank Select Addresses
DQ
Data Bus
CK
Clock
CKE
Clock Enable
DQM
Data Input/Output Mask
RAS#
Row Address Strobe
CAS#
Column Address Strobe
CE#
Chip Enable
VCC
Power Supply pins, 3.3V
VCCQ
Data Bus Power Supply pins,3.3V
VSS
Ground pins
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED3DL3216V
16MX32 SDRAM BLOCK DIAGRAM
ADDR0-12
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
BA0
BA0
BA1
BA1
DQMA
LDQM#
DQMB
UDQM#
CE#
RAS#
CAS#
CAS#
WE#
WE#
CK
DQ8-15
DQA
DQB
CS#
RAS#
CKE
DQ0-7
CK
DQ0-31
CKE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
DQ0-7
DQC
DQ8-15
DQD
BA0
BA1
DQMC
LDQM#
DQMD
UDQM#
CS#
RAS#
CAS#
WE#
CK
CKE
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
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White Electronic Designs
WED3DL3216V
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
CK
Type
Input
Signal
Pulse
CKE
Input
Level
CE#
Input
Pulse
Input
Pulse
Input
Level
A0-12
Input
Level
DQ
Input/Output
Level
RAS#, CAS#,
WE#
BA0, BA1
Polarity
Function
Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock
Activates the CK signal when high and deactivates the CK signal when low. By deactivating the
Active High
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode
CE# disable or enable device operation by masking or enabling all inputs except CK, CKE and
Active Low
DQM.
When sampled at the positive rising edge of the clock, CAS#, RAS# and WE# define the
Active Low
operation to be executed by the SDRAM
−
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-12 defines the row address (RA0-12) when sampled
at the rising clock edge.
During a Read or Write command cycle, A0-9 defines the column address (CA0-9) when
sampled at the rising edge of the clock. In addition to the row address, A10/AP is used to
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If A10/AP is high,
−
autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10/AP is low,
autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control
which bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the
state of BA0, BA1. If A10/AP is low, than BA0, BA1 is used to define which bank to precharge.
−
Data Input/Output are multiplexed on the same pins
ABSOLUTE MAXIMUM RATINGS*
Parameter
Power Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
VCC/VCCQ
VIN
VOUT
TOPR
TTSG
PD
IOS
Min
-1.0
-1.0
-1.0
-0
-55
—
—
Max
+4.6
+4.6
+4.6
+70
+125
1.5
50
Units
V
V
V
°C
°C
W
mA
* Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED3DL3216V
RECOMMENDED DC OPERATING CONDITIONS
CAPACITANCE
(VOLTAGE REFERENCED TO: VSS = 0V, 0°C ≤ TA ≤ 70°C; COMMERCIAL OR TA = -40°C
TO +85°C; INDUSTRIAL)
(TA = 25°C, f = 1MHZ, VCC = 3.3V)
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
(IOH = -2mA)
Output Low Voltage
(IOL = 2mA)
Input Leakage Voltage
Output Leakage
Voltage
Symbol
VCC/VCCQ
VIH
VIL
VOH
Min
3.0
2.0
-0.3
2.4
Typ
3.3
3.0
—
—
Max
3.6
VCC +0.3
0.8
—
Unit
V
V
V
V
VOL
—
—
0.4
V
IIL
IOL
-5
-5
—
—
5
5
µA
µA
Parameter
Input Capacitance
Input/Output Capacitance (DQ)
Symbol
Max
Unit
CI1
4
pF
COUT
5
pF
OPERATING CURRENT CHARACTERISTICS
(VCC = 3.3V, TA = 0°C TO 70°C; COMMERCIAL OR TA = -40°C TO +85°C; INDUSTRIAL)
Parameter
Operating Current (One Bank Active)1
Operating Current (Burst Mode)
1
Precharge Standby Current
in Power Down Mode
Symbol
Conditions
-7
-8
-10
Units
ICC1
Burst Length = 1, tRC ≥ tRC(min), IOL = 0mA
300
280
260
mA
ICC4
Page Burst, 4 banks active, tCCD = 2 clocks
300
280
260
mA
ICC2P
CKE ≤ VIL(max), tCC = 15ns
2
2
2
mA
ICC2PS
CKE, CK ≤ VIL(max), tCC = ∞, Inputs Stable
2
2
2
mA
ICC1N
Precharge Standby Current
in Non-Power Down Mode
CKE = VIH, tCC = 15ns
Input Change one time every 30ns
140
140
140
mA
ICC1NS
CKE ≥ VIH (min), tCC = ∞
No Input Change
70
70
70
mA
Precharge Standby Current
in Power Down Mode
ICC3P
CKE ≤ VIL (max), tCC = 15ns
12
12
12
mA
ICC3PS
CKE ≤ VIL (max), tCC = ∞
12
12
12
mA
ICC3N
CKE = VIH, tCC = 15ns
Input Change one time every 30ns
60
60
60
mA
ICC3NS
CKE ≥ VIH (min), tCC = ∞, No Input Change
50
50
50
mA
Refresh Current
ICC5
tRC ≥ tRC (min)
600
570
550
mA
Self Refresh Current
ICC6
CKE ≤ 0.2V
6.5
6.5
6.5
mA
Active Standby Current in
Non-Power Down Mode
(One Bank Active)
2
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED3DL3216V
SDRAM AC CHARACTERISTICS
Parameter
Symbol
CL = 3
CL = 2
Clock to valid Output delay1,2
Output Data Hold Time2
Clock HIGH Pulse Width3
Clock LOW Pulse Width3
Input Setup Time3
Input Hold Time3
CK to Output Low-Z2
CK to Output High-Z
Row Active to Row Active Delay4
RAS to CAS Delay4
Row Precharge Time4
Row Active Time4
Row Cycle Time - Operation4
Row Cycle Time - Auto Refresh4,8
Last Data in to New Column Address Delay5
Last Data in to Row Precharge5
Last Data in to Burst Stop5
Column Address to Column Address Delay6
tCC
tCC
tSAC
tOH
tCH
tCL
tSS
tSH
tSLZ
tSHZ
tRRD
tRCD
tRP
tRAS
tRC
tRFC
tCDL
tRDL
tBDL
tCCD
133MHZ
Min
7
7.5
125MHZ
Max
1000
1000
5.4
3
2.5
2.5
1.5
0.8
2
Min
8
10
3
3
3
2
1
2
5.4
24
24
24
60
90
90
1
1
1
1.5
2
1
Number of Valid OutputData7
100MHZ
Max
1000
1000
6
10,000
Min
10
12
3
3
3
2
1
2
6
20
20
20
50
70
70
1
1
1
1.5
2
1
Max
1000
1000
7
10,000
7
20
20
20
50
80
80
1
1
1
1.5
2
2
10,000
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
CK
ea
NOTES:
1.
Parameters depend on programmed CAS latency.
2.
If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter.
3.
Assumed input rise and fall time = 1ns. If tRISE or tFALL are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter.
4.
The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer.
5.
Minimum delay is required to complete write.
6.
All devices allow every cycle column address changes.
7.
In case of row precharge interrupt, auto precharge and read burst stop.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED3DL3216V
COMMAND TRUTH TABLE
CKE
Function
Register Mode Register Set
Refresh Auto Refresh (CBR)
Entry Self Refresh
Precharge Single Bank Precharge
Precharge all Banks
Bank Activate
Write
Write with Auto Precharge
Read
Read with Auto Precharge
Burst Termination
No Operation
Device Deselect
Clock Suspend/Standby Mode
Data Write/Output Disable
Data Mask/Output Disable
Entry
Power Down Mode
Exit
Previous
Cycle
H
H
H
Current
Cycle
X
H
L
CE#
RAS# CAS# WE#
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
L
L
L
L
L
L
L
L
L
H
X
X
X
H
H
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
H
H
H
L
L
L
L
H
H
X
X
X
X
X
X
DQM
BA
L
H
H
X
X
X
X
X
L
L
H
L
L
L
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
BA
X
BA
BA
BA
BA
BA
X
X
X
X
X
X
X
X
A0-A10
A12, A11,
OP CODE
X
X
Notes
X
X
L
X
H
X
Row Address
L
Column
H
Column
L
Column
H
Column
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2
2
2
2
2
2
3
4
5
5
6
6
NOTES:
1.
All of the SDRAM operations are defined by states of CE#, WE#, RAS#, CAS#, and DQM at the positive rising edge of the clock.
2.
Bank Select (BA), if BA = 0 then bank A is selected, if BA = 1 then bank B is selected.
3.
During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4.
During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and
Write operations. One clock delay is required for mode entry and exit.
5.
The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the
data outputs are disabled and become high impedance after a two clock delay. DQM also provides a data mask function for Write cycles.
When it activates, the Write operation at the clock is prohibited (zero clock latency).
All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not preform any Refresh operations,
therefore the device can’t remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode
entry and exit.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED3DL3216V
CLOCK ENABLE (CKE0) TRUTH TABLE
CKE
Current State
Self Refresh
Power Down
All Banks Idle
Any State
other than
listed above
Command
Previous
Cycle
H
L
L
L
L
L
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
L
H
Current
Cycle
X
H
H
H
H
H
L
X
H
H
X
H
H
H
H
H
L
L
L
L
H
X
H
CE#
RAS#
CAS#
WE#
BA0-1
X
H
L
L
L
L
X
X
H
L
L
H
L
L
L
L
H
L
L
L
L
X
X
X
X
H
H
H
L
X
X
X
X
H
X
H
L
L
L
X
H
L
L
L
X
X
X
X
H
H
L
X
X
X
X
X
L
X
X
H
L
L
X
X
H
L
L
X
X
X
X
H
L
X
X
X
X
X
X
L
X
X
X
H
L
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A10-11 Action
X
X
X
X
X
X
X
X
X
X
INVALID
Exit Self Refresh with Device Deselect
Exit Self Refresh with No Operation
ILLEGAL
ILLEGAL
ILLEGAL
Maintain Self Refresh
INVALID
Power Down Mode exit, all banks idle
ILLEGAL
Maintain Power Down Mode
Refer to the Idle State section of the
Current State Truth Table
X
X
OP Code
CBR Refresh
Mode Register Set
Refer to the Idle State section of the
Current State Truth Table
X
X
OP Code
X
X
X
X
X
X
X
Entry Self Refresh
Mode Register Set
Power Down
Refer to the Operations in the Current
State Truth Table
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clock Suspend
Notes
1
2
1
2
2
2
3
4
3
4
4
5
NOTES:
1.
For the given Current State CKE must be low in the previous cycle.
2.
When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCKS)
must be satisfied before any command other than Exit is issued.
3.
The address inputs (A12-0) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more
information.
4.
The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state.
5.
Must be a legal command as defined in the Current State Truth Table.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED3DL3216V
CURRENT STATE TRUTH TABLE
Command
Action
Current State
Idle
Row Active
Read
Write
Read with
Auto
Precharge
Notes
CE#
RAS#
CAS#
WE#
BA0-1
L
L
L
L
L
L
L
H
L
L
H
L
X
X
L
L
H
H
BA
Row Address
L
H
L
L
BA
L
H
L
H
BA
L
H
H
L
X
A0-A12
OP Code
X
X
Description
Mode Register Set
Set the Mode Register
Auto or Self Refresh
Start Auto orSelf Refresh
Precharge
No Operation
Bank Activate
Activate the specified bank and row
Column
Write w/o Precharge
ILLEGAL
Column
Read w/o Precharge
ILLEGAL
X
Burst Termination
No Operation
2
2,3
4
2
L
H
H
H
X
X
No Operation
No Operation
H
X
X
X
X
X
Device Deselect
No Operation or Power Down
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
Precharge
6
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
2
L
H
L
L
BA
Column
Write
Start Write; Determine if Auto Precharge
L
H
L
H
BA
Column
Read
Start Read; Determine if Auto Precharge
L
H
H
L
X
X
Burst Termination
No Operation
L
H
H
H
X
X
No Operation
No Operation
H
X
X
X
X
X
Device Deselect
No Operation
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
Terminate Burst; Start the Precharge
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
L
H
L
L
BA
Column
Write
Terminate Burst; Start the Write cycle
L
H
L
H
BA
Column
Read
Terminate Burst; Start a new Read cycle
L
H
H
L
X
X
Burst Termination
Terminate the Burst
OP Code
OP Code
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
Terminate Burst; Start the Precharge
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
L
H
L
L
BA
Column
Write
Terminate Burst; Start a new Write cycle
L
H
L
H
BA
Column
Read
Terminate Burst; Start the Read cycle
L
H
H
L
X
X
Burst Termination
Terminate the Burst
OP Code
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
L
H
L
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
ILLEGAL
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
OP Code
5
7,8
4
8,9
4
8,9
4
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
8
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White Electronic Designs
WED3DL3216V
CURRENT STATE TRUTH TABLE (cont.)
Command
Action
Current State
Notes
CE#
Write with
Auto Precharge
Precharging
Row Activating
Write
Recovering
Write
ecovering with
Auto Precharge
RAS#
CAS#
WE#
BA0-1
A0-A12
OP Code
Description
L
L
L
L
L
L
L
H
X
X
Mode Register Set
Auto orSelf Refresh
ILLEGAL
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
L
H
L
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
ILLEGAL
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
No Operation; Bank(s) idle after tRP
OP Code
4
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
L
H
L
L
BA
Column
Write w/o Precharge
ILLEGAL
L
H
L
H
BA
Column
Read w/o Precharge
ILLEGAL
L
H
H
L
X
X
Burst Termination
No Operation; Bank(s) idle after tRP
L
H
H
H
X
X
No Operation
No Operation; Bank(s) idle after tRP
H
X
X
X
X
X
Device Deselect
No Operation; Bank(s) idle after tRP
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
4
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
4,10
L
H
L
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
No Operation; Row active after tRCD
OP Code
X
L
H
H
H
X
X
No Operation
No Operation; Row active after tRCD
H
X
X
X
X
X
Device Deselect
No Operation; Row active after tRCD
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
L
H
L
L
BA
Column
Write
Start Write; Determine if Auto Precharge
L
H
L
H
BA
Column
Read
Start Read; Determine if Auto Precharge
L
H
H
L
X
X
Burst Termination
No Operation; Row active after tDPL
L
H
H
H
X
X
No Operation
No Operation; Row active after tDPL
H
X
X
X
X
X
Device Deselect
No Operation; Row active after tDPL
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
L
H
L
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
No Operation; Precharge after tDPL
OP Code
OP Code
X
L
H
H
L
X
X
Burst Termination
L
H
H
H
X
X
No Operation
No Operation; Precharge after tDPL
H
X
X
X
X
X
Device Deselect
No Operation; Precharge after tDPL
4
4
4
9
4
4,9
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January, 2004
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WED3DL3216V
CURRENT STATE TRUTH TABLE (cont.)
Current
State
Refreshing
Mode
Register
Accessing
Command
Action
Notes
CE#
RAS#
CAS#
WE#
BA0-1
A0-A12
L
L
L
L
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
L
L
H
H
BA
Row Address
L
H
L
L
BA
Column
L
H
L
H
BA
Column
L
H
H
L
X
X
OP Code
Description
Mode Register Set
ILLEGAL
Bank Activate
ILLEGAL
Write
ILLEGAL
Read
ILLEGAL
Burst Termination
No Operation; Idle after tRC
L
H
H
H
X
X
No Operation
No Operation; Idle after tRC
H
X
X
X
X
X
Device Deselect
No Operation; Idle after tRC
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
L
L
H
H
BA
Row Address
L
H
L
L
BA
Column
L
H
L
H
BA
Column
L
H
H
L
X
X
L
H
H
H
X
X
No Operation
No Operation; Idle after two clock cycles
H
X
X
X
X
X
Device Deselect
No Operation; Idle after two clock cycles
OP Code
Bank Activate
ILLEGAL
Write
ILLEGAL
Read
ILLEGAL
Burst Termination
ILLEGAL
NOTES:
1.
CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is
being applied to.
2.
Both Banks must be idle otherwise it is an illegal action.
3.
If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered.
4.
The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being
referenced by the Current State then the action may be legal depending on the state of that bank.
5.
If CKE is inactive (low) than the Power Down mode is entered, otherwise there is a No Operation.
6.
The minimum and maximum Active time (tRAS) must be satisfied.
7.
The RAS# to CAS# Delay (tRCD) must occur before the command is given.
8.
Address A10 is used to determine if the Auto Precharge function is activated.
9.
The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
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WED3DL3216V
MODE REGISTER DEFINITION
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
Mode Register (Mx)
Reserved*
WB Op Mode CAS Latency
BT
Burst Length
*Program M12, M11, M10 = "0, 0, 0"
to ensure compatibility with future devices.
Burst Length
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
Burst Type
M3
0
Sequential
1
Interleaved
M6 M5 M4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
M8
M7
M6-M0
Operating Mode
0
0
Defined
Standard Operation
-
-
-
All other states reserved
M9
Write Burst Mode
0
Programmed Burst Length
1
Single Location Access
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WED3DL3216V
SINGLE BIT READ-WRITE CYCLE (SAME PAGE) @CAS LATENCY=3, BURST LENGTH=1
0
3
2
1
5
4
6
7
8
9
11
10
12
13
14
15
16
17
18
19
CLOCK
tCH
tCC
tCL
HIGH
CKE
tRCD
tRAS
CE#
tSS
tRCD
tSS
tRP
tSH
tSH
RAS#
tSS
tCCD
tSH
CAS#
tSS
tSH
tSS
ADDR
tSH
Ra
Ca
Cb
Cc
Rb
Note 2
Note 2,3
Note 2,3
Note 2,3
Note 4
Note 2
BA
BS
BS
BS
BS
BS
BS
A10/AP
Ra
Note 3
Note 3
Note 3
Note 4
Rb
tRAC
tSS
tSAC
tSH
Qa
DQ
tSLZ
tOH
Db
Qc
tSS
tSH
tSS
tSH
WE#
DQM
Row Active
Read
Write
Row Active
Read
DONT’ CARE
Precharge
NOTES:
1.
All input except CKE & DQM can be don’t care when CE is high at the CK high
going edge.
2.
Bank active & read/write are controlled by BA0~BA1.
BA0
4.
BA1
3.
Enable and disable auto precharge function are controlled by A10/AP in
read/write command.
A10/AP
Active & Read/Write
0
0
0
Bank A
0
1
Bank B
1
0
Bank C
1
1
Bank D
1
A10/AP and BA0~BA1 control bank precharge when precharge command is
asserted.
A10/AP
BA0
BA1
0
0
0
Bank A
0
0
1
Bank B
0
1
0
Bank C
0
1
1
Bank D
1
x
x
All Banks
BA0
BA1
0
0
Operation
Disable auto precharge, leave bank A active at end of burst.
0
1
Disable auto precharge, leave bank B active at end of burst.
1
0
Disable auto precharge, leave bank C active at end of burst.
1
1
Disable auto precharge, leave bank D active at end of burst.
0
0
Enable auto precharge, precharge bank A at end of burst.
0
1
Enable auto precharge, precharge bank B at end of burst.
1
0
Enable auto precharge, precharge bank C at end of burst.
1
1
Enable auto precharge, precharge bank D at end of burst.
Precharge
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WED3DL3216V
POWER UP SEQUENCE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High level is necessary
CE#
tRP
tRFC
tRFC
RAS#
CAS#
Key
ADDR
RAa
BA
RAa
A10/AP
HIGH-Z
DQ
WE#
DQM
High level is necessary
Precharge
(All Banks)
Auto Refresh
Mode Register Set
Auto Refresh
Row Active
(A-Bank)
DON’T CARE
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WED3DL3216V
READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
0
1
2
3
5
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
Note 1
tRC
CE#
tRCD
RAS#
Note 2
CAS#
ADDR
Ra
Ca0
Rb
Cb0
BA
A10/AP
Ra
Rb
tSHZ Note 4
tRAC
Note 3
Qa0
CL = 2
Qa1
Note 3
CL = 3
Qa2
Qa3
Db0
Db1
Db2
Db3
tSHZ Note 4
tRAC
DQ
tRDL
tOH
tSAC
tRDL
tOH
tSAC
Qa0
Qa1
Qa2
Db0
Qa3
Db1
Db2
Db3
WE#
Precharge
(All Banks)
DQM
Row Active
(A-Bank)
Read
(A-bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-bank)
Precharge
(A-Bank)
DON’T CARE
NOTES:
1.
Minimum row cycle times are required to complete internal DRAM operation.
2.
Row precharge can interrupt burst on any cycle. (CAS# Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the
clock.
3.
Access time from Row active command. tCC *(tRCD + CAS# latency - 1) + tSAC.
4.
Output will be Hi-Z after the end of burst (1, 2, 4, 8 & full page bit burst).
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WED3DL3216V
PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CE#
tRCD
RAS#
Note 2
CAS#
ADDR
Ra
Ca0
Rb
Cb0
Cb0
BA
A10/AP
Ra
tRDL
CL = 2
Qa0
Qa1
Qb0
Qb1
Qb2
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
DQ
Dd0
Dd1
Dd0
Dd1
tCDL
CL = 3
Dc0
Dc1
WE#
Precharge
(All Banks)
Note 3
Note 1
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
DON’T CARE
NOTES:
1.
To write data before burst read ends, DQM should be asserted three cycles prior to write command to avoid bus contention.
2.
Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked
internally.
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January, 2004
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White Electronic Designs
WED3DL3216V
PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
Note 1
CE#
RAS#
Note 2
CAS#
ADDR
RAa
CAa
CBb
RBb
CAc
CAe
CBd
BA
A10/AP
RAa
RBb
CL = 2
QAa0 QAa1
QAa2
QAa3 QBb0 QBb1 QBb2
QAa0
QAa1
QAa2
QBb3
QAc0
QAc1
QBd0 QBd1 QAe0
QBb1 QBb2
QBb3
QAc0
QAc1
QBd0 QBd1 QAe0
Read
(A-bank)
Precharge
(A-Bank)
QAe1
DQ
CL = 3
QAa3 QBb0
QAe1
WE#
Precharge
(All Banks)
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Read
(B-bank)
Read
(A-bank)
Read
(B-bank)
Read
(A-bank)
DON’T CARE
NOTES:
1.
CE# can be don’t cared when RAS#, CAS# and WE# are high at the clock high going edge.
2.
To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
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January, 2004
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WED3DL3216V
PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CE#
RAS#
Note 2
CAS#
ADDR
RAa
RBb
CAa
CBd
CAc
CBb
BA
A10/AP
RAa
RBb
tCDL
DAa0
DQ
DAa1
DAa2
DAa3
DBb0
tRDL
DBb1
DBb2 DBb3
DAc0
DAc1
DBd0
DBd1
WE#
Note 1
DQM
Precharge
(All Banks)
Row Active
(A-Bank)
Row Active
(B-Bank)
Write
(A-Bank)
Write
(B-Bank)
Write
(A-Bank)
Write
(B-Bank)
Precharge
(Both Banks)
DON’T CARE
NOTES:
1.
To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2.
To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
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White Electronic Designs
WED3DL3216V
READ & WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
CBb
RAc
14
15
16
17
18
19
QAc0
QAc1
QAc2
QAc0
QAc1
CLOCK
HIGH
CKE
CE#
RAS#
CAS#
ADDR
RAa
RBb
CAa
CAc
BA
A10/AP
RAa
RBb
RAc
tCDL
CL = 2
QAa0
QAa1
QAa2
QAa0
QAa1 QAa2
QAa3
DBb0
DBb1
DBb2
DBb3
DBb0
DBb1
DBb2
DBb3
Note 1
DQ
CL = 3
QAa3
WE#
Precharge
(All Banks)
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Write
(B-Bank)
Precharge
(A-Bank)
Row Active
(B-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
DON’T CARE
NOTE:
1.
tCDL should be met to complete write.
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WED3DL3216V
READ & WRITE CYCLE WITH AUTO PRECHARGE @ BURST LENGTH = 4
0
1
2
3
5
4
6
7
8
9
10
11
12
13
15
14
16
17
18
19
CLOCK
HIGH
CKE
CE#
RAS#
CAS#
ADDR
Ra
Rb
Ra
Rb
Ca
Cb
BA
A10/AP
CL = 2
Qa0
Qa1
Qa2
Qa3
Qa0
Qa1
Qa2
Db0
Db1
Db2
Db3
Db0
Db1
Db2
Db3
DQ
CL = 3
Qa3
WE#
DQM
Row Active
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Row Active
(B-Bank)
Auto Precharge
Start Point
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(B-Bank)
DON’T CARE
NOTE:
1.
tCDL should be controlled to meet minimum tRAS before internal precharge start. (in the case of Burst Length = 1 & 2 and BRSW mode)
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WED3DL3216V
CLOCK SUSPENSION & DQM OPERATION CYCLE @ CAS LATENCY = 2, BURST LENGTH = 4
0
1
3
2
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CE#
RAS#
CAS#
ADDR
Ra
Ca
Cc
Cb
BA
A10/AP
Ra
tSHZ
Qa0
DQ
Qa1
Qa2
tSHZ
Qa3
Qb1
Qb1
Dc2
Dc0
WE#
Note 1
DQM
Row Active
Read
Clock
Suspension
Read
Write
DQM
Read DQM
Write
Write
DQM
Clock
Suspension
DON’T CARE
NOTE:
1.
DQM is needed to prevent bus contention.
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WED3DL3216V
READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP @ BURST
LENGTH = FULL PAGE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
QAb1 QAb2
QAb3
14
18
17
19
CLOCK
HIGH
CKE
CE#
RAS#
CAS#
ADDR
RAa
CAa
CAb
BA
A10/AP
RAa
Note 2
CL = 2
QAa0 QAa1
QAa2
1
1
QAa3 QAa4
QAb0
QAb4 QAb5
DQ
2
CL = 3
QAa0 QAa1
2
QAa2 QAa3 QAa4
QAb0 QAb1 QAb2
QAb3
QAb4 QAb5
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Burst Stop
Read
(A-Bank)
Precharge
(A-Bank)
DON’T CARE
NOTES:
1.
At full page mode, burst is end at the end of burst. So auto precharge is possible.
2.
About the valid DQs after burst stop, it is same as the case of RAS# interrupt. Both cases are illustrated in above timing diagram. See the label 1, 2. But at burst write, Burst
stop and RAS# interrupt should be compared carefully. Refer to the timing diagram of “Full page write burst stop cycle.”
3.
Burst stop is valid at every burst length.
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White Electronic Designs
WED3DL3216V
WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP CYCLE @ BURST
LENGTH = FULL PAGE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CE#
RAS#
CAS#
ADDR
RAa
CAa
CAb
BA
A10/AP
RAa
tRDL
tBDL
Note 2
DAa0 DAa1
DQ
DAa2 DAa3
DAa4
DAb0
DAb1
DAb2
DAb3
DAb4
DAb5
WE#
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Burst Stop
Write
(A-Bank)
Precharge
(A-Bank)
DON’T CARE
NOTES:
1.
At full page mode, burst is end at the end of burst. So auto precharge is possible.
2.
Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by
precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
3.
Burst stop is valid at every burst length.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
22
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED3DL3216V
BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH = 2
@ BURST LENGTH = FULL PAGE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
QAd0
QAd1
19
CLOCK
Note 1
HIGH
CKE
CE#
RAS#
Note 2
CAS#
ADDR
RAa
CAa
RBb
CAb
RAc
CBc
CAd
BA
A10/AP
RAa
CL = 2
RBb
DAa0
RAc
QAb0
QAb1
DBc0
DQ
CL = 3
DAa0
QAb0
QAb1
QAd0
DBc0
QAd1
WE#
Note 1
Note 3
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
Row Active
(B-Bank)
Read with
Auto Precharge
(A-Bank)
Write with
Auto Precharge
(A-Bank)
Precharge
(Both Banks)
DON’T CARE
NOTES:
1.
BRSW mode is enabled by setting As “High” at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length.
2.
When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the
case of BRSW write command, the next cycle starts the precharge.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
23
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED3DL3216V
ACTIVE/PRECHARGE POWER DOWN MODE @ CAS LATENCY = 2, BURST LENGTH = 4
0
2
1
3
4
5
6
7
8
9
11
10
12
13
14
15
16
17
18
19
CLOCK
Note 2
tSS
tSS
CKE
tSS
Note 1
Note 3
CE#
RAS#
CAS#
Ra
ADDR
Ca
BA
A10/AP
Ra
tSHZ
DQ
Qa0
Qa2
Qa1
WE#
DQM
Note 3
Note 1
Precharge
Power-Down
Entry
Row Active
Precharge
Power-Down
Exit
Read
Active
Power-Down
Entry
Active
Power-Down
Exit
Precharge
DON’T CARE
NOTES:
1.
Both banks should be in idle state prior to entering precharge power down mode.
2.
CKE should be set high at least 1 CK + tSS prior to Row active command.
3.
Cannot violate minimum refresh specification (64ms).
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
24
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED3DL3216V
SELF REFRESH ENTRY & EXIT CYCLE
0
3
2
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
tSS
CKE
Note 2
tRFC min
Note 3
Note 1
Note 6
Note 4
Note 5
CE#
RAS#
Note 7
CAS#
ADDR
BA
A10/AP
DQ
HI-Z
HI-Z
WE#
DQM
Self Refresh Exit
Self Refresh Entry
Auto Refresh
DON’T CARE
NOTES:
TO ENTER SELF REFRESH MODE
1.
CE#, RAS# & CAS# with CKE should be low at the same clock cycle.
2.
After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3.
The device remains in self refresh mode as long as CKE stays “Low.” Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4.
System clock restart and be stable before returning CKE high.
5.
CE# starts from high.
6.
Minimum tRFC is required after CKE going high to complete self refresh exit.
7.
4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
25
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
MODE REGISTER SET CYCLE
0
3
2
1
4
5
6
WED3DL3216V
AUTO REFRESH CYCLE
0
1
2
3
4
6
5
7
8
9
10
CLOCK
HIGH
CKE
HIGH
CE#
Note 2
tRFC
RAS#
Note 1
CAS#
Note 3
Ra
Key
ADDR
DQ
HI-Z
HI-Z
WE#
DQM
MRS
New
Command
Auto Refresh
New Command
DON’T CARE
NOTES:
Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
1.
CE#, RAS#, CAS#, & WE# activation at the same clock cycle with address key will set internal mode register.
2.
Minimum 2 clock cycles should be met before new RAS# activation.
3.
Please refer to Mode Register Set table.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
26
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED3DL3216V
PACKAGE DESCRIPTION 119 PIN BGA
JEDEC MO-163
2.79 (0.110)
MAX
7.62 (0.300)
TYP
17.00 (0.669) TYP
R 1.52 (0.060)
MAX (4x)
A
B
A1
Corner
C
D
E
F
1.27 (0.050)
TYP
G
20.32 (0.800)
TYP
H
23.00 (0.905)
TYP
J
K
L
M
N
P
R
T
U
0.711 (0.028)
MAX
1.27 (0.050) TYP
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
Part Number
Clock Frequency
Package
WED3DL3216V7BC
133MHz
119 BGA
WED3DL3216V8BC
125MHz
119 BGA
WED3DL3216V10BC
WED3DL3216V7BI
100MHz
119 BGA
133MHz, Industrial
119 BGA
WED3DL3216V8BI
125MHz, Industrial
119 BGA
WED3DL3216V10BI
100MHz, Industrial
119 BGA
WED3DL3216V7ES
133MHz, Engineering Samples
119 BGA
WED3DL3216V10ES
100 MHz, Engineering Samples
119 BGA
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
27
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com