WEDC WED416S16030C7SI

White Electronic Designs
WED416S16030A
4M x 16 Bits x 4 Banks Synchronous DRAM
FEATURES
DESCRIPTION
The WED416S16030A is 268,435,456 bits of synchronous
high data rate DRAM organized as 4 x 4,196,304 words x
16 bits. Synchronous design allows precise cycle control
with the use of system clock. I/O transactions are possible
on every clock cycle. Range of operating frequencies,
programmable burst lengths and programmable latencies
allow the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
Single 3.3V power supply
Fully Synchronous to positive Clock Edge
Clock Frequency = 133, 125, and 100MHZ
SDRAM CAS Latency = 2
Burst Operation
• Sequential or Interleave
• Burst length = programmable 1,2,4,8 or full page
Available in a 54 pin TSOP type II package the
WED416S16030A is tested over the industrial temp range
(-40°C to +85°C) providing a solution for rugged main
memory applications.
• Burst Read and Write
• Multiple Burst Read and Single Write
DATA Mask Control per byte
Auto Refresh (CBR) and Self Refresh
• 8192 refresh cycles across 64ms
*This product is subject to change without notice.
Automatic and Controlled Precharge Commands
Suspend Mode and Power Down Mode
Industrial Temperature Range
PIN CONFIGURATION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Front
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
VCC
LDQM
WE#
CAS#
RAS#
Pin
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Front
CE#
BA0
BA1
A10/AP
A0
A1
A2
A3
VCC
VSS
A4
A5
A6
A7
A8
A9
A11
A12
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
PIN DESCRIPTION
Front
CKE
CK
UDQM
NC/RFU
VSS
DQ8
VCCQ
DQ9
DQ10
VSSQ
DQ11
DQ12
VCCQ
DQ13
DQ14
VSSQ
DQ15
VSS
A0-12
BA0, BA1
CE#
WE#
CK
CKE
DQ0-15
L(U)DQM
RAS#
CAS#
VDD
VDDQ
VSS
VSSQ
NC
Address Inputs
Bank Select Addresses
Chip Select
Write Enable
Clock Input
Clock Enable
Data Input/Output
Data Input/Output Mask
Row Address Strobe
Column Address Strobe
Power (3.3V)
Data Output Power
Ground
Data Output Ground
No Connection
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED416S16030A
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
CK
Type
Input
Signal
Pulse
CKE
Input
Level
CE#
Input
Pulse
Input
Pulse
Input
Level
A0-12,
A10/AP
Input
Level
DQ0-15
Input/Output
Level
L(U)DQM
Input
Pulse
VCC, VSS
VCCQ, VSSQ
Supply
Supply
RAS#, CAS#
WE#
BA0,BA1
Polarity
Function
Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
Activates the CK signal when high and deactivates the CK signal when low. By deactivating the
Active High
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
CE# disable or enable device operation by masking or enabling all inputs except CK, CKE and
Active Low
DQM.
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the operation
Active Low
to be executed by the SDRAM.
—
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-12 defines the row address (RA0-12) when sampled at
the rising clock edge.
During a Read or Write command cycle, A0-8 defines the column address (CA0-8) when sampled
at the rising clock edge. In addition to the row address, A10/AP is used to invoke Autoprecharge
operation at the end of the Burst Read or Write cycle. If A10/AP is high, autoprecharge is selected
—
and BA0, BA1 defines the bank to be precharged . If A10/AP is low, autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control which
bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the state of BA0,
BA1. If A10/AP is low, then BA0, BA1 is used to define which bank to precharge.
—
Data Input/Output are multiplexed on the same pins
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high.
Mask
In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output
Active High enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input
data to be written if it is low but blocks the Write operation if DQM is high.
Power and ground for the input buffers and the core logic.
Isolated power and ground for the output buffers to improve noise immunity.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
RECOMMENDED DC OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Power Supply Voltage
VDD
Input Voltage
VIN
Output Voltage
VOUT
Operating Temperature
tOPR
Storage Temperature
tSTG
Power Dissipation
PD
Short Circuit Output Current
IOS
Min
-1.0
-1.0
-1.0
-40
-55
WED416S16030A
(Voltage Referenced to: VSS = 0V, 40°C ≤ Ta ≤ 85°C)
Max Units
+4.6
V
+4.6
V
+4.6
V
+85
°C
+125 °C
1.0
W
50
mA
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
3.0
3.3
3.6
V
Notes
Input High Voltage
VIH
2.0
3.0
VCC +0.3
V
Input Low Voltage
VIL
-0.3
—
0.8
V
Output High Voltage
VOH
2.4
—
—
V
(IOH = -4mA)
Output Low Voltage
VOL
—
—
0.4
V
(IOL = 4mA)
Input Leakage Voltage
IIL
-5
—
5
µA
Output Leakage Voltage
IOL
-5
—
5
µA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
(TA = 25°C, f = 1MHZ, VCC = 3.3V TO 3.6V)
Parameter
Symbol
Max
Unit
Input Capacitance (A0-12, BA0-1)
CI1
4
pF
Input Capacitance (CK, CKE, RAS#,
CAS#, WE#, CE#, L(U)DQM )
CI2
4
pF
Input/Output Capacitance (DQ0-15)
COUT
6.5
pF
OPERATING CURRENT CHARACTERISTICS
(VCC = 3.3V, -40°C ≤ Ta ≤ +85°C)
Parameter/Condition
Symbol
All Speeds
Units
Operating Current Active Mode; Burst = 2; READ or WRITE tRC = tRC(MIN)
ICC1
135
mA
Standby Current Power-Down Mode; All banks idle; CKE = LOW
Standby Current: Active Mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD met;
No accesses in progress
ICC2
2
mA
ICC3
40
mA
Operating Current: Burst Mode; Page burst: READ or WRITE; All banks active
ICC4
135
mA
ICC5
ICC6
ICC7
ICC7
285
3.5
2.5
1.5
mA
mA
mA
mA
Auto Refresh Current
CS# = HIGH: CKE = HIGH
Self Refresh Current: CKE ≤ 0.2V
tRFC = tRFC(MIN)
tRFC = 7.81 µs
Standard
Low Power (L)
Notes
3, 18, 19,
32
32
3, 12, 19,
32
3, 18, 19,
32
3, 12, 18,
19, 32, 33
4
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED416S16030A
AC CHARACTERISTICS
OPERATING AC PARAMETERS
(Vcc = 3.3V, -40°C ≤ Ta ≤ +85°C)
Parameter
Clock Cycle Time
Symbol
CAS latency = 3
CAS latency = 2
Clock to Valid Output Delay
Output Data Hold Time
Clock High Pulse Width
Clock Low Pulse Width
Input Setup Time
Input Hold Time
Clock to Output in Low-Z
Clock to Output in High-Z
Row Active to Row Active Delay
RAS# to CAS# Delay
Row Precharge Time
Row Active Time
Row Cycle Time - Operation
Last Data In to New Column Address Delay
Last Data In to Row Precharge
Last Data In to Burst Stop
Column Address to Column Address Delay
CAS latency = 3
Number of Valid Output Data
CAS latency = 2
Data Setup Time
Data Hold Time
tCK
tAC
tOH
tCH
tCL
tCMS
tCMH
tLZ
tHZ
tRRD
tRCD
tRP
tRAS
tRC
tCDL
tRDL
tBDL
tCCD
tDS
tDH
7
7.5
7.5
5.4
3
2.5
2.5
1.5
0.8
1
5.4
15
20
20
45
65
1
2
1
1
2
1
1.5
0.8
75
7.5
8
6
3
2.5
2.5
1.5
0.8
1
6
15
20
20
45
65
1
2
1
1
2
1
1.5
0.8
8
8
10
6
3
3
3
2
1
1
6
20
20
20
50
70
1
2
1
1
2
1
2
1
10
10
1
7
3
3
3
2
1
1
7
20
20
20
50
70
1
2
1
1
2
1
2
1
Unit
Notes
ns
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
CK
1,2
2
3
3
3
3
2
ea
7
4
4
4
4
4
5
5
5
6
ns
ns
NOTES:
1.
Parameters depend on programmed CAS latency.
2.
If clock rise time is longer than 1ns, (tRISE 2-0.5)ns should be added to the parameter.
3.
Assumed input rise and fall time = 1ns. If tRISE & tFALL are longer than 1ns, [(tRISE + tFALL)/2]-1ns should be added to the parameter.
4.
The minimum number of clock cycles required is determined by dividing the minimum time required by the clock cycle time and then
rounding up to the next higher integer.
5.
Minimum delay is required to complete write.
6.
All devices allow every cycle column address changes.
7.
In case of row precharge interrupt, auto precharge and read burst stop.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED416S16030A
COMMAND TRUTH TABLE
CKE
Command
Previous
Cycle
Current
Cycle
CE#
RAS#
CAS#
WE#
DQM
X
H
L
L
L
L
X
L
L
L
H
X
Register
Mode Register Set
H
Refresh
Auto(CBR)
Entry Self
H
Precharge
Single Bank
All Banks
H
X
L
L
H
L
X
H
X
L
L
H
H
H
X
L
H
L
H
X
L
H
H
H
H
X
X
X
L
L
H
X
X
H
X
Bank Activate
Write
Read
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Burst Stop
No Operation
Device Select
Clock Suspend/Standby Mode
L
Write/Output Enable
Data
Mask/Output Disable
Entry
Power Down Mode
Exit
BA0,1
A10/AP
A0-9,
A11-12
Notes
OP CODE
X
X
X
X
BA
X
BA
L
X
BA
L
H
X
BA
L
X
H
X
Row Address
L
Column
Address
H
L
Column
Address
H
H
H
X
H
H
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
4
X
X
X
X
X
L
H
X
X
X
5
L
H
H
X
X
X
X
X
X
X
6
2
2
2
2
3
(X = Don't Care, H = Logic High, L = Logic Low)
NOTES:
1. All of the SDRAM operations are defined by states of CE#, WE#, RAS#, CAS#, and DQM at the positive rising edge of the clock.
2. Bank Select (BA), if BA0, BA1 = 0, 0 then bank A is selected, if BA0, BA1 = 1, 0 then bank B, if BA0, BA1 = 0, 1 then bank C, if BA0, BA1 = 1, 1 then bank D is selected, respectively.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS# latency.
4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is
required for mode entry and exit.
5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high
impedance after a two clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibted (zero clock latency).
6. All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not perform any Refresh operations, therefore the device cannot remain in this
mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED416S16030A
CLOCK ENABLE (CKE0) TRUTH TABLE
CKE
Current State
Self Refresh
Power Down
All Banks Idle
Any State other
than listed
above
Command
Previous
Cycle
Current
Cycle
CE#
RAS#
CAS#
WE#
BA0,1
A0-9, A11-12
H
L
L
L
L
L
L
H
L
L
L
H
H
H
H
H
H
H
H
H
H
L
X
H
H
H
H
H
L
X
H
H
L
H
H
H
H
H
L
L
L
L
L
X
X
H
L
L
L
L
X
X
H
L
X
H
L
L
L
L
H
L
L
L
L
X
X
X
H
H
H
L
X
X
X
X
X
X
H
L
L
L
X
H
L
L
L
X
X
X
H
H
L
X
X
X
X
X
X
X
X
H
L
L
X
X
H
L
L
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
H
L
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
X
X
X
H
L
L
L
H
L
X
X
X
X
X
X
X
X
X
Action
Notes
INVALID
Exit Self Refresh with Device Deselect
Exit Self Refresh with No Operation
ILLEGAL
ILLEGAL
ILLEGAL
Maintain Self Refresh
INVALID
Power Down Mode exit, all banks idle
ILLEGAL
Maintain Power Down Mode
1
Refer to the Idle State section of the
Current State Truth Table
X
X
OP Code
CBR Refresh
Mode Register Set
Refer to the Idle State section of the
Current State Truth Table
X
X
X
OP Code
X
X
X
X
X
X
X
X
X
X
X
X
X
Entry Self Refresh
Mode Register Set
Power Down
Refer to the Operations in the Current
State Truth Table
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clock Suspend
2
1
2
3
4
3
4
4
5
NOTES:
1. For the given Current State CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCKS) must be satisfied before any command
other than Exit is issued.
3. The address inputs (A12-A0) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information.
4. The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state.
Must be a legal command as defined in the Current State Truth Table.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
Rev. 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED416S16030A
CURRENT STATE TRUTH TABLE
Command
Current State
Idle
Row Active
Read
Write
Read with
Auto Precharge
WE#
BA0,1
A11-12
A10/AP-A0
Notes
RAS#
CAS#
L
L
L
L
L
L
L
H
L
L
H
L
X
X
Precharge
No Operation
L
L
H
H
BA
Row Address
Bank Activate
Activate the specified bank and row
L
H
L
L
BA
Column
Write w/o Precharge
ILLEGAL
L
H
L
H
BA
Column
Read w/o Precharge
ILLEGAL
L
H
H
L
X
X
Burst Termination
No Operation
L
H
H
H
X
X
No Operation
No Operation
H
X
X
X
X
X
Device Deselect
No Operation or Power Down
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
Precharge
6
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
4
OP Code
X
X
OP Code
Description
Action
CE#
Mode Register Set
Set the Mode Register
2
Auto orSelf Refresh
Start Auto orSelf Refresh
2,3
L
H
L
L
BA
Column
Write
Start Write; Determine if Auto Precharge
L
H
L
H
BA
Column
Read
Start Read; Determine if Auto Precharge
L
H
H
L
X
X
Burst Termination
No Operation
L
H
H
H
X
X
No Operation
No Operation
H
X
X
X
X
X
Device Deselect
No Operation
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
Terminate Burst; Start the Precharge
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
L
H
L
L
BA
Column
Write
Terminate Burst; Start the Write cycle
L
H
L
H
BA
Column
Read
Terminate Burst; Start a new Read cycle
L
H
H
L
X
X
Burst Termination
Terminate the Burst
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
Terminate Burst; Start the Precharge
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
L
H
L
L
BA
Column
Write
Terminate Burst; Start a new Write cycle
L
H
L
H
BA
Column
Read
Terminate Burst; Start the Read cycle
L
H
H
L
X
X
Burst Termination
Terminate the Burst
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
L
H
L
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
ILLEGAL
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
OP Code
OP Code
OP Code
4
5
7,8
4
8,9
4
8,9
4
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
Rev. 1
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED416S16030A
CURRENT STATE TRUTH TABLE (CONT.)
Command
Current State
Write with
Auto Precharge
Precharging
Row Activating
Write Recovering
Write Recovering
with Auto
Precharge
WE#
BA0,1
A11-12,
A10/AP-A0
RAS#
CAS#
L
L
L
L
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
L
H
L
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
ILLEGAL
OP Code
Description
Action
CE#
Mode Register Set
Notes
ILLEGAL
4
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
No Operation; Bank(s) idle after tRP
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
L
H
L
L
BA
Column
Write w/o Precharge
ILLEGAL
L
H
L
H
BA
Column
Read w/o Precharge
ILLEGAL
L
H
H
L
X
X
Burst Termination
No Operation; Bank(s) idle after tRP
L
H
H
H
X
X
No Operation
No Operation; Bank(s) idle after tRP
H
X
X
X
X
X
Device Deselect
No Operation; Bank(s) idle after tRP
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
4
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
4,10
L
H
L
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
No Operation; Row active after tRCD
L
H
H
H
X
X
No Operation
No Operation; Row active after tRCD
H
X
X
X
X
X
Device Deselect
No Operation; Row active after tRCD
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
L
H
L
L
BA
Column
Write
Start Write; Determine if Auto Precharge
L
H
L
H
BA
Column
Read
Start Read; Determine if Auto Precharge
L
H
H
L
X
X
Burst Termination
No Operation; Row active after tDPL
L
H
H
H
X
X
No Operation
No Operation; Row active after tDPL
H
X
X
X
X
X
Device Deselect
No Operation; Row active after tDPL
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto orSelf Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
L
H
L
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
No Operation; Precharge after tDPL
L
H
H
H
X
X
No Operation
No Operation; Precharge after tDPL
H
X
X
X
X
X
Device Deselect
No Operation; Precharge after tDPL
OP Code
OP Code
OP Code
OP Code
4
4
4
9
4
4,9
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April 2006
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WED416S16030A
CURRENT STATE TRUTH TABLE (CONT.)
Command
Current State
Refreshing
Mode
Register
Accessing
CE#
RAS#
CAS#
WE#
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
H
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
L
H
L
H
L
H
L
H
X
BA0,1
X
X
BA
BA
BA
X
X
X
X
X
BA
BA
BA
X
X
X
A11-12,
A10/AP-A0
OP Code
X
X
Row Address
Column
Column
X
X
X
OP Code
X
X
Row Address
Column
Column
X
X
X
Description
Mode Register Set
Auto orSelf Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto orSelf Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Device Deselect
Action
Notes
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Idle after tRC
No Operation; Idle after tRC
No Operation; Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Idle after two clock cycles
No Operation; Idle after two clock cycles
NOTES:
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being applied to.
2. Both Banks must be idle otherwise it is an illegal action.
3. If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered.
4. The Current State refers only to one of the banks, if BA0, BA1 selects this bank then the action is illegal. If BA0, BA1 selects the bank not being referenced by the Current State then
the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered, otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS# to CAS# Delay (tRCD) must occur before the command is given.
8. Address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
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WED416S16030A
MODE REGISTER DEFINITION
A12 A11 A10 A9
A8
A7
A6
A5
A3
A4
A2
A1 A0
Address Bus
Mode Register (Mx)
Reserved*
WB Op Mode
CAS Latency
BT
Burst Length
*Should program
M12, M11, M10 = "0, 0, 0"
to ensure compatibility
with future devices.
Burst Length
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
Burst Type
M3
0
Sequential
1
Interleaved
M6 M5 M4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
M8
M7
M6-M0
Operating Mode
0
0
Defined
Standard Operation
-
-
-
M9
Write Burst Mode
0
Programmed Burst Length
1
Single Location Access
All other states reserved
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
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WED416S16030A
SINGLE BIT READ-WRITE CYCLE (SAME PAGE) @ CAS LATENCY = 3, BURST LENGTH = 1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
t CH
t CC
t CL
HIGH
CKE
t RCD
t RAS
CE#
t SS
t RCD
t SS
t SH
t RP
t SH
RAS#
t SS
t CCD
t SH
CAS#
t SS
ADDR
t SS
t SH
t SH
Ra
Ca
Cb
Rb
Cc
Note 2
Note 2, 3
Note 2, 3
BA
BS
BS
BS
BS
BS
BS
A10/AP
Ra
Note 3
Note 3
Note 3
Note 4
Rb
t RAC
t SS
t SAC
Qa
DQ
t SLZ
Note 2, 3 Note 4
t SH
Db
t OH
Note 2
Qc
t SS
t SH
t SS
t SH
WE#
DQM
Row Active
Read
Write
Read
Row Active
DON'T CARE
Precharge
NOTES:
1. All input except CKE & DQM can be don't
care when CE# is high at the CK high
going edge.
2. Bank active & read/write are controlled by
BA0~BA1.
4. A10/AP and BA0~BA1 control bank
precharge when precharge
command is asserted.
BA0
BA1
Active & Read/Write
0
0
Bank A
0
1
Bank B
1
0
Bank C
1
1
Bank D
A10/AP
BA0
BA1
Precharge
0
0
0
Bank A
0
0
1
Bank B
0
1
0
Bank C
0
1
1
Bank D
1
x
x
All Banks
3. Enable and disable auto precharge function are controlled by A10/AP in read/write
command.
A10/AP
0
1
BA0
BA1
0
0
Distribute auto precharge, leave bank A active at end of burst.
Operation
0
1
Disable auto precharge, leave bank B active at end of burst.
1
0
Disable auto precharge, leave bank C active at end of burst.
1
1
Disable auto precharge, leave bank D active at end of burst.
0
0
Enable auto precharge, precharge bank A at end of burst.
0
1
Enable auto precharge, precharge bank B at end of burst.
1
0
Enable auto precharge, precharge bank C at end of burst.
1
1
Enable auto precharge, precharge bank D at end of burst.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
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WED416S16030A
POWER UP SEQUENCE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High level is necessary
CE#
t RFC
t RP
t RFC
RAS#
CAS#
Key
ADDR
RAa
BA
RAa
A10/AP
HIGH-Z
DQ
WE#
DQM
High level is necessary
Precharge
(All Banks)
Auto Refresh
Mode Register Set
Auto Refresh
Row Active
(A-Bank)
DON'T CARE
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April 2006
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WED416S16030A
READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
Note 1
t RC
CE#
t RCD
RAS#
Note 2
CAS#
ADDR
Ra
Ca0
Rb
Cb0
BA
A10/AP
Ra
Rb
t SHZ
t RAC
Note 3
Qa0
CL = 2
Qa1
t RAC
DQ
Note 3
Qa2
t RDL
Qa3
Db0
t SHZ
t OH
t SAC
Qa0
CL = 3
Note 4
t OH
t SAC
Qa1
Qa2
Db1
Db2
Note 4
Db3
t RDL
Qa3
Db0
Db1
Db2
Db3
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
DON'T CARE
NOTES:
1. Minimum row cycle times are required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock.
3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC.
4. Output will be Hi-Z after the end of burst (1, 2, 4, 8 & full page bit burst).
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
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WED416S16030A
PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CE#
t RCD
RAS#
Note 2
CAS#
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
BA
A10/AP
Ra
t RDL
Qa0
CL = 2
Qa1
Qb0
Qb1
Qb2
Dc0
DQ
Dc1
Dd0
Dd1
t CDL
Qa0
CL = 3
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
WE#
Note 1
Note 3
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
DON'T CARE
NOTES:
1. To write data before burst read ends, DQM should be asserted three cycles prior to write command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row prechage cycle will be masked internally.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
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White Electronic Designs
WED416S16030A
PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
Note 1
CE#
RAS#
Note 2
CAS#
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
CAe
BA
A10/AP
RAa
RBb
QAa0
CL = 2
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2 QBb3
QAc0
QAc1
QBd0
QBd1 QAe0
QAe1
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb3
QAc0
QAc1
QBd0 QBd1
QAe0
DQ
CL = 3
QBb2
QAe1
WE#
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Read
(B-Bank)
Read
(A-Bank)
Read
(B-Bank)
Read
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
DON'T CARE
NOTES:
1. CE# can be don't cared when RAS#, CAS#, and WE# are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
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April 2006
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White Electronic Designs
WED416S16030A
PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CE#
RAS#
Note 2
CAS#
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
BA
A10/AP
RAa
RBb
t CDL
DAa0
DQ
DAa1
DAa2
DAa3
DBb0
t RDL
DBb1
DBb2
DBb3
DAc0
DAc1
DBd0
DBd1
WE#
Note 1
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Write
(B-Bank)
Write
(A-Bank)
Write
(A-Bank)
Write
(B-Bank)
Precharge
(Both Banks)
DON'T CARE
NOTES:
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
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April 2006
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White Electronic Designs
WED416S16030A
READ & WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
QAc0
QAc1
QAc2
QAc0
QAc1
CLOCK
HIGH
CKE
CE#
RAS#
CAS#
ADDR
RAa
RBb
CAa
CBb
RAc
CAc
BA
A10/AP
RAa
RBb
RAc
t CDL
QAa0
CL = 2
QAa1
QAa2
QAa3
QAa0
QAa1
QAa2
DBb0
DBb1
DBb2
DBb3
DBb0
DBb1
DBb2
DBb3
Note 1
DQ
CL = 3
QAa3
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Write
(B-Bank)
Row Active
(B-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
DON'T CARE
NOTES:
1. tCDL should be met to complete write.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
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White Electronic Designs
WED416S16030A
READ & WRITE CYCLE WITH AUTO PRECHARGE @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CE#
RAS#
CAS#
ADDR
Ra
Rb
Ra
Rb
Ca
Cb
BA
A10/AP
Qa0
CL = 2
Qa1
Qa2
Qa3
Qa0
Qa1
Qa2
Db0
Db1
Db2
Db3
Db0
Db1
Db2
Db3
DQ
CL = 3
Qa3
WE#
DQM
Row Active
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Row Active
(B-Bank)
Auto Precharge
Start Point
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(B-Bank)
DON'T CARE
NOTES:
1. tCDL should be controlled to meet minimum tRAS before internal precharge start. (In the case of Burst Length=1 & 2 and BRSW mode)
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April 2006
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White Electronic Designs
WED416S16030A
CLOCK SUSPENSION & DQM OPERATION CYCLE @ CAS LATENCY = 2, BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CE#
RAS#
CAS#
ADDR
Ra
Ca
Cb
Cc
BA
A10/AP
Ra
t SHZ
Qa0
DQ
Qa1
Qa2
t SHZ
Qa3
Qb1
Qb1
Dc0
Dc2
WE#
Note 1
DQM
Row Active
Read
Clock
Suspension
Read
Write
DQM
Read DQM
Write
Write
DQM
Clock
Suspension
DON'T CARE
NOTES:
1. DQM is needed to prevent bus contention.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
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White Electronic Designs
WED416S16030A
READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP @ BURST
LENGTH=FULL PAGE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
QAb0
QAb1
QAb2
QAb3
QAb4
19
CLOCK
HIGH
CKE
CE#
RAS#
CAS#
ADDR
RAa
CAa
CAb
BA
A10/AP
RAa
Note 2
QAa0
CL = 2
1
QAa1
QAa2
QAa3
QAa4
QAa0
QAa1
QAa2
QAa3
1
DQ
2
CL = 3
2
QAa4
QAb5
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Burst Stop
Read
(A-Bank)
Precharge
(A-Bank)
DON'T CARE
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. About the valid DQs after burst stop, it is same as the case of RAS# interrupt. Both cases are illustrated in above timing diagram. See the label 1, 2. But at burst write, Burst stop and
RAS# interrupt should be compared carefully. Refer to the timing diagram of "Full page write burst stop cycle."
3. Burst stop is valid at every burst length.
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April 2006
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WED416S16030A
WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP CYCLE @ BURST
LENGTH=FULL PAGE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CE#
RAS#
CAS#
ADDR
RAa
CAa
CAb
BA
A10/AP
RAa
t BDL
t RDL
Note 2
DAa0
DQ
DAa1
DAa2
DAa3
DAa4
DAb0
DAb1
DAb2
DAb3
DAb4
DAb5
WE#
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Burst Stop
Write
(A-Bank)
Precharge
(A-Bank)
DON'T CARE
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. Data-in at the cycle of interrupted by precharge cannnot be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge
command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after
Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
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April 2006
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WED416S16030A
BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH = 2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
QAd0
QAd1
19
CLOCK
Note 1
HIGH
CKE
CE#
RAS#
Note 2
CAS#
ADDR
RAa
CAa
RBb
CAb
RAc
CBc
CAd
BA
A10/AP
RAa
RBb
DAa0
CL = 2
RAc
QAb0
QAb1
DBc0
DQ
DAa0
CL = 3
QAb0
QAb1
DBc0
QAd0
QAd1
WE#
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Write
(A-Bank)
Row Active
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Read
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Precharge
(Both Banks)
DON'T CARE
NOTES:
1. BRSW mode is enabled by setting A9 "High" at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of
BRSW write command, the next cycle starts the precharge.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
Rev. 1
22
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED416S16030A
ACTIVE/PRECHARGE POWER DOWN MODE @ CAS LATENCY = 2, BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
Note 2
t SS
t SS
CKE
t SS
Note 1
Note 3
CE#
RAS#
CAS#
Ra
ADDR
Ca
BA
Ra
A10/AP
t SHZ
Qa0
DQ
Qa1
Qa2
WE#
DQM
Precharge
Power-Down
Entry
Row Active
Read
Precharge
Active
Power-Down Power-Down
Exit
Entry
Active
Power-Down
Exit
Precharge
DON'T CARE
NOTES:
1. Both banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CK + tSS prior to Row active command.
3. Can not violate minimum refresh specification (64ms).
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
Rev. 1
23
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED416S16030A
SELF REFRESH ENTRY & EXIT CYCLE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
t SS
CKE
Note 2
t RFC min
Note 3
Note 1
Note 6
Note 4
Note 5
CE#
RAS#
Note 7
CAS#
ADDR
BA
A10/AP
DQ
HI-Z
HI-Z
WE#
DQM
Self Refresh Entry
Self Refresh Exit
Auto Refresh
DON'T CARE
NOTES:
TO ENTER SELF REFRESH MODE
1. CE#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in self refresh mode as long as CKE stays "Low." Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CE# starts from high.
6. Minimum tRFC is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
Rev. 1
24
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
MODE REGISTER SET CYCLE
0
1
2
3
4
5
6
WED416S16030A
AUTO REFRESH CYCLE
7
8
0
1
2
3
4
5
6
7
8
9
10
CLOCK
HIGH
HIGH
CKE
CE#
Note 2
t RFC
RAS#
Note 1
CAS#
Note 3
Key
ADDR
DQ
Ra
HI-Z
HI-Z
WE#
DQM
MRS
New
Command
Auto Refresh
New Command
DON'T CARE
NOTES:
Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
1. CE#, RAS#, CAS#, & WE# activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS# activation.
3. Please refer to Mode Register Set table.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
Rev. 1
25
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED416S16030A
PACKAGE DIMENSION: 54 PIN TSOP II
22.35 (0.880)
22.10 (0.870)
Note 1
VIEW A
1.20 (0.047)
MAX
11.96 (0.471)
11.56 (0.455)
10.29 (0.405)
10.03 (0.395)
Note 2
0.15 (0.006)
0.05 (0.002)
0.80 (0.0315)
TYP
0.61 (0.024)
0.41 (0.016)
0.51 (0.020)
0.25 (0.010)
SEE VIEW A
0-8
0.203 (0.008)
0.125 (0.005)
NOTES:
1. Dimension does not include 0.006 inch Flash each side.
2. Dimension does not include 0.010 inch Flash each side.
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
Part Number
WED416S16030C7SI
WED416S16030C75SI
WED416S16030C8SI
WED416S16030C10SI
Operating Frequency
133MHZ (CL2)
133MHZ (CL3)
125MHZ
100MHZ
Package
54 TSOP II
54 TSOP II
54 TSOP II
54 TSOP II
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2006
Rev. 1
26
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com