ETC WED3DL3216V-BC

WED3DL3216V
White Electronic Designs
16Mx32 SDRAM
Preliminary
FEATURES
DESCRIPTION
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The WED3DL3216V is an 16Mx32 Synchronous DRAM
configured as 4x4Mx32. The SDRAM BGA is constructed
with two 16Mx16 SDRAM die mounted on a multi-layer
laminate substrate and packaged in a 119 lead, 17mm
by 23mm, BGA.
40% Space Savings vs. Monolithic Solution
Reduced System Inductance and Capacitance
3.3V Operating Supply Voltage
Fully Synchronous to Positive Clock Edge
Clock Frequencies of 100MHz - 133MHz
The WED3DL3216V is available in clock speeds of
133MHz, 125MHz, and 100MHz. The range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance
memory system applications.
Burst Operation
• Sequential or Interleave
• Burst Length = Programmable 1, 2, 4, 8
or Full Page
• Burst Read and Write
The package and design provides performance enhancements via a 50% reduction in capacitance vs.
two monolithic devices. The design includes internal
ground and power planes which reduces inductance
on the ground and power pins allowing for improved
decoupling and a reduction in system noise.
• Multiple Burst Read and Single Write
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Data Mask Control Per Byte
Auto and Self Refresh
Automatic and Controlled Precharge Commands
Suspend Mode and Power Down Mode
119 Pin BGA, 17mm x 23mm
FIG. 1 PIN CONFIGURATION
PIN DESCRIPTION
(TOP VIEW)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1
V DDQ
NC
NC
DQ C
DQ C
V DDQ
DQ C
DQ C
V DDQ
DQ D
DQ D
V DDQ
DQ D
DQ D
NC
NC
V DDQ
1
May 2002, Rev. 0
ECO# 15233
2
NC
NC
NC
NC
DQ C
DQ C
DQ C
DQ C
VDD
DQ D
DQ D
DQ D
DQ D
NC
A6
NC
NC
2
3
BA 0
A12
BA 1
V SS
V SS
V SS
DQMC
V SS
NC
V SS
DQMD
V SS
V SS
V SS
NC
A5
NC
3
4
NC
CAS
VDD
NC
CE
RAS
NC
CKE
VDD
CLK
NC
WE
A1
A0
VDD
A4
NC
4
5
A10
A11
A9
V SS
V SS
V SS
DQMB
V SS
NC
V SS
DQMA
V SS
V SS
V SS
NC
A3
NC
5
6
A7
NC
A8
NC
DQ B
DQ B
DQ B
DQ B
VDD
DQ A
DQ A
DQ A
DQ A
NC
A2
NC
NC
6
7
V DDQ
NC
NC
DQ B
DQ B
V DDQ
DQ B
DQ B
V DDQ
DQ A
DQ A
V DDQ
DQ A
DQ A
NC
NC
V DDQ
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
A0 – A12
BA0-1
DQ
CLK
CKE
DQM
RAS
CAS
CE
VDD
VDDQ
V SS
Address Bus
Bank Select Addresses
Data Bus
Clock
Clock Enable
Data Input/Output Mask
Row Address Strobe
Column Address Strobe
Chip Enable
Power Supply pins, 3.3V
Data Bus Power Supply pins,3.3V
Ground pins
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
White Electronic Designs
FIG. 2 16MX32 SDRAM BLOCK DIAGRAM
White Electronic Designs Corporation • Westborough, MA • (508) 366-5151
2
WED3DL3216V
WED3DL3216V
White Electronic Designs
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
CLK
CKE
Type
Input
Input
CE
Input
Pulse
Active Low
Input
Pulse
Active Low
Input
Level
—
A0-12,
Input
Level
—
DQ
Input/Output
Level
—
DQM
Input
Pulse
Mask
Active High
VDD, VSS
VDDQ
Supply
Supply
RAS, CAS
WE
BA0,BA1
Signal
Polarity
Pulse Positive Edge
Level
Active High
Function
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self
Refresh mode.
CE disable or enable device operation by masking or enabling all inputs except CLK, CKE
and DQM.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
operation to be executed by the SDRAM.
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-11 defines the row address (RA0-11) when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-8 defines the column address (CA0-8) when
sampled at the rising clock edge. In addition to the row address, A10 /AP is used to invoke
Autoprechargeoperation at the end of the Burst Read or Write cycle. If A10/AP is high,
autoprecharge is selected and BA0, BA1 defines the bank to be precharged . If A10/AP is
low, autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control
whichbank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the
state of BA0,BA1. If A10/AP is low, then BA0, BA1 is used to define which bank to precharge.
Data Input/Output are multiplexed on the same pins
The Data Input/Output mask places the DQ buffers in a high impedance state when
sampled high.
In Read mode, DQM has a latency of two clock cycles and controls the output buffers like
an output enable. In Write mode, DQM has a latency of zero and operates as a word mask
by allowing input data to be written if it is low but blocks the Write operation if DQm is high.
Power and ground for the input buffers and the core logic.
Isolated power and ground for the output buffers to improve noise immunity.
RECOMMENDED DC OPERATING CONDITIONS
(VOLTAGE REFERENCED TO: VSS = 0V, TA = 0°C TO 70°C;
COMMERCIAL OR TA = -40°C TO +85°C; INDUSTRIAL)
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
Min
Max
Units
Power Supply Voltage
VDD/VDDQ
-1.0
+4.6
V
Vin
-1.0
+4.6
V
Output Voltage
Vout
-1.0
+4.6
V
Operating Temperature
Topr
-0
+70
°C
Storage Temperature
Input Voltage
Tstg
-55
+125
°C
Power Dissipation
Pd
—
1.5
W
Short Circuit Output Current
Ios
—
50
mA
Parameter
Supply Voltage
Symbol Min
VDD/VDDQ 3.0
Typ
3.3
Max
3.6
Unit
V
Input High Voltage
VIH
2.0
3.0 VDD +0.3
Input Low Voltage
VIL
-0.3
—
0.8
V
V
Output High Voltage (IOH = -2mA) VOH
2.4
—
—
V
Output Low Voltage (IOL = 2mA)
VOL
—
—
0.4
V
Input Leakage Voltage
Iil
-5
—
5
µA
Output Leakage Voltage
Iol
-5
—
5
µA
CAPACITANCE
(TA = 25°C, f = 1MHZ, VDD = 3.3V)
* Stress greater than those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Parameter
Input Capacitance
Input/Output Capacitance (DQ)
3
Symbol
Max
Unit
C I1
4
pF
C OUT
5
pF
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
White Electronic Designs
WED3DL3216V
OPERATING CURRENT CHARACTERISTICS
(VCC = 3.3V, TA = 0°C TO 70°C; COMMERCIAL OR TA = -40°C TO +85°C; INDUSTRIAL)
Parameter
Operating Current (One Bank Active)1
Operating Current (Burst Mode)1
Symbol
I CC1
I CC4
Conditions
Burst Length = 1, trc ³ trc(min), IOL = 0mA
Page Burst, 4 banks active, tCCD = 2 clocks
-7
300
300
-8
280
280
-10
260
260
Units
mA
mA
I CC2P
I CC2PS
I CC1N
CKE £ Vil(max), tCC = 15ns
CKE, CLK £ VIL(max), tCC = ¥, Inputs Stable
CKE = VIH, tCC = 15ns
Input Change one time every 30ns
2
2
140
2
2
140
2
2
140
mA
mA
mA
in Non-Power Down Mode
I CC1NS
CKE ³ VIH (min), tcc = ¥
No Input Change
70
70
70
mA
Precharge Standby Current
in Power Down Mode
Active Standby Current in
Non-Power Down Mode
I CC3P
I CC3PS
I CC3N
CKE £ VIL (max), tCC = 15ns
CKE £ VIL (max), tCC = ¥
CKE = VIH, tCC = 15ns
Input Change one time every 30ns
12
12
60
12
12
60
12
12
60
mA
mA
mA
(One Bank Active)
Refresh Current2
Self Refresh Current
I CC3NS
I CC5
I CC6
CKE ³ VIH (min), tCC = ¥, No Input Change
tRC ³ tRC (min)
CKE £ 0.2V
50
600
6.5
50
570
6.5
50
550
6.5
mA
mA
mA
Precharge Standby Current
in Power Down Mode
Precharge Standby Current
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
White Electronic Designs Corporation • Westborough, MA • (508) 366-5151
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WED3DL3216V
White Electronic Designs
SDRAM AC CHARACTERISTICS
Symbol
Parameter
CL = 3
CL = 2
Clock to valid Output delay 1,2
Output Data Hold Time 2
Clock HIGH Pulse Width 3
Clock LOW Pulse Width 3
Input Setup Time 3
Input Hold Time 3
CLK to Output Low-Z 2
CLK to Output High-Z
Row Active to Row Active Delay 4
RAS to CAS Delay 4
Row Precharge Time 4
Row Active Time 4
Row Cycle Time - Operation 4
Row Cycle Time - Auto Refresh 4,8
Last Data in to New Column Address Delay 5
Last Data in to Row Precharge 5
Last Data in to Burst Stop 5
Column Address to Column Address Delay 6
Number of Valid OutputData 7
t CC
t CC
tSAC
t OH
t CH
t CL
tSS
t SH
tSLZ
tSHZ
t RRD
t RCD
t RP
tRAS
t RC
t RFC
tCDL
tRDL
tBDL
t CCD
133MHz
Min
Max
7
1000
7.5
1000
5.4
3
2.5
2.5
1.5
0.8
2
5.4
24
24
24
60
10,000
90
90
1
1
1
1.5
2
1
125MHz
Min
Max
8
1000
10
1000
6
3
3
3
2
1
2
6
20
20
20
50
10,000
70
70
1
1
1
1.5
2
1
100MHz
Min
10
12
Max
1000
1000
7
3
3
3
2
1
2
7
20
20
20
50
80
80
1
1
1
1.5
2
2
10,000
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
CLK
CLK
CLK
ea
NOTES:
1. Parameters depend on programmed CAS latency.
2. If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter.
3. Assumed input rise and fall time = 1ns. If tRISE of tFALL are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter.
4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding
up to the next higher integer.
5. Minimum delay is required to complete write.
6. All devices allow every cycle column address changes.
7. In case of row precharge interrupt, auto precharge and read burst stop.
5
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
WED3DL3216V
White Electronic Designs
COMMAND TRUTH TABLE
Function
CKE
Previous Current
Cycle
Cycle
Register
Mode Register Set
H
X
Refresh
Auto Refresh (CBR)
H
H
Entry Self Refresh
H
L
Precharge Single Bank Precharge
H
X
Precharge all Banks
H
X
Bank Activate
H
X
Write
H
X
Write with Auto Precharge
H
X
Read
H
X
Read with Auto Precharge
H
X
Burst Termination
H
X
No Operation
H
X
Device Deselect
H
Clock Suspend/Standby Mode
L
X
Data Write/Output Disable
H
X
Data Mask/Output Disable
H
X
Power Down Mode
Entry
X
L
Exit
X
H
CE
RAS
CAS
WE
DQM
BA
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
X
X
X
X
X
L
L
L
H
H
H
L
L
L
L
H
H
X
X
X
X
X
X
L
H
H
L
L
H
L
L
L
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
BA
X
BA
BA
BA
BA
BA
X
X
X
X
X
X
X
X
A0-A10 A12, A11, Notes
OP CODE
X
X
X
X
L
X
H
X
Row Address
L
Column
H
Column
L
Column
H
Column
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2
2
2
2
2
2
3
X
4
5
5
6
6
NOTES:
1. All of the SDRAM operations are defined by states of CE, WE, RAS, CAS, and DQM at the positive rising edge of the clock.
2. Bank Select (BA), if BA = 0 then bank A is selected, if BA = 1 then bank B is selected.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4. During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data Read and
Write operations. One clock delay is required for mode entry and exit.
5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the
data outputs are disabled and become high impedance after a two clock delay. DQM also provides a data mask function for Write cycles.
When it activates, the Write operation at the clock is prohibited (zero clock latency).
All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not preform any Refresh operations,
therefore the device can’t remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode
entry and exit.
White Electronic Designs Corporation • Westborough, MA • (508) 366-5151
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WED3DL3216V
White Electronic Designs
CLOCK ENABLE (CKE0) TRUTH TABLE
Current State
Self Refresh
Power Down
All Banks Idle
Any State
other than
listed above
CKE
Previous Current
Cycle
Cycle
H
X
L
H
L
H
L
H
L
H
L
H
L
L
H
X
L
H
L
H
H
X
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
L
H
L
H
H
L
X
H
H
H
L
L
L
H
L
Command
CE RAS CAS WE
Action
Notes
INVALID
Exit Self Refresh with Device Deselect
Exit Self Refresh with No Operation
ILLEGAL
ILLEGAL
ILLEGAL
Maintain Self Refresh
INVALID
Power Down Mode exit, all banks idle
ILLEGAL
Maintain Power Down Mode
1
2
2
2
2
2
Refer to the Idle State section of the
Current State Truth Table
CBR Refresh
Mode Register Set
3
BA0-1 A10-11
X
H
L
L
L
L
X
X
H
L
L
H
L
L
L
L
H
L
L
L
L
X
X
X
X
H
H
H
L
X
X
X
X
H
X
H
L
L
L
X
H
L
L
L
X
X
X
X
H
H
L
X
X
X
X
X
L
X
X
H
L
L
X
X
H
L
L
X
X
X
X
H
L
X
X
X
X
X
X
L
X
X
X
H
L
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OP Code
X
X
OP Code
X
X
X
X
X
X
X
Refer to the Idle State section of the
Current State Truth Table
Entry Self Refresh
Mode Register Set
Power Down
Refer to the Operations in the Current
State Truth Table
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clock Suspend
1
2
2
2
4
3
4
4
5
NOTES:
1. For the given Current State CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCKS)
must be satisfied before any command other than Exit is issued.
3. The address inputs (A12-0) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more
information.
4. The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state.
5. Must be a legal command as defined in the Current State Truth Table.
7
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
WED3DL3216V
White Electronic Designs
CURRENT STATE TRUTH TABLE
Current State
Idle
Row Active
Read
Write
Read with
Auto Precharge
Command
CE RAS CAS WE BA 0-1
A0-A12
L
L
L
L
OP Code
L
L
L
H
X
X
L
L
H
L
X
X
L
L
H
H
BA Row Address
L
H
L
L
BA
Column
L
H
L
H
BA
Column
L
H
H
L
X
X
L
H
H
H
X
X
H
X
X
X
X
X
L
L
L
L
OP Code
L
L
L
H
X
X
L
L
H
L
X
X
L
L
H
H
BA Row Address
L
H
L
L
BA
Column
L
H
L
H
BA
Column
L
H
H
L
X
X
L
H
H
H
X
X
H
X
X
X
X
X
L
L
L
L
OP Code
L
L
L
H
X
X
L
L
H
L
X
X
L
L
H
H
BA Row Address
L
H
L
L
BA
Column
L
H
L
H
BA
Column
L
H
H
L
X
X
L
H
H
H
X
X
H
X
X
X
X
X
L
L
L
L
OP Code
L
L
L
H
X
X
L
L
H
L
X
X
L
L
H
H
BA Row Address
L
H
L
L
BA
Column
L
H
L
H
BA
Column
L
H
H
L
X
X
L
H
H
H
X
X
H
X
X
X
X
X
L
L
L
L
OP Code
L
L
L
H
X
X
L
L
H
L
X
X
L
L
H
H
BA Row Address
L
H
L
L
BA
Column
L
H
L
H
BA
Column
L
H
H
L
X
X
L
H
H
H
X
X
H
X
X
X
X
X
White Electronic Designs Corporation • Westborough, MA • (508) 366-5151
Description
Mode Register Set
Auto or Self Refresh
Precharge
Bank Activate
Write w/o Precharge
Read w/o Precharge
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Device Deselect
8
Action
Notes
Set the Mode Register
Start Auto orSelf Refresh
No Operation
Activate the specified bank and row
ILLEGAL
ILLEGAL
No Operation
No Operation
No Operation or Power Down
ILLEGAL
ILLEGAL
Precharge
ILLEGAL
Start Write; Determine if Auto Precharge
Start Read; Determine if Auto Precharge
No Operation
No Operation
No Operation
ILLEGAL
ILLEGAL
Terminate Burst; Start the Precharge
ILLEGAL
Terminate Burst; Start the Write cycle
Terminate Burst; Start a new Read cycle
Terminate the Burst
Continue the Burst
Continue the Burst
ILLEGAL
ILLEGAL
Terminate Burst; Start the Precharge
ILLEGAL
Terminate Burst; Start a new Write cycle
Terminate Burst; Start the Read cycle
Terminate the Burst
Continue the Burst
Continue the Burst
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Continue the Burst
Continue the Burst
2
2,3
4
2
2
5
6
2
7,8
7,8
4
8,9
8,9
4
8,9
8,9
4
4
WED3DL3216V
White Electronic Designs
CURRENT STATE TRUTH TABLE (CONT.)
Current State
Command
CE RAS CAS WE BA0-1
A0-A12
L
L
L
L
OP Code
L
L
L
H
X
X
L
L
H
L
X
X
Write with
L
L
H
H
BA Row Address
Auto Precharge
L
H
L
L
BA
Column
L
H
L
H
BA
Column
L
H
H
L
X
X
L
H
H
H
X
X
H
X
X
X
X
X
L
L
L
L
OP Code
L
L
L
H
X
X
L
L
H
L
X
X
L
L
H
H
BA Row Address
Precharging
L
H
L
L
BA
Column
L
H
L
H
BA
Column
L
H
H
L
X
X
L
H
H
H
X
X
H
X
X
X
X
X
L
L
L
L
OP Code
L
L
L
H
X
X
L
L
H
L
X
X
L
L
H
H
BA Row Address
Row Activating
L
H
L
L
BA
Column
L
H
L
H
BA
Column
L
H
H
L
X
X
L
H
H
H
X
X
H
X
X
X
X
X
L
L
L
L
OP Code
L
L
L
H
X
X
L
L
H
L
X
X
L
L
H
H
BA Row Address
Write
L
H
L
L
BA
Column
Recovering
L
H
L
H
BA
Column
L
H
H
L
X
X
L
H
H
H
X
X
H
X
X
X
X
X
L
L
L
L
OP Code
L
L
L
H
X
X
L
L
H
L
X
X
Write
L
L
H
H
BA Row Address
Recovering with L
H
L
L
BA
Column
Auto Precharge
L
H
L
H
BA
Column
L
H
H
L
X
X
L
H
H
H
X
X
H
X
X
X
X
X
Action
Description
Mode Register Set
Auto orSelf Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto orSelf Refresh
Precharge
Bank Activate
Write w/o Precharge
Read w/o Precharge
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto orSelf Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto orSelf Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto orSelf Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Device Deselect
9
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Continue the Burst
Continue the Burst
ILLEGAL
ILLEGAL
No Operation; Bank(s) idle after t RP
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Bank(s) idle after t RP
No Operation; Bank(s) idle after t RP
No Operation; Bank(s) idle after t RP
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Row active after t RCD
No Operation; Row active after t RCD
No Operation; Row active after t RCD
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Start Write; Determine if Auto Precharge
Start Read; Determine if Auto Precharge
No Operation; Row active after t DPL
No Operation; Row active after t DPL
No Operation; Row active after t DPL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Precharge after t DPL
No Operation; Precharge after t DPL
No Operation; Precharge after t DPL
Notes
4
4
4
4
4
4
4,10
4
4
4
4
9
9
4
4
4,9
4,9
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White Electronic Designs
WED3DL3216V
CURRENT STATE TRUTH TABLE (CONT.)
Current State
Refreshing
Mode Register
Accessing
Command
CE RAS CAS WE BA 0-1
A0-A12
Description
L
L
L
L
OP Code
Mode Register Set
L
L
L
H
X
X
Auto or Self Refresh
L
L
H
L
X
X
Precharge
L
L
H
H
BA Row Address
Bank Activate
L
H
L
L
BA
Column
Write
L
H
L
H
BA
Column
Read
L
H
H
L
X
X
Burst Termination
L
H
H
H
X
X
No Operation
H
X
X
X
X
X
Device Deselect
L
L
L
L
OP Code
Mode Register Set
L
L
L
H
X
X
Auto or Self Refresh
L
L
H
L
X
X
Precharge
L
L
H
H
BA Row Address
Bank Activate
L
H
L
L
BA
Column
Write
L
H
L
H
BA
Column
Read
L
H
H
L
X
X
Burst Termination
L
H
H
H
X
X
No Operation
H
X
X
X
X
X
Device Deselect
Action
Notes
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Idle after t RC
No Operation; Idle after t RC
No Operation; Idle after t RC
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Idle after two clock cycles
No Operation; Idle after two clock cycles
NOTES:
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is
being applied to.
2. Both Banks must be idle otherwise it is an illegal action.
3. If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered.
4. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being
referenced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) than the Power Down mode is entered, otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
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WED3DL3216V
White Electronic Designs
MODE REGISTER DEFINITION
A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
Mode Register (Mx)
Reserved*
WB Op Mode CAS Latency
BT
Burst Length
*Program M12, M11, M10 = "0, 0, 0"
to ensure compatibility with future devices.
Burst Length
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
Burst Type
M3
0
Sequential
1
Interleaved
M6 M5 M4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
M8
M7
M6-M0
Operating Mode
0
0
Defined
Standard Operation
-
-
-
M9
Write Burst Mode
0
Programmed Burst Length
1
Single Location Access
11
All other states reserved
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WED3DL3216V
White Electronic Designs
FIG. 3 SINGLE BIT READ-WRITE CYCLE (SAME PAGE) @CAS LATENCY=3,
BURST LENGTH=1
NOTES:
1. All input except CKE & DQM can be don't care when CE is high
at the CLK high going edge.
2. Bank active & read/write are controlled by BA0~BA1.
BA0
0
0
1
1
4.
BA1
0
1
0
1
3.
A10/AP BA0
0
0
0
1
1
0
1
0
1
1
Active & Read/Write
Bank A
Bank B
Bank C
Bank D
A10/AP and BA0~BA1 control bank precharge when
precharge command is asserted.
A10/AP
0
0
0
0
1
BA0
0
0
1
1
x
BA1
0
1
0
1
x
Precharge
Bank A
Bank B
Bank C
Bank D
All Banks
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Enable and disable auto precharge function are controlled by
A10/AP in read/write command.
12
BA1
0
1
0
1
0
1
0
1
Operation
Disable auto precharge, leave bank A active at end of burst.
Disable auto precharge, leave bank B active at end of burst.
Disable auto precharge, leave bank C active at end of burst.
Disable auto precharge, leave bank D active at end of burst.
Enable auto precharge, precharge bank A at end of burst.
Enable auto precharge, precharge bank B at end of burst.
Enable auto precharge, precharge bank C at end of burst.
Enable auto precharge, precharge bank D at end of burst.
White Electronic Designs
WED3DL3216V
FIG. 4 POWER UP SEQUENCE
13
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WED3DL3216V
FIG. 5 READ & WRITE CYCLE AT SAME BANK @BURST LENGTH=4
NOTES:
1. Minimum row cycle times are required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last
valid output will be Hi-Z(tSHZ) after the clock.
3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC.
4. Output will be Hi-Z after the end of burst (1, 2, 4, 8 & full page bit burst).
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White Electronic Designs
WED3DL3216V
FIG. 6 PAGE READ & WRITE CYCLE AT SAME BANK @BURST LENGTH=4
NOTES:
1. To write data before burst read ends, DQM should be asserted three cycles prior to write command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row
precharge cycle will be masked internally.
15
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WED3DL3216V
FIG. 7 PAGE READ CYCLE AT DIFFERENT BANK @BURST LENGTH=4
NOTES:
1. CE can be don't cared when RAS, CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
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White Electronic Designs
WED3DL3216V
FIG. 8 PAGE WRITE CYCLE AT DIFFERENT BANK @BURST LENGTH=4
NOTES:
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
17
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WED3DL3216V
FIG. 9 READ & WRITE CYCLE AT DIFFERENT BANK @BURST LENGTH=4
NOTE:
1. tCDL should be met to complete write.
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White Electronic Designs
WED3DL3216V
FIG. 10 READ & WRITE CYCLE WITH AUTO PRECHARGE @BURST
LENGTH=4
NOTE:
1. tCDL should be controlled to meet minimum tRAS before internal precharge start.
(in the case of Burst Length = 1 & 2 and BRSW mode)
19
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WED3DL3216V
FIG. 11 CLOCK SUSPENSION & DQM OPERATION CYCLE @CAS
LATENCY=2, BURST LENGTH=4
NOTE:
1. DQM is needed to prevent bus contention.
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White Electronic Designs
WED3DL3216V
FIG. 12 READ INTERRUPTED BY PRECHARGE COMMAND & READ
BURST STOP @BURST LENGTH=FULL PAGE
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated in above timing diagram. See
the label 1, 2. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer to the timing diagram of “Full page
write burst stop cycle.”
3. Burst stop is valid at every burst length.
21
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White Electronic Designs
WED3DL3216V
FIG. 13 WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST
STOP CYCLE @BURST LENGTH=FULL PAGE
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell. It is defined by AC parameter of
tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on
precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
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WED3DL3216V
FIG. 14 BURST READ SINGLE BIT WRITE CYCLE @BURST LENGTH=2
@BURST LENGTH=FULL PAGE
NOTES:
1. BRSW mode is enabled by setting As “High” at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to “1”
regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is
executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge.
23
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WED3DL3216V
FIG. 15 ACTIVE/PRECHARGE POWER DOWN MODE @CAS LATENCY=2,
BURST LENGTH=4
NOTES:
1. Both banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1 CLK + tSS prior to Row active command.
3. Cannot violate minimum refresh specification (64ms).
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White Electronic Designs
WED3DL3216V
FIG. 16 SELF REFRESH ENTRY & EXIT CYCLE
NOTES:
TO ENTER SELF REFRESH MODE
1. CE, RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low.” Once the device enters self refresh mode, minimum tRAS is
required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CE starts from high.
6. Minimum tRFC is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
25
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FIG. 17 MODE REGISTER SET
CYCLE
WED3DL3216V
FIG. 18 AUTO REFRESH CYCLE
NOTES:
Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
1. CE, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
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White Electronic Designs
WED3DL3216V
PACKAGE DESCRIPTION 119 P IN BGA
JEDEC MO-163
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
Part Number
WED3DL3216V7BC
WED3DL3216V8BC
WED3DL3216V10BC
WED3DL3216V7BI
WED3DL3216V8BI
WED3DL3216V10BI
WED3DL3216V7ES
WED3DL3216V10ES
Clock Frequency
133MHz
125MHz
100MHz
133MHz, Industrial
125MHz, Industrial
100MHz, Industrial
133MHz, Engineering Samples
100 MHz, Engineering Samples
Package
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
27
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