WED48S8030E 2M x 8 Bits x 4 Banks Synchronous DR AM DRAM FEATURES DESCRIPTION n Single 3.3V power supply The WED48S8030E is 67,108,864 bits of synchronous high data rate DRAM organized as 4 x 2,097,152 words x 8 bits. Synchronous design allows precise cycle control with the use of system clock, I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. n Fully Synchronous to positive Clock Edge n Clock Frequency = 125, 100MHz n SDRAM CAS Latency = 2 n Burst Operation •Sequential or Interleave •Burst length = programmable 1,2,4,8 or full page Available in a 54 pin TSOP type II package the WED48S8030E is tested over the industrial temp range (-40C to +85C) providing a solution for rugged main memory applications. •Burst Read and Write •Multiple Burst Read and Single Write n DATA Mask Control n Auto Refresh (CBR) and Self Refresh •4096 refresh cycles across 64ms n Automatic and Controlled Precharge Commands n Suspend Mode and Power Down Mode n Industrial Temperature Range FIG. 1 PIN D ESCRIPTION P IN C ONFIGURATION A0-11 BA0, BA1 CE WE CLK CKE DQ0-7 DQM RAS CAS VDD VDDQ VSS VSSQ NC February 2002 Rev. 2 ECO #14194 1 Address Inputs Bank Select Addresses Chip Select Write Enable Clock Input Clock Enable Data Input/Output Data Input/Output Mask Row Address Strobe Column Address Strobe Power (3.3V) Data Output Power Ground Data Output Ground No Connection White Electronic Designs Corporation • (508) 366-5151• www.whiteedc.com WED48S8030E INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type Signal Polarity Function CLK CKE Input Input Pulse Level Positive Edge Active High CE Input Pulse Active Low RAS, CAS WE BA0,BA1 Input Pulse Active Low Input Level — The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. CE disable or enable device operation by masking or enabling all inputs except CLK, CKE and DQM. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-11 defines the row address (RA0-11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-8 defines the column address (CA0-8) when sampled at the, rising clock edge. In addition to the row address, A10/AP is used to invoke Autoprecharge operation at Input Level — the end of the Burst Read or Write cycle. If A10/AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged . If A10/AP is low, autoprecharge is disabled. A0-11 A10/AP DQ0-15 Input/Output Level — DQM Input Pulse Mask Active High VDD, VSS VDDQ, VSSQ Supply Supply During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the state of BA0, BA1. If A10/AP is low, then BA0, BA1 is used to define which bank to precharge. Data Input/Output are multiplexed on the same pins. The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the Write operation if DQM is high. Power and ground for the input buffers and the core logic. Isolated power and ground for the output buffers to improve noise immunity. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 2 WED48S8030E ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Output Current Symbol Min Max Units VDD VIN VOUT TOPR TSTG PD IOS -1.0 -1.0 -1.0 -40 -55 +4.6 +4.6 +4.6 +85 +125 1.0 50 V V V °C °C W mA RECOMMENDED DC OPERATING CONDITIONS (V OLTAGE R EFERENCED T A = -40°C Parameter VSS = 0V, +85°C) Symbol Min Typ VDD VIH VIL VOH VOL I IL I OL 3.0 2.0 -0.3 2.4 — -10 -10 3.3 3.0 — — — — — Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Voltage Output Leakage Voltage Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TO : TO Max Unit Notes 3.6 V VDD +0.3 V 0.8 V — V (IOH= -2mA) 0.4 V (IOL = 2mA) 10 mA 10 mA CAPACITANCE (T A = 25C, F = 1MH Z, VDD = 3.3V Parameter Input Capacitance (A0-11, BA0-1) Input Capacitance (CLK, CKE, RAS, CAS, WE, CE, DQM) Input/Output Capacitance (DQ0-15) TO 3.6V) Symbol Max Unit CI1 CI2 4 4 pF pF COUT 5 pF OPERATING CURRENT CHARACTERISTICS (VCC = 3.3V, T A = -40°C Parameter Operating Current (One Bank Active) Operating Current (Burst Mode) Precharge Standby Current in Power Down Mode Test Condition -8 -10 Units Notes I CC 1 I CC 4 Burst Length = 1, tRC ³ tRC (min) Page Burst, 2 banks active, tCCD = 2 clocks CKE £ VIL (max), tCC= 15ns CKE, CLK £ VIL (max), tCC = ¥, Inputs Stable CKE = VIH, tCC = 15ns Input Change every 30ns CKE ³ VIH (min), tCC = ¥ No Input Change CKE £ VIL (max), tCC = 15ns CKE £ VIL(max), tCC = ¥ CKE = VIH, tCC = 15ns Input Change every 30ns CKE ³ VIH (min), tCC = ¥, No Input Change tRC³ tRC(min) CKE £ 0.2V 100 160 2 2 20 95 130 2 2 20 mA mA mA mA mA 1 1 10 10 mA 5 5 20 5 5 20 mA mA mA 10 190 2 10 175 2 mA mA mA I CC 2P I CC 2PS I CC 1N I CC 1NS I CC 3P I CC 3PS I CC 2N Active Standby Current in Non-Power Down Mode Refresh Current Self Refresh Current NOTES: 1. Measured with outputs open. 2. Refresh period is 64ms. +85°C) Symbol Precharge Standby Current in Non-Power Down Mode Active Standby Current in Power Down Mode TO I CC 2NS I CC 5 I CC 6 3 2 White Electronic Designs Corporation • (508) 366-5151• www.whiteedc.com WED48S8030E AC CHARACTERISTICS OPERATING AC PARAMETERS (VCC = 3.3V, T A = -40°C Parameter Clock Cycle Time Symbol CAS latency = 3 CAS latency = 2 Clock to Valid Output Delay Output Data Hold Time Clock High Pulse Width Clock Low Pulse Width Input Setup Time Input Hold Time Clock to Output in Low-Z Clock to Output in High-Z Row Active to Row Active Delay RAS to CAS Delay Row Precharge Time Row Active Time Row Cycle Time - Operation Row Cycle Time - Auto Refresh Last Data In to New Column Address Delay Last Data In to Row Precharge Last Data In to Burst Stop Column Address to Column Address Delay TO +85°C) -8 tCC tSAC tOH tCH t CL tSS tSH tSLZ tSHZ tRRD tRCD tRP tRAS tRC tRFC t CDL tRDL tBDL tCCD -10 Min Max Min Max 7.5 10 1000 1000 5.4 10 10 1000 1000 6 3 2.5 2.5 1.5 0.8 1 3 3.5 3 2 1 1 5.4 15 20 20 45 65 65 1 1 1 1 2 1 CAS latency = 3 CAS latency = 2 6 100,000 20 20 20 50 70 70 1 1 1 1 2 1 100,000 Units Notes ns 1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLK CLK CLK CLK 1, 2 2 3 3 3 3 2 ea 7 4 4 4 4 4 4, 8 5 5 5 6 NOTES: 1. Parameters depend on programmed CAS latency. 2. If clock rise time is longer than 1ns, (tRISE/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time = 1ns. If tRISE & tfall are longer than 1ns, [(tRISE + tFALL)/2]-1ns should be added to the parameter. 4. The minimum number of clock cycles required is determined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer. 5. Minimum delay is required to complete write. 6. All devices allow every cycle column address changes. 7. In case of row precharge interrupt, auto precharge and read burst stop. 8. A new command may be given tRFC after self refresh exit. REFRESH C YCLE PARAMETERS -8 Parameter Refresh Period Self Refresh Exit Time -10 Symbol Min Max Min Max Units Notes tREF tSREX — tRFC 64 — — t RFC 64 — ms ns 1, 2 3 NOTES: 1. 4096 cycles. 2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device. 3. The self refresh is exited by restarting the external clock and then asserting CKE high. This must be followed by NOPs for a minimum time of tRFC before the SDRAM reaches idle state to begin normal operation. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 4 WED48S8030E COMMAND TRUTH TABLE CKE Command Register Refresh Precharge Previous Cur rent Cycle Cycle H X H L Mode Register Set Auto(CBR) Entry Self Single Bank All Banks Bank Activate Write Read Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable Burst Stop No Operation Device Deselect Clock Suspend/Standby Mode Write/Output Enable Data Mask/Output Disable Entry Power Down Mode Exit H CE RAS CAS WE DQM L L L L X L L L J X BA0,1 A10/Ap A11, A 9-0 OP CODE X X H X L L H H X BA X BA H X L H L L X BA X H X L H L H X BA H H H L X X X X L L H X H H X X H H X X L H X X X X X X H X X X X X X X X X L H L X H X Row Address L Column H Address L Column H Address X X X X X X X X X X X X L H H X X X X X X X H X L L H L X Notes 2 2 2 2 2 2 3 4 5 5 6 6 (X = Dont Care, H = Logic High, L = Logic Low) NOTES: 1. All of the SDRAM operations are defined by states of CE, WE, RAS, CAS, and DQM at the positive rising edge of the clock. 2. Bank Select (BA), if BA0, BA1 = 0, 0 then bank A is selected, if BA0, BA1 = 1, 0 then bank B, if BA0, BA1 = 0, 1 then bank C, if BA0, BA1 = 1, 1 then bank D is selected, respectively. 3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency. 4. During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit. 5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). 6. All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not perform any Refresh operations, therefore the device can’t remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit. 5 White Electronic Designs Corporation • (508) 366-5151• www.whiteedc.com WED48S8030E CLOCK ENABLE (CKE0) TRUTH TABLE CKE Current State Self Refresh Power Down All Banks Idle Any State other than listed above Command Previous Cur rent CE RAS CAS WE BA0,1 A0-11 Action Notes H L L L L L L H L L L H H H H H H H H H H L X H H H H H L X H H L H H H H H L L L L L X X H L L L L X X H L X H L L L L H L L L L X X X H H H L X X X X X X H L L L X H L L L X X X H H L X X X X X X X X H L L X X H L L X X X H L X X X X X X X X X X H L X X X H L X X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down Mode exit, all banks idle ILLEGAL Maintain Power Down Mode 1 2 2 2 2 2 H H X X X X X X H L L L H L X X X X X X X X X X X X X X X X X X X X OP Code X X OP Code X X Refer to the Idle State section of the Current State Truth Table CBR Refresh Mode Register Set Refer to the Idle State section of the Current State Truth Table Entry Self Refresh Mode Register Set Power Down Refer to the Operations in the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend NOTES: 1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCKS) must be satisfied before any command other than Exit is issued. 3. The address inputs (A11-0) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information. 4. The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state. 5. Must be a legal command as defined in the Current State Truth Table. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 6 1 2 2 3 4 3 4 4 5 WED48S8030E MODE REGISTER SET TABLE 7 White Electronic Designs Corporation • (508) 366-5151• www.whiteedc.com WED48S8030E CURRENT STATE TRUTH TABLE Command Current State CE RAS CAS WE BA0,1 A11, Description Action Notes Mode Register Set Auto or Self Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Start Read Start Read; Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Set the Mode Register Start Auto orSelf Refresh No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Write; Determine if Auto Precharge Determine if Auto Precharge No Operation No Operation No Operation ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start the Write cycle Terminate Burst; Start a new Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start a new Write cycle Terminate Burst; Start the Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst 2 2,3 A10/AP-A0 Idle Row Active Read Write Read with Auto Precharge L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X OP Code X X X X BA Row Address BA Column BA Column X X X X X X OP Code X X X X BA Row Address BA Column BA Column X X X X X X OP Code X X X X BA Row Address BA Column BA Column X X X X X X OP Code X X X X BA Row Address BA Column BA Column X X X X X X OP Code X X X X BA Row Address BA Column BA Column X X X X X X White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 8 4 4 5 6 4 7,8 7,8 4 8,9 8,9 4 8,9 8,9 4 4 WED48S8030E CURRENT STATE TRUTH TABLE ( CONT .) Command Current State CE RAS CAS WE BA0,1 A11, Description Action Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Address Bank Activate Write Read Burst Termination No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Row active after tRCD No Operation; Row active after tRCD No Operation; Row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation; Row active after tDPL No Operation; Row active after tDPL No Operation; Row active after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Precharge after tDPL No Operation; Precharge after tDPL No Operation; Precharge after tDPL Notes A10/AP-A0 Write with Auto Precharge Precharging Row Activating Write Recovering Write Recovering with Auto Precharge L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X OP Code X X X X BA Row Address BA Column BA Column X X X X X X OP Code X X X X BA Row Address BA Column BA Column X X X X X X OP Code X X X X BA Row Address BA Column BA Column X X X X X X OP Code X X X X BA Row Address BA Column BA Column X X X X X X OP Code X X X X BA Row BA Column BA Column X X X X X X 9 4 4 4 4 4 4 4,10 4 4 4 4 9 9 4 4 4,9 4,9 White Electronic Designs Corporation • (508) 366-5151• www.whiteedc.com WED48S8030E CURRENT STATE TRUTH TABLE ( CONT .) Command Current State CE RAS CAS WE BA0,1 A11, Description Action Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after tRC No Operation; Idle after tRC No Operation; Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after two clock cycles No Operation; Idle after two clock cycles Notes A10/AP-A0 Refreshing Mode Register Accessing L L L L L L L L H L L L L L L L L H L L L L H H H H X L L L L H H H H X L L H H L L H H X L L H H L L H H X L H L H L H L H X L H L H L H L H X OP Code X X Row Address Column Column X X X OP Code X X X X BA Row Address BA Column BA Column X X X X X X X X BA BA BA X X X NOTES: 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being applied to. 2. All Banks must be idle otherwise it is an illegal action. 3. If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered. 4. The Current State refers only to one of the banks, if BA0, BA1 selects this bank then the action is illegal. If BA0, BA1 selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered, otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 10 WED48S8030E FIG. 2 SINGLE BIT READ-WRITE CYCLE (SAME PAGE) @CAS L ATENCY=3, BURST LENGTH=1 NOTES: 1. All input except CKE & DQM can be don’t care when CE is high at the CLK high going edge. 2. Bank active & read/write are controlled by BA0 ~ BA1. 4. A10/AP and BA0 - BA1 control bank precharge when precharge command is asserted. BA0 BA1 0 0 1 1 0 1 0 1 A10/AP 0 0 0 0 1 3. Enable and disable auto precharge function are controlled by A10/AP in read/write command. Active & Read/Write Bank A Bank B Bank C Bank D BA0 BA1 0 0 0 1 1 0 1 1 x x A10/A P 0 Precharge Bank A Bank B Bank C Bank D All Banks 1 11 BA 0 0 0 1 1 0 0 1 1 BA 1 0 1 0 1 0 1 0 1 Operation Distribute auto precharge,leave bank A active at end of burst. Disable auto precharge,leave bank B active at end of burst. Disable auto precharge,leave bank C active at end of burst. Disable auto precharge,leave bank D active at end of burst. Enable auto precharge,precharge bank A at end of burst. Enable auto precharge,precharge bank B at end of burst. Enable auto precharge,precharge bank C at end of burst. Enable auto precharge,precharge bank D at end of burst. White Electronic Designs Corporation • (508) 366-5151• www.whiteedc.com WED48S8030E FIG. 3 POWER UP SEQUENCE White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 12 WED48S8030E FIG. 4 READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH=4 NOTES: 1. Minimum row cycle times are required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock. 3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC. 4. Output will be Hi-Z after the end of burst (1, 2, 4, 8 & full page bit burst). 13 White Electronic Designs Corporation • (508) 366-5151• www.whiteedc.com WED48S8030E FIG. 5 PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH=4 NOTES: 1. To write data before burst read ends, DQM should be asserted three cycles prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 14 WED48S8030E FIG. 6 PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH=4 NOTES: 1. CE can be don’t cared when RAS, CAS and WE are high at the clock high going edge. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same. 15 White Electronic Designs Corporation • (508) 366-5151• www.whiteedc.com WED48S8030E FIG. 7 PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH=4 NOTES: 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 16 WED48S8030E FIG. 8 READ & WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH=4 NOTE: 1. tCDL should be met to complete write. 17 White Electronic Designs Corporation • (508) 366-5151• www.whiteedc.com WED48S8030E FIG. 9 READ & WRITE CYCLE WITH AUTO PRECHARGE @ BURST LENGTH=4 Note: 1. tCDL should be controlled to meet minimum tRAS before internal precharge start. (In the case of Burst Length=1 & 2 and BRSW mode) White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 18 WED48S8030E FIG. 10 CLOCK SUSPENSION & DQM OPERATION CYCLE @ CAS L ATENCY=2, BURST LENGTH=4 Note: 1. DQM is needed to prevent bus contention. 19 White Electronic Designs Corporation • (508) 366-5151• www.whiteedc.com WED48S8030E FIG. 11 READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP @ BURST LENGTH=FULL PAGE NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated in above timing diagram. See the label 1, 2. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer to the timing diagram of “Full page write burst stop cycle.” 3. Burst stop is valid at every burst length. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 20 WED48S8030E FIG. 12 WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP CYCLE @ BURST LENGTH=FULL PAGE NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length. 21 White Electronic Designs Corporation • (508) 366-5151• www.whiteedc.com WED48S8030E FIG. 13 BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH=2 NOTES: 1. BRSW mode is enabled by setting A9 “High” at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 22 WED48S8030E FIG. 14 ACTIVE/PRECHARGE POWER DOWN MODE @ CAS L ATENCY=2, BURST LENGTH=4 NOTES: 1 .Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + tSS prior to Row active command. 3. Can not violate minimum refresh specification (64ms). 23 White Electronic Designs Corporation • (508) 366-5151• www.whiteedc.com WED48S8030E FIG. 15 SELF REFRESH ENTRY & EXIT CYCLE NOTES: TO ENTER SELF REFRESH MODE 1. CE, RAS & CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE. 3. The device remains in self refresh mode as long as CKE stays “Low.” Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CE starts from high. 6. Minimum tRFC is required after CKE going high to complete self refresh exit. 7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 24 WED48S8030E FIG. 17 AUTO REFRESH CYCLE FIG. 16 MODE REGISTER SET CYCLE NOTES: Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE 1. CE, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. 25 White Electronic Designs Corporation • (508) 366-5151• www.whiteedc.com WED48S8030E PACKAGE DIMENSION:54 PIN TSOP II ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTES: 1. Dimension does not include 0.006 inch Flash each side. 2. Dimension does not include 0.010 inch Flash each side. ORDERING INFORMATION Par t Number Organization WED48S8030E8SI 2Mx8bitsx4banks Operating Frequency Package 125MHz 54 TSOP II WED48S8030E10SI 2Mx8bitsx4banks 100MHz 54 TSOP II This product does not include the prefix “WED” for part marking due to package size constraints. NOTE: White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 26