! "#$"% && Data Manual September 2004 Connectivity Solutions SCPS070C IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated Contents Section 1 2 3 Title Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 PCI4510 Data Manual Document History . . . . . . . . . . . . . . . . . . . . . . . Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Feature/Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Clamping Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Peripheral Component Interconnect (PCI) Interface . . . . . . . . . . . . . . 3.4.1 1394 PCI Bus Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 PCI GRST Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 PCI Bus Lock (LOCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 Loading CardBus (Function 0) Subsystem Identification . . 3.5 PC Card Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 PC Card Insertion/Removal and Recognition . . . . . . . . . . . 3.5.2 Zoomed Video Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 Standardized Zoomed-Video Register Model . . . . . . . . . . . 3.5.4 Internal Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.5 Integrated Pullup Resistors for PC Card Interface . . . . . . . 3.5.6 SPKROUT and CAUDPWM Usage . . . . . . . . . . . . . . . . . . . 3.5.7 LED Socket Activity Indicators . . . . . . . . . . . . . . . . . . . . . . . . 3.5.8 CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Serial EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 Serial-Bus Interface Implementation . . . . . . . . . . . . . . . . . . . 3.6.2 Serial-Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 Serial-Bus EEPROM Application . . . . . . . . . . . . . . . . . . . . . . 3.6.4 Accessing Serial-Bus Devices Through Software . . . . . . . 3.7 Programmable CardBus Interrupt Subsystem . . . . . . . . . . . . . . . . . . . 3.7.1 PC Card Functional and Card Status Change Interrupts . 3.7.2 Interrupt Masks and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.3 Using Parallel IRQ Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.4 Using Parallel PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.5 Using Serialized IRQSER Interrupts . . . . . . . . . . . . . . . . . . . 3.7.6 SMI Support in the PCI4510 Device . . . . . . . . . . . . . . . . . . . Page 1−1 1−1 1−2 1−3 1−4 1−4 1−4 2−1 3−1 3−1 3−1 3−2 3−2 3−2 3−2 3−3 3−3 3−4 3−4 3−4 3−6 3−6 3−6 3−7 3−8 3−8 3−8 3−9 3−9 3−11 3−12 3−13 3−13 3−15 3−15 3−16 3−16 3−16 iii Section 3.8 4 iv Title Page Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−17 3.8.1 1394 Power Management (Function 1) . . . . . . . . . . . . . . . . 3−17 3.8.2 Integrated Low-Dropout Voltage Regulator (LDO-VR) . . . . 3−17 3.8.3 CardBus (Function 0) Clock Run Protocol . . . . . . . . . . . . . . 3−18 3.8.4 CardBus PC Card Power Management . . . . . . . . . . . . . . . . 3−18 3.8.5 16-Bit PC Card Power Management . . . . . . . . . . . . . . . . . . . 3−18 3.8.6 Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−18 3.8.7 Requirements for Suspend Mode . . . . . . . . . . . . . . . . . . . . . 3−19 3.8.8 Ring Indicate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−19 3.8.9 PCI Power Management for CardBus (Function 0) . . . . . . 3−20 3.8.10 CardBus Bridge Power Management . . . . . . . . . . . . . . . . . . 3−21 3.8.11 ACPI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−22 3.8.12 Master List of PME Context Bits and Global Reset-Only Bits for CardBus (Function 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−22 3.8.13 Master List of Global Reset-Only Bits for 1394 OHCI (Function 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−23 3.9 Low-Voltage CardBus Card Detection . . . . . . . . . . . . . . . . . . . . . . . . . . 3−23 3.10 Power Switch Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−24 3.11 IEEE 1394 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−25 3.11.1 PHY Port Cable Connection . . . . . . . . . . . . . . . . . . . . . . . . . . 3−25 3.11.2 Crystal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−26 3.11.3 Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−27 PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1 4.1 PCI Configuration Registers (Function 0) . . . . . . . . . . . . . . . . . . . . . . . 4−1 4.2 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−2 4.3 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−2 4.4 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−3 4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−4 4.6 Class Code and Revision ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . 4−5 4.7 Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−5 4.8 Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−5 4.9 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−6 4.10 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−6 4.11 CardBus Socket Registers/ExCA Base Address Register . . . . . . . . . 4−6 4.12 Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−7 4.13 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−8 4.14 PCI Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−9 4.15 CardBus Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−9 4.16 Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−9 4.17 CardBus Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−10 4.18 CardBus Memory Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 4−10 4.19 CardBus Memory Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 4−11 4.20 CardBus I/O Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−11 Section 4.21 4.22 4.23 4.24 4.25 4.26 4.27 4.28 4.29 4.30 4.31 4.32 4.33 4.34 4.35 4.36 4.37 4.38 4.39 4.40 4.41 4.42 4.43 5 Title CardBus I/O Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PC Card 16-Bit I/F Legacy-Mode Base-Address Register . . . . . . . . . System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Event Status Register . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Event Enable Register . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multifunction Routing Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . Retry Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Card Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . . Power Management Control/Status Bridge Support Extensions Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.44 Serial Bus Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.45 Serial Bus Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.46 Serial Bus Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.47 Serial Bus Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Compatibility Registers (Function 0) . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 ExCA Identification and Revision Register . . . . . . . . . . . . . . . . . . . . . . 5.2 ExCA Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 ExCA Power Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 ExCA Interrupt and General Control Register . . . . . . . . . . . . . . . . . . . 5.5 ExCA Card Status-Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 ExCA Card Status-Change Interrupt Configuration Register . . . . . . . 5.7 ExCA Address Window Enable Register . . . . . . . . . . . . . . . . . . . . . . . . 5.8 ExCA I/O Window Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers . . . . 5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers . . . . 5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers . . . . . 5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers . . . . 5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers . . . Page 4−12 4−12 4−13 4−14 4−15 4−15 4−15 4−16 4−18 4−19 4−20 4−20 4−21 4−22 4−23 4−24 4−25 4−26 4−27 4−27 4−28 4−29 4−30 4−30 4−31 4−31 4−32 5−1 5−4 5−5 5−6 5−7 5−8 5−9 5−10 5−11 5−12 5−12 5−12 5−13 5−13 v Section 6 7 vi Title 5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers . . . 5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers . . . . 5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers . . . 5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers . . 5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers . 5.19 ExCA Card Detect and General Control Register . . . . . . . . . . . . . . . . 5.20 ExCA Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers . . . 5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers . . . 5.23 ExCA Memory Windows 0−4 Page Registers . . . . . . . . . . . . . . . . . . . CardBus Socket Registers (Function 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Socket Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Socket Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Socket Present State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Socket Force Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 Socket Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 Socket Power Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . OHCI Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Class Code and Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 Latency Timer and Class Cache Line Size Register . . . . . . . . . . . . . . 7.7 Header Type and BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8 OHCI Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9 TI Extension Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10 CardBus CIS Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.11 CardBus CIS Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.12 Subsystem Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.13 Power Management Capabilities Pointer Register . . . . . . . . . . . . . . . 7.14 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.15 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.16 MIN_GNT and MAX_LAT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.17 OHCI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.18 Capability ID and Next Item Pointer Registers . . . . . . . . . . . . . . . . . . . 7.19 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . 7.20 Power Management Control and Status Register . . . . . . . . . . . . . . . . 7.21 Power Management Extension Registers . . . . . . . . . . . . . . . . . . . . . . . 7.22 PCI PHY Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.23 PCI Miscellaneous Configuration Register . . . . . . . . . . . . . . . . . . . . . . 7.24 Link Enhancement Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.25 Subsystem Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 5−14 5−15 5−15 5−16 5−17 5−18 5−19 5−20 5−20 5−20 6−1 6−2 6−3 6−4 6−5 6−7 6−8 7−1 7−2 7−2 7−3 7−4 7−5 7−5 7−6 7−6 7−7 7−7 7−8 7−8 7−9 7−9 7−10 7−10 7−11 7−11 7−12 7−13 7−13 7−14 7−15 7−16 7−17 Section 8 Title OHCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 OHCI Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 GUID ROM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Asynchronous Transmit Retries Register . . . . . . . . . . . . . . . . . . . . . . . 8.4 CSR Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 CSR Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 CSR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7 Configuration ROM Header Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8 Bus Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.9 Bus Options Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.10 GUID High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.11 GUID Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.12 Configuration ROM Mapping Register . . . . . . . . . . . . . . . . . . . . . . . . . . 8.13 Posted Write Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.14 Posted Write Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.15 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.16 Host Controller Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.17 Self-ID Buffer Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.18 Self-ID Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.19 Isochronous Receive Channel Mask High Register . . . . . . . . . . . . . . 8.20 Isochronous Receive Channel Mask Low Register . . . . . . . . . . . . . . . 8.21 Interrupt Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.22 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.23 Isochronous Transmit Interrupt Event Register . . . . . . . . . . . . . . . . . . 8.24 Isochronous Transmit Interrupt Mask Register . . . . . . . . . . . . . . . . . . . 8.25 Isochronous Receive Interrupt Event Register . . . . . . . . . . . . . . . . . . . 8.26 Isochronous Receive Interrupt Mask Register . . . . . . . . . . . . . . . . . . . 8.27 Initial Bandwidth Available Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.28 Initial Channels Available High Register . . . . . . . . . . . . . . . . . . . . . . . . 8.29 Initial Channels Available Low Register . . . . . . . . . . . . . . . . . . . . . . . . . 8.30 Fairness Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.31 Link Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.32 Node Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.33 PHY Layer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.34 Isochronous Cycle Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.35 Asynchronous Request Filter High Register . . . . . . . . . . . . . . . . . . . . . 8.36 Asynchronous Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . 8.37 Physical Request Filter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . 8.38 Physical Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . 8.39 Physical Upper Bound Register (Optional Register) . . . . . . . . . . . . . . 8.40 Asynchronous Context Control Register . . . . . . . . . . . . . . . . . . . . . . . . 8.41 Asynchronous Context Command Pointer Register . . . . . . . . . . . . . . Page 8−1 8−4 8−5 8−6 8−6 8−7 8−7 8−8 8−8 8−9 8−10 8−10 8−11 8−11 8−12 8−12 8−13 8−14 8−15 8−16 8−17 8−18 8−20 8−22 8−23 8−24 8−25 8−25 8−26 8−26 8−27 8−28 8−29 8−30 8−31 8−32 8−34 8−35 8−37 8−37 8−38 8−39 vii Section Title Page 8.42 Isochronous Transmit Context Control Register . . . . . . . . . . . . . . . . . . 8−40 8.43 Isochronous Transmit Context Command Pointer Register . . . . . . . . 8−41 8.44 Isochronous Receive Context Control Register . . . . . . . . . . . . . . . . . . 8−41 8.45 Isochronous Receive Context Command Pointer Register . . . . . . . . 8−43 8.46 Isochronous Receive Context Match Register . . . . . . . . . . . . . . . . . . . 8−44 9 TI Extension Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9−1 9.1 DV and MPEG2 Timestamp Enhancements . . . . . . . . . . . . . . . . . . . . . 9−1 9.2 Isochronous Receive Digital Video Enhancements . . . . . . . . . . . . . . . 9−2 9.3 Isochronous Receive Digital Video Enhancements Register . . . . . . . 9−2 9.4 Link Enhancement Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9−4 9.5 Timestamp Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9−5 10 PHY Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10−1 10.1 Base Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10−1 10.2 Port Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10−4 10.3 Vendor Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10−5 10.4 Vendor-Dependent Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10−6 10.5 Power-Class Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10−7 11 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−1 11.1 Absolute Maximum Ratings Over Operating Temperature Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−1 11.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 11−2 11.3 Electrical Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−3 11.4 Electrical Characteristics Over Recommended Ranges of Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−4 11.4.1 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−4 11.4.2 Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−4 11.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−4 11.5 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . 11−5 11.6 Switching Characteristics for PHY Port Interface . . . . . . . . . . . . . . . . . 11−5 11.7 Operating, Timing, and Switching Characteristics of XI . . . . . . . . . . . 11−5 11.8 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . . . . . . . . . . 11−5 11.8.1 CardBus PC Card Clock Specifications . . . . . . . . . . . . . . . . 11−6 11.8.2 3.3-V Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−6 12 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12−1 viii List of Illustrations Figure 2−1 2−2 2−3 3−1 3−2 3−3 3−4 3−5 3−6 3−7 3−8 3−9 3−10 3−11 3−12 3−13 3−14 3−15 3−16 3−17 3−18 3−19 3−20 5−1 5−2 6−1 11−1 11−2 Title PCI4510 GHK Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI4510 RGVF Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI4510 PDV-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . PCI4510 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-State Bidirectional Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Zoomed Video Implementation Using the PCI4510 Device . . . . . . . . . . . Zoomed Video Switching Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sample Application of SPKROUT and CAUDPWM . . . . . . . . . . . . . . . . . . Two Sample LED Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial-Bus Start/Stop Conditions and Bit Transfers . . . . . . . . . . . . . . . . . . Serial-Bus Protocol Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial-Bus Protocol − Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial-Bus Protocol − Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Interface Doubleword Data Collection . . . . . . . . . . . . . . . . . . . . IRQ Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Diagram of Suspend Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RI_OUT Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram of a Status/Enable Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TP Cable Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Compliant DC Isolated Outer Shield Termination . . . . . . . . . . . . . Non-DC Isolated Outer Shield Termination . . . . . . . . . . . . . . . . . . . . . . . . . Load Capacitance for the PCI4510 PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Crystal and Capacitor Layout . . . . . . . . . . . . . . . . . . . . . . . ExCA Register Access Through I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Register Access Through Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . Accessing CardBus Socket Registers Through PCI Memory . . . . . . . . . . Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CardBus PC Card Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 2−2 2−3 2−4 3−1 3−2 3−5 3−5 3−7 3−8 3−9 3−9 3−10 3−10 3−10 3−16 3−19 3−20 3−22 3−25 3−25 3−26 3−27 3−27 5−1 5−1 6−1 11−4 11−6 ix List of Tables Table 2−1 2−2 2−3 2−4 2−5 2−6 2−7 2−8 2−9 2−10 2−11 2−12 2−13 2−14 2−15 2−16 2−17 2−18 2−19 3−1 3−2 3−3 3−4 3−5 3−6 3−7 3−8 3−9 3−10 3−11 3−12 3−13 3−14 4−1 4−2 4−3 4−4 x Title Signal Names Sorted by PDV Terminal Number . . . . . . . . . . . . . . . . . . . . Signal Names Sorted by GHK Terminal Number . . . . . . . . . . . . . . . . . . . . Signal Names Sorted by RGVF Terminal Number . . . . . . . . . . . . . . . . . . . CardBus PC Card Signal Names Sorted Alphabetically . . . . . . . . . . . . . . 16-Bit PC Card Signal Names Sorted Alphabetically . . . . . . . . . . . . . . . . . Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PC Card Power Switch Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multifunction and Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . 16-Bit PC Card Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . 16-Bit PC Card Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . CardBus PC Card Interface System Terminals . . . . . . . . . . . . . . . . . . . . . . CardBus PC Card Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . CardBus PC Card Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . IEEE 1394 Physical Layer Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Smart Card and Memory Card Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Bus Master Command Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PC Card Card-Detect and Voltage-Sense Connections . . . . . . . . . . . . . . Integrated Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Loading Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI4510 Registers Used to Program Serial-Bus Devices . . . . . . . . . . . . . Interrupt Mask and Flag Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PC Card Interrupt Events and Description . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Pin Register Cross Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Requirements for Internal/External 1.8-V Core Power Supply . . . . . . . . . Power-Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TPS2221 Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TPS2211A Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Field Access Tag Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function 0 PCI Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 2−5 2−7 2−9 2−11 2−13 2−15 2−15 2−15 2−16 2−17 2−18 2−19 2−20 2−21 2−22 2−23 2−24 2−25 2−25 3−2 3−4 3−7 3−8 3−11 3−13 3−14 3−14 3−16 3−17 3−18 3−21 3−24 3−24 4−1 4−1 4−3 4−4 Table 4−5 4−6 4−7 4−8 4−9 4−10 4−11 4−12 4−13 4−14 4−15 4−16 4−17 4−18 4−19 4−20 4−21 4−22 4−23 4−24 4−25 5−1 5−2 5−3 5−4 5−5 5−6 5−7 5−8 5−9 5−10 5−11 5−12 5−13 5−14 5−15 6−1 6−2 6−3 Title Secondary Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Interrupt Pin Register—Read-Only INTPIN Per Function . . . . . . . . . Bridge Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Event Status Register Description . . . . . . . . . . . . . . . . . General-Purpose Event Enable Register Description . . . . . . . . . . . . . . . . General-Purpose Input Register Description . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Output Register Description . . . . . . . . . . . . . . . . . . . . . . Multifunction Routing Status Register Description . . . . . . . . . . . . . . . . . . . Retry Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Card Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostic Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Capabilities Register Description . . . . . . . . . . . . . . . Power Management Control/Status Register Description . . . . . . . . . . . . . Power Management Control/Status Bridge Support Extensions Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Bus Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Bus Index Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Bus Slave Address Register Description . . . . . . . . . . . . . . . . . . . . . Serial Bus Control and Status Register Description . . . . . . . . . . . . . . . . . . ExCA Registers and Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Identification and Revision Register Description . . . . . . . . . . . . . . . ExCA Interface Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . ExCA Power Control Register Description—82365SL Support . . . . . . . . ExCA Power Control Register Description—82365SL-DF Support . . . . . ExCA Interrupt and General Control Register Description . . . . . . . . . . . . ExCA Card Status-Change Register Description . . . . . . . . . . . . . . . . . . . . ExCA Card Status-Change Interrupt Configuration Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Address Window Enable Register Description . . . . . . . . . . . . . . . . ExCA I/O Window Control Register Description . . . . . . . . . . . . . . . . . . . . . ExCA Memory Windows 0−4 Start-Address High-Byte Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Memory Windows 0−4 End-Address High-Byte Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Memory Windows 0−4 Offset-Address High-Byte Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Card Detect and General Control Register Description . . . . . . . . . ExCA Global Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Socket Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Socket Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 4−8 4−13 4−14 4−16 4−18 4−19 4−20 4−20 4−21 4−22 4−23 4−24 4−25 4−26 4−28 4−29 4−30 4−30 4−31 4−31 4−32 5−2 5−4 5−5 5−6 5−6 5−7 5−8 5−9 5−10 5−11 5−14 5−15 5−17 5−18 5−19 6−1 6−2 6−3 xi Table 6−4 6−5 6−6 6−7 7−1 7−2 7−3 7−4 7−5 7−6 7−7 7−8 7−9 7−10 7−11 7−12 7−13 7−14 7−15 7−16 7−17 7−18 7−19 7−20 7−21 8−1 8−2 8−3 8−4 8−5 8−6 8−7 8−8 8−9 8−10 8−11 8−12 8−13 8−14 8−15 8−16 8−17 8−18 xii Title Socket Present State Register Description . . . . . . . . . . . . . . . . . . . . . . . . . Socket Force Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . Socket Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Socket Power Management Register Description . . . . . . . . . . . . . . . . . . . Function 1 Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class Code and Revision ID Register Description . . . . . . . . . . . . . . . . . . . Latency Timer and Class Cache Line Size Register Description . . . . . . . Header Type and BIST Register Description . . . . . . . . . . . . . . . . . . . . . . . . OHCI Base Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . TI Base Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Subsystem Identification Register Description . . . . . . . . . . . . . . . . . . . . . . Interrupt Line Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Interrupt Pin Register—Read-Only INTPIN Per Function . . . . . . . . . MIN_GNT and MAX_LAT Register Description . . . . . . . . . . . . . . . . . . . . . OHCI Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capability ID and Next Item Pointer Registers Description . . . . . . . . . . . . Power Management Capabilities Register Description . . . . . . . . . . . . . . . Power Management Control and Status Register Description . . . . . . . . . Power Management Extension Registers Description . . . . . . . . . . . . . . . . PCI PHY Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Link Enhancement Control Register Description . . . . . . . . . . . . . . . . . . . . Subsystem Access Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . OHCI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OHCI Version Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GUID ROM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Transmit Retries Register Description . . . . . . . . . . . . . . . . CSR Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration ROM Header Register Description . . . . . . . . . . . . . . . . . . . . Bus Options Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration ROM Mapping Register Description . . . . . . . . . . . . . . . . . . . Posted Write Address Low Register Description . . . . . . . . . . . . . . . . . . . . Posted Write Address High Register Description . . . . . . . . . . . . . . . . . . . . Host Controller Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . Self-ID Count Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Receive Channel Mask High Register Description . . . . . . . Isochronous Receive Channel Mask Low Register Description . . . . . . . . Interrupt Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Transmit Interrupt Event Register Description . . . . . . . . . . . Isochronous Receive Interrupt Event Register Description . . . . . . . . . . . Page 6−4 6−6 6−7 6−8 7−1 7−3 7−4 7−5 7−5 7−6 7−6 7−7 7−8 7−9 7−10 7−10 7−11 7−11 7−12 7−13 7−13 7−14 7−15 7−16 7−17 8−1 8−4 8−5 8−6 8−7 8−8 8−9 8−11 8−11 8−12 8−13 8−15 8−16 8−17 8−18 8−20 8−22 8−24 Table 8−19 8−20 8−21 8−22 8−23 8−24 8−25 8−26 8−27 8−28 8−29 8−30 8−31 8−32 8−33 8−34 8−35 9−1 9−2 9−3 9−4 10−1 10−2 10−3 10−4 10−5 10−6 10−7 10−8 10−9 Title Initial Bandwidth Available Register Description . . . . . . . . . . . . . . . . . . . . . Initial Channels Available High Register Description . . . . . . . . . . . . . . . . . Initial Channels Available Low Register Description . . . . . . . . . . . . . . . . . Fairness Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Link Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node Identification Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . PHY Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Cycle Timer Register Description . . . . . . . . . . . . . . . . . . . . . . Asynchronous Request Filter High Register Description . . . . . . . . . . . . . Asynchronous Request Filter Low Register Description . . . . . . . . . . . . . . Physical Request Filter High Register Description . . . . . . . . . . . . . . . . . . . Physical Request Filter Low Register Description . . . . . . . . . . . . . . . . . . . Asynchronous Context Control Register Description . . . . . . . . . . . . . . . . . Asynchronous Context Command Pointer Register Description . . . . . . . Isochronous Transmit Context Control Register Description . . . . . . . . . . Isochronous Receive Context Control Register Description . . . . . . . . . . . Isochronous Receive Context Match Register Description . . . . . . . . . . . . TI Extension Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Receive Digital Video Enhancements Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Link Enhancement Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Timestamp Offset Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . Base Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Base Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 0 (Port Status) Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . Page 0 (Port Status) Register Field Descriptions . . . . . . . . . . . . . . . . . . . . Page 1 (Vendor ID) Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . Page 1 (Vendor ID) Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . Page 7 (Vendor-Dependent) Register Configuration . . . . . . . . . . . . . . . . . Page 7 (Vendor-Dependent) Register Field Descriptions . . . . . . . . . . . . . Power Class Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 8−25 8−26 8−26 8−27 8−28 8−29 8−30 8−31 8−32 8−34 8−35 8−37 8−38 8−39 8−40 8−41 8−44 9−1 9−2 9−4 9−5 10−1 10−2 10−4 10−4 10−5 10−5 10−6 10−6 10−7 xiii xiv 1 Introduction The Texas Instruments PCI4510 device is an integrated single-socket PC Card controller with an IEEE 1394 open host controller link-layer controller (LLC) and two-port 1394 PHY. This high performance integrated solution provides the latest in both PC Card and IEEE 1394 technology. 1.1 Description The Texas Instruments PCI4510 device is compliant with PCI Local Bus Specification. Function 0 provides the independent PC Card socket controller compliant with the latest PC Card Standards. The PCI4510 device provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports either 16-bit or CardBus PC Cards in the socket, powered at 5 V or 3.3 V, as required. There are no PCMCIA card and socket service software changes required to move systems from the existing CardBus socket controller to the PCI4510 device. The PCI4510 device is register compatible with the Intel 82365SL–DF ExCA controller and implements the host interface defined in the PC Card Standard. The PCI4510 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and the pipeline architecture provides an unsurpassed performance level with sustained bursting. The PCI4510 device can be programmed to accept posted writes to improve bus utilization. All card signals are internally buffered to allow hot insertion and removal without external buffering. Function 1 of the PCI4510 device is an integrated IEEE 1394a-2000 open host controller interface (OHCI) PHY/link-layer controller (LLC) device that is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management Interface Specification, IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller Interface Specification. It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s. The PCI4510 device provides two 1394 ports that have separate cable bias (TPBIAS). The PCI4510 device also supports the IEEE Std 1394a-2000 power-down features for battery-operated applications and arbitration enhancements. As required by the 1394 Open Host Controller Interface Specification and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI, and it provides plug-and-play (PnP) compatibility. Furthermore, the PCI4510 device is compliant with the PCI Bus Power Management Interface Specification as specified by the PC 2001 Design Guide requirements. The PCI4510 device supports the D0, D1, D2, and D3 power states. The PCI4510 design provides PCI bus master bursting, and it is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are provided to buffer the IEEE 1394 data. The PCI4510 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The PCI4510 device also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal arbitration, and bus-holding buffers. The PCI4510 PHY-layer provides the digital and analog transceiver functions needed to implement a two-port node in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The PCI4510 PHY-layer requires only an external 24.576-MHz crystal as a reference for the cable ports. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals that control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal is supplied to the integrated LLC for synchronization and is used for resynchronization of the received data. Data bits to be transmitted through the cable ports are received from the integrated LLC and are latched internally in 1−1 synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304M, 196.608M, or 393.216M bits/s (referred to as S100, S200, or S400 speeds, respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the twisted-pair B (TPB) cable pair(s), and the encoded strobe information is transmitted differentially on the twisted-pair A (TPA) cable pair(s). Various implementation-specific functions and general-purpose inputs and outputs are provided through several multifunction terminals. These terminals present a system with options, such as PCI LOCK and parallel IRQs. ACPI-complaint general-purpose events may be programmed and controlled through the multifunction terminals, and an ACPI-compliant programming interface is included for the general-purpose inputs and outputs. The PCI4510 device is compliant with the latest PCI Bus Power Management Specification, and provides several low-power modes, which enable the host power system to further reduce power consumption. The PCI4510 device also has a four-pin interface compatible with both the TI TPS2211A and TPS2221 power switches. An advanced CMOS process achieves low power consumption and allows the PCI4510 device to operate at PCI clock rates up to 33 MHz. 1.2 Features The PCI4510 device supports the following features: 1−2 • PC Card Standard 8.0 compliant • PCI Bus Power Management Interface Specification 1.1 compliant • Advanced Configuration and Power Interface Specification 2.0 compliant • PCI Local Bus Specification Revision 2.2 compliant • PC 98/99 and PC2001 compliant • Compliant with the PCI Bus Interface Specification for PCI-to-CardBus Bridges • Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus and IEEE Std 1394a-2000 • Fully compliant with 1394 Open Host Controller Interface Specification 1.1 • Compatible with both TPS2211A and TPS2221 PC Card power switches • 1.8-V core logic and 3.3-V I/O cells with internal voltage regulator to generate 1.8-V core VCC • Universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments • Supports PC Card or CardBus with hot insertion and removal • Supports 132-MBps burst transfers to maximize data throughput on both the PCI bus and the CardBus • Supports serialized IRQ with PCI interrupts • Programmable multifunction terminals • Serial ROM interface for loading subsystem ID and subsystem vendor ID • ExCA-compatible registers are mapped in memory or I/O space • Intel 82365SL–DF register compatible • Supports ring indicate, SUSPEND, PCI CCLKRUN protocol, and PCI bus lock (LOCK) • Provides VGA/palette memory and I/O, and subtractive decoding options, LED activity terminals • Fully interoperable with FireWiret and i.LINKt implementations of IEEE Std 1394 • Compliant with Intel Mobile Power Guideline 2000 • Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume • Power-down features to conserve energy in battery-powered applications include: automatic device power down during suspend, PCI power management for link-layer and inactive ports powered down, ultralow-power sleep mode • Two IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and 400M bits/s • Cable ports monitor line conditions for active connection to remote node • Cable power presence monitoring • Separate cable bias (TPBIAS) for each port • Physical write posting of up to three outstanding transactions • PCI burst transfers and deep FIFOs to tolerate large host latency • External cycle timer control for customized synchronization • Extended resume signaling for compatibility with legacy DV components • PHY-Link logic performs system initialization and arbitration functions • PHY-Link encode and decode functions included for data-strobe bit level encoding • PHY-Link incoming data resynchronized to local clock • Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, and 400M bits/s • Node power class information signaling for system power management • Register bits give software control of contender bit, power class bits, link active control bit, and IEEE Std 1394a-2000 features • Isochronous receive dual-buffer mode • Out-of-order pipelining for asynchronous transmit requests • Register access fail interrupt when the PHY SCLK is not active • PCI power-management D0, D1, D2, and D3 power states • Initial bandwidth available and initial channels available registers • PME support per 1394 Open Host Controller Interface Specification • Advanced submicron, low-power CMOS technology 1.3 Related Documents • Advanced Configuration and Power Interface (ACPI) Specification (Revision 2.0) • 1394 Open Host Controller Interface Specification (Release 1.1) • IEEE Standard for a High Performance Serial Bus (IEEE Std 1394-1995) • IEEE Standard for a High Performance Serial Bus—Amendment 1 (IEEE Std 1394a-2000) • PC Card Standard—Electrical Specification (Release 8.0) • PC 2001 Design Guide • PCI Bus Power Management Interface Specification (Revision 1.1) • PCI Local Bus Specification (Revision 2.2) 1−3 • Mobile Power Guidelines 2000 • Serial Bus Protocol 2 (SBP-2) • Serialized IRQ Support for PCI Systems • PCI Mobile Design Guide • PCI Bus Power Management Interface Specification for PCI to CardBus Bridges • PCI14xx Implementation Guide for D3 Wake-Up • PCI to PCMCIA CardBus Bridge Register Description • Texas Instruments TPS2221 product data sheet, SLVS419 • Texas Instruments TPS2211A product data sheet, SLVS282 1.4 Trademarks Intel is a trademark of Intel Corporation. TI and MicroStar BGA are trademarks of Texas Instruments. FireWire is a trademark of Apple Computer, Inc. i.LINK is a trademark of Sony Corporation of America. Other trademarks are the property of their respective owners. 1.5 Ordering Information ORDERING NUMBER NAME VOLTAGE PACKAGE PCI4510 PC Card and integrated 1394a-2000 OHCI two-port PHY/link-layer controller 3.3-V, 5-V tolerant I/Os 208-terminal LQFP (PDV) 209-ball PBGA (GHK/ZHK) 224-ball PBGA (RGVF/RZVF) 1.6 PCI4510 Data Manual Document History 1−4 DATE PAGE NUMBER 01/2003 1−2 Added a power-switch-compatibility item to the features list REVISION 03/2003 2−1 Added description for ZHK package 01/2003 2−25 Swapped terminal names for ANALOGVCC and ANALOGGND to avoid confusion 01/2003 3−2 Added new subsection 3.4.2 to describe GRST during power up 01/2003 3−10 Modified byte read diagram (Figure 3−10) to better reflect a read transaction to the EEPROM 01/2003 3−21 Modified description of power management capabilities register. This register is not a static read-only register. 08/2004 Chapters 1, 2, 3, 4, 12 Added RGVF/RZVF package and pinout information 2 Terminal Descriptions The PCI4510 device is available in five packages, a 208-terminal quad flatpack (PDV), two 209-terminal MicroStar BGA packages (GHK/ZHK), and two 224-terminal MicroStar BGA packages (RGVF/RZVF). The GHK and ZHK packages are mechanically and electrically identical, but the ZHK is a lead-free design. Throughout the remainder of this manual, only the GHK package designator is used for either the GHK or the ZHK package. The RGVF and RZVF packages are mechanically and electrically identical, but the RZVF is a lead-free design. Throughout the remainder of this manual, only the RGVF package designator is used for either the RGVF or the RZVF package. The terminal layout for the GHK package is shown in Figure 2−1. The terminal layout for the RGVF package is shown in Figure 2−2. The terminal layout for the PDV package is shown in Figure 2−3. 2−1 W PAR VCCP GND AD7 VCC AD3 PC1 TPB0N TPA0N R0 TPB1N TPA1N V AD13 AD11 C/BE0 AD4 AD2 PC0 TPB0P TPA0P R1 TPB1P TPA1P U C/BE1 AD12 AD8 AD5 AD1 TEST0 T SERR R VCC P AD16 C/BE2 IRDY N GND AD19 M VCC L PHY_ TEST _MA GND MC_ PLLGND RSVD MC_ RSVD MC_ RSVD MC_ RSVD MC_ RSVD MC_ RSVD MC_ RSVD MC_ RSVD MC_ RSVD CAD2 //D11 CAD0 //D3 CCD1 //CD1 VR_ PORT VCC CAD6 //D13 CAD3 //D5 CAD4 //D12 CAD1 //D4 GND CAD8 //D15 CC/BE0 //CE1 CAD7 //D7 CRSVD //D14 CAD5 //D6 VR_EN MFUNC6 CAD11 //OE CAD12 //A11 CAD10 //CE2 CAD9 //A10 VCC MFUNC4 MFUNC1 VCCCB CC/BE1 //A8 CAD15 CAD13 //IOWR //IORD GND CPAR //A13 CPERR //A14 CRSVD CAD16 //A18 //A17 CAD14 //A9 CSTOP CBLOCK //A19 //A20 VCC STOP TRDY AD14 AD9 PC2 CPS AD18 FRAME AD17 AD23 AD22 AD20 AD21 VCCP AD25 AD24 IDSEL C/BE3 K GND AD29 AD28 AD27 AD26 J GNT REQ RI_OUT /PME AD31 AD30 H PCLK GRST PRST G VCC VR_ SUSPEND PORT D SDA SCL NC CNA TEST1 SPKROUT NC XO AD0 GND NC XI AD6 DEVSEL PERR MFUNC5 MFUNC3 MFUNC2 ANALOG ANALOG ANALOG VCC GND GND FILTER1 AD10 E ANALOG ANALOG ANALOG TPBIAS0 TPBIAS1 GND VCC VCC FILTER0 AD15 F NC NC NC Bottom View MFUNC0 CLK_48 _RSVD SC_ RSVD CRSVD CAD27 CAUDIO CAD26 //BVD2 //D2 //D0 //A0 NC VD1/ VCCD0 SC_ RSVD CAD31 //D10 CAD28 CSERR CAD25 //D8 //A1 //WAIT CVS2 //VS2 CAD21 //A5 CIRDY //A15 PLLVCC CAD18 CTRDY //A7 //A22 CGNT// WE VD2/ VPPD1 SC_ RSVD SC_ RSVD CAD30 //D9 B VD0/ VCCD1 SC_ RSVD SC_ RSVD CAD29 CCLKRUN CVS1 //WP //D1 //VS1 VD3/ VPPD0 VCC SC_ RSVD GND VCC CSTSCHG //BVD1 GND VCCCB CAD23 //A3 VCC CAD19 //A25 GND CDEVSEL //A21 4 5 6 7 8 9 10 11 12 13 14 15 16 A 1 2 3 CCD2 //CD2 CINT// CAD24 //A2 READY C CAD22 //A4 CAD20 CC/BE2 //A6 //A12 CC/BE3 CREQ// CRST// CAD17 CFRAME //A23 //REG INPACK RESET //A24 Figure 2−1. PCI4510 GHK Terminal Diagram 2−2 CCLK //A16 17 18 19 W AD27 VCCP C/BE3 IDSEL AD19 C/BE2 STOP C/BE1 VCCP C/BE0 AD4 AD0 TPB0N TPA0N TPB1N AD29 AD26 AD24 AD23 AD18 FRAME PERR AD15 AD11 AD7 AD3 PC2 TPB0P TPA0P TPB1P AD30 U REQ T GRST GNT MFUNC SUSPE 6 ND MFUNC MFUNC MFUNC 2 3 4 VD2/ VD3/ MFUNC MFUNC VPPD1 VPPD0 0 5 SDA SCL P N M TPA1P PLLVCC R0 R1 RI_OUT FILTER FILTER /PME 0 1 XI XO VCC AD31 AD28 AD25 J H G B AD16 SC_ SC_ RSVD RSVD TRDY AD20 AD14 AD13 AD10 AD9 AD6 AD5 PAR AD2 ANALOG TPBIAS ANALOG TPBIAS GND 0 GND 1 PC1 ANALOG ANALOG PHY_ VCC VCC TEST_MA PC0 TEST0 GND CNA ANALO DEVSEL AD12 AD8 AD1 VCC GND VCC VCC CPS VCC NC GND GND GND GND GND NC VCC GND GND GND VCC NC VCC GND GND GND VCC NC VCC VCC VCC VCC VCC CAD20 CPAR // CAD14 CC/BE0 // A6 A13 // A9 // CE1 MC_ CC/BE2 CPERR CAD6 // RSVD // A12 // A14 D13 GGND VR_ 1 VD0/ VD1/ SPKR VCCD1 VCCD0 OUT SC_ SC_ SC_ SC_ MC_ SC_ RSVD RSVD RSVD RSVD RSVD VR_ VR_EN MC_ MC_ MC_ RSVD RSVD RSVD MC_ MC_ MC_ MC_ RSVD RSVD RSVD RSVD GND GND PORT GND NC GND NC CCD2 // CAD24 CREQ // CVS2 // CCLK // CBLOC CAD15 CAD8 // CAD3 // CAD0 // CD2 // A2 INPACK VS2 A16 K // A19 // IOWR D15 D5 D3 NC CAD31 CRSVD CAD29 // D10 // D2 // D1 CAD30 CAD28 CCLKRU CINT // CC/BE3 CAD22 CAD19 CFRAM CDEVSE CRSVD CAD13 CAD11 CAD7 // CAD4 // CCD1 // // D9 // D8 N // WP READY // REG // A4 // A25 E // A23 L // A21 // A18 // IORD // OE D7 D12 CD1 CAD27 CSTSCH CSERR CAD26 CAD23 CAD21 CAD18 CIRDY CGNT // CC/BE1 CAD12 CAD10 CRSVD CAD1 // // D0 G // BVD1 // WAIT // A0 // A3 // A5 // A7 // A15 WE // A8 // A11 // CE2 // D14 D4 CAUDIO CVS1 // CAD25 CRST // CAD17 CTRDY CSTOP CAD16 CAD9 // CAD5 // CAD2 // // BVD2 VS1 // A1 RESET // A24 // A22 // A20 // A17 A10 D6 D11 2 3 4 6 7 8 9 10 12 13 14 A 1 NC VCC RSVD PORT SERR PLL PCLK E C IRDY MFUNC F D AD17 AD21 CLK_48 _RSVD AD22 PRST L K TPA1N ANALOG V R NC NC VCCCB 5 VCCCB 11 NC NC TEST1 15 16 17 18 19 Figure 2−2. PCI4510 RGVF Terminal Diagram 2−3 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 CGNT//WE CSTOP//A20 CPERR//A14 CBLOCK//A19 CPAR//A13 VCC CRSVD//A18 CC/BE1//A8 CAD16//A17 CAD14//A9 VCCCB CAD15//IOWR CAD13//IORD GND CAD12//A11 CAD11//OE CAD10//CE2 CAD9//A10 VCC CC/BE0//CE1 CAD8//D15 CAD7//D7 CRSVD//D14 CAD5//D6 CAD6//D13 CAD3//D5 CAD4//D12 CAD1//D4 GND CAD2//D11 CAD0//D3 CCD1//CD1 VR_PORT VCC MC_RSVD MC_RSVD MC_RSVD MC_RSVD MC_RSVD MC_RSVD MC_RSVD MC_RSVD GND MC_RSVD PHY_TEST_MA CNA XO XI PLLGND PLLVCC FILTER1 FILTER0 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 PCI4510 SDA SCL MFUNC0 MFUNC1 SPKROUT GND MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6 SUSPEND VR_PORT VCC VR_EN PRST GRST PCLK GNT REQ RI_OUT/PME AD31 AD30 GND AD29 AD28 AD27 AD26 VCCP AD25 AD24 C/BE3 IDSEL VCC AD23 AD22 AD21 AD20 GND AD19 AD18 AD17 AD16 C/BE2 FRAME IRDY VCC TRDY DEVSEL STOP PERR SERR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 CDEVSEL//A21 CCLK//A16 CTRDY//A22 CIRDY//A15 CFRAME//A23 GND CC/BE2//A12 CAD17//A24 CAD18//A7 CAD19//A25 CVS2//VS2 CAD20//A6 CRST//RESET VCC CAD21//A5 CAD22//A4 CREQ//INPACK CAD23//A3 VCCCB CC/BE3//REG CAD24//A2 CAD25//A1 CAD26//A0 GND CVS1//VS1 CINT//READY(IREQ) CSERR//WAIT CAUDIO//BVD2(SPKR) CSTSCHG//BVD1(STSCHG/RI) CCLKRUN//WP(IOIS16) CCD2//CD2 CAD27//D0 CAD28//D8 VCC CAD29//D1 CAD30//D9 CRSVD//D2 CAD31//D10 GND SC_RSVD SC_RSVD SC_RSVD SC_RSVD SC_RSVD SC_RSVD SC_RSVD VCC CLK_48_RSVD VD0/VCCD1 VD1/VCCD0 VD2/VPPD1 VD3/VPPD0 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 PDV LOW-PROFILE QUAD FLAT PACKAGE (LQFP) TOP VIEW Figure 2−3. PCI4510 PDV-Package Terminal Diagram 2−4 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 NC TPBIAS1 NC TPA1P NC TPA1N ANALOGVCC ANALOGGND TPB1P TPB1N NC ANALOGVCC R1 R0 ANALOGGND NC TPBIAS0 TPA0P TPA0N ANALOGVCC NC ANALOGGND TPB0P TPB0N CPS TEST1 TEST0 PC0 PC1 PC2 AD0 AD1 AD2 AD3 VCC AD4 AD5 AD6 AD7 C/BE0 AD8 AD9 GND AD10 AD11 AD12 VCCP AD13 AD14 AD15 C/BE1 PAR Table 2−1, Table 2−2, and Table 2−3 list the terminal assignments arranged in terminal-number order, with corresponding signal names for both CardBus and 16-bit PC Cards; Table 2−1 is for terminals on the PDV package, Table 2−2 is for terminals on the GHK package, and Table 2−3 is for terminals on the RGVF package. Table 2−4 and Table 2−5 list the terminal assignments arranged in alphanumerical order by signal name, with corresponding terminal numbers for the PDV, GHK, and RGVF packages; Table 2−4 is for CardBus signal names and Table 2−5 is for 16-bit PC Card signal names. Terminal E5 on the GHK package is an identification ball used for device orientation; it has no internal connection within the device. Table 2−1. Signal Names Sorted by PDV Terminal Number TERM. NO. SIGNAL NAME CARDBUS 16-BIT TERM. NO. SIGNAL NAME CARDBUS 16-BIT SIGNAL NAME TERM. NO. CARDBUS 16-BIT 1 SDA SDA 37 AD21 AD21 73 AD1 AD1 2 SCL SCL 38 AD20 AD20 74 AD0 AD0 3 MFUNC0 MFUNC0 39 GND GND 75 PC2 PC2 4 MFUNC1 MFUNC1 40 AD19 AD19 76 PC1 PC1 5 SPKROUT SPKROUT 41 AD18 AD18 77 PC0 PC0 6 GND GND 42 AD17 AD17 78 TEST0 TEST0 7 MFUNC2 MFUNC2 43 AD16 AD16 79 TEST1 TEST1 8 MFUNC3 MFUNC3 44 C/BE2 C/BE2 80 CPS CPS 9 MFUNC4 MFUNC4 45 FRAME FRAME 81 TPB0N TPB0N 10 MFUNC5 MFUNC5 46 IRDY IRDY 82 TPB0P TPB0P 11 MFUNC6 MFUNC6 47 ANALOGGND ANALOGGND SUSPEND SUSPEND 48 VCC TRDY 83 12 VCC TRDY 84 NC NC 13 VR_PORT VR_PORT 49 DEVSEL DEVSEL 85 14 VCC VR_EN 50 STOP STOP 86 ANALOGVCC TPA0N 15 VCC VR_EN ANALOGVCC TPA0N 51 PERR PERR 87 TPA0P TPA0P 16 PRST PRST 52 SERR SERR 88 TPBIAS0 TPBIAS0 17 GRST GRST 53 PAR PAR 89 NC NC 18 PCLK PCLK 54 C/BE1 C/BE1 90 ANALOGGND ANALOGGND 19 GNT GNT 55 AD15 AD15 91 R0 R0 20 REQ REQ 56 AD14 AD14 92 R1 R1 21 RI_OUT/PME RI_OUT/PME 57 AD13 AD13 93 22 AD31 AD31 58 94 AD30 AD30 59 VCCP AD12 ANALOGVCC NC 23 VCCP AD12 ANALOGVCC NC 95 TPB1N TPB1N 24 GND GND 60 AD11 AD11 96 TPB1P TPB1P 25 AD29 AD29 61 AD10 AD10 97 ANALOGGND ANALOGGND 26 AD28 AD28 62 GND GND 98 27 AD27 AD27 63 AD9 AD9 99 ANALOGVCC TPA1N ANALOGVCC TPA1N 28 AD26 AD26 64 AD8 AD8 100 NC NC 29 VCCP AD25 65 C/BE0 C/BE0 101 TPA1P TPA1P 30 VCCP AD25 66 AD7 AD7 102 NC NC 31 AD24 AD24 67 AD6 AD6 103 TPBIAS1 TPBIAS1 32 C/BE3 C/BE3 68 AD5 AD5 104 NC NC 33 IDSEL IDSEL 69 AD4 AD4 105 FILTER0 FILTER0 34 VCC AD23 70 VCC AD3 FILTER1 FILTER1 71 VCC AD3 106 35 VCC AD23 107 36 AD22 AD22 72 AD2 AD2 108 PLLVCC PLLGND PLLVCC PLLGND 2−5 Table 2−1. Signal Names Sorted by PDV Terminal Number (Continued) SIGNAL NAME TERM. NO. 2−6 CARDBUS 16-BIT TERM. NO. SIGNAL NAME CARDBUS 16-BIT TERM. NO. SIGNAL NAME CARDBUS 16-BIT 109 XI XI 143 GND GND 177 CAD24 A2 110 XO XO 144 CAD13 IORD 178 CAD25 A1 111 CNA CNA 145 CAD15 IOWR 179 CAD26 A0 112 PHY_TEST_MA PHY_TEST_MA 146 GND GND MC_RSVD MC_RSVD 147 VCCCB A9 180 113 VCCCB CAD14 181 CVS1 VS1 114 GND GND 148 CAD16 A17 182 CINT READY(IREQ) 115 MC_RSVD MC_RSVD 149 CC/BE1 A8 183 CSERR WAIT 116 MC_RSVD MC_RSVD 150 CRSVD A18 184 CAUDIO BVD2(SPKR) 117 MC_RSVD MC_RSVD 151 CSTSCHG BVD1(STSCHG/RI) MC_RSVD MC_RSVD 152 VCC A13 185 118 VCC CPAR 186 CCLKRUN WP(IOIS1) 119 MC_RSVD MC_RSVD 153 CBLOCK A19 187 CCD2 CD2 120 MC_RSVD MC_RSVD 154 CPERR A14 188 CAD27 D0 121 MC_RSVD MC_RSVD 155 CSTOP A20 189 CAD28 D8 122 MC_RSVD MC_RSVD 156 CGNT WE 190 123 VCC VR_PORT 157 CDEVSEL A21 191 VCC D1 124 VCC VR_PORT VCC CAD29 158 CCLK A16 192 CAD30 D9 125 CCD1 CD1 159 CTRDY A22 193 CRSVD D2 126 CAD0 D3 160 CIRDY A15 194 CAD31 D10 127 CAD2 D11 161 CFRAME A23 195 GND GND 128 GND GND 162 GND GND 196 SC_RSVD SC_RSVD 129 CAD1 D4 163 CC/BE2 A12 197 SC_RSVD SC_RSVD 130 CAD4 D12 164 CAD17 A24 198 SC_RSVD SC_RSVD 131 CAD3 D5 165 CAD18 A7 199 SC_RSVD SC_RSVD 132 CAD6 D13 166 CAD19 A25 200 SC_RSVD SC_RSVD 133 CAD5 D6 167 CVS2 VS2 201 SC_RSVD SC_RSVD 134 CRSVD D14 168 CAD20 A6 202 SC_RSVD SC_RSVD 135 CAD7 D7 169 CRST RESET 203 136 CAD8 D15 170 204 CC/BE0 CE1 171 VCC A5 VCC CLK_48_RSVD 137 VCC CAD21 VCC CLK_48_RSVD 205 VD0/VCCD1 VD0/VCCD1 138 VCC A10 172 CAD22 A4 206 VD1/VCCD0 VD1/VCCD0 139 VCC CAD9 173 CREQ INPACK 207 VD2/VPPD1 VD2/VPPD1 140 CAD10 CE2 174 CAD23 A3 208 VD3/VPPD0 VD3/VPPD0 141 CAD11 OE 175 142 CAD12 A11 176 VCCCB CC/BE3 VCCCB REG Table 2−2. Signal Names Sorted by GHK Terminal Number TERM. NO. SIGNAL NAME CARDBUS 16-BIT TERM. NO. SIGNAL NAME CARDBUS 16-BIT TERM. NO. SIGNAL NAME CARDBUS 16-BIT A04 VD3/VPPD0 VD3/VPPD0 E07 SC_RSVD SC_RSVD H06 MFUNC6 MFUNC6 A05 VCC VCC E08 CAD31 D10 H14 CAD11 OE A06 SC_RSVD SC_RSVD E09 CAD28 D8 H15 CAD12 A11 A07 GND GND E10 CSERR WAIT H17 CAD10 CE2 A08 VCC VCC E11 CAD25 A1 H18 CAD9 A10 A09 CSTSCHG BVD1(STSCHG/RI) E12 CAD21 A5 H19 VCC VCC A10 GND GND E13 CAD18 A7 J01 GNT GNT A11 VCCCB VCCCB E14 CTRDY A22 J02 REQ REQ A12 CAD23 A3 E17 CSTOP A20 J03 RI_OUT/PME RI_OUT/PME A13 VCC VCC E18 CBLOCK A19 J05 AD31 AD31 A14 CAD19 A25 E19 VCC VCC J06 AD30 AD30 A15 GND GND F01 MFUNC5 MFUNC5 J14 CAD8 D15 A16 CDEVSEL A21 F02 MFUNC3 MFUNC3 J15 CC/BE0 CE1 B05 VD0/VCCD1 VD0/VCCD1 F03 MFUNC2 MFUNC2 J17 CAD7 D7 B06 SC_RSVD SC_RSVD F05 MFUNC0 MFUNC0 J18 CRSVD D14 B07 SC_RSVD SC_RSVD F06 CLK_48_RSVD CLK_48_RSVD J19 CAD5 D6 B08 CAD29 D1 F07 SC_RSVD SC_RSVD K01 GND GND B09 CCLKRUN WP(IOIS16) F08 CRSVD D2 K02 AD29 AD29 B10 CVS1 VS1 F09 CAD27 D0 K03 AD28 AD28 B11 CC/BE3 REG F10 CAUDIO BVD2(SPKR) K05 AD27 AD27 B12 CREQ INPACK F11 CAD26 A0 K06 AD26 AD26 B13 CRST RESET F12 CVS2 VS2 K14 CAD6 D13 B14 CAD17 A24 F13 CIRDY A15 K15 CAD3 D5 B15 CFRAME A23 F14 CPAR A13 K17 CAD4 D12 C05 VD2/VPPD1 VD2/VPPD1 F15 CPERR A14 K18 CAD1 D4 C06 SC_RSVD SC_RSVD F17 CRSVD A18 K19 GND GND C07 SC_RSVD SC_RSVD F18 CAD16 A17 L01 VCCP VCCP C08 CAD30 D9 F19 CAD14 A9 L02 AD25 AD25 C09 CCD2 CD2 G01 VCC VCC L03 AD24 AD24 C10 CINT READY(IREQ) G02 VR_PORT VR_PORT L05 IDSEL IDSEL C11 CAD24 A2 G03 SUSPEND SUSPEND L06 C/BE3 C/BE3 C12 CAD22 A4 G05 MFUNC4 MFUNC4 L14 CAD2 D11 C13 CAD20 A6 G06 MFUNC1 MFUNC1 L15 CAD0 D3 C14 CC/BE2 A12 G14 VCCCB VCCCB L17 CCD1 CD1 C15 CCLK A16 G15 CC/BE1 A8 L18 VR_PORT VR_PORT D01 SDA SDA G17 CAD15 IOWR L19 VCC VCC D19 CGNT WE G18 CAD13 IORD M01 VCC VCC E01 GND GND G19 GND GND M02 AD23 AD23 E02 SPKROUT SPKROUT H01 PCLK PCLK M03 AD22 AD22 E03 SCL SCL H02 GRST GRST M05 AD20 AD20 E05 NC NC H03 PRST PRST M06 AD21 AD21 E06 VD1/VCCD0 VD1/VCCD0 H05 VR_EN VR_EN M14 MC_RSVD MC_RSVD 2−7 Table 2−2. Signal Names Sorted by GHK Terminal Number (Continued) TERM. NO. 2−8 SIGNAL NAME CARDBUS 16-BIT SIGNAL NAME TERM. NO. CARDBUS 16-BIT TERM. NO. M15 MC_RSVD MC_RSVD P17 CNA CNA U13 M17 MC_RSVD MC_RSVD P18 PHY_TEST_MA PHY_TEST_MA M18 MC_RSVD MC_RSVD P19 GND GND M19 MC_RSVD MC_RSVD R01 N01 GND GND R02 VCC DEVSEL VCC DEVSEL N02 AD19 AD19 R03 PERR PERR N03 AD18 AD18 R06 AD15 N05 FRAME FRAME R07 AD10 N06 AD17 AD17 R08 N14 PLLGND PLLGND N15 MC_RSVD MC_RSVD N17 MC_RSVD N18 N19 SIGNAL NAME CARDBUS 16-BIT U14 ANALOGVCC ANALOGVCC ANALOGVCC ANALOGVCC U15 TPBIAS1 TPBIAS1 V05 AD13 AD13 V06 AD11 AD11 V07 C/BE0 C/BE0 AD15 V08 AD4 AD4 AD10 V09 AD2 AD2 AD6 AD6 V10 PC0 PC0 R09 AD0 AD0 V11 TPB0P TPB0P R10 TEST1 TEST1 V12 TPA0P TPA0P MC_RSVD R11 R1 R1 MC_RSVD R12 ANALOGVCC ANALOGGND V13 MC_RSVD ANALOGVCC ANALOGGND V14 TPB1P TPB1P MC_RSVD MC_RSVD R13 ANALOGGND ANALOGGND V15 TPA1P TPA1P P01 AD16 AD16 R14 NC NC W04 PAR PAR P02 C/BE2 C/BE2 R17 FILTER1 FILTER1 W05 P03 IRDY IRDY R18 XI XI W06 VCCP GND VCCP GND P05 STOP STOP R19 XO XO W07 AD7 AD7 P06 TRDY TRDY T01 SERR SERR W08 P07 AD14 AD14 T19 FILTER0 FILTER0 W09 VCC AD3 VCC AD3 P08 AD9 AD9 U05 C/BE1 C/BE1 W10 PC1 PC1 P09 PC2 PC2 U06 AD12 AD12 W11 TPB0N TPB0N P10 CPS CPS U07 AD8 AD8 W12 TPA0N TPA0N P11 NC NC U08 AD5 AD5 W13 R0 R0 P12 NC NC U09 AD1 AD1 W14 TPB1N TPB1N P13 NC NC U10 TEST0 TEST0 W15 TPA1N TPA1N P14 NC NC U11 ANALOGGND ANALOGGND W16 NC NC P15 PLLVCC PLLVCC U12 TPBIAS0 TPBIAS0 Table 2−3. Signal Names Sorted by RGVF Terminal Number TERM. NO. SIGNAL NAME CARDBUS 16-BIT TERM. NO. SIGNAL NAME CARDBUS 16-BIT TERM. NO. SIGNAL NAME CARDBUS 16-BIT A02 CAUDIO BVD2(SPKR) C13 CAD7 D7 H11 VCC VCC A03 CVS1 VS1 C14 CAD4 D12 H12 VCC VCC A04 CAD25 A1 C15 CCD1 CD1 H13 GND GND A05 VCCCB VCCCB D01 CAD31 D10 H19 NC NC A06 CRST RESET D02 CRSVD D2 J01 SC_RSVD SC_RSVD A07 CAD17 A24 D03 CAD29 D1 J02 SC_RSVD SC_RSVD A08 CTRDY A22 D19 NC NC J03 SC_RSVD SC_RSVD A09 CSTOP A20 E05 CCD2 CD2 J05 SC_RSVD SC_RSVD A10 CAD16 A17 E06 CAD24 A2 J06 MC_RSVD MC_RSVD A11 VCCCB VCCCB E07 CREQ INPACK J07 SC_RSVD SC_RSVD A12 CAD9 A10 E08 CVS2 VS2 J08 VCC VCC A13 CAD5 D6 E09 CCLK A16 J09 GND GND A14 CAD2 D11 E10 CBLOCK A19 J10 GND GND A18 TEST1 TEST1 E11 CAD15 IOWR J11 GND GND B01 CAD27 D0 E12 CAD8 D15 J12 VCC VCC B02 CSTSCHG BVD1(STSCHG/RI) E13 CAD3 D5 J19 NC NC B03 CSERR WAIT E14 CAD0 D3 K01 SC_RSVD SC_RSVD B04 CAD26 A0 E19 NC NC K02 SC_RSVD SC_RSVD B05 CAD23 A3 F03 MC_RSVD MC_RSVD K08 VCC VCC B06 CAD21 A5 F09 CC/BE2 A12 K09 GND GND B07 CAD18 A7 F10 CPERR A14 K10 GND GND B08 CIRDY A15 F12 CAD6 D13 K11 GND GND B09 CGNT WE F19 NC NC K12 VCC VCC B10 CC/BE1 A8 G01 MC_RSVD MC_RSVD K19 NC NC B11 CAD12 A11 G02 MC_RSVD MC_RSVD L05 VD0/VCCD1 VD0/VCCD1 B12 CAD10 CE2 G03 MC_RSVD MC_RSVD L06 VD1/VCCD0 VD1/VCCD0 B13 CRSVD D14 G05 MC_RSVD MC_RSVD L07 SPKROUT SPKROUT B14 CAD1 D4 G07 GND GND L08 GND GND B18 NC NC G08 GND GND L09 GND GND B19 NC NC G09 CAD20 A6 L10 GND GND C01 CAD30 D9 G10 CPAR A13 L11 GND GND C02 CAD28 D8 G11 CAD14 A9 L12 GND GND C03 CCLKRUN WP(IOIS16) G12 CC/BE0 CE1 L19 NC NC C04 CINT READY(IREQ) G13 GND GND M01 CLK_48 CLK_48 C05 CC/BE3 REG H01 VR_PORT VR_PORT M02 SDA SDA C06 CAD22 A4 H02 VR_EN VR_EN M03 SCL SCL C07 CAD19 A25 H03 MC_RSVD MC_RSVD M05 MFUNC1 MFUNC1 C08 CFRAME A23 H05 MC_RSVD MC_RSVD M07 VCC VCC C09 CDEVSEL A21 H07 MC_RSVD MC_RSVD M08 GND GND C10 CRSVD A18 H08 VCC VCC M09 VCC VCC C11 CAD13 IORD H09 VCC VCC M10 VCC VCC C12 CAD11 OE H10 VCC VCC M11 CPS CPS 2−9 Table 2−3. Signal Names Sorted by RGVF Terminal Number (Continued) TERM. NO. M12 2−10 SIGNAL NAME CARDBUS 16-BIT SIGNAL NAME TERM. NO. VCC VR_PORT R13 M19 VCC VR_PORT N01 VD2/VPPD1 VD2/VPPD1 N02 VD3/VPPD0 N03 N05 N07 CARDBUS 16-BIT TERM. NO. SIGNAL NAME CARDBUS 16-BIT ANALOGVCC ANALOGVCC V05 AD23 AD23 R14 ANALOGVCC ANALOGVCC V06 AD18 AD18 R17 PHY_TEST_MA PHY_TEST_MA V07 FRAME FRAME VD3/VPPD0 R18 XI XI V08 PERR PERR MFUNC0 MFUNC0 R19 XO XO V09 AD15 AD15 MFUNC5 MFUNC5 T01 GRST GRST V10 AD11 AD11 VCC DEVSEL VCC DEVSEL T02 GNT GNT V11 AD7 AD7 N08 T03 RI_OUT/PME RI_OUT/PME V12 AD3 AD3 N09 AD12 AD12 T18 FILTER0 FILTER0 V13 PC2 PC2 N10 AD8 AD8 T19 FILTER1 FILTER1 V14 TPB0P TPB0P N11 AD1 AD1 U01 REQ REQ V15 TPA0P TPA0P N12 ANALOGGND ANALOGGND U02 AD31 AD31 V16 TPB1P TPB1P N19 NC NC U03 AD28 AD28 V17 P01 MFUNC2 MFUNC2 U04 AD25 AD25 V18 ANALOGVCC TPA1P ANALOGVCC TPA1P P02 MFUNC3 MFUNC3 U05 AD22 AD22 V19 P03 MFUNC4 MFUNC4 U06 AD17 AD17 W02 PLLVCC AD27 PLLVCC AD27 P05 PCLK PCLK U07 IRDY IRDY W03 P06 AD20 AD20 U08 SERR SERR W04 VCCP C/BE3 VCCP C/BE3 P09 PAR PAR U09 AD14 AD14 W05 IDSEL IDSEL P12 TEST0 TEST0 U10 AD10 AD10 W06 AD19 AD19 P14 PLLGND PLLGND U11 AD6 AD6 W07 C/BE2 C/BE2 P15 CNA CNA U12 AD2 AD2 W08 STOP STOP P19 NC NC U13 PC1 PC1 W09 C/BE1 C/BE1 R01 MFUNC6 MFUNC6 U14 ANALOGGND ANALOGGND W10 R02 SUSPEND SUSPEND U15 TPBIAS0 TPBIAS0 W11 VCCP C/BE0 VCCP C/BE0 R03 PRST PRST U16 ANALOGGND ANALOGGND W12 AD4 AD4 R06 AD21 AD21 U17 TPBIAS1 TPBIAS1 W13 AD0 AD0 R07 AD16 AD16 U18 R0 R0 W14 TPB0N TPB0N R08 TRDY TRDY U19 R1 R1 W15 TPA0N TPA0N R09 AD13 AD13 V01 AD30 AD30 W16 TPB1N TPB1N R10 AD9 AD9 V02 AD29 AD29 W17 NC NC R11 AD5 AD5 V03 AD26 AD26 W18 TPA1N TPA1N R12 PC0 PC0 V04 AD24 AD24 Table 2−4. CardBus PC Card Signal Names Sorted Alphabetically TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME PDV GHK RGVF PDV GHK RGVF PDV GHK RGVF AD0 74 R09 W13 CAD5 133 J19 A13 CGNT 156 D19 B09 AD1 73 U09 N11 CAD6 132 K14 F12 CINT 182 C10 C04 AD2 72 V09 U12 CAD7 135 J17 C13 CIRDY 160 F13 B08 AD3 71 W09 V12 CAD8 136 J14 E12 CLK_48_RSVD 204 F06 M01 AD4 69 V08 W12 CAD9 139 H18 A12 CNA 111 P17 P15 AD5 68 U08 R11 CAD10 140 H17 B12 CPAR 152 F14 G10 AD6 67 R08 U11 CAD11 141 H14 C12 CPERR 154 F15 F10 AD7 66 W07 V11 CAD12 142 H15 B11 CPS 80 P10 M11 AD8 64 U07 N10 CAD13 144 G18 C11 CREQ 173 B12 E07 AD9 63 P08 R10 CAD14 147 F19 G11 CRST 169 B13 A06 AD10 61 R07 U10 CAD15 145 G17 E11 CRSVD 134 F08 B13 AD11 60 V06 V10 CAD16 148 F18 A10 CRSVD 150 F17 C10 AD12 59 U06 N09 CAD17 164 B14 A07 CRSVD 193 J18 D02 AD13 57 V05 R09 CAD18 165 E13 B07 CSERR 183 E10 B03 AD14 56 P07 U09 CAD19 166 A14 C07 CSTOP 155 E17 A09 AD15 55 R06 V09 CAD20 168 C13 G09 CSTSCHG 185 A09 B02 AD16 43 P01 R07 CAD21 171 E12 B06 CTRDY 159 E14 A08 AD17 42 N06 U06 CAD22 172 C12 C06 CVS1 181 B10 A03 AD18 41 N03 V06 CAD23 174 A12 B05 CVS2 167 F12 E08 AD19 40 N02 W06 CAD24 177 C11 E06 DEVSEL 49 R02 N08 AD20 38 M05 P06 CAD25 178 E11 A04 FILTER0 105 T19 T18 AD21 37 M06 R06 CAD26 179 F11 B04 FILTER1 106 R17 T19 AD22 36 M03 U05 CAD27 188 F09 B01 FRAME 45 N05 V07 AD23 35 M02 V05 CAD28 189 E09 C02 GNT 19 J01 T02 AD24 31 L03 V04 CAD29 191 B08 D03 GRST 17 H02 T01 AD25 30 L02 U04 CAD30 192 C08 C01 IDSEL 33 L05 W05 AD26 28 K06 V03 CAD31 194 E08 D01 IRDY 46 P03 U07 AD27 27 K05 W02 CAUDIO 184 F10 A02 MC_RSVD 113 N15 H07 AD28 26 K03 U03 C/BE0 65 V07 W11 MC_RSVD 115 M14 G05 AD29 25 K02 V02 C/BE1 54 U05 W09 MC_RSVD 116 N17 G03 AD30 23 J06 V01 C/BE2 44 P02 W07 MC_RSVD 117 N18 H03 AD31 22 J05 U02 C/BE3 32 L06 W04 MC_RSVD 118 N19 G02 ANALOGGND 83 U11 N12 CBLOCK 153 E18 E10 MC_RSVD 119 M15 J06 ANALOGGND 90 R12 U14 CC/BE0 137 J15 G12 MC_RSVD 120 M17 H05 ANALOGGND 97 R13 U16 CC/BE1 149 G15 B10 MC_RSVD 121 M18 F03 ANALOGVCC ANALOGVCC 85 R11 R13 CC/BE2 163 C14 F09 MC_RSVD 122 M19 G01 93 U13 R14 CC/BE3 176 B11 C05 MFUNC0 3 F05 N03 ANALOGVCC CAD0 98 U14 V17 CCD1 125 L17 C15 MFUNC1 4 G06 M05 126 L15 E14 CCD2 187 C09 E05 MFUNC2 7 F03 P01 CAD1 129 K18 B14 CCLK 158 C15 E09 MFUNC3 8 F02 P02 CAD2 127 L14 A14 CCLKRUN 186 B09 C03 MFUNC4 9 G05 P03 CAD3 131 K15 E13 CDEVSEL 157 A16 C09 MFUNC5 10 F01 N05 CAD4 130 K17 C14 CFRAME 161 B15 C08 MFUNC6 11 H06 R01 2−11 Table 2−4. CardBus PC Card Signal Names Sorted Alphabetically (Continued) TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME PDV GHK RGVF PDV GHK RGVF PDV GHK RGVF PAR 53 W04 P09 SC_RSVD 199 A06 J05 TPB0P 82 V11 V14 PCLK 18 H01 P05 SC_RSVD 200 B06 J07 TPB1N 95 W14 W16 PC0 77 V10 R12 SC_RSVD 201 E07 K01 TPB1P 96 V14 V16 PC1 76 W10 U13 SC_RSVD 202 C06 K02 TRDY 48 P06 R08 PC2 75 P09 V13 SDA 1 D01 M02 A11 A05 51 R03 V08 SERR 52 T01 U08 VCCCB VCCCB 146 PERR 175 G14 A11 PHY_TEST_MA 112 P18 R17 SPKROUT 5 E02 L07 L01 W03 108 N14 P14 STOP 50 P05 W08 VCCP VCCP 29 PLLGND 58 W05 W10 PLLVCC PRST 107 P15 V19 SUSPEND 12 G03 R02 VD0/VCCD1 205 B05 L05 16 H03 R03 TEST0 78 U10 P12 VD1/VCCD0 206 E06 L06 REQ 20 J02 U01 TEST1 79 R10 A18 VD2/VPPD1 207 C05 N01 RI_OUT/PME 21 J03 T03 TPA0N 86 W12 W15 VD3/VPPD0 208 A04 N02 R0 91 W13 U18 TPA0P 87 V12 V15 VR_EN 15 H05 H02 R1 92 V13 U19 TPA1N 99 W15 W18 VR_PORT 13 G02 H01 SCL 2 E03 M03 TPA1P 101 V15 V18 VR_PORT 124 L18 M19 SC_RSVD 196 B07 J01 TPBIAS0 88 U12 U15 XI 109 R18 R18 SC_RSVD 197 C07 J02 TPBIAS1 103 U15 U17 XO 110 R19 R19 SC_RSVD 198 F07 J03 TPB0N 81 W11 W14 2−12 Table 2−5. 16-Bit PC Card Signal Names Sorted Alphabetically TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME PDV GHK RGVF PDV GHK RGVF PDV GHK RGVF AD0 74 R09 W13 A5 171 E12 B06 D8 189 E09 C02 AD1 73 U09 N11 A6 168 C13 G09 D9 192 C08 C01 AD2 72 V09 U12 A7 165 E13 B07 D10 194 E08 D01 AD3 71 W09 V12 A8 149 G15 B10 D11 127 L14 A14 AD4 69 V08 W12 A9 147 F19 G11 D12 130 K17 C14 AD5 68 U08 R11 A10 139 H18 A12 D13 132 K14 F12 AD6 67 R08 U11 A11 142 H15 B11 D14 134 J18 B13 AD7 66 W07 V11 A12 163 C14 F09 D15 136 J14 E12 AD8 64 U07 N10 A13 152 F14 G10 FILTER0 105 T19 T18 AD9 63 P08 R10 A14 154 F15 F10 FILTER1 106 R17 T19 AD10 61 R07 U10 A15 160 F13 B08 FRAME 45 N05 V07 AD11 60 V06 V10 A16 158 C15 E09 GNT 19 J01 T02 AD12 59 U06 N09 A17 148 F18 A10 GRST 17 H02 T01 AD13 57 V05 R09 A18 150 F17 C10 IDSEL 33 L05 W05 AD14 56 P07 U09 A19 153 E18 E10 INPACK 173 B12 E07 AD15 55 R06 V09 A20 155 E17 A09 IORD 144 G18 C11 AD16 43 P01 R07 A21 157 A16 C09 IOWR 145 G17 E11 AD17 42 N06 U06 A22 159 E14 A08 IRDY 46 P03 U07 AD18 41 N03 V06 A23 161 B15 C08 MC_RSVD 113 N14 H07 AD19 40 N02 W06 A24 164 B14 A07 MC_RSVD 115 M14 G05 AD20 38 M05 P06 A25 166 A14 C07 MC_RSVD 116 N17 G03 AD21 37 M06 R06 BVD1(STSCHG/RI) 185 A09 B02 MC_RSVD 117 N18 H03 AD22 36 M03 U05 BVD2(SPKR) 184 F10 A02 MC_RSVD 118 N19 G02 AD23 35 M02 V05 C/BE0 65 V07 W11 MC_RSVD 119 M15 J06 AD24 31 L03 V04 C/BE1 54 U05 W09 MC_RSVD 120 M17 H05 AD25 30 L02 U04 C/BE2 44 P02 W07 MC_RSVD 121 M18 F03 AD26 28 K06 V03 C/BE3 32 L06 W04 MC_RSVD 122 M19 G01 AD27 27 K05 W02 CD1 125 L17 C15 MFUNC0 3 F05 N03 AD28 26 K03 U03 CD2 187 C09 E05 MFUNC1 4 G06 M05 AD29 25 K02 V02 CE1 137 J15 G12 MFUNC2 7 F03 P01 AD30 23 J06 V01 CE2 140 H17 B12 MFUNC3 8 F02 P02 AD31 22 J05 U02 CLK_48_RSVD 204 F06 M01 MFUNC4 9 G05 P03 ANALOGGND 83 U11 N12 CNA 111 P17 P15 MFUNC5 10 F01 N05 ANALOGGND 90 R12 U14 CPS 80 P10 M11 MFUNC6 11 H06 R01 ANALOGGND 97 R13 U16 DEVSEL 49 R02 N08 OE 141 H14 C12 ANALOGVCC ANALOGVCC 85 R11 R13 D0 188 F09 B01 PAR 53 W04 P09 93 U13 R14 D1 191 B08 D03 PCLK 18 H01 P05 ANALOGVCC A0 98 U14 V17 D2 193 F08 D02 PC0 77 V10 R12 179 F11 B04 D3 126 L15 E14 PC1 76 W10 U13 A1 178 E11 A04 D4 129 K18 B14 PC2 75 P09 V13 A2 177 C11 E06 D5 131 K15 E13 PERR 51 R03 V08 A3 174 A12 B05 D6 133 J19 A13 PHY_TEST_MA 112 P18 R17 A4 172 C12 C06 D7 135 J17 C13 PLLGND 108 N14 P14 2−13 Table 2−5. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued) TERMINAL NUMBER SIGNAL NAME TERMINAL NUMBER SIGNAL NAME PDV GHK RGVF PLLVCC PRST 107 P15 V19 SERR PDV GHK RGVF 52 T01 U08 16 H03 R03 READY(IREQ) 182 C10 C04 SPKROUT 5 E02 L07 STOP 50 P05 W08 REG 176 B11 C05 SUSPEND 12 G03 TERMINAL NUMBER SIGNAL NAME PDV GHK RGVF VCCCB VCCP 175 G14 A11 29 L01 W03 58 W05 W10 R02 VCCP VD0/VCCD1 205 B05 L05 REQ 20 J02 U01 TEST0 78 U10 P12 VD1/VCCD0 206 E06 L06 RESET 169 B13 A06 TEST1 79 R10 A18 VD2/VPPD1 207 C05 N01 RI_OUT/PME 21 J03 T03 TPA0N 86 W12 W15 VD3/VPPD0 208 A04 N02 R0 91 W13 U18 TPA0P 87 V12 V15 VR_EN 15 H05 H02 R1 92 V13 U19 TPA1N 99 W15 W18 VR_PORT 13 G02 H01 SCL 2 E03 M03 TPA1P 101 V15 V18 VR_PORT 124 L18 M19 SC_RSVD 196 B07 J01 TPBIAS0 88 U12 U15 VS1 181 B10 A03 SC_RSVD 197 C07 J02 TPBIAS1 103 U15 U17 VS2 167 F12 E08 SC_RSVD 198 F07 J03 TPB0N 81 W11 W14 WAIT 183 E10 B03 SC_RSVD 199 A06 J05 TPB0P 82 V11 V14 WE 156 D19 B09 SC_RSVD 200 B06 J07 TPB1N 95 W14 W16 WP(IOIS16) 186 B09 C03 SC_RSVD 201 E07 K01 TPB1P 96 V14 V16 XI 109 R18 R18 SC_RSVD 202 C06 K02 TRDY 48 P06 R08 XO 110 R19 R19 1 D01 M02 VCCCB 146 A11 A05 SDA 2−14 The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The terminal numbers are also listed for convenient reference. Table 2−6. Power Supply Terminals TERMINAL NUMBER NAME I/O DESCRIPTION PDV GHK RGVF GND 6, 24, 39, 62, 114, 128, 143, 162, 180, 195 E01, K01, N01, W06, P19, K19, G19, A15, A10, A07 G07, G08, G13, H13, J09, J10, J11, K09, K10, K11, L08, L09, L10, L11, L12, M08 − Device ground terminals VCC 14, 34, 47, 70, 123, 138, 151, 170, 190, 203 G01, M01, R01, W08, L19, H19, E19, A13, A08, A05 H08, H09, H10, H11, H12, J08, J12, K08, K12, M07, M09, M10, M12, N07 − Power supply terminal for I/O and internal voltage regulator VCCCB 146, 175 G14, A11 A05, A11 − Clamp voltage for PC CardBus interface. Matches card signaling environment, 5 V or 3.3 V VCCP VR_EN 29, 58 L01, W05 W03, W10 − Clamp voltage for PCI and miscellaneous I/O, 5 V or 3.3 V 15 H05 H02 I Internal voltage regulator enable. Active low VR_PORT 13, 124 G02, L18 H01, M19 I/O Internal voltage regulator input/output. When VR_EN is low, the regulator is enabled and these terminals are outputs. The two VR_PORT terminals must be tied together and connected to ground through a 0.1 µF bypass capacitor. When VR_EN is high, the regulator is disabled and these terminals are inputs for an external 1.8-V core power source. Table 2−7. PC Card Power Switch Terminals TERMINAL NUMBER NAME I/O PDV GHK RGVF VD1/VCCD0 206 E06 L06 VD0/VCCD1 205 B05 L05 VD3/VPPD0 208 A04 N02 VD2/VPPD1 207 C05 N01 DESCRIPTION O Logic controls to the TPS2211A or TPS2221 PC Card power interface switch to control AVCC O Logic controls to the TPS2211A or TPS2221 PC Card power interface switch to control AVPP Table 2−8. PCI System Terminals TERMINAL NUMBER NAME I/O DESCRIPTION T01 I Global reset. When the global reset is asserted, the GRST signal causes the PCI4510 device to place all output buffers in a high-impedance state and reset all internal registers. When GRST is asserted, the device is completely in its default state. GRST must be connected to POWER_OK. P05 I PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK. I PCI bus reset. When the PCI bus reset is asserted, PRST causes the PCI4510 device to place all output buffers in a high-impedance state and reset internal registers. When PRST is asserted, the device is completely nonfunctional. After PRST is deasserted, the PCI4510 device is in a default state. When SUSPEND and PRST are asserted, the device is protected from PRST clearing the internal registers. All outputs are placed in a high-impedance state, but the contents of the registers are preserved. PDV GHK RGVF GRST 17 H02 PCLK 18 H01 PRST 16 H03 R03 2−15 Table 2−9. PCI Address and Data Terminals TERMINAL NUMBER NAME PDV GHK RGVF AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 22 23 25 26 27 28 30 31 35 36 37 38 40 41 42 43 55 56 57 59 60 61 63 64 66 67 68 69 71 72 73 74 J05 J06 K02 K03 K05 K06 L02 L03 M02 M03 M06 M05 N02 N03 N06 P01 R06 P07 V05 U06 V06 R07 P08 U07 W07 R08 U08 V08 W09 V09 U09 R09 U02 V01 V02 U03 W02 V03 U04 V04 V05 U05 R06 P06 W06 V06 U06 R07 V09 U09 R09 N09 V10 U10 R10 N10 V11 U11 R11 W12 V12 U12 N11 W13 C/BE3 C/BE2 C/BE1 C/BE0 32 44 54 65 L06 P02 U05 V07 W04 W07 W09 W11 PAR 2−16 53 W04 P09 I/O DESCRIPTION I/O PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary-bus PCI cycle, AD31−AD0 contain a 32-bit address or other destination information. During the data phase, AD31−AD0 contain data. I/O PCI-bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary-bus PCI cycle, C/BE3−C/BE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 0 (AD7−AD0), C/BE1 applies to byte 1 (AD15−AD8), C/BE2 applies to byte 2 (AD23−AD16), and C/BE3 applies to byte 3 (AD31−AD24). I/O PCI-bus parity. In all PCI-bus read and write cycles, the PCI4510 device calculates even parity across the AD31−AD0 and C/BE3−C/BE0 buses. As an initiator during PCI cycles, the PCI4510 device outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the PCI4510 device compares its calculated parity to the parity indicator of the initiator. A compare error results in the assertion of a parity error (PERR). Table 2−10. PCI Interface Control Terminals TERMINAL NUMBER I/O DESCRIPTION N08 I/O PCI device select. The PCI4510 device asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI4510 device monitors DEVSEL until a target responds. If no target responds before timeout occurs, then the PCI4510 device terminates the cycle with an initiator abort. N05 V07 I/O PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME is deasserted, the PCI bus transaction is in the final data phase. 19 J01 T02 I PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI4510 device access to the PCI bus after the current data transaction has completed. GNT may or may not follow a PCI bus request, depending on the PCI bus parking algorithm. IDSEL 33 L05 W05 I Initialization device select. IDSEL selects the PCI4510 device during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus. IRDY 46 P03 U07 I/O PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted. PERR 51 R03 V08 I/O PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match PAR when PERR is enabled through bit 6 of the command register (PCI offset 04h, see Section 4.4). REQ 20 J02 U01 O PCI bus request. REQ is asserted by the PCI4510 device to request access to the PCI bus as an initiator. NAME PDV GHK RGVF DEVSEL 49 R02 FRAME 45 GNT SERR 52 T01 U08 O PCI system error. SERR is an output that is pulsed from the PCI4510 device when enabled through bit 8 of the command register (PCI offset 04h, see Section 4.4) indicating a system error has occurred. The PCI4510 device need not be the target of the PCI cycle to assert this signal. When SERR is enabled in the command register, this signal also pulses, indicating that an address parity error has occurred on a CardBus interface. STOP 50 P05 W08 I/O PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers. TRDY 48 P06 R08 I/O PCI target ready. TRDY indicates the ability of the primary bus target to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted. 2−17 Table 2−11. Multifunction and Miscellaneous Terminals TERMINAL NUMBER NAME I/O DESCRIPTION PDV GHK RGVF 204 F06 M01 − MFUNC0 3 F05 N03 I/O Multifunction terminal 0. See Section 4.34, Multifunction Routing Register, for configuration details. MFUNC1 4 G06 M05 I/O Multifunction terminal 1. See Section 4.34, Multifunction Routing Register, for configuration details. MFUNC2 7 F03 P01 I/O Multifunction terminal 2. See Section 4.34, Multifunction Routing Register, for configuration details. MFUNC3 8 F02 P02 I/O Multifunction terminal 3. See Section 4.34, Multifunction Routing Register, for configuration details. MFUNC4 9 G05 P03 I/O Multifunction terminal 4. See Section 4.34, Multifunction Routing Register, for configuration details. MFUNC5 10 F01 N05 I/O Multifunction terminal 5. See Section 4.34, Multifunction Routing Register, for configuration details. MFUNC6 11 H06 R01 I/O Multifunction terminal 6. See Section 4.34, Multifunction Routing Register, for configuration details. — 84, 89, 94, 100, 102, 104 E05 P11, P12, P13, P14, R14, W16 B18, B19, D19, E19, F19, H19, J19, K19, L19, N19, P19, W17 PHY_TEST_MA 112 P18 R17 I PHY test pin. Not for customer use. It must be pulled high with a 4.7-kΩ resistor. RI_OUT/PME 21 J03 T03 O Ring indicate out and power management event output. This terminal provides an output for ring-indicate or PME signals. I/O Serial clock. This terminal provides the serial clock signaling and is implemented as open-drain. For normal operation (a ROM is implemented in the design), this terminal must be pulled high to the ROM VDD with a 2.7-kΩ resistor. Otherwise, it must be pulled low to ground with a 220-Ω resistor. CLK_48_RSVD NC SCL 2 E03 M03 Reserved for future 48-MHz clock terminal No connect. These terminals have no connection anywhere within the package. Terminal E05 on the GHK package is used as a key to indicate the location of the A01 corner of the BGA package. Serial data. At GRST, the SDA signal is sampled to determine if a two-wire serial ROM is present. If the serial ROM is detected, then this terminal provides the serial data signaling. SDA 1 D01 M02 I/O SPKROUT 5 E02 L07 O Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the PCI4510 device from the PC Card interface. SUSPEND 12 G03 R02 I Suspend. SUSPEND protects the internal registers from clearing when the GRST or PRST signal is asserted. See Section 3.8.6, Suspend Mode, for details. TEST0 TEST1 78 79 U10 R10 P12 A18 I/O Terminals TEST[1, 0] are used for factory test of the device and must be connected to ground for normal operation. 2−18 This terminal is implemented as open-drain, and for normal operation (a ROM is implemented in the design), this terminal must be pulled high to the ROM VDD with a 2.7-kΩ resistor. Otherwise, it must be pulled low to ground with a 220-Ω resistor. Table 2−12. 16-Bit PC Card Address and Data Terminals TERMINAL NUMBER NAME I/O DESCRIPTION PDV GHK RGVF A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 166 164 161 159 157 155 153 150 148 158 160 154 152 163 142 139 147 149 165 168 171 172 174 177 178 179 A14 B14 B15 E14 A16 E17 E18 F17 F18 C15 F13 F15 F14 C14 H15 H18 F19 G15 E13 C13 E12 C12 A12 C11 E11 F11 C07 A07 C08 A08 C09 A09 E10 C10 A10 E09 B08 F10 G10 F09 B11 A12 G11 B10 B07 G09 B06 C06 B05 E06 A04 B04 O PC Card address. 16-bit PC Card address lines. A25 is the most significant bit. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 136 134 132 130 127 194 192 189 135 133 131 129 126 193 191 188 J14 J18 K14 K17 L14 E08 C08 E09 J17 J19 K15 K18 L15 F08 B08 F09 E12 B13 F12 C14 A14 D01 C01 C02 C13 A13 E13 B14 E14 D02 D03 B01 I/O PC Card data. 16-bit PC Card data lines. D15 is the most significant bit. 2−19 Table 2−13. 16-Bit PC Card Interface Control Terminals TERMINAL NUMBER NAME BVD1 (STSCHG/RI) PDV 185 GHK A09 I/O DESCRIPTION RGVF B02 I Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and must be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt Configuration Register, for enable bits. See Section 5.5, ExCA Card Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the status bits for this signal. Status change. STSCHG is used to alert the system to a change in the READY, write protect, or battery voltage dead condition of a 16-bit I/O PC Card. Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection. BVD2 (SPKR) 184 F10 A02 I Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and must be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt Configuration Register, for enable bits. See Section 5.5, ExCA Card Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the status bits for this signal. Speaker. SPKR is an optional binary audio signal available only when the card and socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the PCI4510 device and are output on SPKROUT. 125 187 L17 C09 C15 E05 I Card detect 1 and card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low. For signal status, see Section 5.2, ExCA Interface Status Register. CE2 137 140 J15 H17 G12 B12 O Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes. CE1 enables even-numbered address bytes, and CE2 enables odd-numbered address bytes. INPACK 173 B12 E07 I Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read cycle at the current address. IORD 144 G18 C11 O I/O read. IORD is asserted by the PCI4510 device to enable 16-bit I/O PC Card data output during host I/O read cycles. IOWR 145 G17 E11 O I/O write. IOWR is driven low by the PCI4510 device to strobe write data into 16-bit I/O PC Cards during host I/O write cycles. OE 141 H14 C12 O Output enable. OE is driven low by the PCI4510 device to enable 16-bit memory PC Card data output during host memory read cycles. CD1 CD2 CE1 READY (IREQ) 182 C10 C04 I Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command. Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a device on the 16-bit I/O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is requested. REG 176 B11 C05 O Attribute memory select. REG remains high for all common memory accesses. When REG is asserted, access is limited to attribute memory (OE or WE active) and to the I/O space (IORD or IOWR active). Attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. RESET 169 B13 A06 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card. 2−20 Table 2−13. 16-Bit PC Card Interface Control Terminals (Continued) TERMINAL NUMBER NAME I/O DESCRIPTION A03 E08 I/O Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other, determine the operating voltage of the PC Card. E10 B03 I Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the memory or I/O cycle in progress. D19 B09 O Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for memory PC Cards that employ programmable memory technologies. PDV GHK RGVF VS1 VS2 181 167 B10 F12 WAIT 183 WE 156 WP (IOIS16) 186 B09 C03 I Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16) function. I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses. Table 2−14. CardBus PC Card Interface System Terminals TERMINAL NUMBER NAME PDV GHK I/O DESCRIPTION RGVF CCLK 158 C15 E09 O CardBus clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All signals except CRST, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2, CCD1, CVS2, and CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings. CCLKRUN 186 B09 C03 I/O CardBus clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency, and by the PCI4510 device to indicate that the CCLK frequency is going to be decreased. O CardBus reset. CRST brings CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST is asserted, all CardBus PC Card signals are placed in a high-impedance state, and the PCI4510 device drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK. CRST 169 B13 A06 2−21 Table 2−15. CardBus PC Card Address and Data Terminals TERMINAL NUMBER NAME PDV GHK RGVF CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10 CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0 194 192 191 189 188 179 178 177 174 172 171 168 166 165 164 148 145 147 144 142 141 140 139 136 135 132 133 130 131 127 129 126 E08 C08 B08 E09 F09 F11 E11 C11 A12 C12 E12 C13 A14 E13 B14 F18 G17 F19 G18 H15 H14 H17 H18 J14 J17 K14 J19 K17 K15 L14 K18 L15 D01 C01 D03 C02 B01 B04 A04 E06 B05 C06 B06 G09 C07 B07 A07 A10 E11 G11 C11 B11 C12 B12 A12 E12 C13 F12 A13 C14 E13 A14 B14 E14 CC/BE3 CC/BE2 CC/BE1 CC/BE0 176 163 149 137 B11 C14 G15 J15 C05 F09 B10 G12 CPAR 2−22 152 F14 G10 I/O DESCRIPTION I/O CardBus address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31−CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31−CAD0 contain data. CAD31 is the most significant bit. I/O CardBus bus commands and byte enables. CC/BE3−CC/BE0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE3−CC/BE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7−CAD0), CC/BE1 applies to byte 1 (CAD15−CAD8), CC/BE2 applies to byte 2 (CAD23−CAD16), and CC/BE3 applies to byte 3 (CAD31−CAD24). I/O CardBus parity. In all CardBus read and write cycles, the PCI4510 device calculates even parity across the CAD and CC/BE buses. As an initiator during CardBus cycles, the PCI4510 device outputs CPAR with a one-CCLK delay. As a target during CardBus cycles, the PCI4510 device compares its calculated parity to the parity indicator of the initiator; a compare error results in a parity error assertion. Table 2−16. CardBus PC Card Interface Control Terminals TERMINAL NUMBER I/O DESCRIPTION A02 I CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI4510 device supports the binary audio mode and outputs a binary signal from the card to SPKROUT. E18 E10 I/O CCD2 125 187 L17 C09 C15 E05 I CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type. CDEVSEL 157 A16 C09 I/O CardBus device select. The PCI4510 device asserts CDEVSEL to claim a CardBus cycle as the target device. As a CardBus initiator on the bus, the PCI4510 device monitors CDEVSEL until a target responds. If no target responds before timeout occurs, then the PCI4510 device terminates the cycle with an initiator abort. CFRAME 161 B15 C08 I/O CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When CFRAME is deasserted, the CardBus bus transaction is in the final data phase. CGNT 156 D19 B09 O CardBus bus grant. CGNT is driven by the PCI4510 device to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed. CINT 182 C10 C04 I CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host. NAME PDV GHK RGVF CAUDIO 184 F10 CBLOCK 153 CCD1 CardBus lock. CBLOCK is used to gain exclusive access to a target. CIRDY 160 F13 B08 I/O CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY and CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted. CPERR 154 F15 F10 I/O CardBus parity error. CPERR reports parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following the data cycle during which a parity error is detected. CREQ 173 B12 E07 I CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator. CSERR 183 E10 B03 I CardBus system error. CSERR reports address parity errors and other system errors that could lead to catastrophic results. CSERR is driven by the card synchronous to CCLK, but deasserted by a weak pullup; deassertion may take several CCLK periods. The PCI4510 device can report CSERR to the system by assertion of SERR on the PCI interface. CSTOP 155 E17 A09 I/O CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP is used for target disconnects, and is commonly asserted by target devices that do not support burst data transfers. CSTSCHG 185 A09 B02 I CardBus status change. CSTSCHG alerts the system to a change in the card status, and is used as a wake-up mechanism. CTRDY 159 E14 A08 I/O CardBus target ready. CTRDY indicates the ability of the CardBus target to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY and CTRDY are asserted; until this time, wait states are inserted. CVS1 CVS2 181 167 B10 F12 A03 E08 I/O CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and card type. 2−23 Table 2−17. IEEE 1394 Physical Layer Terminals TERMINAL NUMBER NAME CNA PDV GHK RGVF 111 P17 P15 I/O DESCRIPTION I/O Cable not active. This terminal is asserted high when there are no ports receiving incoming bias voltage. If it is not used, then this terminal must be strapped either to GND through a resistor. Cable power status input. This terminal is normally connected to cable power through a 400-kΩ resistor. This circuit drives an internal comparator that is used to detect the presence of cable power. If CPS is not used to detect cable power, then this terminal must be pulled to AVDD. PLL filter terminals. These terminals are connected to an external capacitance to form a lag-lead filter required for stable operation of the internal frequency multiplier PLL running off of the crystal oscillator. A 0.1-µF ±10% capacitor is the only external component required to complete this filter. CPS 80 P10 M11 I FILTER0 FILTER1 105 106 T19 R17 T18 T19 I/O PC0 PC1 PC2 77 76 75 V10 W10 P09 R12 U13 V13 I Power class programming inputs. On hardware reset, these inputs set the default value of the power class indicated during self-ID. Programming is done by tying these terminals high or low. R0 R1 91 92 W13 V13 U18 U19 − Current-setting resistor terminals. These terminals are connected to an external resistance to set the internal operating currents and cable driver output currents. A resistance of 6.34 kΩ ±1% is required to meet the IEEE Std 1394-1995 output voltage limits. TPA0P TPA0N 87 86 V12 W12 V15 W15 I/O TPA1P TPA1N 101 99 V15 W15 V18 W18 I/O TPBIAS0 TPBIAS1 88 103 U12 U15 U15 U17 I/O TPB0P TPB0N 82 81 V11 W11 V14 W14 I/O TPB1P TPB1N 96 95 V14 W14 V16 W16 I/O XI XO 2−24 109 110 R18 R19 R18 R19 − Twisted-pair cable A differential signal terminals. Board trace lengths from each pair of positive and negative differential signal pins must be matched and as short as possible to the external load resistors and to the cable connector. Twisted-pair bias output. This provides the 1.86-V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for signaling to the remote nodes that there is an active cable connection. Each of these pins must be decoupled with a 1.0-µF capacitor to ground. Twisted-pair cable B differential signal terminals. Board trace lengths from each pair of positive and negative differential signal pins must be matched and as short as possible to the external load resistors and to the cable connector. Crystal oscillator inputs. These pins connect to a 24.576-MHz parallel resonant fundamental mode crystal. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used (see Section 3.11.2, Crystal Selection). Terminal 5 has an internal 10-kΩ (nominal value) pulldown resistor. An external clock input can be connected to the XI terminal. When using an external clock input, the XO terminal must be left unconnected. Refer to Section 11.7 for the operating characteristics of the XI terminal. Table 2−18. Power Supply Terminals TERMINAL NUMBER NAME I/O PDV GHK RGVF ANALOGGND 83 90 97 U11 R12 R13 N12 U14 U16 ANALOGVCC 85 93 98 R11 U13 U14 PLLGND 108 N14 PLLVCC 107 P15 DESCRIPTION − Analog circuit ground terminals. R13 R14 V17 − Analog circuit power terminals. A parallel combination of high frequency decoupling capacitors near each terminal is suggested, such as 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. These supply terminals are separated from PLLVCC and PLLGND internal to the device to provide noise isolation. They must be tied at a low-impedance point on the circuit board. P14 − PLL circuit ground terminals. This terminal must be tied to the low-impedance circuit board ground plane. − PLL circuit power terminals. A parallel combination of high frequency decoupling capacitors near the terminal is suggested, such as 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. This supply terminal is separated from AVDx internal to the device to provide noise isolation. It must be tied at a low-impedance point on the circuit board. V19 Table 2−19. Smart Card and Memory Card Terminals TERMINAL NUMBER NAME I/O DESCRIPTION H07, G05, G03, H03, G02, J06, H05, F03, G01 − Memory card terminals. Reserved for future use. These terminals must be left unconnected. J01, J02, J03, J05, J07, K01, K02 − Smart card terminals. Reserved for future use. These terminals must be left unconnected. PDV GHK RGVF MC_RSVD 113, 115, 116, 117, 118, 119, 120, 121, 122 N15, M14, N17, N18, N19, M15, M17, M18, M19 SC_RSVD 196, 197, 198, 199, 200, 201, 202 A06, B06, B07, C06, C07, E07, F07 2−25 2−26 3 Feature/Protocol Descriptions The following sections give an overview of the PCI4510 device. Figure 3−1 shows the connections to the PCI4510 device. The PCI interface includes all address/data and control signals for PCI protocol. The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. PCI Bus 1394 Ports Activity LED TPS2211A or TPS2221 Power Switch Interrupt Controller IRQSER PCI4510 4 2 PC Card Socket Zoomed Video 68 23 19 VGA Controller Multiplexer Zoomed Video External ZV Port 4 Audio Subsystem NOTE: The PC Card interface is 68 terminals for CardBus and 16-bit PC Cards. In ZV mode, 23 terminals are used for routing the ZV signals to the VGA controller and audio subsystem. Figure 3−1. PCI4510 System Block Diagram 3.1 Power Supply Sequencing The PCI4510 device contains 3.3-V I/O buffers with 5-V tolerance requiring a core power supply and clamp voltages. The core power supply is always 1.8 V. The clamp voltages can be either 3.3 V or 5 V, depending on the interface. The following power-up and power-down sequences are recommended. The power-up sequence is: 1. Assert GRST to the device to disable the outputs during power up. Output drivers must be powered up in the high-impedance state to prevent high current levels through the clamp diodes to the 5-V supply. 2. Apply 3.3-V power to VCC. 3. Apply the clamp voltage. The power-down sequence is: 1. Assert GRST to switch the outputs to the high-impedance state. 2. Remove the clamp voltage. 3. Remove the 3.3-V power from VCC. 3.2 I/O Characteristics The PCI4510 device meets the ac specifications of the PC Card Standard (release 8.0) and PCI Local Bus Specification. Figure 3−2 shows a 3-state bidirectional buffer. Section 11.2, Recommended Operating Conditions, provides the electrical characteristics of the inputs and outputs. 3−1 VCCP Tied for Open Drain OE Pad Figure 3−2. 3-State Bidirectional Buffer 3.3 Clamping Voltages The clamping voltages are set to match whatever external environment the PCI4510 device is interfaced with: 3.3 V or 5 V. The I/O sites can be pulled through a clamping diode to a voltage rail that protects the core from external signals. The core power supply is always 3.3 V and is independent of the clamping voltages. For example, PCI signaling can be either 3.3 V or 5 V, and the PCI4510 device must reliably accommodate both voltage levels. This is accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a system designer desires a 5-V PCI bus, then VCCP can be connected to a 5-V power supply. 3.4 Peripheral Component Interconnect (PCI) Interface The PCI4510 device is fully compliant with the PCI Local Bus Specification. The PCI4510 device provides all required signals for PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment by connecting the VCCP terminals to the desired voltage level. In addition to the mandatory PCI signals, the PCI4510 device provides the optional interrupt signals INTA and INTB. 3.4.1 1394 PCI Bus Master As a bus master, the 1394 function of the PCI4510 device supports the memory commands specified in Table 3−1 below. The PCI master supports the memory read, memory read line, and memory read multiple commands. The read command usage for read transactions of greater than two data phases are determined by the selection in bits 9−8 (MR_ENHANCE field) of the PCI miscellaneous configuration register (refer to Section 7.23 for details). For read transactions of one or two data phases, a memory read command is used. Table 3−1. PCI Bus Master Command Support PCI 3.4.2 COMMAND C/BE3−C/BE0 OHCI MASTER FUNCTION Memory read 0110 DMA read from memory Memory write 0111 DMA write to memory Memory read multiple 1100 DMA read from memory Memory read line 1110 DMA read from memory Memory write and invalidate 1111 DMA write to memory PCI GRST Signal During the power-up sequence, GRST and PRST must be asserted. GRST can only be deasserted 100 µs after PCLK is stable. PRST can be deasserted at the same time as GRST or any time thereafter. 3−2 3.4.3 PCI Bus Lock (LOCK) The bus-locking protocol defined in the PCI Local Bus Specification is not highly recommended, but is provided on the PCI4510 device as an additional compatibility feature. The PCI LOCK signal can be routed to the MFUNC4 terminal by setting the appropriate values in bits 19−16 of the multifunction routing status register. See Section 4.34, Multifunction Routing Status Register, for details. Note that the use of LOCK is only supported by PCI-to-CardBus bridges in the downstream direction (away from the processor). PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted, nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a transaction on the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK. Note that the CardBus signal for this protocol is CBLOCK to avoid confusion with the bus clock. An agent may need to do an exclusive operation because a critical access to memory might be broken into several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by PCI to be 16 bytes, aligned. The LOCK protocol defined by the PCI Local Bus Specification allows a resource lock without interfering with nonexclusive real-time data transfer, such as video. The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario, the arbiter does not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A complete bus lock may have a significant impact on the performance of the video. The arbiter that supports complete bus LOCK must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation is in progress. The PCI4510 device supports all LOCK protocols associated with PCI-to-PCI bridges, as also defined for PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can solve a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus target supports delayed transactions and blocks access to the target until it completes a delayed read. This target characteristic is prohibited by the PCI Local Bus Specification, and the issue is resolved by the PCI master using LOCK. 3.4.4 Loading CardBus (Function 0) Subsystem Identification The subsystem vendor ID register (PCI offset 40h, see Section 4.25) and subsystem ID register (PCI offset 42h, see Section 4.26) make up a doubleword of PCI configuration space for function 0. This doubleword register is used for system and option card (mobile dock) identification purposes and is required by some operating systems. Implementation of this unique identifier register is a PC 99/PC 2001 requirement. The PCI4510 device offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers is read-only, but can be made read/write by setting bit 5 (SUBSYSRW) in the system control register (PCI offset 80h, see Section 4.28). Once this bit is set, the BIOS can write a subsystem identification value into the registers at PCI offset 40h. The BIOS must clear the SUBSYSRW bit such that the subsystem vendor ID register and subsystem ID register is limited to read-only access. This approach saves the added cost of implementing the serial electrically erasable programmable ROM (EEPROM). In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register must be loaded with a unique identifier via a serial EEPROM. The PCI4510 device loads the data from the serial EEPROM after a reset of the primary bus. Note that the SUSPEND input gates the PCI reset from the entire PCI4510 core, including the serial-bus state machine (see Section 3.8.6, Suspend Mode, for details on using SUSPEND). The PCI4510 device provides a two-line serial-bus host controller that can interface to a serial EEPROM. See Section 3.6, Serial EEPROM Interface, for details on the two-wire serial-bus controller and applications. 3−3 3.5 PC Card Applications The PCI4510 device supports all the PC Card features and applications as described below. • • • • • • 3.5.1 Card insertion/removal and recognition per the PC Card Standard (release 8.0) Zoomed video support Speaker and audio applications LED socket activity indicators PC Card controller programming model CardBus socket registers PC Card Insertion/Removal and Recognition The PC Card Standard (release 8.0) addresses the card-detection and recognition process through an interrogation procedure that the socket must initiate on card insertion into a cold, nonpowered socket. Through this interrogation, card voltage requirements and interface (16-bit versus CardBus) are determined. The scheme uses the card-detect and voltage-sense signals. The configuration of these four terminals identifies the card type and voltage requirements of the PC Card interface. The encoding scheme is defined in the PC Card Standard (release 8.0) and in Table 3−2. Table 3−2. PC Card Card-Detect and Voltage-Sense Connections CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 KEY INTERFACE Ground Ground Open Open 5V 16-bit PC Card VCC 5V VPP/VCORE Per CIS (VPP) Ground Ground Open Ground 5V 16-bit PC Card 5 V and 3.3 V Per CIS (VPP) Per CIS (VPP) Ground 5V 16-bit PC Card 5 V, 3.3 V, and X.X V Open Ground LV 16-bit PC Card 3.3 V Per CIS (VPP) Open Connect to CCD1 LV CardBus PC Card 3.3 V Per CIS (VPP) Ground Ground Ground LV 16-bit PC Card 3.3 V and X.X V Per CIS (VPP) Connect to CVS2 Ground Connect to CCD2 Ground LV CardBus PC Card 3.3 V and X.X V Per CIS (VPP) Connect to CVS1 Ground Ground Connect to CCD2 LV CardBus PC Card 3.3 V, X.X V, and Y.Y V Per CIS (VPP) Ground Ground Ground Ground Ground Ground Ground Connect to CVS1 Ground Ground Ground Open LV 16-bit PC Card X.X V Per CIS (VPP) Connect to CVS2 Ground Connect to CCD2 Open LV CardBus PC Card 3.3 V 1.8 V (VCORE)† Ground Connect to CVS2 Connect to CCD1 Open LV CardBus PC Card X.X V and Y.Y V Per CIS (VPP) Connect to CVS1 Ground Open Connect to CCD2 LV CardBus PC Card Y.Y V Per CIS (VPP) Ground Connect to CVS1 Ground Connect to CCD1 Reserved Ground Connect to CVS2 Connect to CCD1 Ground Reserved † This hardware voltage selection setting cannot be overridden by CIS configuration settings. 3.5.2 Zoomed Video Support The PCI4510 allows for the implementation of zoomed video (ZV) for PC Cards. Zoomed video is supported by setting bit 6 (ZVENABLE) in the card control register (PCI offset 91h, see Section 4.36) on a per-socket function basis. Setting this bit puts 16-bit PC Card address lines A25−A4 of the PC Card interface in the high-impedance state. These lines can then transfer video and audio data directly to the appropriate controller. Card address lines A3−A0 can still access PC Card CIS registers for PC Card configuration. Figure 3−3 illustrates a PCI4510 ZV implementation. 3−4 Speakers CRT Motherboard PCI Bus VGA Controller Audio Codec Zoomed Video Port 19 PCM Audio Input PC Card 19 4 PC Card Interface PCI4510 Video Audio 4 Figure 3−3. Zoomed Video Implementation Using the PCI4510 Device Not shown in Figure 3−3 is the multiplexing scheme used to route the socket ZV source to the graphics controller. The PCI4510 device provides ZVSTAT and ZVSEL0 signals on the multifunction terminals to switch external bus drivers. Figure 3−4 shows an implementation for switching between two ZV streams using external logic. 1 PCI4510 ZVSTAT ZVSEL0 0 Figure 3−4. Zoomed Video Switching Application Figure 3−4 illustrates an implementation using standard three-state bus drivers with active-low output enables. ZVSEL0 is an active-low output indicating that the CardBus socket ZV mode is enabled. Also shown in Figure 3−4 is a second ZV input that can be provided from a source such as a high-speed serial bus like IEEE 1394. The ZVSTAT signal provides a mechanism to switch the third ZV source. ZVSTAT is an active-high output indicating that the PCI4510 socket is enabled for ZV mode. The implementation shown in Figure 3−4 can be used if PC Card ZV is prioritized over other sources. 3−5 3.5.3 Standardized Zoomed-Video Register Model The standardized zoomed-video register model is defined for the purpose of standardizing the ZV port control for PC Card controllers across the industry. The following list summarizes the standardized zoomed-video register model changes to the existing PC Card register set. • Socket present state register (CardBus socket address + 08h, see Section 6.3) Bit 27 (ZVSUPPORT) has been added. The platform BIOS can set this bit via the socket force event register (CardBus socket address + 0Ch, see Section 6.4) to define whether zoomed video is supported on that socket by the platform. • Socket force event register (CardBus socket address + 0Ch, see Section 6.4) Bit 27 (FZVSUPPORT) has been added. The platform BIOS can use this bit to set bit 27 (ZVSUPPORT) in the socket present state register (CardBus socket address + 08h, see Section 6.3) to define whether zoomed video is supported on that socket by the platform. • Socket control register (CardBus socket address +10h, see Section 6.5) Bit 11 (ZV_ACTIVITY) has been added. This bit is set when zoomed video is enabled for either of the PC Card sockets. Bit 10 (STANDARDZVREG) has been added. This bit defines whether the PC Card controller supports the standardized zoomed-video register model. Bit 9 (ZVEN) is provided for software to enable or disable zoomed video, per socket. If the ZV_EN bit (bit 0) in the diagnostic register (PCI offset 93h, see Section 4.38) is 1, then the standardized zoomed video register model is disabled. For backward compatibility, even if the ZV_EN bit is 0 (enabled), the PCI4510 device allows software to access zoomed video through the legacy address in the card control register (PCI offset 91h, see Section 4.36), or through the new register model in the socket control register (CardBus socket address + 10h, see Section 6.5). 3.5.4 Internal Ring Oscillator The internal ring oscillator provides an internal clock source for the PCI4510 device so that neither the PCI clock nor an external clock is required in order for the PCI4510 device to power down a socket or interrogate a PC Card. This internal oscillator, operating nominally at 16 kHz, is always enabled. 3.5.5 Integrated Pullup Resistors for PC Card Interface The PC Card Standard (release 8.0) requires pullup resistors on various terminals to support both CardBus and 16-bit card configurations. Unlike the PCI12XX, PCI1450, and PCI4450 devices which required external pullup resistors, the PCI4510 device has integrated all of these pullup resistors. The I/O buffer on the BVD1(STSCHG/RI)//CSTSCHG terminal has the capability to switch either pullup or pulldown resistor. The pullup resistor is turned on when a 16-bit PC Card is inserted, and the pulldown resistor is turned on when a CardBus PC Card is inserted. This prevents unexpected CSTSCHG signal assertion. The integrated pullup resistors are listed in Table 3−3. 3−6 Table 3−3. Integrated Pullup Resistors TERMINAL NUMBER SIGNAL NAME 3.5.6 PDV GHK RGVF A14/CPERR 154 F15 F10 A15/CIRDY 160 F13 B08 A19/CBLOCK 153 E18 E10 A20/CSTOP 155 E17 A09 A21/CDEVSEL 157 A16 C09 A22/CTRDY 159 E14 A08 BVD1(STSCHG/RI)/CSTSCHG 185 A09 B02 BVD2(SPKR)/CAUDIO 184 F10 A02 CD1/CCD1 125 L17 C15 E05 CD2/CCD2 187 C09 INPACK/CREQ 173 B12 E07 READY/CINT 182 C10 C04 RESET/CRST 169 B13 A06 VS1/CVS1 181 B10 A03 E08 VS2/CVS2 167 F12 WAIT/CSERR 183 E10 B03 WP(IOIS16)/CCLKRUN 186 B09 C03 SPKROUT and CAUDPWM Usage SPKROUT carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured for I/O mode, the BVD2 terminal becomes SPKR. This terminal is also used in CardBus binary audio applications, and is referred to as CAUDIO. SPKR passes a TTL-level digital audio signal to the PCI4510 device. The CardBus CAUDIO signal also can pass a single-amplitude binary waveform. The binary audio signals from the PC Card socket are XORed in the PCI4510 device to produce SPKROUT. This output is enabled by bit 1 (SPKROUTEN) in the card control register (PCI offset 91h, see Section 4.36). Older controllers support CAUDIO in binary or PWM mode but use the same terminal (SPKROUT). Some audio chips may not support both modes on one terminal and may have a separate terminal for binary and PWM. The PCI4510 implementation includes a signal for PWM, CAUDPWM, which can be routed to an MFUNC terminal. Bit 2 (AUD2MUX), located in the card control register, is programmed on a per-socket function basis to route a CardBus CAUDIO PWM terminal to CAUDPWM. If both CardBus functions enable CAUDIO PWM routing to CAUDPWM, then CardBus socket audio takes precedence. See Section 4.34, Multifunction Routing Status Register, for details on configuring the MFUNC terminals. Figure 3−5 provides an illustration of a sample application using SPKROUT and CAUDPWM. System Core Logic BINARY_SPKR SPKROUT Speaker Subsystem PCI4510 CAUDPWM PWM_SPKR Figure 3−5. Sample Application of SPKROUT and CAUDPWM 3−7 3.5.7 LED Socket Activity Indicators The socket activity LEDs are provided to indicate when a PC Card is being accessed. The LED_SKT signal can be routed to the multifunction terminals. When configured for LED output, this terminal outputs an active high signal to indicate socket activity. The LED_SKT output indicates socket activity to the CardBus socket. See Section 4.34, Multifunction Routing Status Register, for details on configuring the multifunction terminals. The active-high LED signal is driven for 64 ms. When the LED is not being driven high, it is driven to a low state. Either of the two circuits shown in Figure 3−6 can be implemented to provide LED signaling, and the board designer must implement the circuit that best fits the application. The LED activity signals are valid when a card is inserted, powered, and not in reset. For PC Card-16, the LED activity signals are pulsed when READY(IREQ) is low. For CardBus cards, the LED activity signals are pulsed if CFRAME, IRDY, or CREQ are active. Current Limiting R ≈ 500 Ω LED PCI4510 ApplicationSpecific Delay Current Limiting R ≈ 500 Ω LED PCI4510 Figure 3−6. Two Sample LED Circuits As indicated, the LED signals are driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LEDs appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when the SUSPEND signal is asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state. If any additional socket activity occurs during this counter cycle, then the counter is reset and the LED signal remains driven. If socket activity is frequent (at least once every 64 ms), then the LED signals remain driven. 3.5.8 CardBus Socket Registers The PCI4510 device contains all registers for compatibility with the PC Card Standard. These registers exist as the CardBus socket registers and are listed in Table 3−4. Table 3−4. CardBus Socket Registers REGISTER NAME OFFSET Socket event 00h Socket mask 04h Socket present state 08h Socket force event 0Ch Socket control 10h Reserved Socket power management 14h−1Ch 20h 3.6 Serial EEPROM Interface The PCI4510 device has a dedicated serial bus interface that can be used with an EEPROM to load certain registers in the PCI4510 device. The EEPROM is detected by a pullup resistor on the SCL terminal. An EEPROM interface 3−8 exists in function 1 1394 OHCI and function 0 CardBus. The PCI4510 device includes a busy indication between the interfaces to allow all of the functions to load. Function 0 is loaded first, followed by function 1. 3.6.1 Serial-Bus Interface Implementation The PCI4510 device drives SCL at nearly 100 kHz during data transfers, which is the maximum specified frequency for standard mode I2C. The serial EEPROM must be located at address A0h. Some serial device applications may include PC Card power switches, ZV source switches, card ejectors, or other devices that may enhance the user’s PC Card experience. The serial EEPROM device and PC Card power switches are discussed in the sections that follow. 3.6.2 Serial-Bus Interface Protocol The SCL and SDA signals are bidirectional, open-drain signals and require pullup resistors. The PCI4510 device, which supports up to 100-Kb/s data-transfer rate, is compatible with standard mode I2C using 7-bit addressing. All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start condition, which is signaled when the SDA line transitions to the low state while SCL is in the high state, as illustrated in Figure 3−7. The end of a requested data transfer is indicated by a stop condition, which is signaled by a low-to-high transition of SDA while SCL is in the high state, as shown in Figure 3−7. Data on SDA must remain stable during the high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control signals, that is, a start or a stop condition. SDA SCL Start Condition Stop Condition Change of Data Allowed Data Line Stable, Data Valid Figure 3−7. Serial-Bus Start/Stop Conditions and Bit Transfers Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by the receiver pulling the SDA signal low, so that it remains low during the high state of the SCL signal. Figure 3−8 illustrates the acknowledge protocol. SCL From Master 1 2 3 7 8 9 SDA Output By Transmitter SDA Output By Receiver Figure 3−8. Serial-Bus Protocol Acknowledge The PCI4510 device is a serial bus master; all other devices connected to the serial bus external to the PCI4510 device are slave devices. As the bus master, the PCI4510 device drives the SCL clock at nearly 100 kHz during bus cycles and places SCL in a high-impedance state (zero frequency) during idle states. 3−9 Typically, the PCI4510 device masters byte reads and byte writes under software control. Doubleword reads are performed by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under software control. See Section 3.6.3, Serial-Bus EEPROM Application, for details on how the PCI4510 device automatically loads the subsystem identification and other register defaults through a serial-bus EEPROM. Figure 3−9 illustrates a byte write. The PCI4510 device issues a start condition and sends the 7-bit slave device address and the command bit zero. A 0 in the R/W command bit indicates that the data transfer is a write. The slave device acknowledges if it recognizes the address. If no acknowledgment is received by the PCI4510 device, then an appropriate status bit is set in the serial-bus control and status register (PCI offset B3h, see Section 4.47). The word address byte is then sent by the PCI4510 device, and another slave acknowledgment is expected. Then the PCI4510 device delivers the data byte MSB first and expects a final acknowledgment before issuing the stop condition. Slave Address S Word Address b6 b5 b4 b3 b2 b1 b0 0 A Data Byte b7 b6 b5 b4 b3 b2 b1 b0 A b7 b6 b5 b4 b3 b2 b1 b0 A P R/W A = Slave Acknowledgement S/P = Start/Stop Condition Figure 3−9. Serial-Bus Protocol − Byte Write Figure 3−10 illustrates a byte read. The read protocol is very similar to the write protocol, except the R/W command bit must be set to 1 to indicate a read-data transfer. In addition, the PCI4510 master must acknowledge reception of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data transfers. The SCL signal remains driven by the PCI4510 master. Slave Address S Word Address b6 b5 b4 b3 b2 b1 b0 Start 0 A Slave Address b7 b6 b5 b4 b3 b2 b1 b0 A S b6 b5 b4 b3 b2 b1 b0 Restart R/W 1 A R/W Data Byte b7 b6 b5 b4 b3 b2 b1 b0 M P Stop A = Slave Acknowledgement M = Master Acknowledgement S/P = Start/Stop Condition Figure 3−10. Serial-Bus Protocol − Byte Read Figure 3−11 illustrates EEPROM interface doubleword data collection protocol. Slave Address S 1 0 1 0 0 Word Address 0 0 Start 0 A Slave Address b7 b6 b5 b4 b3 b2 b1 b0 M A = Slave Acknowledgement S 1 0 1 0 Data Byte 2 M Data Byte 1 M = Master Acknowledgement M Data Byte 0 0 0 1 R/W M P S/P = Start/Stop Condition Figure 3−11. EEPROM Interface Doubleword Data Collection 3−10 0 Restart R/W Data Byte 3 A A 3.6.3 Serial-Bus EEPROM Application When the PCI bus is reset and the serial-bus interface is detected, the PCI4510 device attempts to read the subsystem identification and other register defaults from a serial EEPROM. See Table 3−5 for the EEPROM loading map. This format must be followed for the PCI4510 device to load initializations from a serial EEPROM. All bit fields must be considered when programming the EEPROM. The serial EEPROM is addressed at slave address 1010 000b by the PCI4510 device. All hardware address bits for the EEPROM must be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample application (see Figure 3−11) assumes the 1010b high-address nibble. The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND. Table 3−5. EEPROM Loading Map SERIAL ROM OFFSET BYTE DESCRIPTION FUNCTION 1 – 1394 OHCI 00h PCI 3Fh, MaxLat, bits 7−4 PCI 3Eh, MinGnt, bits 3−0 01h PCI 2Ch, subsystem vendor ID, byte 0 02h PCI 2Dh, subsystem vendor ID, byte 1 03h PCI 2Eh, subsystem ID, byte 0 04h PCI 2Fh, subsystem ID, byte 1 05h PCI F4h, Link_Enh, byte 0, bits 7, 2, 1 OHCI 50h, host controller control, bit 23 06h [7] [6] [5:3] [2] [1] [0] Link_Enh. enab_unfair HCControl.Program Phy Enable RSVD Link_Enh, bit 2 Link_Enh. enab_accel RSVD Mini-ROM addr, bits 6:5 are used to indicate that the MINI ROM is present 00b = No MINI ROM 01b = MINI ROM starts at offset 20h 10b = MINI ROM starts at offset 40h 11b = MINI ROM starts at offset 60h 07h OHCI 24h, GUIDHi, byte 0 08h OHCI 25h, GUIDHi, byte 1 09h OHCI 26h, GUIDHi, byte 2 0Ah OHCI 27h, GUIDHi, byte 3 0Bh OHCI 28h, GUIDLo, byte 0 0Ch OHCI 29h, GUIDLo, byte 1 0Dh OHCI 2Ah, GUIDLo, byte 2 0Eh OHCI 2Bh, GUIDLo, byte 3 0Fh Checksum (Reserved—no bit loaded) 10h PCI F5h, Link_Enh, byte 1, bits 7, 6, 5, 4 11h PCI F0h, PCI miscellaneous, byte 0, bits 5, 4, 2, 1, 0 12h PCI F1h, PCI miscellaneous, byte 1, bits 7, 2, 1, 0 13h Reserved 14h Reserved (CardBus CIS pointer) 15h Reserved 16h PCI ECh, PCI PHY control, bits 7, 3, 2, 1, 0 17h−1Fh Reserved 3−11 Table 3−5. EEPROM Loading Map (Continued) SERIAL ROM OFFSET BYTE DESCRIPTION FUNCTION 0 – CARDBUS 21h PCI 04h, command register, bits 8, 6−5, 2−0 [7] [6] [5] [4:3] [2] [1] [0] Command register bit 8 Command register bit 6 Command register bit 5 RSVD Command register bit 2 Command register bit 1 Command register bit 0 22h PCI 40h, subsystem vendor ID, byte 0 23h PCI 41h, subsystem vendor ID, byte 1 24h PCI 42h, subsystem ID, byte 0 25h PCI 43h, subsystem ID, byte 1 26h PCI 44h, PC Card 16-bit I/F legacy mode base address register, byte 0, bits 7−1 27h PCI 45h, PC Card 16-bit I/F legacy mode base address register, byte 1 28h PCI 46h, PC Card 16-bit I/F legacy mode base address register, byte 2 29h PCI 47h, PC Card 16-bit I/F legacy mode base address register, byte 3 2Ah PCI 80h, system control, byte 0 2Bh PCI 81h, system control, byte 1 2Ch Reserved—Load all 0s 2Dh PCI 83h, system control, byte 3 2Eh PCI 8Ch, multifunction routing, byte 0 2Fh PCI 8Dh, multifunction routing, byte 1 30h PCI 8Eh, multifunction routing, byte 2 31h PCI 8Fh, multifunction routing, byte 3 32h PCI 90h retry status, bits 7, 6 33h PCI 91h, card control, bit 7 34h PCI 92h, device control, bits 6, 5, 3−0 35h PCI 93h, diagnostic, bits 7, 4−0 36h PCI A2h, power management capabilities, bit 15 (bit 7 of EEPROM offset 36h corresponds to bit 15) 37h Reserved—Load all 0s 38h Reserved—Load all 0s 39h ExCA 00h, ExCA identification and revision, bits 7−0 3Ah PCI 86h, general control, byte 0, bits 3, 1, 0 3Bh PCI 87h, general control, byte 1, bit 2 3Ch PCI 89h, GPE Enable, bits 7, 6, 4−0 3Dh PCI 8Bh, general-purpose output, bits 4−0 3Eh−49h Reserved—Load all 0s 3.6.4 Accessing Serial-Bus Devices Through Software The PCI4510 device provides a programming mechanism to control serial bus devices through software. The programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3−6 lists the registers used to program a serial-bus device through software. 3−12 Table 3−6. PCI4510 Registers Used to Program Serial-Bus Devices PCI OFFSET REGISTER NAME DESCRIPTION B0h Serial-bus data Contains the data byte to send on write commands or the received data byte on read commands. B1h Serial-bus index The content of this register is sent as the word address on byte writes or reads. This register is not used in the quick command protocol. B2h Serial-bus slave address Write transactions to this register initiate a serial-bus transaction. The slave device address and the R/W command selector are programmed through this register. B3h Serial-bus control and status Read data valid, general busy, and general error status are communicated through this register. In addition, the protocol-select bit is programmed through this register. 3.7 Programmable CardBus Interrupt Subsystem Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic nature of PC Cards and the abundance of PC Card I/O applications require substantial interrupt support from the PCI4510 device. The PCI4510 device provides several interrupt signaling schemes to accommodate the needs of a variety of platforms. The different mechanisms for dealing with interrupts in this device are based on various specifications and industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the CardBus socket register set provides interrupt control for the CardBus PC Card functions. The PCI4510 device is, therefore, backward compatible with existing interrupt control register definitions, and new registers have been defined where required. The PCI4510 device detects PC Card interrupts and events at the PC Card interface and notifies the host controller using one of several interrupt signaling protocols. To simplify the discussion of interrupts in the PCI4510 device, PC Card interrupts are classified either as card status change (CSC) or as functional interrupts. The method by which any type of PCI4510 interrupt is communicated to the host interrupt controller varies from system to system. The PCI4510 device offers system designers the choice of using parallel PCI interrupt signaling, parallel ISA-type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. It is possible to use the parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs. All interrupt signaling is provided through the seven multifunction terminals, MFUNC0−MFUNC6. 3.7.1 PC Card Functional and Card Status Change Interrupts PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by 16-bit I/O PC Cards and by CardBus PC Cards. Card status change (CSC)-type interrupts are defined as events at the PC Card interface that are detected by the PCI4510 device and may warrant notification of host card and socket services software for service. CSC events include both card insertion and removal from PC Card socket, as well as transitions of certain PC Card signals. Table 3−7 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The three types of cards that can be inserted into any PC Card socket are: • • • 16-bit memory card 16-bit I/O card CardBus cards 3−13 Table 3−7. Interrupt Mask and Flag Registers CARD TYPE 16-bit memory 16-bit I/O All 16-bit PC Cards CardBus EVENT MASK FLAG Battery conditions (BVD1, BVD2) ExCA offset 05h/805h bits 1 and 0 ExCA offset 04h/804h bits 1 and 0 Wait states (READY) ExCA offset 05h/805h bit 2 ExCA offset 04h/804h bit 2 Change in card status (STSCHG) ExCA offset 05h/805h bit 0 ExCA offset 04h/804h bit 0 Interrupt request (IREQ) Always enabled PCI configuration offset 91h bit 0 Power cycle complete ExCA offset 05h/805h bit 3 ExCA offset 04h/804h bit 3 Change in card status (CSTSCHG) Socket mask bit 0 Socket event bit 0 Interrupt request (CINT) Always enabled PCI configuration offset 91h bit 0 Power cycle complete Socket mask bit 3 Socket event bit 3 Card insertion or removal Socket mask bits 2 and 1 Socket event bits 2 and 1 Functional interrupt events are valid only for 16-bit I/O and CardBus cards; that is, the functional interrupts are not valid for 16-bit memory cards. Furthermore, card insertion and removal-type CSC interrupts are independent of the card type. Table 3−8. PC Card Interrupt Events and Description CARD TYPE 16-bit memory 16-bit I/O CardBus All PC Cards EVENT TYPE SIGNAL DESCRIPTION BVD1(STSCHG)//CSTSCHG A transition on BVD1 indicates a change in the PC Card battery conditions. BVD2(SPKR)//CAUDIO A transition on BVD2 indicates a change in the PC Card battery conditions. Battery conditions (BVD1, BVD2) CSC Wait states (READY) CSC READY(IREQ)//CINT Change in card status (STSCHG) CSC BVD1(STSCHG)//CSTSCHG The assertion of STSCHG indicates a status change on the PC Card. Interrupt request (IREQ) Functional READY(IREQ)//CINT The assertion of IREQ indicates an interrupt request from the PC Card. Change in card status (CSTSCHG) CSC BVD1(STSCHG)//CSTSCHG Interrupt request (CINT) Functional READY(IREQ)//CINT Card insertion or removal CSC CD1//CCD1 CD2//CCD2 Power cycle complete CSC N/A A transition on READY indicates a change in the ability of the memory PC Card to accept or provide data. The assertion of CSTSCHG indicates a status change on the PC Card. The assertion of CINT indicates an interrupt request from the PC Card. A transition on either CD1//CCD1 or CD2//CCD2 indicates an insertion or removal of a 16-bit or CardBus PC Card. An interrupt is generated when a PC Card power-up cycle has completed. The naming convention for PC Card signals describes the function for 16-bit memory, I/O cards, and CardBus. For example, READY(IREQ)//CINT includes READY for 16-bit memory cards, IREQ for 16-bit I/O cards, and CINT for CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name second, enclosed in parentheses. The CardBus signal name follows after a double slash (//). The PC Card Standard describes the power-up sequence that must be followed by the PCI4510 device when an insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon completion of this power-up sequence, the PCI4510 interrupt scheme can be used to notify the host system (see Table 3−8), denoted by the power cycle complete event. This interrupt source is considered a PCI4510 internal event, because it depends on the completion of applying power to the socket rather than on a signal change at the PC Card interface. 3−14 3.7.2 Interrupt Masks and Flags Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 3−8 by setting the appropriate bits in the PCI4510 device. By individually masking the interrupt sources listed, software can control those events that cause a PCI4510 interrupt. Host software has some control over the system interrupt the PCI4510 device asserts by programming the appropriate routing registers. The PCI4510 device allows host software to route PC Card CSC and PC Card functional interrupts to separate system interrupts. Interrupt routing somewhat specific to the interrupt signaling method used is discussed in more detail in the following sections. When an interrupt is signaled by the PCI4510 device, the interrupt service routine must determine which of the events listed in Table 3−7 caused the interrupt. Internal registers in the PCI4510 device provide flags that report the source of an interrupt. By reading these status bits, the interrupt service routine can determine the action to be taken. Table 3−7 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts. Notice that there is not a mask bit to stop the PCI4510 device from passing PC Card functional interrupts through to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there must never be a card interrupt that does not require service after proper initialization. Table 3−7 lists the various methods of clearing the interrupt flag bits. The flag bits in the ExCA registers (16-bit PC Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1 to the flag bit to clear and the other is by reading the flag bit register. The selection of flag bit clearing methods is made by bit 2 (IFCMODE) in the ExCA global control register (ExCA offset 1Eh/81Eh, see Section 5.20), and defaults to the flag-cleared-on-read method. The CardBus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event register (see Section 6.1). Although some of the functionality is shared between the CardBus registers and the ExCA registers, software must not program the chip through both register sets when a CardBus card is functioning. 3.7.3 Using Parallel IRQ Interrupts The seven multifunction terminals, MFUNC6−MFUNC0, implemented in the PCI4510 device can be routed to obtain a subset of the ISA IRQs. The IRQ choices provide ultimate flexibility in PC Card host interruptions. To use the parallel ISA-type IRQ interrupt signaling, software must program the device control register (PCI offset 92h, see Section 4.37), to select the parallel IRQ signaling scheme. See Section 4.34, Multifunction Routing Status Register, for details on configuring the multifunction terminals. A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA, to signal CSC events. This requirement is dictated by certain card and socket-services software. The INTA requirement calls for routing the MFUNC0 terminal for INTA signaling. The INTRTIE bit is used, in this case, to route socket interrupt events to INTA. This leaves (at a maximum) six different IRQs to support legacy 16-bit PC Card functions. As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ10, IRQ11, and IRQ15. The multifunction routing status register must be programmed to a value of 0FBA 5432h. This value routes the MFUNC0 terminal to INTA signaling and routes the remaining terminals as illustrated in Figure 3−12. Not shown is that INTA must also be routed to the programmable interrupt controller (PIC), or to some circuitry that provides parallel PCI interrupts to the host. 3−15 PCI4510 MFUNC1 IRQ3 PIC MFUNC2 IRQ4 MFUNC3 IRQ5 MFUNC4 IRQ10 MFUNC5 IRQ11 MFUNC6 IRQ15 Figure 3−12. IRQ Implementation Power-on software is responsible for programming the multifunction routing status register to reflect the IRQ configuration of a system implementing the PCI4510 device. The multifunction routing status register is shared between the two PCI4510 functions, and only one write to function 0 or 1 is necessary to configure the MFUNC6−MFUNC0 signals. Writing to function 0 only is recommended. See Section 4.34, Multifunction Routing Status Register, for details on configuring the multifunction terminals. The parallel ISA-type IRQ signaling from the MFUNC6−MFUNC0 terminals is compatible with the input signal requirements of the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs. Design constraints may demand more MFUNC6−MFUNC0 IRQ terminals than the PCI4510 device makes available. 3.7.4 Using Parallel PCI Interrupts Parallel PCI interrupts are available when exclusively in parallel PCI interrupt/parallel ISA IRQ signaling mode, and when only IRQs are serialized with the IRQSER protocol. Both INTA and INTB can be routed to MFUNC terminals (MFUNC0 and MFUNC1). However, interrupts of both socket functions can be routed to INTA (MFUNC0) if bit 29 (INTRTIE) is set in the system control register (PCI offset 80h, see Section 4.28). The INTRTIE bit affects the read-only value provided through accesses to the interrupt pin register (PCI offset 3Dh, see Section 4.23). When the INTRTIE bit is set, both functions return a value of 01h on reads from the interrupt pin register for both parallel and serial PCI interrupts. Table 3−9 summarizes the interrupt signaling modes. Table 3−9. Interrupt Pin Register Cross Reference INTPIN INTRTIE BIT 3.7.5 FUNCTION 0 FUNCTION 1 0 01h 02h 1 01h 01h Using Serialized IRQSER Interrupts The serialized interrupt protocol implemented in the PCI4510 device uses a single terminal to communicate all interrupt status information to the host controller. The protocol defines a serial packet consisting of a start cycle, multiple interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI clock. The packet data describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA, INTB, INTC, and INTD. For details on the IRQSER protocol, refer to the document Serialized IRQ Support for PCI Systems. 3.7.6 SMI Support in the PCI4510 Device The PCI4510 device provides a mechanism for interrupting the system when power changes have been made to the PC Card socket interfaces. The interrupt mechanism is designed to fit into a system maintenance interrupt (SMI) scheme. SMI interrupts are generated by the PCI4510 device, when enabled, after a write cycle to either the socket control register (CB offset 10h, see Section 6.5) of the CardBus register set, or the ExCA power control register (ExCA offset 02h/802h, see Section 5.3) causes a power cycle change sequence to be sent on the power switch interface. The SMI control is programmed through three bits in the system control register (PCI offset 80h, see Section 4.28). These bits are SMIROUTE (bit 26), SMISTATUS (bit 25), and SMIENB (bit 24). Table 3−10 describes the SMI control bits function. 3−16 Table 3−10. SMI Control BIT NAME FUNCTION SMIROUTE This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2. SMISTAT This socket dependent bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1. SMIENB When set, SMI interrupt generation is enabled. This bit is shared by functions 0 and 1. If CSC SMI interrupts are selected, then the SMI interrupt is sent as the CSC on a per-socket basis. The CSC interrupt can be either level or edge mode, depending upon the CSCMODE bit in the ExCA global control register (ExCA offset 1Eh/81Eh, see Section 5.20). If IRQ2 is selected by SMIROUTE, then the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data slot. In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either MFUNC3 or MFUNC6 through the multifunction routing status register (PCI offset 8Ch, see Section 4.34). 3.8 Power Management Overview In addition to the low-power CMOS technology process used for the PCI4510 device, various features are designed into the device to allow implementation of popular power-saving techniques. These features and techniques are as follows: • • • • • • • • 3.8.1 Clock run protocol Cardbus PC Card power management 16-bit PC Card power management Suspend mode Ring indicate PCI power management Cardbus bridge power management ACPI support 1394 Power Management (Function 1) The PCI4510 device complies with PCI Bus Power Management Interface Specification. The device supports the D0 (uninitialized), D0 (active), D1, D2, and D3 power states as defined by the power management definition in the 1394 Open Host Controller Interface Specification, Appendix A.4. PME is supported to provide notification of wake events. Per Section A.4.2, the 1394 OHCI sets PMCSR.PME_STS in the D0 state due to unmasked interrupt events. In previous OHCI implementations, unmasked interrupt events was interpreted as (IntEvent.n && IntMask.n && IntMask.masterIntEnable), where n represents a specific interrupt event. Based on feedback from Microsoft this implementation may cause problems with the existing Windows power management arcitecture as a PME and an interrupt could be simultaneously signaled on a transition from the D1 to D0 state where interrupts were enabled to generate wake events. If bit 10 (ignore_mstrIntEna_for_pme) in the PCI miscellaneous configuration register (OHCI offset F0h, see Section 7.23) is set, then the PCI4510 device implements the preferred behavior as (IntEvent.n && IntMask.n). Otherwise, the PCI4510 device implements the preferred behavior as (IntEvent.n && IntMask.n && IntMask.masterIntEnable). In addition, when the ignore_mstrIntEna_for_pme bit is set, it causes bit 26 of the OHCI vendor ID register (OHCI offset 40h, see Section 8.15) to read 1, otherwise, bit 26 reads 0. An open drain buffer is used for PME. 3.8.2 Integrated Low-Dropout Voltage Regulator (LDO-VR) The PCI4510 device requires 1.8-V core voltage. The core power can be supplied by the PCI4510 device itself using the internal LDO-VR. The core power can alternatively be supplied by an external power supply through the VR_PORT terminal. Table 3−11 lists the requirements for both the internal core power supply and the external core power supply. 3−17 Table 3−11. Requirements for Internal/External 1.8-V Core Power Supply SUPPLY VR_EN VR_PORT Internal VCC 3.3 V GND 1.8-V output Internal 1.8-V LDO-VR is enabled. A 1.0-µF bypass capacitor is required on the VR_PORT terminal for decoupling. This output is not for external use. External 3.3 V VCC 1.8-V input Internal 1.8-V LDO-VR is disabled. An external 1.8-V power supply, of minimum 50-mA capacity, is required. A 0.1-µF bypass capacitor on the VR_PORT terminal is required. 3.8.3 NOTE CardBus (Function 0) Clock Run Protocol The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCI4510 device. CLKRUN signaling is provided through the MFUNC6 terminal. Since some chip sets do not implement CLKRUN, this is not always available to the system designer, and alternate power-saving features are provided. For details on the CLKRUN protocol see the PCI Mobile Design Guide. The PCI4510 device does not permit the central resource to stop the PCI clock under any of the following conditions: • Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.28) is set. • The 16-bit PC Card resource manager is busy. • The PCI4510 CardBus master state machine is busy. A cycle may be in progress on CardBus. • The PCI4510 master is busy. There may be posted data from CardBus to PCI in the PCI4510 device. • Interrupts are pending. • The CardBus CCLK for the socket has not been stopped by the PCI4510 CCLKRUN manager. The PCI4510 device restarts the PCI clock using the CLKRUN protocol under any of the following conditions: • A 16-bit PC Card IREQ or a CardBus CINT has been asserted by either card. • A CardBus CBWAKE (CSTSCHG) or 16-bit PC Card STSCHG/RI event occurs in the socket. • A CardBus attempts to start the CCLK using CCLKRUN. • A CardBus card arbitrates for the CardBus bus using CREQ. 3.8.4 CardBus PC Card Power Management The PCI4510 device implements its own card power-management engine that can turn off the CCLK to a socket when there is no activity to the CardBus PC Card. The PCI clock-run protocol is followed on the CardBus CCLKRUN interface to control this clock management. 3.8.5 16-Bit PC Card Power Management The COE bit (bit 7) of the ExCA power control register (ExCA offset 02h/802h, see Section 5.3) and PWRDWN bit (bit 0) of the ExCA global control register (ExCA offset 1Eh/81Eh, see Section 5.20) bits are provided for 16-bit PC Card power management. The COE bit places the card interface in a high-impedance state to save power. The power savings when using this feature are minimal. The COE bit resets the PC Card when used, and the PWRDWN bit does not. Furthermore, the PWRDWN bit is an automatic COE, that is, the PWRDWN performs the COE function when there is no card activity. NOTE: The 16-bit PC Card must implement the proper pullup resistors for the COE and PWRDWN modes. 3.8.6 Suspend Mode The SUSPEND signal, provided for backward compatibility, gates the PRST (PCI reset) signal and the GRST (global reset) signal from the PCI4510 device. Besides gating PRST and GRST, SUSPEND also gates PCLK inside the PCI4510 device in order to minimize power consumption. 3−18 It should also be noted that asynchronous signals, such as card status change interrupts and RI_OUT, can be passed to the host system without a PCI clock. However, if card status change interrupts are routed over the serial interrupt stream, then the PCI clock must be restarted in order to pass the interrupt, because neither the internal oscillator nor an external clock is routed to the serial-interrupt state machine. Figure 3−13 is a signal diagram of the suspend function. RESET GNT SUSPEND PCLK External Terminals Internal Signals RESETIN SUSPENDIN PCLKIN Figure 3−13. Signal Diagram of Suspend Function 3.8.7 Requirements for Suspend Mode The suspend mode prevents the clearing of all register contents on the assertion of reset (PRST or GRST) which would require the reconfiguration of the PCI4510 device by software. Asserting the SUSPEND signal places the PCI outputs of the controller in a high-impedance state and gates the PCLK signal internally to the controller unless a PCI transaction is currently in process (GNT is asserted). It is important that the PCI bus not be parked on the PCI4510 device when SUSPEND is asserted because the outputs are in a high-impedance state. The GPIOs, MFUNC signals, and RI_OUT signal are all active during SUSPEND, unless they are disabled in the appropriate PCI4510 registers. 3.8.8 Ring Indicate The RI_OUT output is an important feature in power management, allowing a system to go into a suspended mode and wake up on modem rings and other card events. TI-designed flexibility permits this signal to fit wide platform requirements. RI_OUT on the PCI4510 device can be asserted under any of the following conditions: • A 16-bit PC Card modem in a powered socket asserts RI to indicate to the system the presence of an incoming call. • A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake-up. • A powered CardBus card asserts CSTSCHG from the insertion/removal of cards or change in battery voltage levels. 3−19 Figure 3−14 shows various enable bits for the PCI4510 RI_OUT function; however, it does not show the masking of CSC events. See Table 3−7 for a detailed description of CSC interrupt masks and flags. RI_OUT Function CSTSMASK PC Card Socket RIENB CSC Card I/F RINGEN RI_OUT RI CDRESUME CSC Figure 3−14. RI_OUT Functional Diagram RI from the 16-bit PC Card interface is masked by bit 7 (RINGEN) in the ExCA interrupt and general control register (ExCA offset 03h/803h, see Section 5.4). This is programmed on a per-socket basis and is only applicable when a 16-bit card is powered in the socket. The CBWAKE signaling to RI_OUT is enabled through the same mask as the CSC event for CSTSCHG. The mask bit (bit 0, CSTSMASK) is programmed through the socket mask register (CB offset 04h, see Section 6.2) in the CardBus socket registers. RI_OUT can be routed through any of three different pins, RI_OUT/PME, MFUNC2, or MFUNC4. The RI_OUT function is enabled by setting bit 7 (RIENB) in the card control register (PCI offset 91h, see Section 4.36). The PME function is enabled by setting bit 8 (PME_ENABLE) in the power management control/status register (PCI offset A4h, see Section 4.42). When bit 0 (RIMUX) in the system control register (PCI offset 80h, see Section 4.28) is set to 0, both the RI_OUT function and the PME function are routed to the RI_OUT/PME terminal. If both functions are enabled and RIMUX is set to 0, then the RI_OUT/PME terminal becomes RI_OUT only and PME assertions are never seen. Therefore, in a system using both the RI_OUT function and the PME function, RIMUX must be set to 1 and RI_OUT must be routed to either MFUNC2 or MFUNC4. 3.8.9 PCI Power Management for CardBus (Function 0) The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges establishes the infrastructure required to let the operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of seven power-management states, resulting in varying levels of power savings. The seven power-management states of PCI functions are: • • • • • • • D0-uninitialized − Before device configuration, device not fully functional D0-active − Fully functional state D1 − Low-power state D2 − Low-power state D3hot − Low-power state. Transition state before D3cold D3cold − PME signal-generation capable. Main power is removed and VAUX is available. D3off − No power and completely nonfunctional NOTE 1: In the D0-uninitialized state, the PCI4510 device does not generate PME and/or interrupts. When bits 0 (IO_EN) and 1 (MEM_EN) of the command register (PCI offset 04h, see Section 4.4) are both set, the PCI4510 device switches the state to D0-active. Transition from D3cold to the D0-uninitialized state happens at the deassertion of PRST. The assertion of GRST forces the controller to the D0-uninitialized state immediately. NOTE 2: The PWR_STATE bits (bits 1−0) of the power-management control/status register (PCI offset A4h, see Section 4.42) only code for four power states, D0, D1, D2, and D3hot. The differences between the three D3 states is invisible to the software because the controller is not accessible in the D3cold or D3off state. Similarly, bus power states of the PCI bus are B0−B3. The bus power states B0−B3 are derived from the device power state of the originating bridge device. 3−20 For the operating system (OS) to manage the device power states on the PCI bus, the PCI function must support four power-management operations. These operations are: • • • • Capabilities reporting Power status reporting Setting the power state System wake-up The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of capabilities in addition to the standard PCI capabilities is indicated by a 1 in bit 4 (CAPLIST) of the status register (PCI offset 06h, see Section 4.5). The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCI4510 device, a CardBus bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset of 14h. The first byte of each capability register block is required to be a unique ID of that capability. PCI power management has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there are no more items in the list, then the next item pointer must be set to 0. The registers following the next item pointer are specific to the capability of the function. The PCI power-management capability implements the register block outlined in Table 3−12. Table 3−12. Power-Management Registers REGISTER NAME Power-management capabilities Data Power-management control/ status register bridge support extensions OFFSET Next item pointer Capability ID Power-management control/status (CSR) A0h A4h The power management capabilities register (PCI offset A2h, see Section 4.41) provides information on the capabilities of the function related to power management. The power-management control/status register (PCI offset A4h, see Section 4.42) enables control of power-management states and enables/monitors power-management events. The data register is an optional register that can provide dynamic data. For more information on PCI power management, see the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges. 3.8.10 CardBus Bridge Power Management The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges was approved by PCMCIA in December of 1997. This specification follows the device and bus state definitions provided in the PCI Bus Power Management Interface Specification published by the PCI special interest group (SIG). The main issue addressed in the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges is wake-up from D3hot or D3cold without losing wake-up context (also called PME context). The specific issues addressed by the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges for D3 wake-up are as follows: • Preservation of device context. The specification states that a reset must occur during the transition from D3 to D0. Some method to preserve wake-up context must be implemented so that the reset does not clear the PME context registers. • Power source in D3cold if wake-up support is required from this state. The Texas Instruments PCI4510 device addresses these D3 wake-up issues in the following manner: • Two resets are provided to handle preservation of PME context bits: − Global reset (GRST) is used only on the initial boot up of the system after power up. It places the PCI4510 device in its default state and requires BIOS to configure the device before becoming fully functional. 3−21 − • PCI reset (PRST) has dual functionality based on whether PME is enabled or not. If PME is enabled, then PME context is preserved. If PME is not enabled, then PRST acts the same as a normal PCI reset. Please see the master list of PME context bits in Section 3.8.12. Power source in D3cold if wake-up support is required from this state. Since VCC is removed in D3cold, an auxiliary power source must be supplied to the PCI4510 VCC terminals. Consult the PCI14xx Implementation Guide for D3 Wake-Up or the PCI Power Management Interface Specification for PCI to CardBus Bridges for further information. 3.8.11 ACPI Support The Advanced Configuration and Power Interface (ACPI) Specification provides a mechanism that allows unique pieces of hardware to be described to the ACPI driver. The PCI4510 device offers a generic interface that is compliant with ACPI design rules. Two doublewords of general-purpose ACPI programming bits reside in PCI4510 PCI configuration space at offset 88h. The programming model is broken into status and control functions. In compliance with ACPI, the top level event status and enable bits reside in the general-purpose event status register (PCI offset 88h, see Section 4.30) and general-purpose event enable register (PCI offset 89h, see Section 4.31). The status and enable bits are implemented as defined by ACPI and illustrated in Figure 3−15. Status Bit Event Input Enable Bit Event Output Figure 3−15. Block Diagram of a Status/Enable Cell The status and enable bits generate an event that allows the ACPI driver to call a control method associated with the pending status bit. The control method can then control the hardware by manipulating the hardware control bits or by investigating child status bits and calling their respective control methods. A hierarchical implementation would be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report events. For more information of ACPI, see the Advanced Configuration and Power Interface (ACPI) Specification. 3.8.12 Master List of PME Context Bits and Global Reset-Only Bits for CardBus (Function 0) If the PME enable bit (bit 8) of the power-management control/status register (PCI offset A4h, see Section 4.42) is asserted, then the assertion of PRST does not clear the following PME context bits. If the PME enable bit is not asserted, then the PME context bits are cleared with PRST. The PME context bits are: • • • • • • • • • • • Bridge control register (PCI offset 3Eh): bit 6 System control register (PCI offset 80h): bits 10, 9, 8 Power management CSR register (PCI offset A4h): bit 15, 8 ExCA power control register (ExCA offset 802h): bits 7, 5 (82365SL mode only), 4−3, 1−0 ExCA interrupt and general control register (ExCA offset 803h): bits 6−5 ExCA card status change register (ExCA offset 804h): bits 3−0 ExCA card status change interrupt configuration register (ExCA offset 805h): bits 3−0 CardBus socket event register (CardBus offset 00h): bits 3−0 CardBus socket mask register (CardBus offset 04h): bits 3−0 CardBus socket present state register (CardBus offset 08h): bits 27, 13−7, 5−1 CardBus socket control register (CardBus offset 10h): bits 6−4, 2−0 Global reset places all registers in their default state regardless of the state of the PME enable bit. The GRST signal is gated only by the SUSPEND signal. This means that assertion of SUSPEND blocks the GRST signal internally, thus preserving all register contents. The registers cleared only by GRST are: • 3−22 Status register (PCI offset 06h): bits 15−11, 8 • • • • • • • • • • • • • • • • • • • • • • • • Secondary status register (PCI offset 16h): bits 15−11, 8 CardBus subsystem vendor ID register (PCI offset 42h) CardBus subsystem ID register (PCI offset 40h) PC Card 16-bit I/F legacy mode base address register (PCI offset 44h) System control register (PCI offset 80h): bits 31−28, 26−24, 22−13, 11, 6−0 General control register (PCI offset 86h): bits 15−14, 10, 3, 1−0 General-purpose event status register (PCI offset 88h): bits 7−6, 4−0 General-purpose event enable register (PCI offset 89h): bits 7−6, 4−0 General-purpose output register (PCI offset 8Bh): bits 4−0 Multifunction routing register (PCI offset 8Ch) Retry status register (PCI offset 90h): bits 7−5, 3, 1 Card control register (PCI offset 91h) Device control register (PCI offset 92h): bits 7−5, 3−0 Diagnostic register (PCI offset 93h) Socket DMA register 0 (PCI offset 94h): bits 1−0 Socket DMA register 1 (PCI offset 98h): bits 15−4, 2−0 Power management capabilities register (PCI offset A2h): bit 15 Serial bus data register (PCI offset B0h) Serial bus index register (PCI offset B1h) Serial bus slave address register (PCI offset B2h) Serial bus control/status register (PCI offset B3h): bits 7, 5−0 ExCA identification and revision register (ExCA offset 800h) ExCA global control register (ExCA offset 81Eh): bits 2−0 CardBus socket power management register (CardBus offset 20h): bits 25−24 3.8.13 Master List of Global Reset-Only Bits for 1394 OHCI (Function 1) Global reset places all registers in their default state regardless of the state of the PME enable bit. The GRST signal is gated only by the SUSPEND signal. This means that assertion of SUSPEND blocks the GRST signal internally, thus preserving all register contents. The registers cleared only by GRST are: • • • • • • • • • • • • • • • CIS offset register (PCI offset 28h): bits 7−3 Subsystem vendor ID register (PCI offset 2Ch) Subsystem ID register (PCI offset 2Eh) Maximum latency/minimum grant register (PCI offset 3Eh) Power management control and status register (PCI offset 48h): bits 15, 8, 1, 0 PHY control register (PCI offset ECh): bits 7, 4−0 Miscellaneous configuration register (PCI offset F0h): bits 15, 10−8, 5−0 Link enhancement control register (PCI offset F4h): bits 15−12, 10, 8−7, 2−1 OHCI bus options register (OHCI offset 20h): bits 15−12 OHCI GUID Hi register (OHCI offset 24h) OHCI GUID Lo register (OHCI offset 28h) OHCI Host controller control set/clear (OHCI offset 50h/54h): bit 23 OHCI link control set/clear (OHCI offset E0h/E4h): bit 6 PHY-Link loopback test register (local offset C14h): bits 6−4, 0 Link test control register (local offset C00h): bits 12−8 3.9 Low-Voltage CardBus Card Detection The card detection logic of PCI4510 device include the detection of Cardbus cards with VCC = 3.3 V and VPP/VCORE = 1.8 V. The reporting of the 1.8-V CardBus card (VCC = 3.3 V, VPP/VCORE = 1.8 V) is reported through the socket present state register as follows based on bit 10 (12V_SW_SEL) in the general control register (PCI offset 86h, see Section 4.29): • If the 12V_SW_SEL bit is 0 (TPS2221 is used), then the 1.8-V CardBus card causes the 3VCARD bit in the socket present state register to be set. 3−23 • If the 12V_SW_SEL bit is 1 (TPS2211A is used), then the 1.8-V CardBus card causes the XVCARD bit in the socket present state register to be set. 3.10 Power Switch Interface The power switch interface of the PCI4510 device is a 4-pin parallel interface. This 4-pin interface is implemented such that the PCI4510 device can connect to both the TPS2211A and TPS2221 power switches. Bit 10 (12V_SW_SEL) in the general control register (PCI offset 86h, see Section 4.29) selects the power switch that is implemented. The PCI4510 device defaults to use the control logic for the TPS2221 power switch. See Table 3−13 and Table 3−14 below for the power switch control logic. Table 3−13. TPS2221 Control Logic VD0/VCCD1 VD1/VCCD0 VD2/VPPD1 VD3/VPPD0 0 0 0 0 VCC 0V VPP/VCORE 0V 0 0 0 1 Hi-Z Hi-Z 0 0 1 0 Hi-Z Hi-Z 0 0 1 1 Hi-Z Hi-Z 0 1 0 0 3.3V 0V 0 1 0 1 3.3V 3.3V 0 1 1 0 3.3V 5V 0 1 1 1 3.3V 1.8V 1 0 0 0 5V 0V 1 0 0 1 5V 3.3V 1 0 1 0 5V 5V 1 0 1 1 5V 1.8V 1 1 0 0 Hi-Z Hi-Z 1 1 0 1 3.3V Hi-Z 1 1 1 0 5V Hi-Z 1 1 1 1 Hi-Z Hi-Z Table 3−14. TPS2211A Control Logic 3−24 VD0/VCCD1 VD1/VCCD0 VD2/VPPD1 VD3/VPPD0 0 0 0 0 VCC 0V VPP/VCORE 0V 0 0 0 1 0V 12V 0 0 1 0 0V 0V 0 0 1 1 0V Hi-Z 0 1 0 0 3.3V 0V 0 1 0 1 3.3V 12V 0 1 1 0 3.3V 3.3V 0 1 1 1 3.3V Hi-Z 1 0 0 0 5V 0V 1 0 0 1 5V 12V 1 0 1 0 5V 5V 1 0 1 1 5V Hi-Z 1 1 0 0 0V 0V 1 1 0 1 0V 12V 1 1 1 0 0V 0V 1 1 1 1 0V Hi-Z 3.11 IEEE 1394 Application Information 3.11.1 PHY Port Cable Connection PCI4510 400 kΩ CPS Cable Power Pair 1 µF TPBIAS 56 Ω 56 Ω TPA+ Cable Pair A TPA− Cable Port TPB+ Cable Pair B TPB− 56 Ω 220 pF (see Note A) 56 Ω 5 kΩ Outer Shield Termination NOTE A: IEEE Std 1394-1995 calls for a 250-pF capacitor, which is a nonstandard component value. A 220-pF capacitor is recommended. Figure 3−16. TP Cable Connections Outer Cable Shield 1 MΩ 0.01 µF 0.001 µF Chassis Ground Figure 3−17. Typical Compliant DC Isolated Outer Shield Termination 3−25 Outer Cable Shield Chassis Ground Figure 3−18. Non-DC Isolated Outer Shield Termination 3.11.2 Crystal Selection The PCI4510 device is designed to use an external 24.576-MHz crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. This oscillator in turn drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data at the S100 through S400 media data rates. A variation of less than ±100 ppm from nominal for the media data rates is required by IEEE Std 1394-1995. Adjacent PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHY devices must be able to compensate for this difference over the maximum packet length. Large clock variations may cause resynchronization overflows or underflows, resulting in corrupted packet data. The following are some typical specifications for crystals used with the PHYs from TI in order to achieve the required frequency accuracy and stability: • Crystal mode of operation: Fundamental • Frequency tolerance @ 25°C: Total frequency variation for the complete circuit is ±100 ppm. A crystal with ±30 ppm frequency tolerance is recommended for adequate margin. • Frequency stability (over temperature and age): A crystal with ±30 ppm frequency stability is recommended for adequate margin. NOTE: The total frequency variation must be kept below ±100 ppm from nominal with some allowance for error introduced by board and device variations. Trade-offs between frequency tolerance and stability may be made as long as the total frequency variation is less than ±100 ppm. For example, the frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible variation due to the crystal alone. Crystal aging also contributes to the frequency variation. • Load capacitance: For parallel resonant mode crystal circuits, the frequency of oscillation is dependent upon the load capacitance specified for the crystal. Total load capacitance (CL) is a function of not only the discrete load capacitors, but also board layout and circuit. It is recommended that load capacitors with a maximum of ±5% tolerance be used. For example, load capacitors (C9 and C10 in Figure 3−19) of 16 pF each were appropriate for the layout of the PCI4510 evaluation module (EVM), which uses a crystal specified for 12-pF loading. The load specified for the crystal includes the load capacitors (C9 and C10), the loading of the PHY pins (CPHY), and the loading of the board itself (CBD). The value of CPHY is typically about 1 pF, and CBD is typically 0.8 pF per centimeter of board etch; a typical board can have 3 pF to 6 pF or more. The load capacitors C9 and C10 combine as capacitors in series so that the total load capacitance is: C L + C9 C10 ) C PHY ) C BD C9 ) C10 3−26 C9 X1 X1 24.576 MHz IS CPHY + CBD X0 C10 Figure 3−19. Load Capacitance for the PCI4510 PHY The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency, minimizing noise introduced into the PHY phase-lock loop, and minimizing any emissions from the circuit. The crystal and two load capacitors must be considered as a unit during layout. The crystal and the load capacitors must be placed as close as possible to one another while minimizing the loop area created by the combination of the three components. Varying the size of the capacitors may help in this. Minimizing the loop area minimizes the effect of the resonant current (Is) that flows in this resonant circuit. This layout unit (crystal and load capacitors) must then be placed as close as possible to the PHY X1 and X0 terminals to minimize etch lengths, as shown in Figure 3−20. C9 C10 X1 For more details on crystal selection, see application report SLLA051 available from the TI website: http://www.ti.com/sc/1394. Figure 3−20. Recommended Crystal and Capacitor Layout 3.11.3 Bus Reset In the PCI4510 device, the initiate bus reset (IBR) bit may be set to 1 in order to initiate a bus reset and initialization sequence. The IBR bit is located in PHY register 1, along with the root-holdoff bit (RHB) and Gap_Count field, as required by IEEE Std 1394a-2000. Therefore, whenever the IBR bit is written, the RHB and Gap_Count are also written. The RHB and Gap_Count may also be updated by PHY-config packets. The PCI4510 device is IEEE 1394a-2000 compliant, and therefore both the reception and transmission of PHY-config packets cause the RHB and Gap_Count to be loaded, unlike older IEEE 1394-1995 compliant PHY devices which decode only received PHY-config packets. The gap-count is set to the maximum value of 63 after 2 consecutive bus resets without an intervening write to the Gap_Count, either by a write to PHY register 1 or by a PHY-config packet. This mechanism allows a PHY-config packet to be transmitted and then a bus reset initiated so as to verify that all nodes on the bus have updated their RHBs and Gap_Count values, without having the Gap_Count set back to 63 by the bus reset. The subsequent connection of a new node to the bus, which initiates a bus reset, then causes the Gap_Count of each node to be set to 63. Note, however, that if a subsequent bus reset is instead initiated by a write to register 1 to set the IBR bit, all other nodes on the bus have their Gap_Count values set to 63, while this node Gap_Count remains set to the value just loaded by the write to PHY register 1. 3−27 Therefore, in order to maintain consistent gap-counts throughout the bus, the following rules apply to the use of the IBR bit, RHB, and Gap_Count in PHY register 1: 3−28 • Following the transmission of a PHY-config packet, a bus reset must be initiated in order to verify that all nodes have correctly updated their RHBs and Gap_Count values and to ensure that a subsequent new connection to the bus causes the Gap_Count to be set to 63 on all nodes in the bus. If this bus reset is initiated by setting the IBR bit to 1, then the RHB and Gap_Count field must also be loaded with the correct values consistent with the just-transmitted PHY-config packet. In the PCI4510 device, the RHB and Gap_Count are updated to their correct values upon the transmission of the PHY-config packet, so these values may first be read from register 1 and then rewritten. • Other than to initiate the bus reset, which must follow the transmission of a PHY-config packet, whenever the IBR bit is set to 1 in order to initiate a bus reset, the Gap_Count value must also be set to 63 so as to be consistent with other nodes on the bus, and the RHB must be maintained with its current value. • The PHY register 1 must not be written to except to set the IBR bit. The RHB and Gap_Count must not be written without also setting the IBR bit to 1. 4 PC Card Controller Programming Model This chapter describes the PCI4510 PCI configuration registers that make up the 256-byte PCI configuration header for each PCI4510 function. A bit description table, typically included when the register contains bits of more than one type or purpose, indicates bit field names, a detailed field description, and field access tags which appear in the type column. Table 4−1 describes the field access tags. Table 4−1. Bit Field Access Tag Descriptions ACCESS TAG NAME R Read Field can be read by software. MEANING W Write Field can be written by software to any value. S Set C Clear U Update Field can be set by a write of 1. Writes of 0 have no effect. Field can be cleared by a write of 1. Writes of 0 have no effect. Field can be autonomously updated by the PCI4510 device. 4.1 PCI Configuration Registers (Function 0) The PCI4510 device is a multifunction PCI device, and the PC Card controller is integrated as PCI function 0. The configuration header, compliant with the PCI Local Bus Specification as a CardBus bridge header, is PC99/PC2001 compliant as well. Table 4−2 illustrates the PCI configuration header, which includes both the predefined portion of the configuration space and the user-definable registers. Table 4−2. Function 0 PCI Configuration Register Map REGISTER NAME OFFSET Device ID Vendor ID Status Command Class code BIST Header type Latency timer 00h 04h Revision ID 08h Cache line size 0Ch CardBus socket registers/ExCA base address register Secondary status CardBus latency timer Subordinate bus number 10h Reserved Capability pointer CardBus bus number PCI bus number 14h 18h CardBus memory base register 0 1Ch CardBus memory limit register 0 20h CardBus memory base register 1 24h CardBus memory limit register 1 28h CardBus I/O base register 0 2Ch CardBus I/O limit register 0 30h CardBus I/O base register 1 34h CardBus I/O limit register 1 Bridge control 38h Interrupt pin Subsystem ID Interrupt line Subsystem vendor ID 3Ch 40h PC Card 16-bit I/F legacy-mode base-address 44h Reserved 48h−7Ch System control 80h 4−1 Table 4−2. Function 0 PCI Configuration Register Map (Continued) REGISTER NAME OFFSET General control General-purpose output Reserved General-purpose event enable General-purpose input 84h General-purpose event status 88h Multifunction routing status† Diagnostic Device control 8Ch Card control Retry status 90h Reserved Power management capabilities 94h−9Ch Next item pointer Power management control/status register bridge support extensions Data (Reserved) Capability ID A0h A4h Power management control/status Reserved Serial bus control/status Serial bus slave address A8h−ACh Serial bus data Serial bus index B0h Reserved B4h−FCh 4.2 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG that identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch. Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 Vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 Register: Offset: Type: Default: Vendor ID 00h (Function 0) Read-only 104Ch 4.3 Device ID Register The device ID register contains a value assigned to the PCI4510 device by Texas Instruments. The device identification for the PCI4510 device is AC44. Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 Device ID Type R R R R R R R R R R R R R R R R Default 1 0 1 0 1 1 0 0 0 1 0 0 0 1 0 0 Register: Offset: Type: Default: 4−2 Device ID 02h (Function 0) Read-only AC44h 4.4 Command Register The PCI command register provides control over the PCI4510 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification (see Table 4−3). None of the bit functions in this register are shared among the PCI4510 PCI functions. Three command registers exist in the PCI4510 device, one for each function. Software manipulates the PCI4510 functions as separate entities when enabling functionality through the command register. The SERR_EN and PERR_EN enable bits in this register are internally wired OR between the three functions, and these control bits appear to software to be separate for each function. Bit 15 14 13 12 11 10 9 8 Type R R R R R R R RW Default 0 0 0 0 0 0 0 0 Name 7 6 5 4 3 2 1 0 R RW RW R R RW RW RW 0 0 0 0 0 0 0 0 Command Register: Offset: Type: Default: Command 04h Read-only, Read/Write 0000h Table 4−3. Command Register Description BIT SIGNAL TYPE 15−10 RSVD R Reserved. Bits 15−10 return 0s when read. 9 FBB_EN R Fast back-to-back enable. The PCI4510 device does not generate fast back-to-back transactions; therefore, this bit is read-only. This bit returns a 0 when read. FUNCTION 8 SERR_EN RW System error (SERR) enable. This bit controls the enable for the SERR driver on the PCI interface. SERR can be asserted after detecting an address parity error on the PCI bus. Both this bit and bit 6 must be set to 1 for the PCI4510 device to report address parity errors. 0 = Disables the SERR output driver (default) 1 = Enables the SERR output driver 7 STEP_EN R Address/data stepping control. The PCI4510 device does not support address/data stepping, and this bit is hardwired to 0. Writes to this bit have no effect. 6 PERR_EN RW Parity error response enable. This bit controls the PCI4510 device response to parity errors through the PERR signal. Data parity errors are indicated by asserting PERR, while address parity errors are indicated by asserting SERR. 0 = PCI4510 device ignores detected parity errors (default). 1 = PCI4510 device responds to detected parity errors. 5 VGA_EN RW VGA palette snoop. When set to 1, palette snooping is enabled (that is, the PCI4510 device does not respond to palette register writes and snoops the data). When the bit is 0, the PCI4510 device treats all palette accesses like all other accesses. 4 MWI_EN R Memory write-and-invalidate enable. This bit controls whether a PCI initiator device can generate memory write-and-invalidate commands. The PCI4510 controller does not support memory write-and-invalidate commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. This bit returns 0 when read. Writes to this bit have no effect. 3 SPECIAL R Special cycles. This bit controls whether or not a PCI device ignores PCI special cycles. The PCI4510 device does not respond to special cycle operations; therefore, this bit is hardwired to 0. This bit returns 0 when read. Writes to this bit have no effect. RW Bus master control. This bit controls whether or not the PCI4510 device can act as a PCI bus initiator (master). The PCI4510 device can take control of the PCI bus only when this bit is set. 0 = Disables the PCI4510 ability to generate PCI bus accesses (default) 1 = Enables the PCI4510 ability to generate PCI bus accesses 2 MAST_EN 1 MEM_EN RW Memory space enable. This bit controls whether or not the PCI4510 device can claim cycles in PCI memory space. 0 = Disables the PCI4510 response to memory space accesses (default) 1 = Enables the PCI4510 response to memory space accesses 0 IO_EN RW I/O space control. This bit controls whether or not the PCI4510 device can claim cycles in PCI I/O space. 0 = Disables the PCI4510 device from responding to I/O space accesses (default) 1 = Enables the PCI4510 device to respond to I/O space accesses 4−3 4.5 Status Register The status register provides device information to the host system. Bits in this register can be read normally. A bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit functions adhere to the definitions in the PCI Bus Specification, as seen in the bit descriptions. PCI bus status is shown through each function. See Table 4−4 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 Name Type Default 7 6 5 4 3 2 1 0 Status RW RW RW RW RW R R RW R R R R R R R R 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Register: Offset: Type: Default: Status 06h (Function 0) Read-only, Read/Write 0210h Table 4−4. Status Register Description BIT SIGNAL TYPE FUNCTION 15 PAR_ERR RW Detected parity error. This bit is set when a parity error is detected, either an address or data parity error. Write a 1 to clear this bit. 14 SYS_ERR RW Signaled system error. This bit is set when SERR is enabled and the PCI4510 device signaled a system error to the host. Write a 1 to clear this bit. 13 MABORT RW Received master abort. This bit is set when a cycle initiated by the PCI4510 device on the PCI bus has been terminated by a master abort. Write a 1 to clear this bit. 12 TABT_REC RW Received target abort. This bit is set when a cycle initiated by the PCI4510 device on the PCI bus was terminated by a target abort. Write a 1 to clear this bit. 11 TABT_SIG RW Signaled target abort. This bit is set by the PCI4510 device when it terminates a transaction on the PCI bus with a target abort. Write a 1 to clear this bit. 10−9 PCI_SPEED R DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired to 01b indicating that the PCI4510 device asserts this signal at a medium speed on nonconfiguration cycle accesses. Data parity error detected. Write a 1 to clear this bit. 4−4 0 = The conditions for setting this bit have not been met. 1 = A data parity error occurred and the following conditions were met: a. PERR was asserted by any PCI device including the PCI4510 device. b. The PCI4510 device was the bus master during the data parity error. c. The parity error response bit is set in the command register (PCI offset 04h, see Section 4.4). 8 DATAPAR RW 7 FBB_CAP R Fast back-to-back capable. The PCI4510 device cannot accept fast back-to-back transactions; thus, this bit is hardwired to 0. 6 UDF R UDF supported. The PCI4510 device does not support user-definable features; therefore, this bit is hardwired to 0. 5 66MHZ R 66-MHz capable. The PCI4510 device operates at a maximum PCLK frequency of 33 MHz; therefore, this bit is hardwired to 0. 4 CAPLIST R Capabilities list. This bit returns 1 when read. This bit indicates that capabilities in addition to standard PCI capabilities are implemented. The linked list of PCI power-management capabilities is implemented in this function. 3−0 RSVD R These bits return 0s when read. 4.6 Class Code and Revision ID Registers The class code and revision ID register recognizes the PCI4510 device as a bridge device (06h) and CardBus bridge device (07h) with a (00h) programming interface. Furthermore, the TI chip revision (02h) is indicated in the least significant byte. Bit 31 30 29 28 27 26 25 24 Name 23 22 21 20 19 18 17 16 Class code Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Class code Revision ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Register: Offset: Type: Default: Class code and revision ID 08h (Function 0) Read-only 0607 0002h 4.7 Cache Line Size Register The cache line size register is programmed by host software to indicate the system cache line size. Bit 7 6 5 4 RW RW RW RW 0 0 0 0 Name Type Default 3 2 1 0 RW RW RW RW 0 0 0 0 Cache line size Register: Offset: Type: Default: Cache line size 0Ch (Function 0) Read/Write 00h 4.8 Latency Timer Register The latency timer register specifies the latency timer for the PCI4510 device, in units of PCI clock cycles. When the PCI4510 device is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires before the PCI4510 transaction has terminated, then the PCI4510 device terminates the transaction when its GNT is deasserted. Bit 7 6 5 4 Name Type Default 3 2 1 0 Latency timer RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Latency timer 0Dh Read/Write 00h 4−5 4.9 Header Type Register The header type register returns 82h when read, indicating that the PCI4510 configuration spaces adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI registers 00h−7Fh, and 80h−FFh is user-definable extension registers. Bit 7 6 5 4 3 2 1 0 Type R R R R Default 1 0 0 R R R R 0 0 0 1 0 Name Header type Register: Offset: Type: Default: Header type 0Eh (Function 0) Read-only 82h 4.10 BIST Register Because the PCI4510 device does not support a built-in self-test (BIST), this register returns the value of 00h when read. Bit 7 6 5 4 Name 3 2 1 0 BIST Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: BIST 0Fh (Function 0) Read-only 00h 4.11 CardBus Socket Registers/ExCA Base Address Register This register is programmed with a base address referencing the CardBus socket registers and the memory-mapped ExCA register set. Bits 31−12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI memory address space on a 4-Kbyte boundary. Bits 11−0 are read-only, returning 0s when read. When software writes all 1s to this register, the value read back is FFFF F000h, indicating that at least 4K bytes of memory address space are required. The CardBus registers start at offset 000h, and the memory-mapped ExCA registers begin at offset 800h. The system maps each socket control register separately. Bit 31 30 29 28 27 Name Type 26 25 24 23 22 21 20 19 18 17 16 CardBus socket registers/ExCA base address RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default CardBus socket registers/ExCA base address RW RW RW RW R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: 4−6 CardBus socket registers/ExCA base address 10h Read-only, Read/Write 0000 0000h 4.12 Capability Pointer Register The capability pointer register provides a pointer into the PCI configuration header where the PCI power management register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. Each socket has its own capability pointer register. This register is read-only and returns A0h when read. Bit 7 6 5 Name 4 3 2 1 0 Capability pointer Type R R R R R R R R Default 1 0 1 0 0 0 0 0 Register: Offset: Type: Default: Capability pointer 14h Read-only A0h 4−7 4.13 Secondary Status Register The secondary status register is compatible with the PCI-PCI bridge secondary status register. It indicates CardBus-related device information to the host system. This register is very similar to the PCI status register (PCI offset 06h, see Section 4.5), and status bits are cleared by a writing a 1. This register is not shared by the two socket functions, but is accessed on a per-socket basis. See Table 4−5 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 Name Type Default 8 7 6 5 4 3 2 1 0 Secondary status RC RC RC RC RC R R RC R R R R R R R R 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Secondary status 16h Read-only, Read/Clear 0200h Table 4−5. Secondary Status Register Description BIT SIGNAL TYPE FUNCTION 15 CBPARITY RC Detected parity error. This bit is set when a CardBus parity error is detected, either an address or data parity error. Write a 1 to clear this bit. 14 CBSERR RC Signaled system error. This bit is set when CSERR is signaled by a CardBus card. The PCI4510 device does not assert the CSERR signal. Write a 1 to clear this bit. 13 CBMABORT RC Received master abort. This bit is set when a cycle initiated by the PCI4510 device on the CardBus bus is terminated by a master abort. Write a 1 to clear this bit. 12 REC_CBTA RC Received target abort. This bit is set when a cycle initiated by the PCI4510 device on the CardBus bus is terminated by a target abort. Write a 1 to clear this bit. 11 SIG_CBTA RC Signaled target abort. This bit is set by the PCI4510 device when it terminates a transaction on the CardBus bus with a target abort. Write a 1 to clear this bit. 10−9 CB_SPEED R CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired to 01b indicating that the PCI4510 device asserts this signal at a medium speed. CardBus data parity error detected. Write a 1 to clear this bit. 4−8 0 = The conditions for setting this bit have not been met. 1 = A data parity error occurred and the following conditions were met: a. CPERR was asserted on the CardBus interface. b. The PCI4510 device was the bus master during the data parity error. c. The parity error response enable bit (bit 0) is set in the bridge control register (PCI offset 3Eh, see Section 4.24). 8 CB_DPAR RC 7 CBFBB_CAP R Fast back-to-back capable. The PCI4510 device cannot accept fast back-to-back transactions; therefore, this bit is hardwired to 0. 6 CB_UDF R User-definable feature support. The PCI4510 device does not support user-definable features; therefore, this bit is hardwired to 0. 5 CB66MHZ R 66-MHz capable. The PCI4510 CardBus interface operates at a maximum CCLK frequency of 33 MHz; therefore, this bit is hardwired to 0. 4−0 RSVD R These bits return 0s when read. 4.14 PCI Bus Number Register The PCI bus number register is programmed by the host system to indicate the bus number of the PCI bus to which the PCI4510 device is connected. The PCI4510 device uses this register in conjunction with the CardBus bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses. Bit 7 6 5 Name Type Default 4 3 2 1 0 PCI bus number RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: PCI bus number 18h (Function 0) Read/Write 00h 4.15 CardBus Bus Number Register The CardBus bus number register is programmed by the host system to indicate the bus number of the CardBus bus to which the PCI4510 device is connected. The PCI4510 device uses this register in conjunction with the PCI bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for each PCI4510 controller function. Bit 7 6 5 RW RW RW RW 0 0 0 0 Name Type Default 4 3 2 1 0 RW RW RW RW 0 0 0 0 CardBus bus number Register: Offset: Type: Default: CardBus bus number 19h Read/Write 00h 4.16 Subordinate Bus Number Register The subordinate bus number register is programmed by the host system to indicate the highest numbered bus below the CardBus bus. The PCI4510 device uses this register in conjunction with the PCI bus number and CardBus bus number registers to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for each CardBus controller function. Bit 7 6 5 Name Type Default 4 3 2 1 0 Subordinate bus number RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Subordinate bus number 1Ah Read/Write 00h 4−9 4.17 CardBus Latency Timer Register The CardBus latency timer register is programmed by the host system to specify the latency timer for the PCI4510 CardBus interface, in units of CCLK cycles. When the PCI4510 device is a CardBus initiator and asserts CFRAME, the CardBus latency timer begins counting. If the latency timer expires before the PCI4510 transaction has terminated, then the PCI4510 device terminates the transaction at the end of the next data phase. A recommended minimum value for this register of 20h allows most transactions to be completed. Bit 7 6 5 4 Name 3 2 1 0 CardBus latency timer Type RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Default Register: Offset: Type: Default: CardBus latency timer 1Bh (Function 0) Read/Write 00h 4.18 CardBus Memory Base Registers 0, 1 These registers indicate the lower address of a PCI memory address range. They are used by the PCI4510 device to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. Bits 31−12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11−0 are read-only and always return 0s. Writes to these bits have no effect. Bits 8 and 9 of the bridge control register (PCI offset 3Eh, see Section 4.24) specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero in order for the PCI4510 device to claim any memory transactions through CardBus memory windows (i.e., these windows by default are not enabled to pass the first 4 Kbytes of memory to CardBus). Bit 31 30 29 28 27 26 25 RW RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 RW RW RW RW R R R R R 0 0 0 0 0 0 0 0 0 Name Type Default 22 21 20 19 18 17 16 RW RW RW RW RW RW RW 0 0 0 0 0 0 0 6 5 4 3 2 1 0 R R R R R R R 0 0 0 0 0 0 0 Memory base registers 0, 1 Register: Offset: Type: Default: 4−10 23 Memory base registers 0, 1 Name Type 24 Memory base registers 0, 1 1Ch, 24h Read-only, Read/Write 0000 0000h 4.19 CardBus Memory Limit Registers 0, 1 These registers indicate the upper address of a PCI memory address range. They are used by the PCI4510 device to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. Bits 31−12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11−0 are read-only and always return 0s. Writes to these bits have no effect. Bits 8 and 9 of the bridge control register (PCI offset 3Eh, see Section 4.24) specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero in order for the PCI4510 device to claim any memory transactions through CardBus memory windows (that is, these windows by default are not enabled to pass the first 4 Kbytes of memory to CardBus). Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Memory limit registers 0, 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Memory limit registers 0, 1 RW RW RW RW R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Memory limit registers 0, 1 20h, 28h Read-only, Read/Write 0000 0000h 4.20 CardBus I/O Base Registers 0, 1 The I/O base registers indicate the lower address of a PCI I/O address range. These registers are used by the PCI4510 device to determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64-Kbyte page. The upper 16 bits (31−16) are a page register which locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 31−2 are read/write. Bits 1 and 0 are read-only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary. Either the I/O base register or the I/O limit register must be nonzero to enable any I/O transactions. Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 I/O base registers 0, 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default I/O base registers 0, 1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: I/O base registers 0, 1 2Ch, 34h Read-only, Read/Write 0000 0000h 4−11 4.21 CardBus I/O Limit Registers 0, 1 These registers indicate the upper address of a PCI I/O address range. They are used by the PCI4510 device to determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. The lower 16 bits of this register locate the top of the I/O window within a 64-Kbyte page, and the upper 16 bits are a page register which locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 15−2 are read/write and allow the I/O limit address to be located anywhere in the 64-Kbyte page (indicated by bits 31−16 of the appropriate I/O base register) on doubleword boundaries. Bits 31−16 are read-only and always return 0s when read. The page is set in the I/O base register. Bits 1−0 are read-only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary. Writes to read-only bits have no effect. The PCI4510 device assumes that the lower 2 bits of the limit address are 1s. These I/O windows are enabled when either the I/O base register or the I/O limit register is nonzero. By default, the I/O windows are not enabled to pass the first doubleword of I/O to CardBus. Either the I/O base register or the I/O limit register must be nonzero to enable any I/O transactions. Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Name Default 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 RW RW RW RW RW RW R R 0 0 0 0 0 0 0 0 I/O limit registers 0, 1 Name Type 24 I/O limit registers 0, 1 Register: Offset: Type: Default: I/O limit registers 0, 1 30h, 38h Read-only, Read/Write 0000 0000h 4.22 Interrupt Line Register The interrupt line register communicates interrupt line routing information to the host system. This register is not used by the PCI4510 device, because there are many programmable interrupt signaling options. This register is considered reserved; however, host software can read and write to this register. Each PCI4510 function has an interrupt line register. Bit 7 6 5 4 Name Type Default 2 1 0 RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 Register: Offset: Type: Default: 4−12 3 Interrupt line Interrupt line 3Ch Read/Write FFh 4.23 Interrupt Pin Register The value read from this register is function dependent, and depends on interrupt tie bit 29 (INTRTIE) in the system control register (PCI offset 80h, see Section 4.28). INTRTIE is compatible with other TI CardBus controllers and ties INTA to INTB internally. The internal interrupt connections set by INTRTIE are communicated to host software through this standard register interface. Refer to Table 4−6 for a complete description of the register contents. Bit 7 6 5 4 Name 3 2 1 0 Interrupt pin Type R R R R R R R R Default 0 0 0 0 0 0 0 1 Register: Offset: Type: Default: Interrupt pin 3Dh Read-only 01h Table 4−6. PCI Interrupt Pin Register—Read-Only INTPIN Per Function INTRTIE BIT INTPIN FUNCTION 0 (CARDBUS) INTPIN FUNCTION 1 (1394 OHCI) 0 01h (INTA) 02h (INTB) 1 01h (INTA) 01h (INTA) † When configuring the PCI4510 functions to share PCI interrupts, multifunction terminal MFUNC3 must be configured as IRQSER prior to setting the INTRTIE bit. 4−13 4.24 Bridge Control Register The bridge control register provides control over various PCI4510 bridging functions. See Table 4−7 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 Type R R R R R RW RW RW Default 0 0 0 0 0 0 1 1 Name 8 7 6 5 4 3 2 1 0 RW RW RW R RW RW RW RW 0 1 0 0 0 0 0 0 Bridge control Register: Offset: Type: Default: Bridge control 3Eh (Function 0) Read-only, Read/Write 0340h Table 4−7. Bridge Control Register Description BIT SIGNAL TYPE 15−11 RSVD R 10 POSTEN RW Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables the posting of write data on burst cycles. Operating with write posting disabled impairs performance on burst cycles. Note that burst write data can be posted, but various write transactions may not. RW Memory window 1 type. This bit specifies whether or not memory window 1 is prefetchable. This bit is socket dependent. This bit is encoded as: 0 = Memory window 1 is nonprefetchable. 1 = Memory window 1 is prefetchable (default). RW Memory window 0 type. This bit specifies whether or not memory window 0 is prefetchable. This bit is socket dependent. This bit is encoded as: 0 = Memory window 0 is nonprefetchable. 1 = Memory window 0 is prefetchable (default). RW PCI interrupt − IREQ routing enable. This bit selects whether PC Card functional interrupts are routed to PCI interrupts or to the IRQ specified in the ExCA registers. 0 = Functional interrupts are routed to PCI interrupts (default). 1 = Functional interrupts are routed by ExCA registers. 9 8 7 6 PREFETCH1 PREFETCH0 INTR CRST RW FUNCTION These bits return 0s when read. CardBus reset. When this bit is set, the CRST signal is asserted on the CardBus interface. The CRST signal can also be asserted by passing a PRST assertion to CardBus. 0 = CRST is deasserted. 1 = CRST is asserted (default). This bit is not cleared by the assertion of PRST. It is only cleared by the assertion of GRST. 4−14 Master abort mode. This bit controls how the PCI4510 device responds to a master abort when the PCI4510 device is an initiator on the CardBus interface. This bit is common between each socket. 0 = Master aborts not reported (default). 1 = Signal target abort on PCI and signal SERR, if enabled. 5 MABTMODE RW 4 RSVD R 3 VGAEN RW VGA enable. This bit affects how the PCI4510 device responds to VGA addresses. When this bit is set, accesses to VGA addresses are forwarded. 2 ISAEN RW ISA mode enable. This bit affects how the PCI4510 device passes I/O cycles within the 64-Kbyte ISA range. This bit is not common between sockets. When this bit is set, the PCI4510 device does not forward the last 768 bytes of each 1K I/O range to CardBus. 1 CSERREN RW CSERR enable. This bit controls the response of the PCI4510 device to CSERR signals on the CardBus bus. This bit is separate for each socket. 0 = CSERR is not forwarded to PCI SERR (default) 1 = CSERR is forwarded to PCI SERR. 0 CPERREN RW CardBus parity error response enable. This bit controls the response of the PCI4510 device to CardBus parity errors. This bit is separate for each socket. 0 = CardBus parity errors are ignored (default). 1 = CardBus parity errors are reported using CPERR. This bit returns 0 when read. 4.25 Subsystem Vendor ID Register The subsystem vendor ID register, used for system and option card identification purposes, may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register (PCI offset 80h, see Section 4.28). When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read-only. The default mode is read-only. Bit 15 14 13 12 11 10 9 R R R R R R R R 0 0 0 0 0 0 0 0 Name Type Default 8 7 6 5 4 3 2 1 0 R R R R R R R R 0 0 0 0 0 0 0 0 Subsystem vendor ID Register: Offset: Type: Default: Subsystem vendor ID 40h (Function 0) Read-only, (Read/Write when bit 5 in the system control register is 0) 0000h 4.26 Subsystem ID Register The subsystem ID register, used for system and option card identification purposes, may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register (PCI offset 80h, see Section 4.28). When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read-only. The default mode is read-only. If a ROM is present, then the subsystem ID and subsystem vendor ID will be loaded from ROM after a reset. Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 Subsystem ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Subsystem ID 42h (Function 0) Read-only, (Read/Write when bit 5 in the system control register is 0) 0000h 4.27 PC Card 16-Bit I/F Legacy-Mode Base-Address Register The PCI4510 device supports the index/data scheme of accessing the ExCA registers, which is mapped by this register. An address written to this register is the address for the index register and the address+1 is the data address. Using this access method, applications requiring index/data ExCA access can be supported. The base address can be mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only, returning 1 when read. See the ExCA register set description in Section 5 for register offsets. Bit 31 30 29 28 27 Name Type 26 25 24 23 22 21 20 19 18 17 16 PC Card 16-bit I/F legacy-mode base-address RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Name Type Default PC Card 16-bit I/F legacy-mode base-address Register: Offset: Type: Default: PC Card 16-bit I/F legacy-mode base-address 44h (Function 0) Read-only, Read/Write 0000 0001h 4−15 4.28 System Control Register System-level initializations are performed through programming this doubleword register. Some of the bits are global in nature and must be accessed only through function 0. See Table 4−8 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 RW RW RW R R RW RW RW Default 0 0 0 0 1 0 0 0 Bit 15 14 13 12 11 10 9 8 RW RW R R R R R R 1 0 0 1 0 0 0 0 Name Type Default 23 22 21 20 19 18 17 16 R RW RW RW RW RW RW RW 0 1 0 0 0 1 0 0 7 6 5 4 3 2 1 0 R RW RW RW RW R RW RW 0 1 1 0 0 0 0 0 System control Name Type 24 System control Register: Offset: Type: Default: System control 80h (Function 0) Read-only, Read/Write 0844 9060h Table 4−8. System Control Register Description BIT TYPE FUNCTION 31−30 SER_STEP RW Serial input stepping. In the serial PCI interrupt mode, these bits are used to configure the serial stream PCI interrupt frames, and can be used to accomplish an even distribution of interrupts signaled on the four PCI interrupt slots. 00 = INTA/INTB signal in INTA/INTB slots (default) 01 = INTA/INTB signal in INTB/INTC slots 10 = INTA/INTB signal in INTC/INTD slots 11 = INTA/INTB signal in INTD/INTA slots 29 INTRTIE RW This bit ties INTA to INTB internally (to INTA), and reports this through the interrupt pin register (PCI offset 3Dh, see Section 4.23). This bit has no effect on INTC or INTD. 28 RSVD R Reserved. Bit 28 returns 0 when read. 27 OSEN R Internal oscillator enable. The PCI4510 device hardwires this bit to 1 such that the internal oscillator is always enabled. 26 SMIROUTE RW SMI interrupt routing. This bit selects whether IRQ2 or CSC is signaled when a write occurs to power a PC Card socket. 0 = PC Card power change interrupts are routed to IRQ2 (default). 1 = A CSC interrupt is generated on PC Card power changes. RW SMI interrupt status. This socket-dependent bit is set when a write occurs to set the socket power, and the SMIENB bit is set. Writing a 1 to this bit clears the status. 0 = SMI interrupt is signaled. 1 = SMI interrupt is not signaled. SMI interrupt mode enable. When this bit is set, the SMI interrupt signaling generates an interrupt when a write to the socket power control occurs. This bit is shared and defaults to 0 (disabled). 0 = SMI interrupt mode is disabled (default). 1 = SMI interrupt mode is enabled. 25 4−16 SIGNAL SMISTATUS 24 SMIENB RW 23 RSVD R Reserved 22 CBRSVD RW CardBus reserved terminals signaling. When this bit is set and a CardBus card has been inserted, the RSVD CardBus terminals are driven low. When this bit is low, these signals are placed in a high-impedance state. 0 = Place the CardBus RSVD terminals in a high-impedance state. 1 = Drive the CardBus RSVD terminals low (default). 21 VCCPROT RW VCC protection enable. This bit is socket dependent. 0 = VCC protection is enabled for 16-bit cards (default). 1 = VCC protection is disabled for 16-bit cards. Table 4−8. System Control Register Description (Continued) BIT SIGNAL TYPE FUNCTION 20 REDUCEZV RW Reduced zoomed video enable. When this bit is enabled, AD25−AD22 of the card interface for 16-bit PC Cards are placed in the high impedance state. This bit is encoded as: 0 = Reduced zoomed video is disabled (default). 1 = Reduced zoomed video is enabled. 19−16 RSVD RW Reserved. Do not change the default value. RW Memory read burst enable downstream. When this bit is set, the PCI4510 device allows memory read transactions to burst downstream. 0 = MRBURSTDN downstream is disabled. 1 = MRBURSTDN downstream is enabled (default). 15 MRBURSTDN 14 MRBURSTUP RW Memory read burst enable upstream. When this bit is set, the PCI4510 device allows memory read transactions to burst upstream. 0 = MRBURSTUP upstream is disabled (default). 1 = MRBURSTUP upstream is enabled. 13 SOCACTIVE R Socket activity status. When set, this bit indicates access has been performed to or from a PC Card. Reading this bit causes it to be cleared. This bit is socket dependent. 0 = No socket activity (default) 1 = Socket activity 12 RSVD R Reserved. This bit returns 1 when read. R Power-stream-in-progress status bit. When set, this bit indicates that a power stream to the power switch is in progress and a powering change has been requested. When this bit is cleared, it indicates that the power stream is complete. 0 = Power stream is complete, delay has expired (default). 1 = Power stream is in progress. R Power-up delay-in-progress status bit. When set, this bit indicates that a power-up stream has been sent to the power switch, and proper power may not yet be stable. This bit is cleared when the power-up delay has expired. 0 = Power-up delay has expired (default). 1 = Power-up stream sent to switch. Power might not be stable. R Power-down delay-in-progress status bit. When set, this bit indicates that a power-down stream has been sent to the power switch, and proper power may not yet be stable. This bit is cleared when the power-down delay has expired. 0 = Power-down delay has expired (default). 1 = Power-down stream sent to switch. Power might not be stable. 11 10 9 PWRSTREAM DELAYUP DELAYDOWN 8 INTERROGATE R Interrogation in progress. When set, this bit indicates an interrogation is in progress, and clears when the interrogation completes. This bit is socket-dependent. 0 = Interrogation not in progress (default) 1 = Interrogation in progress 7 RSVD R Reserved. This bit returns 0 when read. 6 PWRSAVINGS RW Power savings mode enable. When this bit is set, the PCI4510 device consumes less power with no performance loss. This bit is shared between the two PCI4510 CardBus functions. 0 = Power savings mode disabled 1 = Power savings mode enabled (default) 5 SUBSYSRW RW Subsystem ID and subsystem vendor ID, ExCA ID and revision register read/write enable. This bit also controls read/write for the function 3 subsystem ID register. 0 = Registers are read/write. 1 = Registers are read-only (default). 4 CB_DPAR RW CardBus data parity SERR signaling enable. 0 = CardBus data parity not signaled on PCI SERR signal (default) 1 = CardBus data parity signaled on PCI SERR signal 3 RSVD RW Reserved. Do not change the default value. 2 RSVD R Reserved. This bit returns 0 when read. 4−17 Table 4−8. System Control Register Description (Continued) BIT SIGNAL 1 KEEPCLK TYPE FUNCTION RW Keep clock. When this bit is set, the PCI4510 device follows the CLKRUN protocol to maintain the system PCLK and the CCLK (CardBus clock). This bit is global to the PCI4510 functions. 0 = Allow system PCLK and CCLK to stop (default) 1 = Never allow system PCLK or CCLK clock to stop Note that the functionality of this bit has changed relative to that of the PCI12XX family of TI CardBus controllers. In these CardBus controllers, setting this bit only maintains the PCI clock, not the CCLK. In the PCI4510 device, setting this bit maintains both the PCI clock and the CCLK. 0 RIMUX PME/RI_OUT select bit. When this bit is 1, the PME signal is routed to the PME/RI_OUT terminal (PDV 21, GHK J03, RGVF T03). When this bit is 0 and bit 7 (RIENB) of the card control register is 1, the RI_OUT signal is routed to the PME/RI_OUT terminal. If this bit is 0 and bit 7 (RIENB) of the card control register is 0, then the output (21, J03, or T03) is placed in a high-impedance state. This terminal is encoded as: 0 = RI_OUT signal is routed to the PME/RI_OUT terminal if bit 7 of the card control register is 1. (default) 1 = PME signal is routed to the PME/RI_OUT terminal of the PCI4510 controller. RW NOTE: If this bit (bit 0) is 0 and bit 7 of the card control register (PCI offset 91h, see Section 4.36) is 0, then the output on the PME/RI_OUT terminal is placed in a high-impedance state. 4.29 General Control Register The general control register provides top level PCI arbitration control. It also provides the ability to disable the 1394 OHCI function and provides control over miscellaneous new functionality. See Table 4−9 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 Type R R R R R RW R R Default 0 0 0 0 0 0 0 0 Name 8 7 6 5 4 3 2 1 0 R R R R RW R RW RW 0 0 0 0 0 0 0 0 General control Register: Offset: Type: Default: General control 86h Read/Write, Read-only 0000h Table 4−9. General Control Register Description BIT SIGNAL TYPE 15−11 RSVD R 10 12V_SW_SEL RW 4−18 9−4 RSVD R 3 DISABLE_OHCI RW 2 RSVD R 1−0 ARB_CTRL RW FUNCTION Reserved. These bits return 0s when read. Power switch select. This bit selects which power switch is implemented in the system. 0 = The TPS2221 power switch is used (default). 1 = The TPS2211A power switch is used. Reserved. These bits return 0s when read. When set, the open HCI 1394 controller function is completely nonaccessible and nonfunctional. Reserved. This bit returns 0 when read. Controls top level PCI arbitration 00 = 1394 open HCI priority 01 = CardBus priority 10 = Fair round robin 11 = Fair round robin 4.30 General-Purpose Event Status Register The general-purpose event status register contains status bits that are set when general events occur, and can be programmed to generate general-purpose event signaling through GPE. See Table 4−10 for a complete description of the register contents. Bit 7 6 5 Name Type Default 4 3 2 1 0 General-purpose event status RCU RCU R RCU RCU RCU RCU RCU 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: General-purpose event status 88h Read/Clear/Update, Read-only 00h Table 4−10. General-Purpose Event Status Register Description BIT SIGNAL TYPE FUNCTION 7 PWR_STS RCU Power change status. This bit is set when software changes the VCC or VPP power state of either socket. 6 VPP12_STS RCU 12-V VPP request status. This bit is set when software has changed the requested VPP level to or from 12 V for either socket. 5 RSVD R 4 GP4_STS RCU GPI4 status. This bit is set on a change in status of the MFUNC5 terminal input level if configured as a general-purpose input, GPI4. 3 GP3_STS RCU GPI3 status. This bit is set on a change in status of the MFUNC4 terminal input level if configured as a general-purpose input, GPI3. 2 GP2_STS RCU GPI2 status. This bit is set on a change in status of the MFUNC2 terminal input level if configured as a general-purpose input, GPI2. 1 GP1_STS RCU GPI1 status. This bit is set on a change in status of the MFUNC1 terminal input level if configured as a general-purpose input, GPI1. 0 GP0_STS RCU GPI0 status. This bit is set on a change in status of the MFUNC0 terminal input level if configured as a general-purpose input, GPI0. Reserved. This bit returns 0 when read. A write has no effect. 4−19 4.31 General-Purpose Event Enable Register The general-purpose event enable register contains bits that are set to enable GPE signals. See Table 4−11 for a complete description of the register contents. Bit 7 6 5 Name Type Default 4 3 2 1 0 General-purpose event enable RW RW R RW RW RW RW RW 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: General-purpose event enable 89h Read-only, Read/Write 00h Table 4−11. General-Purpose Event Enable Register Description BIT SIGNAL TYPE FUNCTION 7 PWR_EN RW Power change GPE enable. When this bit is set, GPE is signaled on PWR_STS events. 6 VPP12_EN RW 12-V VPP GPE enable. When this bit is set, GPE is signaled on VPP12_STS events. 5 RSVD R 4 GP4_EN RW Reserved. This bit returns 0 when read. A write has no effect. GPI4 GPE enable. When this bit is set, GPE is signaled on GP4_STS events. 3 GP3_EN RW GPI3 GPE enable. When this bit is set, GPE is signaled on GP3_STS events. 2 GP2_EN RW GPI2 GPE enable. When this bit is set, GPE is signaled on GP2_STS events. 1 GP1_EN RW GPI1 GPE enable. When this bit is set, GPE is signaled on GP1_STS events. 0 GP0_EN RW GPI0 GPE enable. When this bit is set, GPE is signaled on GP0_STS events. 4.32 General-Purpose Input Register The general-purpose input register contains the logical value of the data input to the GPI terminals. See Table 4−12 for a complete description of the register contents. Bit 7 6 5 Type R R R RU Default 0 0 0 X Name 4 3 2 1 0 RU RU RU RU X X X X General-purpose input Register: Offset: Type: Default: General-purpose input 8Ah Read/Update, Read-only XXh Table 4−12. General-Purpose Input Register Description 4−20 BIT SIGNAL TYPE 7−5 RSVD R FUNCTION 4 GPI4_DATA RU GPI4 data input. This bit represents the logical value of the data input from GPI4. 3 GPI3_DATA RU GPI3 data input. This bit represents the logical value of the data input from GPI3. 2 GPI2_DATA RU GPI2 data input. This bit represents the logical value of the data input from GPI2. 1 GPI1_DATA RU GPI1 data input. This bit represents the logical value of the data input from GPI1. 0 GPI0_DATA RU GPI0 data input. This bit represents the logical value of the data input from GPI0. Reserved. These bits return 0s when read. Writes have no effect. 4.33 General-Purpose Output Register The general-purpose output register is used to drive the GPO4−GPO0 outputs. See Table 4−13 for a complete description of the register contents. Bit 7 6 5 Name 4 3 2 1 0 General-purpose output Type R R R RW RW RW RW RW Default 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: General-purpose output 8Bh Read-only, Read/Write 00h Table 4−13. General-Purpose Output Register Description BIT SIGNAL TYPE FUNCTION 7−5 RSVD R 4 GPO4_DATA RW Reserved. These bits return 0s when read. Writes have no effect. This bit represents the logical value of the data driven to GPO4. 3 GPO3_DATA RW This bit represents the logical value of the data driven to GPO3. 2 GPO2_DATA RW This bit represents the logical value of the data driven to GPO2. 1 GPO1_DATA RW This bit represents the logical value of the data driven to GPO1. 0 GPO0_DATA RW This bit represents the logical value of the data driven to GPO0. 4−21 4.34 Multifunction Routing Status Register The multifunction routing status register is used to configure the MFUNC0−MFUNC6 terminals. These terminals may be configured for various functions. This register is intended to be programmed once at power-on initialization. The default value for this register can also be loaded through a serial ROM. All bits in this register are GRST only bits. See Table 4−14 for a complete description of the register contents. Bit 31 30 29 28 27 26 Name 25 24 23 22 21 20 19 18 17 16 Multifunction routing status Type R R R R RW RW RW RW RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Multifunction routing status RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Multifunction routing status 8Ch Read/Write, Read-only 0000 1000h Table 4−14. Multifunction Routing Status Register Description BIT SIGNAL TYPE 31−28 RSVD R 27−24 23−20 19−16 15−12 11−8 4−22 MFUNC6_SEL MFUNC5_SEL MFUNC4_SEL MFUNC3_SEL MFUNC2_SEL FUNCTION Bits 31−28 return 0s when read. RW Multifunction terminal 6 select. This bit controls the mapping of the MFUNC6 terminal as follows: 0000 = RSVD 0100 = IRQ4 1000 = IRQ8 1100 = IRQ12 0101 = IRQ5 1001 = IRQ9 1101 = IRQ13 0001 = CLKRUN 0010 = IRQ2 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 RW Multifunction terminal 5 select. This bit controls the mapping of the MFUNC5 terminal as follows: 0000 = GPI4 0100 = IRQ4 1000 = CAUDPWM 1100 = LED_SKT 0001 = GPO4 0101 = IRQ5 1001 = IRQ9 1101 = LED_SKT 0010 = PCGNT 0110 = ZVSTAT 1010 = IRQ10 1110 = GPE 0011 = IRQ3 0111 = RSVD 1011 = OHCI_LED 1111 = IRQ15 RW Multifunction terminal 4 select. This bit controls the mapping of the MFUNC4 terminal as follows: 0000 = GPI3 0100 = IRQ4 1000 = CAUDPWM 1100 = RI_OUT 0001 = GPO3 0101 = IRQ5 1001 = IRQ9 1101 = LED_SKT 0010 = LOCK 0110 = ZVSTAT 1010 = RSVD 1110 = GPE 0011 = IRQ3 0111 = RSVD 1011 = IRQ11 1111 = IRQ15 RW Multifunction terminal 3 select. This bit controls the mapping of the MFUNC3 terminal as follows: 0000 = RSVD 0100 = IRQ4 1000 = IRQ8 1100 = IRQ12 0001 = IRQSER 0101 = IRQ5 1001 = IRQ9 1101 = IRQ13 0010 = IRQ2 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 RW Multifunction terminal 2 select. This bit controls the mapping of the MFUNC2 terminal as follows: 0000 = GPI2 0100 = IRQ4 1000 = CAUDPWM 1100 = RI_OUT 0001 = GPO2 0101 = IRQ5 1001 = IRQ9 1101 = TEST_MUX 0010 = PCREQ 0110 = ZVSTAT 1010 = IRQ10 1110 = GPE 0011 = IRQ3 0111 = ZVSEL0 1011 = RSVD 1111 = IRQ7 Table 4−14. Multifunction Routing Status Register Description (Continued) BIT 7−4 3−0 SIGNAL MFUNC1_SEL MFUNC0_SEL TYPE FUNCTION RW Multifunction terminal 1 select. This bit controls the mapping of the MFUNC1 terminal as follows: 0000 = GPI1 0100 = OHCI_LED 1000 = CAUDPWM 1100 = LED_SKT 0001 = GPO1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0110 = ZVSTAT 1010 = IRQ10 1110 = GPE 0010 = INTB 0011 = IRQ3 0111 = ZVSEL0 1011 = IRQ11 1111 = IRQ15 RW Multifunction terminal 0 select. This bit controls the mapping of the MFUNC0 terminal as follows: 0000 = GPI0 0100 = IRQ4 1000 = CAUDPWM 1100 = LED_SKT 0001 = GPO0 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0110 = ZVSTAT 1010 = IRQ10 1110 = GPE 0010 = INTA 0011 = IRQ3 0111 = ZVSEL0 1011 = IRQ11 1111 = IRQ15 4.35 Retry Status Register The contents of the retry status register enable the retry time-out counters and display the retry expiration status. The flags are set when the PCI4510 device retries a PCI or CardBus master request, and the master does not return within 215 PCI clock cycles. The flags are cleared by writing a 1 to the bit. These bits are expected to be incorporated into the command register (PCI offset 04h, see Section 4.4), status register (PCI offset 06h, see Section 4.5), and bridge control register (PCI offset 3Eh, see Section 4.24) by the PCI SIG. Access this register only through function 0. See Table 4−15 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 RW RW R R RC R RC R 1 0 0 0 0 0 0 Name Type Default Retry status 1 Register: Offset: Type: Default: Retry status 90h (Function 0) Read-only, Read/Write, Read/Clear C0h Table 4−15. Retry Status Register Description BIT SIGNAL TYPE 7 PCIRETRY RW PCI retry time-out counter enable. This bit is encoded as: 0 = PCI retry counter disabled 1 = PCI retry counter enabled (default) 6 CBRETRY RW CardBus retry time-out counter enable. This bit is encoded as: 0 = CardBus retry counter disabled 1 = CardBus retry counter enabled (default) 5−4 RSVD R 3 TEXP_CBA RC 2 RSVD R 1 TEXP_PCI RC 0 RSVD R FUNCTION Reserved. These bits return 0s when read. CardBus target A retry expired. Write a 1 to clear this bit. 0 = Inactive (default) 1 = Retry has expired. Reserved. This bit returns 0 when read. PCI target retry expired. Write a 1 to clear this bit. 0 = Inactive (default) 1 = Retry has expired. Reserved. This bit returns 0 when read. 4−23 4.36 Card Control Register The card control register provides several control bits for RI_OUT, ZV, and other functionalities. See Table 4−16 for a complete description of the register contents. The RI_OUT signal is enabled through this register. Bit 7 6 5 4 3 2 1 0 RW RW R R R RW RW RW 0 0 0 0 0 0 0 0 Name Type Default Card control Register: Offset: Type: Default: Card control 91h Read-only, Read/Write 00h Table 4−16. Card Control Register Description BIT SIGNAL TYPE 7 RIENB RW Ring indicate enable. When this bit is 1, the RI_OUT output is enabled. This bit defaults to 0. 6 ZVENABLE RW Compatibility ZV mode enable. When this bit is 1, the corresponding PC Card socket interface ZV terminals enter a high-impedance state. This bit defaults to 0. 5−3 RSVD R 2 1 0 AUD2MUX SPKROUTEN IFG RW RW RW FUNCTION Reserved. These bits default to 0. CardBus audio-to-MFUNC. When this bit is set, the CAUDIO CardBus signal must be routed through an MFUNC terminal. If this bit is set for both functions, then function 0 is routed. 0 = CAUDIO set to CAUDPWM on MFUNC terminal (default) 1 = CAUDIO is not routed. Speaker output enable. When this bit is 1, it enables SPKR on the PC Card and routes it to SPKROUT on the PCI bus. This bit is encoded as: 0 = SPKR to SPKROUT not enabled (default) 1 = SPKR to SPKROUT enabled Interrupt flag. This bit is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. This bit is set when a functional interrupt is signaled from a PC Card interface, and is socket dependent (that is, not global). Write back a 1 to clear this bit. 0 = No PC Card functional interrupt detected (default) 1 = PC Card functional interrupt detected 4−24 4.37 Device Control Register The device control register is provided for PCI1130 compatibility. The interrupt mode select is programmed through this register. The socket-capable force bits are also programmed through this register. See Table 4−17 for a complete description of the register contents. Bit 7 6 5 4 Name Type Default 3 2 1 0 Device control RW RW RW R RW RW RW RW 0 1 1 0 0 1 1 0 Register: Offset: Type: Default: Device control 92h (Function 0) Read-only, Read/Write 66h Table 4−17. Device Control Register Description BIT SIGNAL TYPE FUNCTION 7 SKTPWR_LOCK RW Socket power lock bit. When this bit is set to 1, software cannot power down the PC Card socket while in D3. It may be necessary to lock socket power in order to support wake on LAN or RING if the operating system is programmed to power down a socket when the CardBus controller is placed in the D3 state. 6 3VCAPABLE RW 3-V socket capable force bit. 0 = Not 3-V capable 1 = 3-V capable (default) 5 IO16R2 RW Diagnostic bit. This bit defaults to 1. 4 RSVD R 3 TEST RW TI test bit. Write only 0 to this bit. This bit can be set to shorten the interrogation counter. Reserved. This bit returns 0 when read. A write has no effect. 2−1 INTMODE RW Interrupt mode. These bits select the interrupt signaling mode. The interrupt mode bits are encoded: 00 = Parallel PCI interrupts only 01 = Parallel IRQ and parallel PCI interrupts 10 = IRQ serialized interrupts and parallel PCI interrupts INTA and INTB 11 = IRQ and PCI serialized interrupts (default) 0 RSVD RW Reserved. NAND tree enable bit. There is a NAND tree diagnostic structure in the PCI4510 device, and it tests only the terminals that are inputs or I/Os. Any output-only terminal on the PCI4510 device is excluded from the NAND tree test. 4−25 4.38 Diagnostic Register The diagnostic register is provided for internal TI test purposes. It is a read/write register, but only 0s must be written to it. See Table 4−18 for a complete description of the register contents. Bit 7 6 5 4 Name Type Default 3 2 1 0 Diagnostic RW R RW RW RW RW RW RW 0 1 1 0 0 0 0 0 Register: Offset: Type: Default: Diagnostic 93h (Function 0) Read/Write 60h Table 4−18. Diagnostic Register Description 4−26 BIT SIGNAL TYPE FUNCTION 7 TRUE_VAL RW 6 RSVD R 5 CSC RW CSC interrupt routing control 0 = CSC interrupts routed to PCI if ExCA 803 bit 4 = 1 1 = CSC interrupts routed to PCI if ExCA 805 bits 7−4 = 0000b (default). In this case, the setting of ExCA 803 bit 4 is a don’t care. 4 DIAG4 RW Diagnostic RETRY_DIS. Delayed transaction disable. 3 DIAG3 RW 2 DIAG2 RW Diagnostic RETRY_EXT. Extends the latency from 16 to 64. Diagnostic DISCARD_TIM_SEL_CB. Set = 210, reset = 215. 1 DIAG1 RW Diagnostic DISCARD_TIM_SEL_PCI. Set = 210, reset = 215. 0 ZV_EN RW Zoomed video enable. 0 = Enable new ZV register model (default) 1 = Disable new ZV register mode This bit defaults to 0. This bit is encoded as: 0 = Reads true values in PCI vendor ID and PCI device ID registers (default) 1 = Reads all 1s in reads to the PCI vendor ID and PCI device ID registers Reserved. This bit is read-only and returns 1 when read. 4.39 Capability ID Register The capability ID register identifies the linked list item as the register for PCI power management. The register returns 01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value. Bit 7 6 5 4 Name 3 2 1 0 Capability ID Type R R R R R R R R Default 0 0 0 0 0 0 0 1 Register: Offset: Type: Default: Capability ID A0h Read-only 01h 4.40 Next Item Pointer Register The contents of this register indicate the next item in the linked list of the PCI power management capabilities. Because the PCI4510 function only includes one capability item, this register returns 0s when read. Bit 7 6 5 4 Type R R R R Default 0 0 0 0 Name 3 2 1 0 R R R R 0 0 0 0 Next item pointer Register: Offset: Type: Default: Next item pointer A1h Read-only 00h 4−27 4.41 Power Management Capabilities Register The power management capabilities register contains information on the capabilities of the PC Card function related to power management. Both PCI4510 CardBus bridge functions support D0, D1, D2, and D3 power states. Default register value is FE12h for operation in accordance with PCI Bus Power Management Interface Specification revision 1.1. See Table 4−19 for a complete description of the register contents. Bit 15 14 13 12 11 10 Name Type Default 9 8 7 6 5 4 3 2 1 0 Power management capabilities RW R R R R R R R R R R R R R R R 1 1 1 1 1 1 1 0 0 0 1 1 0 0 1 0 Register: Offset: Type: Default: Power management capabilities A2h (Function 0) Read-only, Read/Write FE32h Table 4−19. Power Management Capabilities Register Description BIT SIGNAL TYPE FUNCTION This 5-bit field indicates the power states from which the PCI4510 device functions can assert PME. A 0 for any bit indicates that the function cannot assert the PME signal while in that power state. These 5 bits return 0Fh when read. Each of these bits is described below: 15 RW PME support 14−11 Bit 15 − defaults to a 1 indicating the PME signal can be asserted from the D3cold state. This bit is read/write because wake-up support from D3cold is contingent on the system providing an auxiliary power source to the VCC terminals. If the system designer chooses not to provide an auxiliary power source to the VCC terminals for D3cold wake-up support, then BIOS must write a 0 to this bit. R Bit 14 − contains the value 1 to indicate that the PME signal can be asserted from the D3hot state. Bit 13 − contains the value 1 to indicate that the PME signal can be asserted from the D2 state. Bit 12 − contains the value 1 to indicate that the PME signal can be asserted from the D1 state. Bit 11 − contains the value 1 to indicate that the PME signal can be asserted from the D0 state. 10 D2_Support R This bit returns a 1 when read, indicating that the function supports the D2 device power state. 9 D1_Support R This bit returns a 1 when read, indicating that the function supports the D1 device power state. 8−6 RSVD R Reserved. These bits return 000b when read. 5 DSI R Device-specific initialization. This bit returns 0 when read. Auxiliary power source. This bit is meaningful only if bit 15 (D3cold supporting PME) is set. When this bit is set, it indicates that support for PME in D3cold requires auxiliary power supplied by the system by way of a proprietary delivery vehicle. 4 AUX_PWR R A 0 (zero) in this bit field indicates that the function supplies its own auxiliary power source. If the function does not support PME while in the D3cold state (bit 15=0), then this field must always return 0. 3 PMECLK R When this bit is 1, it indicates that the function relies on the presence of the PCI clock for PME operation. When this bit is 0, it indicates that no PCI clock is required for the function to generate PME. Functions that do not support PME generation in any state must return 0 for this field. 2−0 4−28 Version R These 3 bits return 010b when read, indicating that there are 4 bytes of general-purpose power management (PM) registers as described in draft revision 1.1 of the PCI Bus Power Management Interface Specification. 4.42 Power Management Control/Status Register The power management control/status register determines and changes the current power state of the PCI4510 CardBus function. The contents of this register are not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See Table 4−20 for a complete description of the register contents. All PCI registers, ExCA registers, and CardBus registers are reset as a result of a D3hot-to-D0 state transition, with the exception of the PME context bits (if PME is enabled) and the GRST only bits. Bit 15 14 13 12 11 10 RWC R R R R R R RW R 0 0 0 0 0 0 0 0 0 Name Type Default 9 8 7 6 5 4 3 2 1 0 R R R R R RW RW 0 0 0 0 0 0 0 Power management control/status Register: Offset: Type: Default: Power management control/status A4h (Function 0) Read-only, Read/Write, Read/Write/Clear 0000h Table 4−20. Power Management Control/Status Register Description BIT SIGNAL TYPE FUNCTION PME status. This bit is set when the CardBus function would normally assert the PME signal, independent of the state of the PME_EN bit. This bit is cleared by a writeback of 1, and this also clears the PME signal if PME was asserted by this function. Writing a 0 to this bit has no effect. 15 PMESTAT RC 14−13 DATASCALE R This 2-bit field returns 0s when read. The CardBus function does not return any dynamic data. 12−9 DATASEL R Data select. This 4-bit field returns 0s when read. The CardBus function does not return any dynamic data. 8 PME_ENABLE RW This bit enables the function to assert PME. If this bit is cleared, then assertion of PME is disabled. This bit is not cleared by the assertion of PRST. It is only cleared by the assertion of GRST. 7−2 RSVD R Reserved. These bits return 0s when read. Power state. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. This field is encoded as: 1−0 PWRSTATE RW 00 = D0 01 = D1 10 = D2 11 = D3hot 4−29 4.43 Power Management Control/Status Bridge Support Extensions Register This register supports PCI bridge-specific functionality. It is required for all PCI-to-PCI bridges. See Table 4−21 for a complete description of the register contents. Bit 7 6 5 Name 4 3 2 1 0 Power management control/status bridge support extensions Type R R R R R R R R Default 1 1 0 0 0 0 0 0 Register: Offset: Type: Default: Power management control/status bridge support extensions A6h (Function 0) Read-only C0h Table 4−21. Power Management Control/Status Bridge Support Extensions Register Description BIT SIGNAL TYPE FUNCTION Bus power/clock control enable. This bit returns 1 when read. This bit is encoded as: 0 = Bus power/clock control is disabled. 1 = Bus power/clock control is enabled (default). 7 BPCC_EN A 0 indicates that the bus power/clock control policies defined in the PCI Bus Power Management Interface Specification are disabled. When the bus power/clock control enable mechanism is disabled, the power state field (bits 1−0) of the bridge power management control/status register (PCI offset A4h, see Section 4.42) cannot be used by the system software to control the power or the clock of the bridge secondary bus. A 1 indicates that the bus power/clock control mechanism is enabled. R 6 B2_B3 R B2/B3 support for D3hot. The state of this bit determines the action that is to occur as a direct result of programming the function to D3hot. This bit is only meaningful if bit 7 (BPCC_EN) is a 1. This bit is encoded as: 0 = When the bridge is programmed to D3hot, its secondary bus has its power removed (B3). 1 = When the bridge function is programmed to D3hot, its secondary bus PCI clock is stopped (B2) (default). 5−0 RSVD R Reserved. These bits return 0s when read. 4.44 Serial Bus Data Register The serial bus data register is for programmable serial bus byte reads and writes. This register represents the data when generating cycles on the serial bus interface. To write a byte, this register must be programmed with the data, the serial bus index register must be programmed with the byte address, the serial bus slave address must be programmed with both the 7-bit slave address, and the read/write indicator bit must be reset. On byte reads, the byte address is programmed into the serial bus index register, the serial bus slave address register must be programmed with both the 7-bit slave address and the read/write indicator bit, and bit 5 (REQBUSY) in the serial bus control and status register (see Section 4.47) must be polled until clear. Then the contents of this register are valid read data from the serial bus interface. See Table 4−22 for a complete description of the register contents. Bit 7 6 5 4 Name Type Default 3 2 1 0 Serial bus data RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Serial bus data B0h (Function 0) Read/Write 00h Table 4−22. Serial Bus Data Register Description BIT 7−0 4−30 SIGNAL SBDATA TYPE FUNCTION RW Serial bus data. This bit field represents the data byte in a read or write transaction on the serial interface. On reads, the REQBUSY bit must be polled to verify that the contents of this register are valid. 4.45 Serial Bus Index Register The serial bus index register is for programmable serial bus byte reads and writes. This register represents the byte address when generating cycles on the serial bus interface. To write a byte, the serial bus data register must be programmed with the data, this register must be programmed with the byte address, and the serial bus slave address must be programmed with both the 7-bit slave address and the read/write indicator. On byte reads, the word address is programmed into this register, the serial bus slave address must be programmed with both the 7-bit slave address and the read/write indicator bit, and bit 5 (REQBUSY) in the serial bus control and status register (see Section 4.47) must be polled until clear. Then the contents of the serial bus data register are valid read data from the serial bus interface. See Table 4−23 for a complete description of the register contents. Bit 7 6 5 Name Type Default 4 3 2 1 0 Serial bus index RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Serial bus index B1h (Function 0) Read/Write 00h Table 4−23. Serial Bus Index Register Description BIT SIGNAL TYPE FUNCTION 7−0 SBINDEX RW Serial bus index. This bit field represents the byte address in a read or write transaction on the serial interface. 4.46 Serial Bus Slave Address Register The serial bus slave address register is for programmable serial bus byte read and write transactions. To write a byte, the serial bus data register must be programmed with the data, the serial bus index register must be programmed with the byte address, and this register must be programmed with both the 7-bit slave address and the read/write indicator bit. On byte reads, the byte address is programmed into the serial bus index register, this register must be programmed with both the 7-bit slave address and the read/write indicator bit, and bit 5 (REQBUSY) in the serial bus control and status register (see Section 4.47) must be polled until clear. Then the contents of the serial bus data register are valid read data from the serial bus interface. See Table 4−24 for a complete description of the register contents. Bit 7 6 5 Name Type Default 4 3 2 1 0 Serial bus slave address RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Serial bus slave address B2h (Function 0) Read/Write 00h Table 4−24. Serial Bus Slave Address Register Description BIT SIGNAL TYPE FUNCTION 7−1 SLAVADDR RW Serial bus slave address. This bit field represents the slave address of a read or write transaction on the serial interface. 0 RWCMD RW Read/write command. Bit 0 indicates the read/write command bit presented to the serial bus on byte read and write accesses. 0 = A byte write access is requested to the serial bus interface. 1 = A byte read access is requested to the serial bus interface. 4−31 4.47 Serial Bus Control and Status Register The serial bus control and status register communicates serial bus status information and selects the quick command protocol. Bit 5 (REQBUSY) in this register must be polled during serial bus byte reads to indicate when data is valid in the serial bus data register. See Table 4−25 for a complete description of the register contents. Bit 7 6 5 Name Type Default 4 3 2 1 0 Serial bus control and status RW R R R RW RW RC RC 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Serial bus control and status B3h (Function 0) Read-only, Read/Write, Read/Clear 00h Table 4−25. Serial Bus Control and Status Register Description BIT SIGNAL TYPE FUNCTION 7 PROT_SEL RW Protocol select. When bit 7 is set, the send-byte protocol is used on write requests and the receive-byte protocol is used on read commands. The word address byte in the serial bus index register (see Section 4.45) is not output by the PCI4510 device when bit 7 is set. 6 RSVD R Reserved. Bit 6 returns 0 when read. 5 REQBUSY R Requested serial bus access busy. Bit 5 indicates that a requested serial bus access (byte read or write) is in progress. A request is made, and bit 5 is set, by writing to the serial bus slave address register (see Section 4.46). Bit 5 must be polled on reads from the serial interface. After the byte read access has been requested, the read data is valid in the serial bus data register. R Serial ROM busy status. Bit 4 indicates the status of the PCI4510 serial ROM circuitry. Bit 4 is set during the loading of the subsystem ID and other default values from the serial bus ROM. 0 = Serial ROM circuitry is not busy 1 = Serial ROM circuitry is busy 4 3 SBDETECT RW Serial bus detect. When bit 3 is set, it indicates that the serial bus interface is detected through a pullup resistor on the SCL terminal after reset. 0 = Serial bus interface not detected 1 = Serial bus interface detected 2 SBTEST RW Serial bus test. When bit 2 is set, the serial bus clock frequency is increased for test purposes. 0 = Serial bus clock at normal operating frequency, 100 kHz (default) 1 = Serial bus clock frequency increased for test purposes 1 REQ_ERR RC Requested serial bus access error. Bit 1 indicates when a data error occurs on the serial interface during a requested cycle and may be set due to a missing acknowledge. Bit 1 is cleared by a writeback of 1. 0 = No error detected during user requested byte read or write cycle 1 = Data error detected during user requested byte read or write cycle RC ROM data error status. Bit 0 indicates when a data error occurs on the serial interface during the auto-load from the serial bus ROM and may be set due to a missing acknowledge. Bit 0 is also set on invalid ROM data formats. See Section 3.6.3, Serial Bus EEPROM Application, for details on ROM data format. Bit 0 is cleared by a writeback of 1. 0 = No error detected during auto-load from serial bus ROM 1 = Data error detected during auto-load from serial bus ROM 0 4−32 ROMBUSY ROM_ERR 5 ExCA Compatibility Registers (Function 0) The ExCA registers implemented in the PCI4510 device are register-compatible with the Intel 82365SL−DF PCMCIA controller. ExCA registers are identified by an offset value that is compatible with the legacy I/O index/data scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed through this scheme by writing the register offset value into the index register (I/O base) and reading or writing the data register (I/O base + 1). The I/O base address used in the index/data scheme is programmed in the PC Card 16-bit I/F legacy-mode base address register (PCI offset 44h, see Section 4.27), which is shared by both card sockets. The offsets from this base address run contiguously from 00h to 3Fh for the socket. See Figure 5−1 for an ExCA I/O mapping illustration. Host I/O Space PCI4510 Configuration Registers Offset Offset CardBus Socket/ExCA Base Address 10h PC Card ExCA Registers Index Data 16-Bit Legacy-Mode Base Address 00h 3Fh 44h Figure 5−1. ExCA Register Access Through I/O The TI PCI4510 device also provides a memory-mapped alias of the ExCA registers by directly mapping them into PCI memory space. They are located through the CardBus socket register/ExCA base-address register (PCI offset 10h, see Section 4.11) at memory offset 800h. Each socket has a separate base address programmable by function. See Figure 5−2 for an ExCA memory mapping illustration. Note that memory offsets are 800h−844h for function 0. This illustration also identifies the CardBus socket register mapping, which is mapped into the same 4-K window at memory offset 00h. PCI4510 Configuration Registers Offset Host Memory Space Offset 00h CardBus Socket/ExCA Base Address 10h CardBus Socket Registers 20h 800h 16-Bit Legacy-Mode Base Address 44h ExCA Registers 844h Figure 5−2. ExCA Register Access Through Memory 5−1 The interrupt registers in the ExCA register set, as defined by the 82365SL−DL specification, control such card functions as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing registers and the host interrupt signaling method selected for the PCI4510 device to ensure that all possible PCI4510 interrupts can potentially be routed to the programmable interrupt controller. The ExCA registers that are critical to the interrupt signaling are the ExCA interrupt and general control register (ExCA offset 03h/803h, see Section 5.4) and the ExCA card status-change interrupt configuration register (ExCA offset 05h/805h, see Section 5.6). Access to I/O-mapped 16-bit PC cards is available to the host system via two ExCA I/O windows. These are regions of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section. I/O windows have byte granularity. Access to memory-mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These are regions of host memory space into which the card memory space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section. Table 5−1 identifies each ExCA register and its respective ExCA offset. Memory windows have 4-Kbyte granularity. Table 5−1. ExCA Registers and Offsets PCI MEMORY ADDRESS OFFSET (HEX) ExCA OFFSET (HEX) Identification and revision 800 00 Interface status 801 01 Power control 802 02 Interrupt and general control 803 03 Card status change 804 04 Card status-change interrupt configuration 805 05 Address window enable 806 06 I / O window control 807 07 I / O window 0 start-address low byte 808 08 EXCA REGISTER NAME 5−2 I / O window 0 start-address high byte 809 09 I / O window 0 end-address low byte 80A 0A I / O window 0 end-address high byte 80B 0B I / O window 1 start-address low byte 80C 0C I / O window 1 start-address high byte 80D 0D I / O window 1 end-address low byte 80E 0E I / O window 1 end-address high byte 80F 0F Memory window 0 start-address low byte 810 10 Memory window 0 start-address high byte 811 11 Memory window 0 end-address low byte 812 12 Memory window 0 end-address high byte 813 13 Memory window 0 offset-address low byte 814 14 Memory window 0 offset-address high byte 815 15 Card detect and general control 816 16 Reserved 817 17 Memory window 1 start-address low byte 818 18 Memory window 1 start-address high byte 819 19 Memory window 1 end-address low byte 81A 1A Memory window 1 end-address high byte 81B 1B Memory window 1 offset-address low byte 81C 1C Memory window 1 offset-address high byte 81D 1D Table 5−1. ExCA Registers and Offsets (Continued) PCI MEMORY ADDRESS OFFSET (HEX) ExCA OFFSET (HEX) Global control 81E 1E Reserved 81F 1F Memory window 2 start-address low byte 820 20 Memory window 2 start-address high byte 821 21 Memory window 2 end-address low byte 822 22 Memory window 2 end-address high byte 823 23 Memory window 2 offset-address low byte 824 24 Memory window 2 offset-address high byte 825 25 Reserved 826 26 Reserved 827 27 Memory window 3 start-address low byte 828 28 EXCA REGISTER NAME Memory window 3 start-address high byte 829 29 Memory window 3 end-address low byte 82A 2A Memory window 3 end-address high byte 82B 2B Memory window 3 offset-address low byte 82C 2C Memory window 3 offset-address high byte 82D 2D Reserved 82E 2E Reserved 82F 2F Memory window 4 start-address low byte 830 30 Memory window 4 start-address high byte 831 31 Memory window 4 end-address low byte 832 32 Memory window 4 end-address high byte 833 33 Memory window 4 offset-address low byte 834 34 Memory window 4 offset-address high byte 835 35 I/O window 0 offset-address low byte 836 36 I/O window 0 offset-address high byte 837 37 I/O window 1 offset-address low byte 838 38 I/O window 1 offset-address high byte 839 39 Reserved 83A 3A Reserved 83B 3B Reserved 83C 3C Reserved 83D 3D Reserved 83E 3E Reserved 83F 3F Memory window page 0 840 − Memory window page 1 841 − Memory window page 2 842 − Memory window page 3 843 − Memory window page 4 844 − A bit description table, typically included when a register contains bits of more than one type or purpose, indicates bit field names, which appear in the signal column; a detailed field description, which appears in the function column; and field access tags, which appear in the type column of the bit description table. Table 4−1 describes the field access tags. 5−3 5.1 ExCA Identification and Revision Register The ExCA identification and revision register provides host software with information on 16-bit PC Card support and Intel 82365SL-DF compatibility. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register (PCI offset 80h, see Section 4.28). See Table 5−2 for a complete description of the register contents. Bit 7 6 5 Name 4 3 2 1 0 ExCA identification and revision Type R R RW RW RW RW RW RW Default 1 0 0 0 0 1 0 0 Register: Offset: Type: Default: ExCA identification and revision CardBus socket address + 800h; ExCA offset 00h Read-only, Read/Write 84h Table 5−2. ExCA Identification and Revision Register Description 5−4 BIT SIGNAL TYPE FUNCTION 7−6 IFTYPE R Interface type. These bits, which are hardwired as 10b, identify the 16-bit PC Card support provided by the PCI4510 device. The PCI4510 device supports both I/O and memory 16-bit PC cards. 5−4 RSVD RW Reserved. Bits 5 and 4 can be used for Intel 82365SL-DF emulation. 3−0 365REV RW Intel 82365SL-DF revision. This field stores the Intel 82365SL-DF revision supported by the PCI4510 device. Host software can read this field to determine compatibility to the Intel 82365SL-DF register set. Writing 0010b to this field puts the controller in 82365SL mode. 5.2 ExCA Interface Status Register The ExCA interface status register provides information on the current status of the PC Card interface. An X in the default bit value indicates that the value of the bit after reset depends on the state of the PC Card interface. See Table 5−3 for a complete description of the register contents. Bit 7 6 5 Name 4 3 2 1 0 ExCA interface status Type R R R R R R R R Default 0 0 X X X X X X Register: Offset: Type: Default: ExCA interface status CardBus socket address + 801h; ExCA offset 01h Read-only 00XX XXXXb Table 5−3. ExCA Interface Status Register Description BIT SIGNAL TYPE 7 RSVD R 6 CARDPWR R 5 READY R 4 3 2 1−0 CARDWP CDETECT2 CDETECT1 BVDSTAT FUNCTION Reserved. Bit 7 returns 0 when read. Card power. Bit 6 indicates the current power status of the PC Card socket. This bit reflects how the ExCA power control register (ExCA offset 02h/802h, see Section 5.3) is programmed. Bit 6 is encoded as: 0 = VCC and VPP to the socket turned off (default) 1 = VCC and VPP to the socket turned on Ready. Bit 5 indicates the current status of the READY signal at the PC Card interface. 0 = PC Card not ready for data transfer 1 = PC Card ready for data transfer R Card write protect (WP). Bit 4 indicates the current status of the WP signal at the PC Card interface. This signal reports to the PCI4510 device whether or not the memory card is write protected. Furthermore, write protection for an entire PCI4510 16-bit memory window is available by setting the appropriate bit in the memory window offset-address high-byte register. 0 = WP is 0. PC Card is read/write. 1 = WP is 1. PC Card is read-only. R Card detect 2. Bit 3 indicates the status of the CD2 signal at the PC Card interface. Software may use this and bit 2 (CDETECT1) to determine if a PC Card is fully seated in the socket. 0 = CD2 is 1. No PC Card is inserted. 1 = CD2 is 0. PC Card is at least partially inserted. R Card detect 1. Bit 2 indicates the status of the CD1 signal at the PC Card interface. Software may use this and bit 3 (CDETECT2) to determine if a PC Card is fully seated in the socket. 0 = CD1 is 1. No PC Card is inserted. 1 = CD1 is 0. PC Card is at least partially inserted. R Battery voltage detect. When a 16-bit memory card is inserted, the field indicates the status of the battery voltage detect signals (BVD1, BVD2) at the PC Card interface, where bit 1 reflects the BVD2 status and bit 0 reflects BVD1. 00 = Battery dead 01 = Battery dead 10 = Battery low; warning 11 = Battery good When a 16-bit I/O card is inserted, this field indicates the status of SPKR (bit 1) and STSCHG (bit 0) at the PC Card interface. In this case, the two bits in this field directly reflect the current state of these card outputs. 5−5 5.3 ExCA Power Control Register The ExCA power control register provides PC Card power control. Bit 7 (COE) of this register controls the 16-bit output enables on the socket interface, and can be used for power management in 16-bit PC Card applications. See Table 5−4 and Table 5−5 for a complete description of the register contents. Bit 7 6 5 Name Type Default 4 3 2 1 0 ExCA power control RW R R RW RW R RW RW 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: ExCA power control CardBus socket address + 802h; ExCA offset 02h Read-only, Read/Write 00h Table 5−4. ExCA Power Control Register Description—82365SL Support BIT SIGNAL TYPE FUNCTION 7 COE RW Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the PCI4510 device. This bit is encoded as: 0 = 16-bit PC Card outputs disabled (default) 1 = 16-bit PC Card outputs enabled 6 RSVD R 5 AUTOPWRSWEN RW Auto power switch enable. 0 = Automatic socket power switching based on card detects is disabled. 1 = Automatic socket power switching based on card detects is enabled. PC Card power enable. 0 = VCC = No connection 1 = VCC is enabled and controlled by bit 2 (EXCAPOWER) of the system control register (PCI offset 80h, see Section 4.28). 4 CAPWREN RW 3−2 RSVD R 1−0 EXCAVPP RW Reserved. Bit 6 returns 0 when read. Reserved. Bits 3 and 2 return 0s when read. PC Card VPP power control. Bits 1 and 0 are used to request changes to card VPP. The PCI4510 device ignores this field unless VCC to the socket is enabled. This field is encoded as: 00 = No connection (default) 01 = VCC 10 = 12 V 11 = Reserved Table 5−5. ExCA Power Control Register Description—82365SL-DF Support BIT TYPE FUNCTION Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the PCI4510 device. This bit is encoded as: 0 = 16-bit PC Card outputs disabled (default) 1 = 16-bit PC Card outputs enabled 7 COE RW 6−5 RSVD R 4−3 EXCAVCC RW 2 RSVD R 1−0 5−6 SIGNAL EXCAVPP RW Reserved. Bits 6 and 5 return 0s when read. VCC. Bits 4 and 3 are used to request changes to card VCC. This field is encoded as: 00 = 0 V (default) 01 = 0 V reserved 10 = 5 V 11 = 3.3 V Reserved. Bit 2 returns 0 when read. VPP. Bits 1 and 0 are used to request changes to card VPP. The PCI4510 device ignores this field unless VCC to the socket is enabled. This field is encoded as: 00 = No connection (default) 01 = VCC 10 = 12 V 11 = Reserved 5.4 ExCA Interrupt and General Control Register The ExCA interrupt and general control register controls interrupt routing for I/O interrupts, as well as other critical 16-bit PC Card functions. See Table 5−6 for a complete description of the register contents. Bit 7 6 5 Name Type Default 4 3 2 1 0 ExCA interrupt and general control RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: ExCA interrupt and general control CardBus socket address + 803h; ExCA offset 03h Read/Write 00h Table 5−6. ExCA Interrupt and General Control Register Description BIT SIGNAL TYPE FUNCTION 7 RINGEN RW Card ring indicate enable. Bit 7 enables the ring indicate function of the BVD1/RI signal. This bit is encoded as: 0 = Ring indicate disabled (default) 1 = Ring indicate enabled 6 RESET RW Card reset. Bit 6 controls the 16-bit PC Card RESET signal, and allows host software to force a card reset. Bit 6 affects 16-bit cards only. This bit is encoded as: 0 = RESET signal asserted (default) 1 = RESET signal deasserted 5 CARDTYPE RW Card type. Bit 5 indicates the PC card type. This bit is encoded as: 0 = Memory PC Card installed (default) 1 = I/O PC Card installed RW PCI interrupt CSC routing enable bit. When bit 4 is set (high), the card status change interrupts are routed to PCI interrupts. When low, the card status change interrupts are routed using bits 7−4 (CSCSELECT field) in the ExCA card status-change interrupt configuration register (ExCA offset 05h/805h, see Section 5.6). This bit is encoded as: 0 = CSC interrupts are routed by ExCA registers (default). 1 = CSC interrupts are routed to PCI interrupts. RW Card interrupt select for I/O PC Card functional interrupts. Bits 3−0 select the interrupt routing for I/O PC Card functional interrupts. This field is encoded as: 0000 = No interrupt routing (default). Functional interrupts are routed to PCI interrupts. This bit setting is ORed with bit 4 (CSCROUTE) for backward compatibility. 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0100 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled 4 3−0 CSCROUTE INTSELECT 5−7 5.5 ExCA Card Status-Change Register The ExCA card status-change register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card functions. The register enables these interrupt sources to generate an interrupt to the host. When the interrupt source is disabled, the corresponding bit in this register always reads 0. When an interrupt source is enabled, the corresponding bit in this register is set to indicate that the interrupt source is active. After generating the interrupt to the host, the interrupt service routine must read this register to determine the source of the interrupt. The interrupt service routine is responsible for resetting the bits in this register as well. Resetting a bit is accomplished by one of two methods: a read of this register or an explicit write back of 1 to the status bit. The choice of these two methods is based on bit 2 (interrupt flag clear mode select) in the ExCA global control register (ExCA offset 1E/81E, see Section 5.20). See Table 5−7 for a complete description of the register contents. Bit 7 6 5 Name 4 3 2 1 0 ExCA card status-change Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: ExCA card status-change CardBus socket address + 804h; ExCA offset 04h Read-only 00h Table 5−7. ExCA Card Status-Change Register Description BIT SIGNAL TYPE 7−4 RSVD R Reserved. Bits 7−4 return 0s when read. R Card detect change. Bit 3 indicates whether a change on the CD1 or CD2 signal occurred at the PC Card interface. This bit is encoded as: 0 = No change detected on either CD1 or CD2 signal 1 = Change detected on either CD1 or CD2 signal 3 2 CDCHANGE READYCHANGE R FUNCTION Ready change. When a 16-bit memory is installed in the signal socket, bit 2 includes whether the source of a PCI4510 interrupt was due to a change on the READY signal at the PC Card interface, indicating that the PC Card is now ready to accept new data. This bit is encoded as: 0 = No low-to-high transition detected on the READY signal (default) 1 = Detected low-to-high transition on the READY signal When a 16-bit I/O card is installed, bit 2 is always 0. 1 BATWARN R Battery warning change. When a 16-bit memory card is installed in the socket, bit 1 indicates whether the source of a PCI4510 interrupt was due to a battery-low warning condition. This bit is encoded as: 0 = No battery warning condition (default) 1 = Detected battery warning condition When a 16-bit I/O card is installed, bit 1 is always 0. 0 BATDEAD R Battery dead or status change. When a 16-bit memory card is installed in the socket, bit 0 indicates whether the source of a PCI4510 interrupt was due to a battery dead condition. This bit is encoded as: 0 = STSCHG signal deasserted (default) 1 = STSCHG signal asserted Ring indicate. When the PCI4510 device is configured for ring indicate operation, bit 0 indicates the status of the RI signal. 5−8 5.6 ExCA Card Status-Change Interrupt Configuration Register The ExCA card status-change interrupt configuration register controls interrupt routing for card status-change interrupts, as well as masking CSC interrupt sources. See Table 5−8 for a complete description of the register contents. Bit 7 6 5 Name Type Default 4 3 2 1 0 ExCA status-change-interrupt configuration RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: ExCA card status-change interrupt configuration CardBus socket address + 805h; ExCA offset 05h Read/Write 00h Table 5−8. ExCA Card Status-Change Interrupt Configuration Register Description BIT SIGNAL TYPE FUNCTION Interrupt select for card status change. Bits 7−4 select the interrupt routing for card status-change interrupts. 0000 = CSC interrupts are routed to PCI interrupts if bit 5 (CSC) of the diagnostic register (PCI offset 93h, see Section 4.38) is set to 1. In this case bit 4 (CSCROUTE) of the ExCA interrupt and general control register (ExCA offset 03h/803h, see Section 5.4) is a don’t care. This is the default setting. 0000 = No ISA interrupt routing if bit 5 (CSC) of the diagnostic register is set to 0 (see Section 4.38). In this case, CSC interrupts are routed to PCI interrupts by setting bit 4 (CSCROUTE) of the ExCA interrupt and general control register (ExCA offset 03h/803h, see Section 5.4) to 1. 7−4 CSCSELECT RW This field is encoded as: 0000 = No interrupt routing (default) 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0110 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled 3 CDEN RW Card detect enable. Bit 3 enables interrupts on CD1 or CD2 changes. This bit is encoded as: 0 = Disables interrupts on CD1 or CD2 line changes (default) 1 = Enables interrupts on CD1 or CD2 line changes 2 READYEN RW Ready enable. Bit 2 enables/disables a low-to-high transition on the PC Card READY signal to generate a host interrupt. This interrupt source is considered a card status change. This bit is encoded as: 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation RW Battery warning enable. Bit 1 enables/disables a battery warning condition to generate a CSC interrupt. This bit is encoded as: 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation RW Battery dead enable. Bit 0 enables/disables a battery dead condition on a memory PC Card or assertion of the STSCHG I/O PC Card signal to generate a CSC interrupt. 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation 1 0 BATWARNEN BATDEADEN 5−9 5.7 ExCA Address Window Enable Register The ExCA address window enable register enables/disables the memory and I/O windows to the 16-bit PC Card. By default, all windows to the card are disabled. The PCI4510 device does not acknowledge PCI memory or I/O cycles to the card if the corresponding enable bit in this register is 0, regardless of the programming of the memory or I/O window start/end/offset address registers. See Table 5−9 for a complete description of the register contents. Bit 7 6 5 Name Type Default 4 3 2 1 0 ExCA address window enable RW RW R RW RW RW RW RW 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: ExCA address window enable CardBus socket address + 806h; ExCA offset 06h Read-only, Read/Write 00h Table 5−9. ExCA Address Window Enable Register Description BIT SIGNAL TYPE 7 IOWIN1EN RW I/O window 1 enable. Bit 7 enables/disables I/O window 1 for the PC Card. This bit is encoded as: 0 = I/O window 1 disabled (default) 1 = I/O window 1 enabled 6 IOWIN0EN RW I/O window 0 enable. Bit 6 enables/disables I/O window 0 for the PC Card. This bit is encoded as: 0 = I/O window 0 disabled (default) 1 = I/O window 0 enabled 5 RSVD R Reserved. Bit 5 returns 0 when read. 4 MEMWIN4EN RW Memory window 4 enable. Bit 4 enables/disables memory window 4 for the PC Card. This bit is encoded as: 0 = Memory window 4 disabled (default) 1 = Memory window 4 enabled 3 MEMWIN3EN RW Memory window 3 enable. Bit 3 enables/disables memory window 3 for the PC Card. This bit is encoded as: 0 = Memory window 3 disabled (default) 1 = Memory window 3 enabled RW Memory window 2 enable. Bit 2 enables/disables memory window 2 for the PC Card. This bit is encoded as: 0 = Memory window 2 disabled (default) 1 = Memory window 2 enabled RW Memory window 1 enable. Bit 1 enables/disables memory window 1 for the PC Card. This bit is encoded as: 0 = Memory window 1 disabled (default) 1 = Memory window 1 enabled RW Memory window 0 enable. Bit 0 enables/disables memory window 0 for the PC Card. This bit is encoded as: 0 = Memory window 0 disabled (default) 1 = Memory window 0 enabled 2 1 0 5−10 FUNCTION MEMWIN2EN MEMWIN1EN MEMWIN0EN 5.8 ExCA I/O Window Control Register The ExCA I/O window control register contains parameters related to I/O window sizing and cycle timing. See Table 5−10 for a complete description of the register contents. Bit 7 6 5 RW RW RW RW 0 0 0 0 Name Type Default 4 3 2 1 0 RW RW RW RW 0 0 0 0 ExCA I/O window control Register: Offset: Type: Default: ExCA I/O window control CardBus socket address + 807h; ExCA offset 07h Read/Write 00h Table 5−10. ExCA I/O Window Control Register Description BIT 7 6 5 4 3 2 SIGNAL WAITSTATE1 ZEROWS1 IOIS16W1 DATASIZE1 WAITSTATE0 ZEROWS0 TYPE FUNCTION RW I/O window 1 wait state. Bit 7 controls the I/O window 1 wait state for 16-bit I/O accesses. Bit 7 has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state. RW I/O window 1 zero wait state. Bit 6 controls the I/O window 1 wait state for 8-bit I/O accesses. Bit 6 has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. RW I/O window 1 IOIS16 source. Bit 5 controls the I/O window 1 automatic data sizing feature that uses the IOIS16 signal from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as: 0 = Window data width is determined by bit 4 (DATASIZE1) (default). 1 = Window data width is determined by the IOIS16 signal. RW I/O window 1 data size. Bit 4 controls the I/O window 1 data size. Bit 4 is ignored if bit 5 (IOIS16W1) is set. This bit is encoded as: 0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits. RW I/O window 0 wait state. Bit 3 controls the I/O window 0 wait state for 16-bit I/O accesses. Bit 3 has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state. RW I/O window 0 zero wait state. Bit 2 controls the I/O window 0 wait state for 8-bit I/O accesses. Bit 2 has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. 1 IOIS16W0 RW I/O window 0 IOIS16 source. Bit 1 controls the I/O window 0 automatic data sizing feature that uses the IOIS16 signal from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as: 0 = Window data width is determined by bit 0 (DATASIZE0) (default). 1 = Window data width is determined by the IOIS16 signal. 0 DATASIZE0 RW I/O window 0 data size. Bit 0 controls the I/O window 0 data size. Bit 0 is ignored if bit 1 (IOIS16W0) is set. This bit is encoded as: 0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits. 5−11 5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the start address. Bit 7 6 Name Type Default 5 4 3 2 1 0 ExCA I/O windows 0 and 1 start-address low-byte RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Register: Offset: Register: Offset: Type: Default: ExCA I/O window 0 start-address low-byte CardBus socket address + 808h; ExCA offset 08h ExCA I/O window 1 start-address low-byte CardBus socket address + 80Ch; ExCA offset 0Ch Read/Write 00h 5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers These registers contain the high byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of these registers correspond to the upper 8 bits of the end address. Bit 7 6 Name Type Default 5 4 3 2 1 0 ExCA I/O windows 0 and 1 start-address high-byte RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Register: Offset: Register: Offset: Type: Default: ExCA I/O window 0 start-address high-byte CardBus socket address + 809h; ExCA offset 09h ExCA I/O window 1 start-address high-byte CardBus socket address + 80Dh; ExCA offset 0Dh Read/write 00h 5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the end address. Bit 7 6 5 RW RW RW RW RW 0 0 0 0 0 Name Type Default 3 2 1 0 RW RW RW 0 0 0 ExCA I/O windows 0 and 1 end-address low-byte Register: Offset: Register: Offset: Type: Default: 5−12 4 ExCA I/O window 0 end-address low-byte CardBus socket address + 80Ah; ExCA offset 0Ah ExCA I/O window 1 end-address low-byte CardBus socket address + 80Eh; ExCA offset 0Eh Read/Write 00h 5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers These registers contain the high byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these registers correspond to the upper 8 bits of the end address. Bit 7 6 Name Type Default 5 4 3 2 1 0 ExCA I/O windows 0 and 1 end-address high-byte RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Register: Offset: Register: Offset: Type: Default: ExCA I/O window 0 end-address high-byte CardBus socket address + 80Bh; ExCA offset 0Bh ExCA I/O window 1 end-address high-byte CardBus socket address + 80Fh; ExCA offset 0Fh Read/write 00h 5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19−A12 of the start address. Bit 7 6 5 RW RW RW RW RW 0 0 0 0 0 Name Type Default 4 3 2 1 0 RW RW RW 0 0 0 ExCA memory windows 0−4 start-address low-byte Register: Offset: Register: Offset: Register: Offset: Register: Offset: Register: Offset: Type: Default: ExCA memory window 0 start-address low-byte CardBus socket address + 810h; ExCA offset 10h ExCA memory window 1 start-address low-byte CardBus socket address + 818h; ExCA offset 18h ExCA memory window 2 start-address low-byte CardBus socket address + 820h; ExCA offset 20h ExCA memory window 3 start-address low-byte CardBus socket address + 828h; ExCA offset 28h ExCA memory window 4 start-address low-byte CardBus socket address + 830h; ExCA offset 30h Read/Write 00h 5−13 5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The lower 4 bits of these registers correspond to bits A23−A20 of the start address. In addition, the memory window data width and wait states are set in this register. See Table 5−11 for a complete description of the register contents. Bit 7 6 Name Type Default 5 4 3 2 1 0 ExCA memory windows 0−4 start-address high-byte RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Register: Offset: Register: Offset: Register: Offset: Register: Offset: Register: Offset: Type: Default: ExCA memory window 0 start-address high-byte CardBus socket address + 811h; ExCA offset 11h ExCA memory window 1 start-address high-byte CardBus socket address + 819h; ExCA offset 19h ExCA memory window 2 start-address high-byte CardBus socket address + 821h; ExCA offset 21h ExCA memory window 3 start-address high-byte CardBus socket address + 829h; ExCA offset 29h ExCA memory window 4 start-address high-byte CardBus socket address + 831h; ExCA offset 31h Read/Write 00h Table 5−11. ExCA Memory Windows 0−4 Start-Address High-Byte Registers Description BIT 7 5−14 SIGNAL DATASIZE TYPE FUNCTION RW Data size. Bit 7 controls the memory window data width. This bit is encoded as: 0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits. 6 ZEROWAIT RW Zero wait state. Bit 6 controls the memory window wait state for 8- and 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 8- and 16-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. 16-bit cycles are reduced to equivalent of two ISA cycles. 5−4 SCRATCH RW Scratch pad bits. Bits 5 and 4 have no effect on memory window operation. 3−0 STAHN RW Start-address high nibble. Bits 3−0 represent the upper address bits A23−A20 of the memory window start address. 5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19−A12 of the end address. Bit 7 6 Name Type Default 5 4 3 2 1 0 ExCA memory windows 0−4 end-address low-byte RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Register: Offset: Register: Offset: Register: Offset: Register: Offset: Register: Offset: Type: Default: ExCA memory window 0 end-address low-byte CardBus socket address + 812h; ExCA offset 12h ExCA memory window 1 end-address low-byte CardBus socket address + 81Ah; ExCA offset 1Ah ExCA memory window 2 end-address low-byte CardBus socket address + 822h; ExCA offset 22h ExCA memory window 3 end-address low-byte CardBus socket address + 82Ah; ExCA offset 2Ah ExCA memory window 4 end-address low-byte CardBus socket address + 832h; ExCA offset 32h Read/Write 00h 5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers These registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The lower 4 bits of these registers correspond to bits A23−A20 of the end address. In addition, the memory window wait states are set in this register. See Table 5−12 for a complete description of the register contents. Bit 7 6 RW RW R R RW 0 0 0 0 0 Name Type Default 5 4 3 2 1 0 RW RW RW 0 0 0 ExCA memory windows 0−4 end-address high-byte Register: Offset: Register: Offset: Register: Offset: Register: Offset: Register: Offset: Type: Default: ExCA memory window 0 end-address high-byte CardBus socket address + 813h; ExCA offset 13h ExCA memory window 1 end-address high-byte CardBus socket address + 81Bh; ExCA offset 1Bh ExCA memory window 2 end-address high-byte CardBus socket address + 823h; ExCA offset 23h ExCA memory window 3 end-address high-byte CardBus socket address + 82Bh; ExCA offset 2Bh ExCA memory window 4 end-address high-byte CardBus socket address + 833h; ExCA offset 33h Read-only, Read/Write 00h Table 5−12. ExCA Memory Windows 0−4 End-Address High-Byte Registers Description BIT SIGNAL TYPE FUNCTION Wait state. Bits 7 and 6 specify the number of equivalent ISA wait states to be added to 16-bit memory accesses. The number of wait states added is equal to the binary value of these two bits. 7−6 MEMWS RW 5−4 RSVD R 3−0 ENDHN RW Reserved. Bits 5 and 4 return 0s when read. End-address high nibble. Bits 3−0 represent the upper address bits A23−A20 of the memory window end address. 5−15 5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers These registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19−A12 of the offset address. Bit 7 6 Name Type Default 4 3 2 1 0 RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Register: Offset: Register: Offset: Register: Offset: Register: Offset: Register: Offset: Type: Default: 5−16 5 ExCA memory windows 0−4 offset-address low-byte ExCA memory window 0 offset-address low-byte CardBus socket address + 814h; ExCA offset 14h ExCA memory window 1 offset-address low-byte CardBus socket address + 81Ch; ExCA offset 1Ch ExCA memory window 2 offset-address low-byte CardBus socket address + 824h; ExCA offset 24h ExCA memory window 3 offset-address low-byte CardBus socket address + 82Ch; ExCA offset 2Ch ExCA memory window 4 offset-address low-byte CardBus socket address + 834h; ExCA offset 34h Read/Write 00h 5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers These registers contain the high 6 bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. The lower 6 bits of these registers correspond to bits A25−A20 of the offset address. In addition, the write protection and common/attribute memory configurations are set in this register. See Table 5−13 for a complete description of the register contents. Bit 7 6 Name Type 5 4 3 2 1 0 ExCA memory windows 0−4 offset-address high-byte RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Default Register: Offset: Register: Offset: Register: Offset: Register: Offset: Register: Offset: Type: Default: ExCA memory window 0 offset-address high-byte CardBus socket address + 815h; ExCA offset 15h ExCA memory window 1 offset-address high-byte CardBus socket address + 81Dh; ExCA offset 1Dh ExCA memory window 2 offset-address high-byte CardBus socket address + 825h; ExCA offset 25h ExCA memory window 3 offset-address high-byte CardBus socket address + 82Dh; ExCA offset 2Dh ExCA memory window 4 offset-address high-byte CardBus socket address + 835h; ExCA offset 35h Read/Write 00h Table 5−13. ExCA Memory Windows 0−4 Offset-Address High-Byte Registers Description BIT 7 SIGNAL WINWP TYPE FUNCTION RW Write protect. Bit 7 specifies whether write operations to this memory window are enabled. This bit is encoded as: 0 = Write operations are allowed (default). 1 = Write operations are not allowed. 6 REG RW Bit 6 specifies whether this memory window is mapped to card attribute or common memory. This bit is encoded as: 0 = Memory window is mapped to common memory (default). 1 = Memory window is mapped to attribute memory. 5−0 OFFHB RW Offset-address high byte. Bits 5−0 represent the upper address bits A25−A20 of the memory window offset address. 5−17 5.19 ExCA Card Detect and General Control Register The ExCA card detect and general control register controls how the ExCA registers for the socket respond to card removal, as well as reports the status of the VS1 and VS2 signals at the PC Card interface. See Table 5−14 for a complete description of the register contents. Bit 7 6 5 Name 4 3 2 1 0 ExCA I/O card detect and general control Type R R RW RW R R RW R Default X X 0 0 0 0 0 0 Register: Offset: Type: Default: ExCA card detect and general control CardBus socket address + 816h; ExCA offset 16h Read-only, Read/Write XX00 0000b Table 5−14. ExCA Card Detect and General Control Register Description BIT SIGNAL TYPE FUNCTION 7 VS2STAT R VS2 state. Bit 7 reports the current state of the VS2 signal at the PC Card interface and, therefore, does not have a default value. 0 = VS2 is low 1 = VS2 is high R VS1 state. Bit 6 reports the current state of the VS1 signal at the PC Card interface and, therefore, does not have a default value. 0 = VS1 is low 1 = VS1 is high RW Software card detect interrupt. If bit 3 (CDEN) in the ExCA card status-change interrupt configuration register (ExCA offset 05h/805, see Section 5.6) is set, then writing a 1 to bit 5 causes a card-detect card-status change interrupt for the associated card socket. If bit 3 (CDEN) in the ExCA card status-change-interrupt configuration register (ExCA offset 05h/805, see Section 5.6) is cleared to 0, then writing a 1 to bit 5 has no effect. A read operation of this bit always returns 0. Card detect resume enable. If bit 4 is set to 1, then once a card detect change has been detected on CD1 and CD2 inputs, the RI_OUT signal goes from high to low. The RI_OUT signal remains low until bit 0 (card status change) in the ExCA card status-change register is cleared (see Section 5.5). If this bit is a 0, then the card detect resume functionality is disabled. 0 = Card detect resume disabled (default) 1 = Card detect resume enabled 6 5 5−18 VS1STAT SWCSC 4 CDRESUME RW 3−2 RSVD R 1 REGCONFIG RW 0 RSVD R Reserved. Bits 3 and 2 return 0s when read. Register configuration on card removal. Bit 1 controls how the ExCA registers for the socket react to a card removal event. This bit is encoded as: 0 = No change to ExCA registers on card removal (default) 1 = Reset ExCA registers on card removal Reserved. Bit 0 returns 0 when read. 5.20 ExCA Global Control Register The ExCA global control register controls both PC Card sockets and is not duplicated for each socket. The host interrupt mode bits in this register are retained for Intel 82365SL-DF compatibility. See Table 5−15 for a complete description of the register contents. Bit 7 6 5 Name 4 3 2 1 0 ExCA global control Type R R R R RW RW RW RW Default 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: ExCA global control CardBus socket address + 81Eh; ExCA offset 1Eh Read-only, Read/Write 00h Table 5−15. ExCA Global Control Register Description BIT SIGNAL TYPE 7−4 RSVD R FUNCTION Reserved. Bits 7−5 return 0s when read. 3 INTMODEA RW Level/edge interrupt mode select. Bit 3 selects the signaling mode for the PCI4510 host interrupt for card interrupts. This bit is encoded as: 0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode. 2 IFCMODE RW Interrupt flag clear mode select. Bit 2 selects the interrupt flag clear mechanism for the flags in the ExCA card status change register (ExCA offset 04h/804h, see Section 5.5). This bit is encoded as: 0 = Interrupt flags are cleared by read of CSC register (default). 1 = Interrupt flags are cleared by explicit writeback of 1. 1 CSCMODE RW Card status change level/edge mode select. Bit 1 selects the signaling mode for the PCI4510 host interrupt for card status changes. This bit is encoded as: 0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode. RW Power-down mode select. When bit 0 is set to 1, the PCI4510 device is in power-down mode. In power-down mode, the PCI4510 card outputs are high-impedance until an active cycle is executed on the card interface. Following an active cycle, the outputs are again high-impedance. The PCI4510 device still receives functional interrupts and/or card status-change interrupts; however, an actual card access is required to wake up the interface. This bit is encoded as: 0 = Power-down mode is disabled (default). 1 = Power-down mode is enabled. 0 PWRDWN 5−19 5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the offset address, and bit 0 is always 0. Bit 7 6 5 RW RW RW RW RW 0 0 0 0 0 Name Type Default 4 3 2 1 0 RW RW R 0 0 0 ExCA I/O windows 0 and 1 offset-address low-byte Register: Offset: Register: Offset: Type: Default: ExCA I/O window 0 offset-address low-byte CardBus socket address + 836h; ExCA offset 36h ExCA I/O window 1 offset-address low-byte CardBus socket address + 838h; ExCA offset 38h Read-only, Read/Write 00h 5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers These registers contain the high byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of these registers correspond to the upper 8 bits of the offset address. Bit 7 6 5 RW RW RW RW RW 0 0 0 0 0 Name Type Default 4 3 2 1 0 RW RW RW 0 0 0 ExCA I/O windows 0 and 1 offset-address high-byte Register: Offset: Register: Offset: Type: Default: ExCA I/O window 0 offset-address high-byte CardBus socket address + 837h; ExCA offset 37h ExCA I/O window 1 offset-address high-byte CardBus socket address + 839h; ExCA offset 39h Read/Write 00h 5.23 ExCA Memory Windows 0−4 Page Registers The upper 8 bits of a 4-byte PCI memory address are compared to the contents of this register when decoding addresses for 16-bit memory windows. Each window has its own page register, all of which default to 00h. By programming this register to a nonzero value, host software can locate 16-bit memory windows in any 1 of 256 16-Mbyte regions in the 4-Gbyte PCI address space. These registers are only accessible when the ExCA registers are memory-mapped; that is, these registers cannot be accessed using the index/data I/O scheme. Bit 7 6 5 RW RW RW RW 0 0 0 0 Name Type Default 3 2 1 0 RW RW RW RW 0 0 0 0 ExCA memory windows 0−4 page Register: Offset: Type: Default: 5−20 4 ExCA memory windows 0−4 page CardBus socket address + 840h, 841h, 842h, 843h, 844h Read-only, Read/Write, Read/Clear 00h 6 CardBus Socket Registers (Function 0) The 1997 PC Card Standard requires a CardBus socket controller to provide five 32-bit registers that report and control socket-specific functions. The PCI4510 device provides the CardBus socket/ExCA base address register (offset 10h, see Section 4.11) to locate these CardBus socket registers in PCI memory address space (see Figure 6−1). Table 6−1 gives the location of the socket registers in relation to the CardBus socket/ExCA base address. The PCI4510 device implements an additional register at offset 20h that provides power management control for the socket. PCI4510 Configuration Registers Offset Host Memory Space Offset 00h CardBus Socket/ExCA Base Address 10h CardBus Socket Registers 20h 800h 16-Bit Legacy-Mode Base Address 44h ExCA Registers 844h Figure 6−1. Accessing CardBus Socket Registers Through PCI Memory Table 6−1. CardBus Socket Registers REGISTER NAME OFFSET Socket event 00h Socket mask 04h Socket present state 08h Socket force event 0Ch Socket control 10h Reserved Socket power management 14h−1Ch 20h 6−1 6.1 Socket Event Register This register indicates a change in socket status has occurred. These bits do not indicate what the change is, only that one has occurred. Software must read the socket present state register (see Section 6.3) for current status. Each bit in this register can be cleared by writing a 1 to that bit. The bits in this register can be set to a 1 by software through writing a 1 to the corresponding bit in the socket force event register (see Section 6.4). All bits in this register are cleared by PCI reset. They can be immediately set again, if, when coming out of PC Card reset, the bridge finds the status unchanged (that is, CSTSCHG reasserted or card detect is still true). Software needs to clear this register before enabling interrupts. If it is not cleared and interrupts are enabled, then an unmasked interrupt is generated based on any bit that is set. See Table 6−2 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 Socket event Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Socket event Type R R R R R R R R R R R R RWC RWC RWC RWC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Socket event CardBus Socket Address + 00h Read-only, Read/Write to Clear 0000 0000h Table 6−2. Socket Event Register Description BIT SIGNAL TYPE 31−4 RSVD R 3 PWREVENT RWC Power cycle. This bit is set when the PCI4510 device detects that bit 3 (PWRCYCLE) in the socket present state register (offset 08h, see Section 6.3) has changed. This bit is cleared by writing a 1. 2 CD2EVENT RWC CCD2. This bit is set when the PCI4510 device detects that bit 2 (CDETECT2) in the socket present state register (offset 08h, see Section 6.3) has changed. This bit is cleared by writing a 1. 1 CD1EVENT RWC CCD1. This bit is set when the PCI4510 device detects that bit 1 (CDETECT1) in the socket present state register (offset 08h, see Section 6.3) has changed. This bit is cleared by writing a 1. RWC CSTSCHG. This bit is set when bit 0 (CARDSTS) in the socket present state register (offset 08h, see Section 6.3) has changed state. For CardBus cards, this bit is set on the rising edge of the CSTSCHG signal. For 16-bit PC Cards, this bit is set on both transitions of the CSTSCHG signal. This bit is reset by writing a 1. 0 6−2 CSTSEVENT FUNCTION These bits return 0s when read. 6.2 Socket Mask Register This register allows software to control the CardBus card events which generate a status change interrupt. The state of these mask bits does not prevent the corresponding bits from reacting in the socket event register (offset 00h, see Section 6.1). See Table 6−3 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 Socket mask Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Socket mask Type R R R R R R R R R R R R RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Socket mask CardBus Socket Address + 04h Read-only, Read/Write 0000 0000h Table 6−3. Socket Mask Register Description BIT SIGNAL TYPE 31−4 RSVD R 3 PWRMASK RW FUNCTION These bits return 0s when read. Power cycle. This bit masks bit 3 (PWRCYCLE) in the socket present state register (offset 08h, see Section 6.3) from causing a status change interrupt. 0 = PWRCYCLE event does not cause a CSC interrupt (default). 1 = PWRCYCLE event causes a CSC interrupt. Card detect mask. These bits mask bits 2 (CDETECT2) and 1 (CDETECT1) in the socket present state register (offset 08h, see Section 6.3) from causing a CSC interrupt. 2−1 0 CDMASK CSTSMASK RW RW 00 = Insertion/removal does not cause a CSC interrupt (default). 01 = Reserved (undefined) 10 = Reserved (undefined) 11 = Insertion/removal causes a CSC interrupt. CSTSCHG mask. This bit masks bit 0 (CARDSTS) in the socket present state register (offset 08h, see Section 6.3) from causing a CSC interrupt. 0 = CARDSTS event does not cause a CSC interrupt (default). 1 = CARDSTS event causes a CSC interrupt. 6−3 6.3 Socket Present State Register This register reports information about the socket interface. Writes to the socket force event register (offset 0Ch, see Section 6.4), as well as general socket interface status, are reflected here. Information about PC Card VCC support and card type is only updated at each insertion. Also note that the PCI4510 device uses the CCD1 and CCD2 signals during card identification, and changes on these signals during this operation are not reflected in this register. Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 Socket present state Type R R R R R R R R R R R R R R R R Default 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Socket present state Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 X 0 0 0 X X X Register: Offset: Type: Default: Socket present state CardBus Socket Address + 08h Read-only 3000 00XXh Table 6−4. Socket Present State Register Description BIT SIGNAL TYPE FUNCTION 31 YVSOCKET R YV socket. This bit indicates whether or not the socket can supply VCC = Y.Y V to PC Cards. The PCI4510 device does not support Y.Y-V VCC; therefore, this bit is always reset unless overridden by the socket force event register (offset 0Ch, see Section 6.4). This bit defaults to 0. 30 XVSOCKET R XV socket. This bit indicates whether or not the socket can supply VCC = X.X V to PC Cards. The PCI4510 device does not support X.X-V VCC; therefore, this bit is always reset unless overridden by the socket force event register (offset 0Ch, see Section 6.4). This bit defaults to 0. 29 3VSOCKET R 3-V socket. This bit indicates whether or not the socket can supply VCC = 3.3 Vdc to PC Cards. The PCI4510 device does support 3.3-V VCC; therefore, this bit is always set unless overridden by the socket force event register (offset 0Ch, see Section 6.4). 28 5VSOCKET R 5-V socket. This bit indicates whether or not the socket can supply VCC = 5 Vdc to PC Cards. The PCI4510 device does support 5-V VCC; therefore, this bit is always set unless overridden by bit 6 of the device control register (PCI offset 92h, see Section 4.37). 27 ZVSUPPORT R Zoomed video support. This bit indicates whether or not the socket has support for zoomed video. 0 = ZV support disabled 1 = ZV support enabled 26−14 RSVD R These bits return 0s when read. 13 YVCARD R YV card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = Y.Y Vdc. This bit can be set by writing a 1 to bit 13 (FYVCARD) in the socket force event register (offset 0Ch, see Section 6.4). 12 XVCARD R XV card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = X.X Vdc. This bit can be set by writing a 1 to bit 12 (FXVCARD) in the socket force event register (offset 0Ch, see Section 6.4). 11 3VCARD R 3-V card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = 3.3 Vdc. This bit can be set by writing a 1 to bit 11 (F3VCARD) in the socket force event register (offset 0Ch, see Section 6.4). 10 5VCARD R 5-V card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = 5 Vdc. This bit can be set by writing a 1 to bit 10 (F5VCARD) in the socket force event register (offset 0Ch, see Section 6.4). 9 6−4 BADVCCREQ R Bad VCC request. This bit indicates that the host software has requested that the socket be powered at an invalid voltage. 0 = Normal operation (default) 1 = Invalid VCC request by host software Table 6−4. Socket Present State Register Description (Continued) BIT 8 7 SIGNAL DATALOST NOTACARD TYPE R R FUNCTION Data lost. This bit indicates that a PC Card removal event may have caused lost data because the cycle did not terminate properly or because write data still resides in the PCI4510 device. 0 = Normal operation (default) 1 = Potential data loss due to card removal Not a card. This bit indicates that an unrecognizable PC Card has been inserted in the socket. This bit is not updated until a valid PC Card is inserted into the socket. 0 = Normal operation (default) 1 = Unrecognizable PC Card detected READY(IREQ)//CINT. This bit indicates the current status of the READY(IREQ)//CINT signal at the PC Card interface. 6 IREQCINT R 5 CBCARD R CardBus card detected. This bit indicates that a CardBus PC Card is inserted in the socket. This bit is not updated until another card interrogation sequence occurs (card insertion). 4 16BITCARD R 16-bit card detected. This bit indicates that a 16-bit PC Card is inserted in the socket. This bit is not updated until another card interrogation sequence occurs (card insertion). 3 PWRCYCLE R 0 = READY(IREQ)//CINT is low. 1 = READY(IREQ)//CINT is high. Power cycle. This bit indicates the status of each card powering request. This bit is encoded as: 2 CDETECT2 R 1 CDETECT1 R 0 CARDSTS R 0 = Socket is powered down (default). 1 = Socket is powered up. CCD2. This bit reflects the current status of the CCD2 signal at the PC Card interface. Changes to this signal during card interrogation are not reflected here. 0 = CCD2 is low (PC Card may be present) 1 = CCD2 is high (PC Card not present) CCD1. This bit reflects the current status of the CCD1 signal at the PC Card interface. Changes to this signal during card interrogation are not reflected here. 0 = CCD1 is low (PC Card may be present). 1 = CCD1 is high (PC Card not present). CSTSCHG. This bit reflects the current status of the CSTSCHG signal at the PC Card interface. 0 = CSTSCHG is low. 1 = CSTSCHG is high. 6.4 Socket Force Event Register This register is used to force changes to the socket event register (offset 00h, see Section 6.1) and the socket present state register (offset 08h, see Section 6.3). Bit 14 (CVSTEST) in this register must be written when forcing changes that require card interrogation. See Table 6−5 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 Socket force event Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Socket force event Type R W W W W W W W W R W W W W W W Default X X X X X X X X X X X X X X X X Register: Offset: Type: Default: Socket force event CardBus Socket Address + 0Ch Read-only, Write-only 0000 XXXXh 6−5 Table 6−5. Socket Force Event Register Description BIT SIGNAL TYPE 31−28 RSVD R These bits return 0s when read. 27 FZVSUPPORT W Force zoomed video support. Writes to this bit cause bit 27 (ZVSUPPORT) in the socket present state register (offset 08h, see Section 6.3) to be written. 26−15 RSVD R These bits return 0s when read. 14 CVSTEST W Card VS test. When this bit is set, the PCI4510 device reinterrogates the PC Card, updates the socket present state register (offset 08h, see Section 6.3), and re-enables the socket power control. 13 FYVCARD W Force YV card. Writes to this bit cause bit 13 (YVCARD) in the socket present state register (offset 08h, see Section 6.3) to be written. When set, this bit disables the socket power control. 12 FXVCARD W Force XV card. Writes to this bit cause bit 12 (XVCARD) in the socket present state register (offset 08h, see Section 6.3) to be written. When set, this bit disables the socket power control. 11 F3VCARD W Force 3-V card. Writes to this bit cause bit 11 (3VCARD) in the socket present state register (offset 08h, see Section 6.3) to be written. When set, this bit disables the socket power control. 10 F5VCARD W Force 5-V card. Writes to this bit cause bit 10 (5VCARD) in the socket present state register (offset 08h, see Section 6.3) to be written. When set, this bit disables the socket power control. 9 FBADVCCREQ W Force BadVccReq. Changes to bit 9 (BADVCCREQ) in the socket present state register (offset 08h, see Section 6.3) can be made by writing this bit. 8 FDATALOST W Force data lost. Writes to this bit cause bit 8 (DATALOST) in the socket present state register (offset 08h, see Section 6.3) to be written. 7 FNOTACARD W Force not a card. Writes to this bit cause bit 7 (NOTACARD) in the socket present state register (offset 08h, see Section 6.3) to be written. 6 RSVD R This bit returns 0 when read. 5 FCBCARD W Force CardBus card. Writes to this bit cause bit 5 (CBCARD) in the socket present state register (offset 08h, see Section 6.3) to be written. 4 F16BITCARD W Force 16-bit card. Writes to this bit cause bit 4 (16BITCARD) in the socket present state register (offset 08h, see Section 6.3) to be written. 3 FPWRCYCLE W Force power cycle. Writes to this bit cause bit 3 (PWREVENT) in the socket event register (offset 00h, see Section 6.1) to be written, and bit 3 (PWRCYCLE) in the socket present state register (offset 08h, see Section 6.3) is unaffected. 2 FCDETECT2 W Force CCD2. Writes to this bit cause bit 2 (CD2EVENT) in the socket event register (offset 00h, see Section 6.1) to be written, and bit 2 (CDETECT2) in the socket present state register (offset 08h, see Section 6.3) is unaffected. 1 FCDETECT1 W Force CCD1. Writes to this bit cause bit 1 (CD1EVENT) in the socket event register (offset 00h, see Section 6.1) to be written, and bit 1 (CDETECT1) in the socket present state register (offset 08h, see Section 6.3) is unaffected. 0 FCARDSTS W Force CSTSCHG. Writes to this bit cause bit 0 (CSTSEVENT) in the socket event register (offset 00h, see Section 6.1) to be written. Bit 0 (CARDSTS) in the socket present state register (offset 08h, see Section 6.3) is unaffected. 6−6 FUNCTION 6.5 Socket Control Register This register provides control of the voltages applied to the socket VPP and VCC. The PCI4510 device ensures that the socket is powered up only at acceptable voltages when a CardBus card is inserted. See Table 6−6 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Socket control Name Socket control Type R R R R R R RW R RW RW RW RW R RW RW RW Default 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Socket control CardBus Socket Address + 10h Read-only, Read/Write 0000 0400h Table 6−6. Socket Control Register Description BIT SIGNAL TYPE 31−12 RSVD R These bits return 0s when read. FUNCTION 11 ZV_ACTIVITY R This bit returns 0 when the ZVEN bits (bit 0) for both sockets are 0 (disabled). If either ZVEN bit is set to 1, then the ZV_ACTIVITY bit returns 1. 10 STANDARDZVREG R Standardized zoomed video register model supported. Because the PCI4510 device supports this register model, this bit is hardwired to 1. 9 ZVEN RW 8 RSVD R Zoomed video enable. This bit enables zoomed video for the socket. These bits return 0s when read. This bit controls how the CardBus clock run state machine decides when to stop the CardBus clock to the CardBus card: 7 STOPCLK RW 0 = The PCI4510 clock run master tries to stop the clock to the CardBus card under the following two conditions: The CardBus interface is idle for eight clocks, and There is a request from the PCI master to stop the PCI clock. 1 = The PCI4510 clock run master tries to stop the clock to the CardBus card under the following condition: The CardBus interface is idle for eight clocks. In summary, if this bit is set to1, then the CardBus controller tries to stop the clock to the CardBus card independent of the PCI clock run signal. The only condition that has to be satisfied in this case is the CardBus interface sampled idle for eight clocks. 6−4 VCCCTRL RW 3 RSVD R 2−0 VPPCTRL RW VCC control. These bits are used to request card VCC changes. 000 = Request power off (default) 100 = Request VCC = X.X V 001 = Reserved 101 = Request VCC = Y.Y V 010 = Request VCC = 5 V 110 = Reserved 011 = Request VCC = 3.3 V 111 = Reserved This bit returns 0 when read. VPP control. These bits are used to request card VPP changes. 000 = Request power off (default) 100 = Request VPP = X.X V 001 = Request VPP = 12 V 101 = Request VPP = Y.Y V 010 = Request VPP = 5 V 110 = Reserved 011 = Request VPP = 3.3 V 111 = Reserved 6−7 6.6 Socket Power Management Register This register provides power management control over the socket through a mechanism for slowing or stopping the clock on the card interface when the card is idle. See Table 6−7 for a complete description of the register contents. Bit 31 30 29 28 27 26 Name 25 24 23 22 21 20 19 18 17 16 Socket power management Type R R R R R R R R R R R R R R R RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Socket power management Type R R R R R R R R R R R R R R R RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Socket power management CardBus Socket Address + 20h Read-only, Read/Write 0000 0000h Table 6−7. Socket Power Management Register Description BIT SIGNAL TYPE 31−26 RSVD R 25 SKTACCES R 24 SKTMODE R 23−17 RSVD R 16 CLKCTRLEN RW 15−1 RSVD R FUNCTION Reserved. These bits return 0s when read. Socket access status. This bit provides information on whether a socket access has occurred. This bit is cleared by a read access. 0 = No PC Card access has occurred (default). 1 = PC Card has been accessed. Socket mode status. This bit provides clock mode information. 0 = Normal clock operation 1 = Clock frequency has changed. These bits return 0s when read. CardBus clock control enable. This bit, when set, enables clock control according to bit 0 (CLKCTRL). 0 6−8 CLKCTRL RW 0 = Clock control disabled (default) 1 = Clock control enabled These bits return 0s when read. CardBus clock control. This bit determines whether the CardBus CLKRUN protocol attempts to stop or slow the CardBus clock during idle states. Bit 16 (CLKCTRLEN) enables this bit. 0 = Allows the CardBus CLKRUN protocol to attempt to stop the CardBus clock (default) 1 = Allows the CardBus CLKRUN protocol to attempt to slow the CardBus clock by a factor of 16 7 OHCI Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI4510 1394 open host controller interface. All registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state for each register. A bit description table, typically included when the register contains bits of more than one type or purpose, indicates bit field names, a detailed field description, and field access tags which appear in the type column. Table 4−1 describes the field access tags. PCI4510 device is a multifunction PCI device. The 1394 OHCI is integrated as PCI function 1. The function 1 configuration header is compliant with the PCI Local Bus Specification as a standard header. Table 7−1 illustrates the configuration header that includes both the predefined portion of the configuration space and the user-definable registers. Table 7−1. Function 1 Configuration Register Map REGISTER NAME OFFSET Device ID Vendor ID 00h Status Command 04h Class code BIST Header type Latency timer Revision ID 08h Cache line size 0Ch OHCI base address 10h TI extension base address 14h CardBus CIS base address 18h Reserved 1Ch−27h CardBus CIS pointer Subsystem ID 28h Subsystem vendor ID Reserved Reserved 30h PCI power management capabilities pointer 34h Interrupt line 3Ch Reserved MAX_LAT MIN_GNT Interrupt pin 38h PCI OHCI control Power management capabilities PM data PMCSR_BSE Next item pointer 2Ch 40h Capability ID Power management control and status 44h 48h Reserved 4Ch−ECh PCI miscellaneous configuration F0h Link enhancement control F4h Subsystem access F8h Reserved FCh 7−1 7.1 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch. Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 Vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 Register: Offset: Type: Default: Vendor ID 00h Read-only 104Ch 7.2 Device ID Register The device ID register contains a value assigned to the PCI4510 device by Texas Instruments. The device identification for the PCI4510 device is 8029h. Bit 15 14 13 12 11 10 9 Type R R R R R R R R Default 1 0 0 0 0 0 0 0 Name 7 6 5 4 3 2 1 0 R R R R R R R R 0 0 1 0 1 0 0 1 Device ID Register: Offset: Type: Default: 7−2 8 Device ID 02h Read-only 8029h 7.3 Command Register The command register provides control over the PCI4510 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 7−2 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 Command Type R R R R R R R RW R RW R RW R RW RW R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Command 04h Read/Write, Read-only 0000h Table 7−2. Command Register Description BIT FIELD NAME TYPE 15−10 RSVD R Reserved. Bits 15−10 return 0s when read. DESCRIPTION 9 FBB_ENB R Fast back-to-back enable. The PCI4510 device does not generate fast back-to-back transactions; therefore, bit 9 returns 0 when read. 8 SERR_ENB RW SERR enable. When bit 8 is set to 1, the PCI4510 SERR driver is enabled. SERR can be asserted after detecting an address parity error on the PCI bus. 7 STEP_ENB R Address/data stepping control. The PCI4510 device does not support address/data stepping; therefore, bit 7 is hardwired to 0. 6 PERR_ENB RW Parity error enable. When bit 6 is set to 1, the PCI4510 device is enabled to drive PERR response to parity errors through the PERR signal. 5 VGA_ENB R VGA palette snoop enable. The PCI4510 device does not feature VGA palette snooping; therefore, bit 5 returns 0 when read. 4 MWI_ENB RW Memory write and invalidate enable. When bit 4 is set to 1, the PCI4510 device is enabled to generate MWI PCI bus commands. If this bit is cleared, then the PCI4510 device generates memory write commands instead. 3 SPECIAL R Special cycle enable. The PCI4510 function does not respond to special cycle transactions; therefore, bit 3 returns 0 when read. 2 MASTER_ENB RW Bus master enable. When bit 2 is set to 1, the PCI4510 device is enabled to initiate cycles on the PCI bus. 1 MEMORY_ENB RW Memory response enable. Setting bit 1 to 1 enables the PCI4510 device to respond to memory cycles on the PCI bus. This bit must be set to access OHCI registers. 0 IO_ENB R I/O space enable. The PCI4510 device does not implement any I/O-mapped functionality; therefore, bit 0 returns 0 when read. 7−3 7.4 Status Register The status register provides status over the PCI4510 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 7−3 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 Name Type Default 7 6 5 4 3 2 1 0 Status RCU RCU RCU RCU RCU R R RCU R R R R R R R R 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Register: Offset: Type: Default: Status 06h Read/Clear/Update, Read-only 0210h Table 7−3. Status Register Description BIT FIELD NAME TYPE DESCRIPTION 15 PAR_ERR RCU Detected parity error. Bit 15 is set to 1 when either an address parity or data parity error is detected. 14 SYS_ERR RCU Signaled system error. Bit 14 is set to 1 when SERR is enabled and the PCI4510 device has signaled a system error to the host. 13 MABORT RCU Received master abort. Bit 13 is set to 1 when a cycle initiated by the PCI4510 device on the PCI bus has been terminated by a master abort. 12 TABORT_REC RCU Received target abort. Bit 12 is set to 1 when a cycle initiated by the PCI4510 device on the PCI bus was terminated by a target abort. 11 TABORT_SIG RCU Signaled target abort. Bit 11 is set to 1 by the PCI4510 device when it terminates a transaction on the PCI bus with a target abort. 10−9 PCI_SPEED R DEVSEL timing. Bits 10 and 9 encode the timing of DEVSEL and are hardwired to 01b, indicating that the PCI4510 device asserts this signal at a medium speed on nonconfiguration cycle accesses. 8 DATAPAR RCU Data parity error detected. Bit 8 is set to 1 when the following conditions have been met: a. PERR was asserted by any PCI device including the PCI4510 device. b. The PCI4510 device was the bus master during the data parity error. c. Bit 6 (PERR_EN) in the command register at offset 04h in the PCI configuration space (see Section 7.3) is set to 1. 7−4 7 FBB_CAP R Fast back-to-back capable. The PCI4510 device cannot accept fast back-to-back transactions; therefore, bit 7 is hardwired to 0. 6 UDF R User-definable features (UDF) supported. The PCI4510 device does not support the UDF; therefore, bit 6 is hardwired to 0. 5 66MHZ R 66-MHz capable. The PCI4510 device operates at a maximum PCLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0. 4 CAPLIST R Capabilities list. Bit 4 returns 1 when read, indicating that capabilities additional to standard PCI are implemented. The linked list of PCI power-management capabilities is implemented in this function. 3−0 RSVD R Reserved. Bits 3−0 return 0s when read. 7.5 Class Code and Revision ID Register The class code and revision ID register categorizes the PCI4510 device as a serial bus controller (0Ch), controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the least significant byte. See Table 7−4 for a complete description of the register contents. Bit 31 30 29 28 27 26 R R R R R R R R R Name Type 25 24 23 22 21 20 19 18 17 16 R R R R R R R Class code and revision ID Default 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Type R R R R R R R R R R R R R R R R Default 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Name Class code and revision ID Register: Offset: Type: Default: Class code and revision ID 08h Read-only 0C00 1000h Table 7−4. Class Code and Revision ID Register Description BIT FIELD NAME TYPE DESCRIPTION 31−24 BASECLASS R Base class. This field returns 0Ch when read, which broadly classifies the function as a serial bus controller. 23−16 SUBCLASS R Subclass. This field returns 00h when read, which specifically classifies the function as controlling an IEEE 1394 serial bus. 15−8 PGMIF R Programming interface. This field returns 10h when read, which indicates that the programming model is compliant with the 1394 Open Host Controller Interface Specification. 7−0 CHIPREV R Silicon revision. This field returns 00h when read, which indicates the silicon revision of the PCI4510 device. 7.6 Latency Timer and Class Cache Line Size Register The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the PCI4510 device. See Table 7−5 for a complete description of the register contents. Bit 15 14 13 12 11 10 RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 Name Type Default 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW 0 0 0 0 0 0 0 Latency timer and class cache line size Register: Offset: Type: Default: Latency timer and class cache line size 0Ch Read/Write 0000h Table 7−5. Latency Timer and Class Cache Line Size Register Description BIT FIELD NAME TYPE DESCRIPTION 15−8 LATENCY_TIMER RW PCI latency timer. The value in this register specifies the latency timer for the PCI4510 device, in units of PCI clock cycles. When the PCI4510 device is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires before the PCI4510 transaction has terminated, then the PCI4510 device terminates the transaction when its GNT is deasserted. 7−0 CACHELINE_SZ RW Cache line size. This value is used by the PCI4510 device during memory write and invalidate, memory-read line, and memory-read multiple transactions. 7−5 7.7 Header Type and BIST Register The header type and built-in self-test (BIST) register indicates the PCI4510 PCI header type and no built-in self-test. See Table 7−6 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 Header type and BIST Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Header type and BIST 0Eh Read-only 0000h Table 7−6. Header Type and BIST Register Description BIT FIELD NAME TYPE DESCRIPTION 15−8 BIST R Built-in self-test. The PCI4510 device does not include a BIST; therefore, this field returns 00h when read. 7−0 HEADER_TYPE R PCI header type. The PCI4510 device includes the standard PCI header, which is communicated by returning 00h when this field is read. 7.8 OHCI Base Address Register The OHCI base address register is programmed with a base address referencing the memory-mapped OHCI control. When BIOS writes all 1s to this register, the value read back is FFFF F800h, indicating that at least 2K bytes of memory address space are required for the OHCI registers. See Table 7−7 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 RW RW RW RW RW RW RW RW Name Type 24 23 22 21 20 19 18 17 16 RW RW RW RW RW RW RW RW OHCI base address Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name Type Default OHCI base address Register: Offset: Type: Default: OHCI base address 10h Read/Write, Read-only 0000 0000h Table 7−7. OHCI Base Address Register Description BIT FIELD NAME TYPE DESCRIPTION 31−11 OHCIREG_PTR RW OHCI register pointer. This field specifies the upper 21 bits of the 32-bit OHCI base address register. 10−4 OHCI_SZ R OHCI register size. This field returns 0s when read, indicating that the OHCI registers require a 2K-byte region of memory. 3 OHCI_PF R OHCI register prefetch. Bit 3 returns 0 when read, indicating that the OHCI registers are nonprefetchable. 2−1 OHCI_MEMTYPE R OHCI memory type. This field returns 0s when read, indicating that the OHCI base address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. 0 OHCI_MEM R OHCI memory indicator. Bit 0 returns 0 when read, indicating that the OHCI registers are mapped into system memory space. 7−6 7.9 TI Extension Base Address Register The TI extension base address register is programmed with a base address referencing the memory-mapped TI extension registers. When BIOS writes all 1s to this register, the value read back is FFFF C000h, indicating that at least 16K bytes of memory address space are required for the TI registers. See Table 7−8 for a complete description of the register contents. Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 TI extension base address RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default TI extension base address RW RW R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: TI extension base address 14h Read/Write, Read-only 0000 0000h Table 7−8. TI Base Address Register Description BIT FIELD NAME TYPE 31−14 TIREG_PTR RW DESCRIPTION 13−4 TI_SZ R TI register size. This field returns 0s when read, indicating that the TI registers require a 16K-byte region of memory. TI register pointer. This field specifies the upper 18 bits of the 32-bit TI base address register. 3 TI_PF R TI register prefetch. Bit 3 returns 0 when read, indicating that the TI registers are nonprefetchable. 2−1 TI_MEMTYPE R TI memory type. This field returns 0s when read, indicating that the TI base address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. 0 TI_MEM R TI memory indicator. Bit 0 returns 0 when read, indicating that the TI registers are mapped into system memory space. 7.10 CardBus CIS Base Address Register This register returns 0s when read because the 1394 function is not implemented as a CadBus device. Bit 31 30 29 28 27 26 Name 25 24 23 22 21 20 19 18 17 16 CardBus CIS base address Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CardBus CIS base address Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: CardBus CIS base address 18h Read-only 0000 0000h 7−7 7.11 CardBus CIS Pointer Register This register returns 0s when read because the 1394 function is not implemented as a CadBus device. Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 CardBus CIS pointer Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CardBus CIS pointer Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: CardBus CIS pointer 28h Read-only 0000 0000h 7.12 Subsystem Identification Register The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCI configuration space (see Section 7.25). See Table 7−9 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 RU RU RU RU RU RU RU RU RU Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name Type Default 23 22 21 20 19 18 17 16 RU RU RU RU RU RU RU 0 0 0 0 0 0 0 6 5 4 3 2 1 0 Subsystem identification Name Type 24 Subsystem identification RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Subsystem identification 2Ch Read/Update 0000 0000h Table 7−9. Subsystem Identification Register Description BIT FIELD NAME TYPE 31−16 OHCI_SSID RU Subsystem device ID. This field indicates the subsystem device ID. 15−0 OHCI_SSVID RU Subsystem vendor ID. This field indicates the subsystem vendor ID. 7−8 DESCRIPTION 7.13 Power Management Capabilities Pointer Register The power management capabilities pointer register provides a pointer into the PCI configuration header where the power-management register block resides. The PCI4510 configuration header doublewords at offsets 44h and 48h provide the power-management registers. This register is read-only and returns 44h when read. Bit 7 6 5 Name 4 3 2 1 0 Power management capabilities pointer Type R R R R R R R R Default 0 1 0 0 0 1 0 0 Register: Offset: Type: Default: Power management capabilities pointer 34h Read-only 44h 7.14 Interrupt Line Register The interrupt line register communicates interrupt line routing information. See Table 7−10 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Name Type Default Interrupt line Register: Offset: Type: Default: Interrupt line 3Ch Read/Write 00h Table 7−10. Interrupt Line Register Description BIT FIELD NAME TYPE DESCRIPTION 7−0 INTR_LINE RW Interrupt line. This field is programmed by the system and indicates to software which interrupt line the PCI4510 PCI_INTA is connected to. 7−9 7.15 Interrupt Pin Register The value read from this register is function dependent, and depends on interrupt tie bit 29 (INTRTIE) in the system control register (Function 0, PCI offset 80h, see Section 4.28). INTRTIE is compatible with other TI CardBus controllers and ties INTA to INTB internally. The internal interrupt connections set by INTRTIE are communicated to host software through this standard register interface. Refer to Table 7−11 for a complete description of the register contents. Bit 7 6 5 4 Name 3 2 1 0 Interrupt pin Type R R R R R R R R Default 0 0 0 0 0 0 1 0 Register: Offset: Type: Default: Interrupt pin 3Dh Read-only 02h Table 7−11. PCI Interrupt Pin Register—Read-Only INTPIN Per Function INTRTIE BIT INTPIN FUNCTION 0 (CARDBUS) INTPIN FUNCTION 1 (1394 OHCI) 0 01h (INTA) 02h (INTB) 1 01h (INTA) 01h (INTA) † When configuring the PCI4510 functions to share PCI interrupts, multifunction terminal MFUNC3 must be configured as IRQSER prior to setting the INTRTIE bit. 7.16 MIN_GNT and MAX_LAT Register The MIN_GNT and MAX_LAT register communicates to the system the desired setting of bits 15−8 in the latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see Section 7.6). If a serial EEPROM is detected, then the contents of this register are loaded through the serial EEPROM interface after a GRST. If no serial EEPROM is detected, then this register returns a default value that corresponds to the MAX_LAT = 4, MIN_GNT = 2. See Table 7−12 for a complete description of the register contents. Bit 15 14 13 12 11 10 Name Type Default 9 8 7 6 5 4 3 2 1 0 MIN_GNT and MAX_LAT RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 Register: Offset: Type: Default: MIN_GNT and MAX_LAT 3Eh Read/Update 0402h Table 7−12. MIN_GNT and MAX_LAT Register Description BIT FIELD NAME TYPE DESCRIPTION 15−8 MAX_LAT RU Maximum latency. The contents of this field may be used by host BIOS to assign an arbitration priority level to the PCI4510 device. The default for this register indicates that the PCI4510 device may need to access the PCI bus as often as every 0.25 µs; thus, an extremely high priority level is requested. The contents of this field may also be loaded through the serial EEPROM. 7−0 MIN_GNT RU Minimum grant. The contents of this field may be used by host BIOS to assign a latency timer register value to the PCI4510 device. The default for this register indicates that the PCI4510 device may need to sustain burst transfers for nearly 64 µs and thus request a large value be programmed in bits 15−8 of the PCI4510 latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see Section 7.6). 7−10 7.17 OHCI Control Register The PCI OHCI control register is defined by the 1394 Open Host Controller Interface Specification and provides a bit for big endian PCI support. See Table 7−13 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 OHCI control Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name OHCI control Type R R R R R R R R R R R R R R R RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: OHCI control 40h Read/Write, Read-only 0000 0000h Table 7−13. OHCI Control Register Description BIT FIELD NAME TYPE 31−1 RSVD R 0 GLOBAL_SWAP RW DESCRIPTION Reserved. Bits 31−1 return 0s when read. When bit 0 is set to 1, all quadlets read from and written to the PCI interface are byte-swapped (big endian). 7.18 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item. See Table 7−14 for a complete description of the register contents. Bit 15 14 13 12 11 10 Name 9 8 7 6 5 4 3 2 1 0 Capability ID and next item pointer Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Register: Offset: Type: Default: Capability ID and next item pointer 44h Read-only 0001h Table 7−14. Capability ID and Next Item Pointer Registers Description BIT FIELD NAME TYPE DESCRIPTION 15−8 NEXT_ITEM R Next item pointer. The PCI4510 device supports only one additional capability that is communicated to the system through the extended capabilities list; therefore, this field returns 00h when read. 7−0 CAPABILITY_ID R Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI SIG for PCI power-management capability. 7−11 7.19 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the PCI4510 device related to PCI power management. See Table 7−15 for a complete description of the register contents. Bit 15 14 13 12 11 10 Name Type Default 9 8 7 6 5 4 3 2 1 0 Power management capabilities RU R R R R R R R R R R R R R R R 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 Register: Offset: Type: Default: Power management capabilities 46h Read/Update, Read-only 7E02h Table 7−15. Power Management Capabilities Register Description BIT FIELD NAME TYPE DESCRIPTION 15 PME_D3COLD RU PME support from D3cold. This bit can be set to 1 or cleared to 0 via bit 15 (PME_D3COLD) in the PCI miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 7.23). The PCI miscellaneous configuration register is loaded from ROM. When this bit is set to 1, it indicates that the PCI4510 device is capable of generating a PME wake event from D3cold. This bit state is dependent upon the PCI4510 VAUX implementation and may be configured by using bit 15 (PME_D3COLD) in the PCI miscellaneous configuration register (see Section 7.23). 14−11 PME_SUPPORT R PME support. This 4-bit field indicates the power states from which the PCI4510 device may assert PME. This field returns a value of 1111b by default, indicating that PME may be asserted from the D3hot, D2, D1, and D0 power states. 10 D2_SUPPORT R D2 support. Bit 10 is hardwired to 1, indicating that the PCI4510 device supports the D2 power state. 9 D1_SUPPORT R D1 support. Bit 9 is hardwired to 1, indicating that the PCI4510 device supports the D1 power state. 8−6 AUX_CURRENT R Auxiliary current. This 3-bit field reports the 3.3-VAUX auxiliary current requirements. When bit 15 (PME_D3COLD) is cleared, this field returns 000b; otherwise, it returns 001b. 000b = Self-powered 001b = 55 mA (3.3-VAUX maximum current required) 7−12 5 DSI R Device-specific initialization. This bit returns 0 when read, indicating that the PCI4510 device does not require special initialization beyond the standard PCI configuration header before a generic class driver is able to use it. 4 RSVD R Reserved. Bit 4 returns 0 when read. 3 PME_CLK R PME clock. This bit returns 0 when read, indicating that no host bus clock is required for the PCI4510 device to generate PME. 2−0 PM_VERSION R Power-management version. This field returns 010b when read, indicating that the PCI4510 device is compatible with the registers described in the PCI Bus Power Management Interface Specification (Revision 1.1). 7.20 Power Management Control and Status Register The power management control and status register implements the control and status of the PCI power-management function. This register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See Table 7−16 for a complete description of the register contents. Bit 15 14 13 12 11 10 RWC R R R R R R RW R 0 0 0 0 0 0 0 0 0 Name Type Default 9 8 7 6 5 4 3 2 1 0 R R R R R RW RW 0 0 0 0 0 0 0 Power management control and status Register: Offset: Type: Default: Power management control and status 48h Read/Clear, Read/Write, Read-only 0000h Table 7−16. Power Management Control and Status Register Description BIT FIELD NAME TYPE DESCRIPTION 15 PME_STS RWC Bit 15 is set to 1 when the PCI4510 device normally asserts the PME signal independent of the state of bit 8 (PME_ENB). This bit is cleared by a writeback of 1, which also clears the PME signal driven by the PCI4510 device. Writing a 0 to this bit has no effect. 14−13 DATA_SCALE R This field returns 0s, because the data register is not implemented. 12−9 DATA_SELECT R This field returns 0s, because the data register is not implemented. 8 PME_ENB RW 7−2 RSVD R 1−0 PWR_STATE RW When bit 8 is set to 1, PME assertion is enabled. When bit 8 is cleared, PME assertion is disabled. This bit defaults to 0 if the function does not support PME generation from D3cold. If the function supports PME from D3cold, then this bit is sticky and must be explicitly cleared by the operating system each time it is initially loaded. Reserved. Bits 7−2 return 0s when read. Power state. This 2-bit field sets the PCI4510 device power state and is encoded as follows: 00 = Current power state is D0. 01 = Current power state is D1. 10 = Current power state is D2. 11 = Current power state is D3. 7.21 Power Management Extension Registers The power management extension register provides extended power-management features not applicable to the PCI4510 device; thus, it is read-only and returns 0 when read. See Table 7−17 for a complete description of the register contents. Bit 15 14 13 12 11 10 Type R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 Name 9 8 7 6 5 4 3 2 1 0 R R R R R R R 0 0 0 0 0 0 0 Power management extension Register: Offset: Type: Default: Power management extension 4Ah Read-only 0000h Table 7−17. Power Management Extension Registers Description BIT FIELD NAME TYPE 15−0 RSVD R DESCRIPTION Reserved. Bits 15−0 return 0s when read. 7−13 7.22 PCI PHY Control Register The PCI PHY control register provides a method for enabling the PHY CNA output. See Table 7−18 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 PCI PHY control Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name PCI PHY control Type R R R R R R R R RW R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Register: Offset: Type: Default: PCI PHY control ECh Read/Write, Read-only 0000 0008h Table 7−18. PCI PHY Control Register 7−14 BIT FIELD NAME TYPE 31−8 RSVD R DESCRIPTION 7 CNAOUT RW When bit 7 is set to 1, the PHY CNA output is routed to terminal 96. When implementing a serial EEPROM, this bit can be set by programming bit 7 of offset 16h in the EEPROM to 1. See Table 3−5, EEPROM Loading Map. 6−4 RSVD R Reserved. Bits 6−4 return 0s when read. These bits are affected when implementing a serial EEPROM; thus, bits 6−4 at EEPROM byte offset 16h must be programmed to 0. See Table 3−5, EEPROM Loading Map. 3 RSVD R Reserved. Bit 3 defaults to 1 to indicate compliance with IEEE Std 1394a-2000. If a serial EEPROM is implemented, then bit 3 at EEPROM byte offset 16h must be set to 1. See Table 3−5, EEPROM Loading Map. 2−0 RSVD R Reserved. Bits 2−0 return 0s when read. These bits are affected when implementing a serial EEPROM; thus, bits 2−0 at EEPROM byte offset 16h must be programmed to 0. See Table 3−5, EEPROM Loading Map. Reserved. Bits 31−8 return 0s when read. 7.23 PCI Miscellaneous Configuration Register The PCI miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 7−19 for a complete description of the register contents. Bit 31 30 29 28 27 26 Type R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name Default 24 23 22 21 20 19 18 17 16 R R R R R R R 0 0 0 0 0 0 0 6 5 4 3 2 1 0 Miscellaneous configuration Name Type 25 Miscellaneous configuration RW R RW R R RW RW RW R R R RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Miscellaneous configuration F0h Read/Write, Read-only 0000 0000h Table 7−19. Miscellaneous Configuration Register BIT FIELD NAME TYPE 31−16 RSVD R 15 PME_D3COLD RW 14−11 RSVD R 10 ignore_mstrIntEna _for_pme RW DESCRIPTION Reserved. Bits 31−16 return 0s when read. PME support from D3cold. This bit programs bit 15 (PME_D3COLD) in the power management capabilities register at offset 46h in the PCI configuration space (see Section 7.19). Reserved. Bits 14−11 return 0s when read. Ignore IntMask.msterIntEnable bit for PME generation. When set, this bit causes the PME generation behavior to be changed as described in Section 3.8. When set, this bit also causes bit 26 of the OHCI vendor ID register at OHCI offset 40h (see Section 8.15) to read 1, otherwise, bit 26 reads 0. 0 = PME behavior generated from unmasked interrupt bits and IntMask.masterIntEnable bit (default) 1 = PME generation does not depend on the value of IntMask.masterIntEnable 9−8 MR_ENHANCE RW This field selects the read command behavior of the PCI master for read transactions of greater than two data phases. For read transactions of one or two data phases, a memory read command is used. The default of this field is 00. This register is loaded by the serial EEPROM word 12, bits 1−0. 00 = Memory read line (default) 01 = Memory read 7−5 RSVD R 4 DIS_TGT_ABT RW 10 = Memory read multiple 11 = Reserved, behavior reverts to default Reserved. Bits 7−5 return 0s when read. Bit 4 defaults to 0, which provides OHCI-Lynx compatible target abort signaling. When this bit is set to 1, it enables the no-target-abort mode, in which the PCI4510 device returns indeterminate data instead of signaling target abort. The PCI4510 LLC is divided into the PCLK and SCLK domains. If software tries to access registers in the link that are not active because the SCLK is disabled, then a target abort is issued by the link. On some systems, this can cause a problem resulting in a fatal system error. Enabling this bit allows the link to respond to these types of requests by returning FFh. It is recommended that this bit be set to 1. 3 GP2IIC RW When bit 3 is set to 1, the GPIO3 and GPIO2 signals are internally routed to the SCL and SDA, respectively. The GPIO3 and GPIO2 terminals are also placed in the high-impedance state. 2 DISABLE_ SCLKGATE RW When bit 2 is set to 1, the internal SCLK runs identically with the chip input. This is a test feature only and must be cleared to 0 (all applications). 1 DISABLE_ PCIGATE RW When bit 1 is set to 1, the internal PCI clock runs identically with the chip input. This is a test feature only and must be cleared to 0 (all applications). 0 KEEP_PCLK RW When bit 0 is set to 1, the PCI clock is always kept running through the CLKRUN protocol. When this bit is cleared, the PCI clock can be stopped using CLKRUN on MFUNC6. 7−15 7.24 Link Enhancement Control Register The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial EEPROM, if present. After these bits are set to 1, their functionality is enabled only if bit 22 (aPhyEnhanceEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. See Table 7−20 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 Type R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name Default 23 22 21 20 19 18 17 16 R R R R R R R 0 0 0 0 0 0 0 6 5 4 3 2 1 0 Link enhancement control Name Type 24 Link enhancement control RW R RW RW R RW R RW RW R R R R R RW R 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Link enhancement control F4h Read/Write, Read-only 0000 1000h Table 7−20. Link Enhancement Control Register Description BIT FIELD NAME TYPE 31−16 RSVD R 15 dis_at_pipeline RW 14 RSVD R 13−12 atx_thresh RW DESCRIPTION Reserved. Bits 31−16 return 0s when read. Disable AT pipelining. When bit 15 is set to 1, out-of-order AT pipelining is disabled. Reserved. This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the PCI4510 device retries the packet, it uses a 2K-byte threshold, resulting in a store-and-forward operation. 00 = Threshold ~ 2K bytes resulting in a store-and-forward operation 01 = Threshold ~ 1.7K bytes (default) 10 = Threshold ~ 1K bytes 11 = Threshold ~ 512 bytes These bits fine-tune the asynchronous transmit threshold. For most applications the 1.7K-byte threshold is optimal. Changing this value may increase or decrease the 1394 latency depending on the average PCI bus latency. Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than the AT threshold, then the remaining data must be received before the AT FIFO is emptied; otherwise, an underrun condition occurs, resulting in a packet error at the receiving node. As a result, the link then commences store-and-forward operation. Wait until it has the complete packet in the FIFO before retransmitting it on the second attempt to ensure delivery. An AT threshold of 2K results in store-and-forward operation, which means that asynchronous data will not be transmitted until an end-of-packet token is received. Restated, setting the AT threshold to 2K results in only complete packets being transmitted. Note that this device will always use store-and-forward when the asynchronous transmit retries register at OHCI offset 08h (see Section 8.3) is cleared. 7−16 11 RSVD R 10 enab_mpeg_ts RW Reserved. Bit 11 returns 0 when read. Enable MPEG CIP timestamp enhancement. When bit 9 is set to 1, the enhancement is enabled for MPEG CIP transmit streams (FMT = 20h). 9 RSVD R 8 enab_dv_ts RW Reserved. Bit 9 returns 0 when read. Enable DV CIP timestamp enhancement. When bit 8 is set to 1, the enhancement is enabled for DV CIP transmit streams (FMT = 00h). 7 enab_unfair RW Enable asynchronous priority requests. OHCI-Lynx compatible. Setting bit 7 to 1 enables the link to respond to requests with priority arbitration. It is recommended that this bit be set to 1. Table 7−20. Link Enhancement Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 6 RSVD R This bit is not assigned in the PCI4510 follow-on products, because this bit location loaded by the serial EEPROM from the enhancements field corresponds to bit 23 (programPhyEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16). Reserved. Bits 5−2 return 0s when read. 5−2 RSVD R 1 enab_accel RW 0 RSVD R Enable acceleration enhancements. OHCI-Lynx compatible. When bit 1 is set to 1, the PHY layer is notified that the link supports the IEEE Std 1394a-2000 acceleration enhancements, that is, ack-accelerated, fly-by concatenation, etc. It is recommended that this bit be set to 1. Reserved. Bit 0 returns 0 when read. 7.25 Subsystem Access Register Write access to the subsystem access register updates the subsystem identification registers identically to OHCI-Lynx. The system ID value written to this register may also be read back from this register. See Table 7−21 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name Type Default 23 22 21 20 19 18 17 16 RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Subsystem access Name Type 24 Subsystem access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Subsystem access F8h Read/Write 0000 0000h Table 7−21. Subsystem Access Register Description BIT FIELD NAME TYPE 31−16 SUBDEV_ID RW Subsystem device ID alias. This field indicates the subsystem device ID. DESCRIPTION 15−0 SUBVEN_ID RW Subsystem vendor ID alias. This field indicates the subsystem vendor ID. 7−17 7−18 8 OHCI Registers The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a 2K-byte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see Section 7.8). These registers are the primary interface for controlling the PCI4510 IEEE 1394 link function. This section provides the register interface and bit descriptions. Several set/clear register pairs in this programming model are implemented to solve various issues with typical read-modify-write control registers. There are two addresses for a set/clear register: RegisterSet and RegisterClear. See Table 8−1 for a register listing. A 1 bit written to RegisterSet causes the corresponding bit in the set/clear register to be set to 1; a 0 bit leaves the corresponding bit unaffected. A 1 bit written to RegisterClear causes the corresponding bit in the set/clear register to be cleared; a 0 bit leaves the corresponding bit in the set/clear register unaffected. Typically, a read from either RegisterSet or RegisterClear returns the contents of the set or clear register, respectively. However, sometimes reading the RegisterClear provides a masked version of the set or clear register. The interrupt event register is an example of this behavior. Table 8−1. OHCI Register Map DMA CONTEXT — REGISTER NAME ABBREVIATION OFFSET OHCI version Version 00h GUID ROM GUID_ROM 04h Asynchronous transmit retries ATRetries 08h CSR data CSRData 0Ch CSR compare CSRCompareData 10h CSR control CSRControl 14h Configuration ROM header ConfigROMhdr 18h Bus identification BusID 1Ch Bus options BusOptions 20h GUID high GUIDHi 24h GUID low GUIDLo 28h Reserved — Configuration ROM mapping ConfigROMmap 34h Posted write address low PostedWriteAddressLo 38h Posted write address high PostedWriteAddressHi 3Ch Vendor ID VendorID 40h Reserved — Host controller control Reserved 2Ch−30h 44h−4Ch HCControlSet 50h HCControlClr 54h — 58h−5Ch 8−1 Table 8−1. OHCI Register Map (Continued) DMA CONTEXT Self-ID REGISTER NAME OFFSET — 60h Self-ID buffer pointer SelfIDBuffer 64h Self-ID count SelfIDCount 68h Reserved — 6Ch IRChannelMaskHiSet 70h IRChannelMaskHiClear 74h IRChannelMaskLoSet 78h IRChannelMaskLoClear 7Ch IntEventSet 80h IntEventClear 84h — Isochronous receive channel mask high Isochronous receive channel mask low Interrupt event Interrupt mask Isochronous transmit interrupt event Isochronous transmit interrupt mask — Isochronous receive interrupt event IntMaskSet 88h IntMaskClear 8Ch IsoXmitIntEventSet 90h IsoXmitIntEventClear 94h IsoXmitIntMaskSet 98h IsoXmitIntMaskClear 9Ch IsoRecvIntEventSet A0h IsoRecvIntEventClear A4h IsoRecvIntMaskSet A8h IsoRecvIntMaskClear ACh Initial bandwidth available InitialBandwidthAvailable B0h Initial channels available high InitialChannelsAvailableHi B4h Initial channels available low InitialChannelsAvailableLo B8h Reserved — Fairness control FairnessControl DCh LinkControlSet E0h LinkControlClear E4h Isochronous receive interrupt mask Link control BCh−D8h Node identification NodeID E8h PHY layer control PhyControl ECh Isochronous cycle timer Isocyctimer Reserved — Asynchronous request filter high Asynchronous request filter low Physical request filter high Physical request filter low 8−2 ABBREVIATION Reserved F0h F4h−FCh AsyncRequestFilterHiSet 100h AsyncRequestFilterHiClear 104h AsyncRequestFilterLoSet 108h AsyncRequestFilterLoClear 10Ch PhysicalRequestFilterHiSet 110h PhysicalRequestFilterHiClear 114h PhysicalRequestFilterLoSet 118h PhysicalRequestFilterLoClear 11Ch Physical upper bound PhysicalUpperBound Reserved — 120h 124h−17Ch Table 8−1. OHCI Register Map (Continued) DMA CONTEXT Asynchronous Request Transmit [ ATRQ ] Asynchronous Response Transmit [ ATRS ] Asynchronous Request Receive [ ARRQ ] Asynchronous Response Receive [ ARRS ] REGISTER NAME Asynchronous context control Transmit Context n n = 0, 1, 2, 3, …, 7 184h — 188h CommandPtr 18Ch Reserved — Asynchronous context control 190h−19Ch ContextControlSet 1A0h ContextControlClear 1A4h Reserved — 1A8h Asynchronous context command pointer CommandPtr 1ACh Reserved — 1B0h−1BCh ContextControlSet 1C0h ContextControlClear 1C4h Reserved — 1C8h Asynchronous context command pointer CommandPtr Reserved — Asynchronous context control Asynchronous context control 1CCh 1D0h−1DCh ContextControlSet 1E0h ContextControlClear 1E4h Reserved — 1E8h Asynchronous context command pointer CommandPtr Reserved — 1F0h−1FCh ContextControlSet 200h + 16*n 1ECh ContextControlClear 204h + 16*n Reserved — 208h + 16*n Isochronous transmit context command pointer CommandPtr 20Ch + 16*n Reserved — 210h−3FCh ContextControlSet 400h + 32*n ContextControlClear 404h + 32*n Reserved — 408h + 32*n Isochronous receive context command pointer CommandPtr 40Ch + 32*n Isochronous receive context match ContextMatch 410h + 32*n Isochronous receive context control n = 0, 1, 2, 3 180h ContextControlClear Asynchronous context command pointer Isochronous Receive Context n OFFSET Reserved Isochronous transmit context control Isochronous ABBREVIATION ContextControlSet 8−3 8.1 OHCI Version Register The OHCI version register indicates the OHCI version support and whether or not the serial EEPROM is present. See Table 8−2 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 OHCI version Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 X 0 0 0 0 0 0 0 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name OHCI version Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Register: Offset: Type: Default: OHCI version 00h Read-only 0X01 0010h Table 8−2. OHCI Version Register Description BIT FIELD NAME TYPE 31−25 RSVD R Reserved. Bits 31−25 return 0s when read. 24 GUID_ROM R The PCI4510 device sets bit 24 to 1 if the serial EEPROM is detected. If the serial EEPROM is present, then the Bus_Info_Block is automatically loaded on system (hardware) reset. 23−16 version R Major version of the OHCI. The PCI4510 device is compliant with the 1394 Open Host Controller Interface Specification (Release 1.1); thus, this field reads 01h. 15−8 RSVD R Reserved. Bits 15−8 return 0s when read. 7−0 revision R Minor version of the OHCI. The PCI4510 device is compliant with the 1394 Open Host Controller Interface Specification (Release 1.1); thus, this field reads 10h. 8−4 DESCRIPTION 8.2 GUID ROM Register The GUID ROM register accesses the serial EEPROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI version register at OHCI offset 00h (see Section 8.1) is set to 1. See Table 8−3 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 GUID ROM RSU R R R R R RSU R RU RU RU RU RU RU RU RU Default 0 0 0 0 0 0 0 0 X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name GUID ROM Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: GUID ROM 04h Read/Set/Update, Read/Update, Read-only 00XX 0000h Table 8−3. GUID ROM Register Description BIT FIELD NAME TYPE DESCRIPTION 31 addrReset RSU Software sets bit 31 to 1 to reset the GUID ROM address to 0. When the PCI4510 device completes the reset, it clears this bit. The PCI4510 device does not automatically fill bits 23−16 (rdData field) with the 0th byte. 30−26 RSVD R 25 rdStart RSU Reserved. Bits 30−26 return 0s when read. A read of the currently addressed byte is started when bit 25 is set to 1. This bit is automatically cleared when the PCI4510 device completes the read of the currently addressed GUID ROM byte. 24 RSVD R 23−16 rdData RU Reserved. Bit 24 returns 0 when read. 15−8 RSVD R Reserved. Bits 15−8 return 0s when read. 7−0 miniROM R The miniROM field defaults to 0 indicating that no mini-ROM is implemented. If bit 5 of EEPROM offset 6h is set to 1, then this field returns 20h indicating that valid mini-ROM data begins at offset 20h of the GUID ROM. This field contains the data read from the GUID ROM. 8−5 8.3 Asynchronous Transmit Retries Register The asynchronous transmit retries register indicates the number of times the PCI4510 device attempts a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See Table 8−4 for a complete description of the register contents. Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Asynchronous transmit retries R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Type R R R R RW RW RW RW RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name Asynchronous transmit retries Register: Offset: Type: Default: Asynchronous transmit retries 08h Read/Write, Read-only 0000 0000h Table 8−4. Asynchronous Transmit Retries Register Description BIT FIELD NAME TYPE DESCRIPTION 31−29 secondLimit R The second limit field returns 0s when read, because outbound dual-phase retry is not implemented. 28−16 cycleLimit R The cycle limit field returns 0s when read, because outbound dual-phase retry is not implemented. 15−12 RSVD R Reserved. Bits 15−12 return 0s when read. 11−8 maxPhysRespRetries RW This field tells the physical response unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. 7−4 maxATRespRetries RW This field tells the asynchronous transmit response unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. 3−0 maxATReqRetries RW This field tells the asynchronous transmit DMA request unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. 8.4 CSR Data Register The CSR data register accesses the bus management CSR registers from the host through compare-swap operations. This register contains the data to be stored in a CSR if the compare is successful. Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 CSR data Type R R R R R R R R R R R R R R R R Default X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Type R R R R R R R R R R R R R R R R Default X X X X X X X X X X X X X X X X Name CSR data Register: Offset: Type: Default: 8−6 CSR data 0Ch Read-only XXXX XXXXh 8.5 CSR Compare Register The CSR compare register accesses the bus management CSR registers from the host through compare-swap operations. This register contains the data to be compared with the existing value of the CSR resource. Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 CSR compare Type R R R R R R R R R R R R R R R R Default X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CSR compare Type R R R R R R R R R R R R R R R R Default X X X X X X X X X X X X X X X X Register: Offset: Type: Default: CSR compare 10h Read-only XXXX XXXXh 8.6 CSR Control Register The CSR control register accesses the bus management CSR registers from the host through compare-swap operations. This register controls the compare-swap operation and selects the CSR resource. See Table 8−5 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 RU R R R R R R R Default 1 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name Type 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 CSR control Name CSR control Type R R R R R R R R R R R R R R RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X Register: Offset: Type: Default: CSR control 14h Read/Write, Read/Update, Read-only 8000 000Xh Table 8−5. CSR Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31 csrDone RU Bit 31 is set to 1 by the PCI4510 device when a compare-swap operation is complete. It is cleared whenever this register is written. 30−2 RSVD R 1−0 csrSel RW Reserved. Bits 30−2 return 0s when read. This field selects the CSR resource as follows: 00 = BUS_MANAGER_ID 01 = BANDWIDTH_AVAILABLE 10 = CHANNELS_AVAILABLE_HI 11 = CHANNELS_AVAILABLE_LO 8−7 8.7 Configuration ROM Header Register The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset FFFF F000 0400h. See Table 8−6 for a complete description of the register contents. Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Configuration ROM header RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Configuration ROM header RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW X X X X X X X X X X X X X X X X Register: Offset: Type: Default: Configuration ROM header 18h Read/Write 0000 XXXXh Table 8−6. Configuration ROM Header Register Description BIT FIELD NAME TYPE DESCRIPTION 31−24 info_length RW IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. 23−16 crc_length RW IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. 15−0 rom_crc_value RW IEEE 1394 bus-management field. Must be valid at any time bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. The reset value is undefined if no serial EEPROM is present. If a serial EEPROM is present, then this field is loaded from the serial EEPROM. 8.8 Bus Identification Register The bus identification register externally maps to the first quadlet in the Bus_Info_Block and contains the constant 3133 3934h, which is the ASCII value of 1394. Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 1 1 0 0 0 1 Bit 15 14 13 12 11 10 9 8 Type R R R R R R R R Default 0 0 1 1 1 0 0 1 Name 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 1 1 0 0 1 1 7 6 5 4 3 2 1 0 R R R R R R R R 0 0 1 1 0 1 0 0 Bus identification Name Bus identification Register: Offset: Type: Default: 8−8 24 Bus identification 1Ch Read-only 3133 3934h 8.9 Bus Options Register The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 8−7 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 Bus options RW RW RW RW RW R R R RW RW RW RW RW RW RW RW Default X X X X 0 0 0 0 X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Bus options RW RW RW RW R R R R RW RW R R R R R R 1 0 1 0 0 0 0 0 X X 0 0 0 0 1 0 Register: Offset: Type: Default: Bus options 20h Read/Write, Read-only X0XX A0X2h Table 8−7. Bus Options Register Description BIT FIELD NAME TYPE DESCRIPTION 31 irmc RW Isochronous resource-manager capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. 30 cmc RW Cycle master capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. 29 isc RW Isochronous support capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. 28 bmc RW Bus manager capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. 27 pmc RW Power-management capable. IEEE 1394 bus-management field. When bit 27 is set to 1, this indicates that the node is power-management capable. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. 26−24 RSVD R 23−16 cyc_clk_acc RW Cycle master clock accuracy, in parts per million. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. 15−12 max_rec RW Maximum request. IEEE 1394 bus-management field. Hardware initializes this field to indicate the maximum number of bytes in a block request packet that is supported by the implementation. This value, max_rec_bytes, must be 512 or greater, and is calculated by 2^(max_rec + 1). Software may change this field; however, this field must be valid at any time bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. A received block write request packet with a length greater than max_rec_bytes may generate an ack_type_error. This field is not affected by a software reset, and defaults to value indicating 2048 bytes on a system (hardware) reset. 11−8 RSVD R 7−6 g RW 5−3 RSVD R Reserved. Bits 5−3 return 0s when read. 2−0 Lnk_spd R Link speed. This field returns 010, indicating that the link speeds of 100M bits/s, 200M bits/s, and 400M bits/s are supported. Reserved. Bits 26−24 return 0s when read. Reserved. Bits 11−8 return 0s when read. Generation counter. This field is incremented if any portion of the configuration ROM has been incremented since the prior bus reset. 8−9 8.10 GUID High Register The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the third quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes to 0s on a system (hardware) reset, which is an illegal GUID value. If a serial EEPROM is detected, then the contents of this register are loaded through the serial EEPROM interface after a PRST. At that point, the contents of this register cannot be changed. If no serial EEPROM is detected, then the contents of this register are loaded by the BIOS after a PRST. At that point, the contents of this register cannot be changed. Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 GUID high Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name GUID high Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: GUID high 24h Read-only 0000 0000h 8.11 GUID Low Register The GUID low register represents the lower quadlet in a 64-bit global unique ID (GUID) which maps to chip_ID_lo in the Bus_Info_Block. This register initializes to 0s on a system (hardware) reset and behaves identical to the GUID high register at OHCI offset 24h (see Section 8.10). Bit 31 30 29 28 27 26 25 24 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 GUID low Name GUID low Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: 8−10 GUID low 28h Read-only 0000 0000h 8.12 Configuration ROM Mapping Register The configuration ROM mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node. See Table 8−8 for a complete description of the register contents. Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Configuration ROM mapping RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Configuration ROM mapping RW RW RW RW RW RW R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Configuration ROM mapping 34h Read/Write 0000 0000h Table 8−8. Configuration ROM Mapping Register Description BIT FIELD NAME TYPE DESCRIPTION 31−10 configROMaddr RW If a quadlet read request to 1394 offset FFFF F000 0400h through offset FFFF F000 07FFh is received, then the low-order 10 bits of the offset are added to this register to determine the host memory address of the read request. 9−0 RSVD R Reserved. Bits 9−0 return 0s when read. 8.13 Posted Write Address Low Register The posted write address low register communicates error information if a write request is posted and an error occurs while the posted data packet is being written. See Table 8−9 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 RU RU RU RU RU RU RU RU RU Default X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 Name Type Default 23 22 21 20 19 18 17 16 RU RU RU RU RU RU RU X X X X X X X 6 5 4 3 2 1 0 Posted write address low Name Type 24 Posted write address low RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU X X X X X X X X X X X X X X X X Register: Offset: Type: Default: Posted write address low 38h Read/Update XXXX XXXXh Table 8−9. Posted Write Address Low Register Description BIT FIELD NAME TYPE 31−0 offsetLo RU DESCRIPTION The lower 32 bits of the 1394 destination offset of the write request that failed. 8−11 8.14 Posted Write Address High Register The posted write address high register communicates error information if a write request is posted and an error occurs while writing the posted data packet. See Table 8−10 for a complete description of the register contents. Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Posted write address high RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU Default X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Posted write address high RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU X X X X X X X X X X X X X X X X Register: Offset: Type: Default: Posted write address high 3Ch Read/Update XXXX XXXXh Table 8−10. Posted Write Address High Register Description BIT FIELD NAME TYPE DESCRIPTION 31−16 sourceID RU This field is the 10-bit bus number (bits 31−22) and 6-bit node number (bits 21−16) of the node that issued the write request that failed. 15−0 offsetHi RU The upper 16 bits of the 1394 destination offset of the write request that failed. 8.15 Vendor ID Register The vendor ID register holds the company ID of an organization that specifies any vendor-unique registers. The PCI4510 device implements Texas Instruments unique behavior with regards to OHCI. Thus, this register is read-only and returns 0108 0028h when read. Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 Vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 Register: Offset: Type: Default: 8−12 Vendor ID 40h Read-only 0108 0028h 8.16 Host Controller Control Register The host controller control set/clear register pair provides flags for controlling the PCI4510 device. See Table 8−11 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 Host controller control RSU RSC RSC R R R R R R RSC R R RSC RSC RSC RSCU Default 0 X 0 0 0 0 0 0 1 0 0 0 0 X 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Host controller control Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Host controller control 50h set register 54h clear register Read/Set/Clear/Update, Read/Set/Clear, Read/Clear, Read-only X08X 0000h Table 8−11. Host Controller Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31 BIBimage Valid RSU When bit 31 is set to 1, the PCI4510 physical response unit is enabled to respond to block read requests to host configuration ROM and to the mechanism for atomically updating configuration ROM. Software creates a valid image of the bus_info_block in host configuration ROM before setting this bit. When this bit is cleared, the PCI4510 device returns ack_type_error on block read requests to host configuration ROM. Also, when this bit is cleared and a 1394 bus reset occurs, the configuration ROM mapping register at OHCI offset 34h (see Section 8.12), configuration ROM header register at OHCI offset 18h (see Section 8.7), and bus options register at OHCI offset 20h (see Section 8.9) are not updated. Software can set this bit only when bit 17 (linkEnable) is 0. Once bit 31 is set to 1, it can be cleared by a system (hardware) reset, a software reset, or if a fetch error occurs when the PCI4510 device loads bus_info_block registers from host memory. 30 noByteSwapData RSC Bit 30 controls whether physical accesses to locations outside the PCI4510 device itself, as well as any other DMA data accesses are byte swapped. 29 AckTardyEnable RSC Bit 29 controls the acknowledgement of ack_tardy. When bit 29 is set to 1, ack_tardy may be returned as an acknowledgment to accesses from the 1394 bus to the PCI4510 device, including accesses to the bus_info_block. The PCI4510 device returns ack_tardy to all other asynchronous packets addressed to the PCI4510 node. When the PCI4510 device sends ack_tardy, bit 27 (ack_tardy) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) is set to 1 to indicate the attempted asynchronous access. Software ensures that bit 27 (ack_tardy) in the interrupt event register is 0. Software also unmasks wake-up interrupt events such as bit 19 (phy) and bit 27 (ack_tardy) in the interrupt event register before placing the PCI4510 device into the D1 power mode. Software must not set this bit if the PCI4510 node is the 1394 bus manager. 28−24 RSVD R Reserved. Bits 28−24 return 0s when read. 23 programPhyEnable R Bit 23 informs upper-level software that lower-level software has consistently configured the IEEE 1394a-2000 enhancements in the link and PHY layers. When this bit is 1, generic software such as the OHCI driver is responsible for configuring IEEE 1394a-2000 enhancements in the PHY layer and bit 22 (aPhyEnhanceEnable). When this bit is 0, the generic software may not modify the IEEE 1394a-2000 enhancements in the PHY layer and cannot interpret the setting of bit 22 (aPhyEnhanceEnable). This bit is initialized from serial EEPROM. This bit defaults to 1. 8−13 Table 8−11. Host Controller Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 22 aPhyEnhanceEnable RSC When bits 23 (programPhyEnable) and 17 (linkEnable) are 1, the OHCI driver can set bit 22 to 1 to use all IEEE 1394a-2000 enhancements. When bit 23 (programPhyEnable) is cleared to 0, the software does not change PHY enhancements or this bit. 21−20 RSVD R 19 LPS RSC Reserved. Bits 21 and 20 return 0s when read. Bit 19 controls the link power status. Software must set this bit to 1 to permit the link-PHY communication. A 0 prevents link-PHY communication. The OHCI-link is divided into two clock domains (PCLK and PHY_SCLK). If software tries to access any register in the PHY_SCLK domain while the PHY_SCLK is disabled, then a target abort is issued by the link. This problem can be avoided by setting bit 4 (DIS_TGT_ABT) to 1 in the miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 7.23). This allows the link to respond to these types of request by returning all Fs (hex). OHCI registers at offsets DCh−F0h and 100h−11Ch are in the PHY_SCLK domain. After setting LPS, software must wait approximately 10 ms before attempting to access any of the OHCI registers. This gives the PHY_SCLK time to stabilize. 18 postedWriteEnable RSC Bit 18 enables (1) or disables (0) posted writes. Software changes this bit only when bit 17 (linkEnable) is 0. 17 linkEnable RSC Bit 17 is cleared to 0 by either a system (hardware) or software reset. Software must set this bit to 1 when the system is ready to begin operation and then force a bus reset. This bit is necessary to keep other nodes from sending transactions before the local system is ready. When this bit is cleared, the PCI4510 device is logically and immediately disconnected from the 1394 bus, no packets are received or processed, nor are packets transmitted. 16 SoftReset RSCU When bit 16 is set to 1, all PCI4510 states are reset, all FIFOs are flushed, and all OHCI registers are set to their system (hardware) reset values, unless otherwise specified. PCI registers are not affected by this bit. This bit remains set to 1 while the software reset is in progress and reverts back to 0 when the reset has completed. 15−0 RSVD R Reserved. Bits 15−0 return 0s when read. 8.17 Self-ID Buffer Pointer Register The self-ID buffer pointer register points to the 2K-byte aligned base address of the buffer in host memory where the self-ID packets are stored during bus initialization. Bits 31−11 are read/write accessible. Bits 10−0 are reserved, and return 0s when read. Bit 31 30 29 28 27 26 25 RW RW RW RW RW RW RW RW Default X X X X X X X X Bit 15 14 13 12 11 10 9 8 Name Type Default 22 21 20 19 18 17 16 RW RW RW RW RW RW RW RW X X X X X X X X 7 6 5 4 3 2 1 0 Self-ID buffer pointer RW RW RW RW RW R R R R R R R R R R R X X X X X 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: 8−14 23 Self-ID buffer pointer Name Type 24 Self-ID buffer pointer 64h Read/Write, Read-only XXXX XX00h 8.18 Self-ID Count Register The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-ID packet errors, and keeps a count of the self-ID data in the self-ID buffer. See Table 8−12 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 Self-ID count RU R R R R R R R RU RU RU RU RU RU RU RU Default X 0 0 0 0 0 0 0 X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Self-ID count Type R R R R R RU RU RU RU RU RU RU RU RU R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Self-ID count 68h Read/Update, Read-only X0XX 0000h Table 8−12. Self-ID Count Register Description BIT FIELD NAME TYPE DESCRIPTION 31 selfIDError RU When bit 31 is set to 1, an error was detected during the most recent self-ID packet reception. The contents of the self-ID buffer are undefined. This bit is cleared after a self-ID reception in which no errors are detected. Note that an error can be a hardware error or a host bus write error. 30−24 RSVD R 23−16 selfIDGeneration RU 15−11 RSVD R 10−2 selfIDSize RU 1−0 RSVD R Reserved. Bits 30−24 return 0s when read. The value in this field increments each time a bus reset is detected. This field rolls over to 0 after reaching 255. Reserved. Bits 15−11 return 0s when read. This field indicates the number of quadlets that have been written into the self-ID buffer for the current bits 23−16 (selfIDGeneration field). This includes the header quadlet and the self-ID data. This field is cleared to 0s when the self-ID reception begins. Reserved. Bits 1 and 0 return 0s when read. 8−15 8.19 Isochronous Receive Channel Mask High Register The isochronous receive channel mask high set/clear register enables packet receives from the upper 32 isochronous data channels. A read from either the set register or clear register returns the content of the isochronous receive channel mask high register. See Table 8−13 for a complete description of the register contents. Bit 31 30 29 28 27 Name Type 26 25 24 23 22 21 20 19 18 17 16 Isochronous receive channel mask high RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Isochronous receive channel mask high RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC X X X X X X X X X X X X X X X X Register: Offset: Type: Default: Isochronous receive channel mask high 70h set register 74h clear register Read/Set/Clear XXXX XXXXh Table 8−13. Isochronous Receive Channel Mask High Register Description 8−16 BIT FIELD NAME TYPE DESCRIPTION 31 isoChannel63 RSC When bit 31 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 63. 30 isoChannel62 RSC When bit 30 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 62. 29 isoChannel61 RSC When bit 29 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 61. 28 isoChannel60 RSC When bit 28 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 60. 27 isoChannel59 RSC When bit 27 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 59. 26 isoChannel58 RSC When bit 26 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 58. 25 isoChannel57 RSC When bit 25 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 57. 24 isoChannel56 RSC When bit 24 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 56. 23 isoChannel55 RSC When bit 23 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 55. 22 isoChannel54 RSC When bit 22 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 54. 21 isoChannel53 RSC When bit 21 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 53. 20 isoChannel52 RSC When bit 20 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 52. 19 isoChannel51 RSC When bit 19 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 51. 18 isoChannel50 RSC When bit 18 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 50. 17 isoChannel49 RSC When bit 17 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 49. 16 isoChannel48 RSC When bit 16 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 48. 15 isoChannel47 RSC When bit 15 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 47. 14 isoChannel46 RSC When bit 14 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 46. 13 isoChannel45 RSC When bit 13 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 45. 12 isoChannel44 RSC When bit 12 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 44. 11 isoChannel43 RSC When bit 11 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 43. 10 isoChannel42 RSC When bit 10 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 42. 9 isoChannel41 RSC When bit 9 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 41. 8 isoChannel40 RSC When bit 8 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 40. 7 isoChannel39 RSC When bit 7 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 39. Table 8−13. Isochronous Receive Channel Mask High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 6 isoChannel38 RSC When bit 6 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 38. 5 isoChannel37 RSC When bit 5 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 37. 4 isoChannel36 RSC When bit 4 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 36. 3 isoChannel35 RSC When bit 3 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 35. 2 isoChannel34 RSC When bit 2 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 34. 1 isoChannel33 RSC When bit 1 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 33. 0 isoChannel32 RSC When bit 0 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 32. 8.20 Isochronous Receive Channel Mask Low Register The isochronous receive channel mask low set/clear register enables packet receives from the lower 32 isochronous data channels. See Table 8−14 for a complete description of the register contents. Bit 31 30 29 28 27 26 RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 Name Type Default 24 23 22 21 20 19 18 17 16 RSC RSC RSC RSC RSC RSC X X X X X X 5 4 3 2 1 0 Isochronous receive channel mask low Name Type 25 Isochronous receive channel mask low RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC X X X X X X X X X X X X X X X X Register: Offset: Type: Default: Isochronous receive channel mask low 78h set register 7Ch clear register Read/Set/Clear XXXX XXXXh Table 8−14. Isochronous Receive Channel Mask Low Register Description BIT FIELD NAME TYPE DESCRIPTION 31 isoChannel31 RSC When bit 31 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 31. 30 isoChannel30 RSC When bit 30 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 30. 29−2 isoChanneln RSC Bits 29 through 2 (isoChanneln, where n = 29, 28, 27, …, 2) follow the same pattern as bits 31 and 30. 1 isoChannel1 RSC When bit 1 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 1. 0 isoChannel0 RSC When bit 0 is set to 1, the PCI4510 device is enabled to receive from isochronous channel number 0. 8−17 8.21 Interrupt Event Register The interrupt event set/clear register reflects the state of the various PCI4510 interrupt sources. The interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register. This register is fully compliant with the 1394 Open Host Controller Interface Specification, and the PCI4510 device adds a vendor-specific interrupt function to bit 30. When the interrupt event register is read, the return value is the bit-wise AND function of the interrupt event and interrupt mask registers. See Table 8−15 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 R RSC RSC R RSCU RSCU RSCU RSCU Name Type 23 22 21 20 19 18 17 16 RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU Interrupt event Default 0 X 0 0 0 X X X X X X X X 0 X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSCU R R R R R RSCU RSCU RU RU RSCU RSCU RSCU RSCU RSCU RSCU 0 0 0 0 0 0 X X X X X X X X X X Name Type Default Interrupt event Register: Offset: Type: Default: Interrupt event 80h set register 84h clear register [returns the content of the interrupt event register bit-wise ANDed with the interrupt mask register when read] Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only XXXX 0XXXh Table 8−15. Interrupt Event Register Description BIT FIELD NAME TYPE 31 RSVD R 30 RSVD RSC Reserved. Do not write to this bit. 29 SoftInterrupt RSC Bit 29 is used by software to generate a PCI4510 interrupt for its own use. 28 RSVD R 27 ack_tardy RSCU DESCRIPTION Reserved. Bit 31 returns 0 when read. Reserved. Bit 28 returns 0 when read. Bit 27 is set to 1 when bit 29 (AckTardyEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1 and any of the following conditions occur: a. Data is present in a receive FIFO that is to be delivered to the host. b. The physical response unit is busy processing requests or sending responses. c. The PCI4510 device sent an ack_tardy acknowledgment. 8−18 26 phyRegRcvd RSCU The PCI4510 device has received a PHY register data byte which can be read from bits 23−16 in the PHY layer control register at OHCI offset ECh (see Section 8.33). 25 cycleTooLong RSCU If bit 21 (cycleMaster) in the link control register at OHCI offset E0h/E4h (see Section 8.31) is set to 1, then this indicates that over 125 µs has elapsed between the start of sending a cycle start packet and the end of a subaction gap. Bit 21 (cycleMaster) in the link control register is cleared by this event. 24 unrecoverableError RSCU This event occurs when the PCI4510 device encounters any error that forces it to stop operations on any or all of its subunits, for example, when a DMA context sets its dead bit to 1. While bit 24 is set to 1, all normal interrupts for the context(s) that caused this interrupt are blocked from being set to 1. 23 cycleInconsistent RSCU A cycle start was received that had values for the cycleSeconds and cycleCount fields that are different from the values in bits 31−25 (cycleSeconds field) and bits 24−12 (cycleCount field) in the isochronous cycle timer register at OHCI offset F0h (see Section 8.34). Table 8−15. Interrupt Event Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 22 cycleLost RSCU A lost cycle is indicated when no cycle_start packet is sent or received between two successive cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after a cycleSynch event without an intervening cycle start. Bit 22 may be set to 1 either when a lost cycle occurs or when logic predicts that one will occur. 21 cycle64Seconds RSCU Indicates that the 7th bit of the cycle second counter has changed. 20 cycleSynch RSCU Indicates that a new isochronous cycle has started. Bit 20 is set to 1 when the low-order bit of the cycle count toggles. 19 phy RSCU Indicates that the PHY layer requests an interrupt through a status transfer. 18 regAccessFail RSCU Indicates that a PCI4510 register access has failed due to a missing SCLK clock signal from the PHY layer. When a register access fails, bit 18 is set to 1 before the next register access. 17 busReset RSCU Indicates that the PHY layer has entered bus reset mode. 16 selfIDcomplete RSCU A self-ID packet stream has been received. It is generated at the end of the bus initialization process. Bit 16 is turned off simultaneously when bit 17 (busReset) is turned on. 15 selfIDcomplete2 RSCU Secondary indication of the end of a self-ID packet stream. Bit 15 is set to 1 by the PCI4510 device when it sets bit 16 (selfIDcomplete), and retains the state, independent of bit 17 (busReset). 14−10 RSVD R 9 lockRespErr RSCU Reserved. Bits 14−10 return 0s when read. Indicates that the PCI4510 device sent a lock response for a lock request to a serial bus register, but did not receive an ack_complete. 8 postedWriteErr RSCU Indicates that a host bus error occurred while the PCI4510 device was trying to write a 1394 write request, which had already been given an ack_complete, into system memory. 7 isochRx RU Isochronous receive DMA interrupt. Indicates that one or more isochronous receive contexts have generated an interrupt. This is not a latched event; it is the logical OR of all bits in the isochronous receive interrupt event register at OHCI offset A0h/A4h (see Section 8.25) and isochronous receive interrupt mask register at OHCI offset A8h/ACh (see Section 8.26). The isochronous receive interrupt event register indicates which contexts have been interrupted. 6 isochTx RU Isochronous transmit DMA interrupt. Indicates that one or more isochronous transmit contexts have generated an interrupt. This is not a latched event; it is the logical OR of all bits in the isochronous transmit interrupt event register at OHCI offset 90h/94h (see Section 8.23) and isochronous transmit interrupt mask register at OHCI offset 98h/9Ch (see Section 8.24). The isochronous transmit interrupt event register indicates which contexts have been interrupted. 5 RSPkt RSCU Indicates that a packet was sent to an asynchronous receive response context buffer and the descriptor xferStatus and resCount fields have been updated. 4 RQPkt RSCU Indicates that a packet was sent to an asynchronous receive request context buffer and the descriptor xferStatus and resCount fields have been updated. 3 ARRS RSCU Asynchronous receive response DMA interrupt. Bit 3 is conditionally set to 1 upon completion of an ARRS DMA context command descriptor. 2 ARRQ RSCU Asynchronous receive request DMA interrupt. Bit 2 is conditionally set to 1 upon completion of an ARRQ DMA context command descriptor. 1 respTxComplete RSCU Asynchronous response transmit DMA interrupt. Bit 1 is conditionally set to 1 upon completion of an ATRS DMA command. 0 reqTxComplete RSCU Asynchronous request transmit DMA interrupt. Bit 0 is conditionally set to 1 upon completion of an ATRQ DMA command. 8−19 8.22 Interrupt Mask Register The interrupt mask set/clear register enables the various PCI4510 interrupt sources. Reads from either the set register or the clear register always return the contents of the interrupt mask register. In all cases except masterIntEnable (bit 31) and vendorSpecific (bit 30), the enables for each interrupt event align with the interrupt event register bits detailed in Table 8−15. This register is fully compliant with the 1394 Open Host Controller Interface Specification and the PCI4510 device adds an interrupt function to bit 30. See Table 8−16 for a complete description of bits 31 and 30. Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 Interrupt mask RSCU RSC RSC R RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default X X 0 0 0 X X X X X X X X 0 X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Interrupt mask RSC R R R R R RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC 0 0 0 0 0 0 X X X X X X X X X X Register: Offset: Type: Default: Interrupt mask 88h set register 8Ch clear register Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only XXXX 0XXXh Table 8−16. Interrupt Mask Register Description 8−20 BIT FIELD NAME TYPE DESCRIPTION 31 masterIntEnable RSCU Master interrupt enable. If bit 31 is set to 1, then external interrupts are generated in accordance with the interrupt mask register. If this bit is cleared, then external interrupts are not generated regardless of the interrupt mask register settings. 30 VendorSpecific RSC When this bit and bit 30 (vendorSpecific) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this vendor-specific interrupt mask enables interrupt generation. 29 SoftInterrupt RSC When this bit and bit 29 (SoftInterrupt) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this soft-interrupt mask enables interrupt generation. 28 RSVD R 27 ack_tardy RSC When this bit and bit 27 (ack_tardy) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this acknowledge-tardy interrupt mask enables interrupt generation. 26 phyRegRcvd RSC When this bit and bit 26 (phyRegRcvd) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this PHY-register interrupt mask enables interrupt generation. 25 cycleTooLong RSC When this bit and bit 25 (cycleTooLong) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this cycle-too-long interrupt mask enables interrupt generation. 24 unrecoverableError RSC When this bit and bit 24 (unrecoverableError) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this unrecoverable-error interrupt mask enables interrupt generation. 23 cycleInconsistent RSC When this bit and bit 23 (cycleInconsistent) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this inconsistent-cycle interrupt mask enables interrupt generation. 22 cycleLost RSC When this bit and bit 22 (cycleLost) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this lost-cycle interrupt mask enables interrupt generation. 21 cycle64Seconds RSC When this bit and bit 21 (cycle64Seconds) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this 64-second-cycle interrupt mask enables interrupt generation. 20 cycleSynch RSC When this bit and bit 20 (cycleSynch) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this isochronous-cycle interrupt mask enables interrupt generation. 19 phy RSC When this bit and bit 19 (phy) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this PHY-status-transfer interrupt mask enables interrupt generation. Reserved. Bit 28 returns 0 when read. Table 8−16. Interrupt Mask Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 18 regAccessFail RSC When this bit and bit 18 (regAccessFail) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this register-access-failed interrupt mask enables interrupt generation. 17 busReset RSC When this bit and bit 17 (busReset) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this bus-reset interrupt mask enables interrupt generation. 16 selfIDcomplete RSC When this bit and bit 16 (selfIDcomplete) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this self-ID-complete interrupt mask enables interrupt generation. 15 selfIDcomplete2 RSC When this bit and bit 15 (selfIDcomplete2) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this second-self-ID-complete interrupt mask enables interrupt generation. 14−10 RSVD R 9 lockRespErr RSC When this bit and bit 9 (lockRespErr) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this lock-response-error interrupt mask enables interrupt generation. 8 postedWriteErr RSC When this bit and bit 8 (postedWriteErr) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this posted-write-error interrupt mask enables interrupt generation. 7 isochRx RSC When this bit and bit 7 (isochRx) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this isochronous-receive-DMA interrupt mask enables interrupt generation. 6 isochTx RSC When this bit and bit 6 (isochTx) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this isochronous-transmit-DMA interrupt mask enables interrupt generation. 5 RSPkt RSC When this bit and bit 5 (RSPkt) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this receive-response-packet interrupt mask enables interrupt generation. 4 RQPkt RSC When this bit and bit 4 (RQPkt) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this receive-request-packet interrupt mask enables interrupt generation. 3 ARRS RSC When this bit and bit 3 (ARRS) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this asynchronous-receive-response-DMA interrupt mask enables interrupt generation. 2 ARRQ RSC When this bit and bit 2 (ARRQ) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this asynchronous-receive-request-DMA interrupt mask enables interrupt generation. 1 respTxComplete RSC When this bit and bit 1 (respTxComplete) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this response-transmit-complete interrupt mask enables interrupt generation. 0 reqTxComplete RSC When this bit and bit 0 (reqTxComplete) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) are set to 1, this request-transmit-complete interrupt mask enables interrupt generation. Reserved. Bits 14−10 return 0s when read. 8−21 8.23 Isochronous Transmit Interrupt Event Register The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* command completes and its interrupt bits are set to 1. Upon determining that the isochTx (bit 6) interrupt has occurred in the interrupt event register at OHCI offset 80h/84h (see Section 8.21), software can check this register to determine which context(s) caused the interrupt. The interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register. See Table 8−17 for a complete description of the register contents. Bit 31 30 29 28 27 26 Name 25 24 23 22 21 20 19 18 17 16 Isochronous transmit interrupt event Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Isochronous transmit interrupt event Type R R R R R R R R RSC RSC RSC RSC RSC RSC RSC RSC Default 0 0 0 0 0 0 0 0 X X X X X X X X Register: Offset: Isochronous transmit interrupt event 90h set register 94h clear register [returns the contents of the isochronous transmit interrupt event register bit-wise ANDed with the isochronous transmit interrupt mask register when read] Read/Set/Clear, Read-only 0000 00XXh Type: Default: Table 8−17. Isochronous Transmit Interrupt Event Register Description BIT FIELD NAME TYPE DESCRIPTION 31−8 RSVD R 7 isoXmit7 RSC Isochronous transmit channel 7 caused the interrupt event register bit 6 (isochTx) interrupt. 6 isoXmit6 RSC Isochronous transmit channel 6 caused the interrupt event register bit 6 (isochTx) interrupt. 5 isoXmit5 RSC Isochronous transmit channel 5 caused the interrupt event register bit 6 (isochTx) interrupt. 4 isoXmit4 RSC Isochronous transmit channel 4 caused the interrupt event register bit 6 (isochTx) interrupt. 3 isoXmit3 RSC Isochronous transmit channel 3 caused the interrupt event register bit 6 (isochTx) interrupt. 2 isoXmit2 RSC Isochronous transmit channel 2 caused the interrupt event register bit 6 (isochTx) interrupt. 1 isoXmit1 RSC Isochronous transmit channel 1 caused the interrupt event register bit 6 (isochTx) interrupt. 0 isoXmit0 RSC Isochronous transmit channel 0 caused the interrupt event register bit 6 (isochTx) interrupt. 8−22 Reserved. Bits 31−8 return 0s when read. 8.24 Isochronous Transmit Interrupt Mask Register The isochronous transmit interrupt mask set/clear register enables the isochTx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register. In all cases the enables for each interrupt event align with the isochronous transmit interrupt event register bits detailed in Table 8−17. Bit 31 30 29 28 27 26 Name 25 24 23 22 21 20 19 18 17 16 Isochronous transmit interrupt mask Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Isochronous transmit interrupt mask Type R R R R R R R R RSC RSC RSC RSC RSC RSC RSC RSC Default 0 0 0 0 0 0 0 0 X X X X X X X X Register: Offset: Type: Default: Isochronous transmit interrupt mask 98h set register 9Ch clear register Read/Set/Clear, Read-only 0000 00XXh 8−23 8.25 Isochronous Receive Interrupt Event Register The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes and its interrupt bits are set to 1. Upon determining that the isochRx (bit 7) interrupt in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) has occurred, software can check this register to determine which context(s) caused the interrupt. The interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register. See Table 8−18 for a complete description of the register contents. Bit 31 30 29 28 27 26 Name 25 24 23 22 21 20 19 18 17 16 Isochronous receive interrupt event Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Isochronous receive interrupt event Type R R R R R R R R R R R R RSC RSC RSC RSC Default 0 0 0 0 0 0 0 0 0 0 0 0 X X X X Register: Offset: Isochronous receive interrupt event A0h set register A4h clear register [returns the contents of isochronous receive interrupt event register bit-wise ANDed with the isochronous receive mask register when read] Read/Set/Clear, Read-only 0000 000Xh Type: Default: Table 8−18. Isochronous Receive Interrupt Event Register Description BIT FIELD NAME TYPE DESCRIPTION 31−4 RSVD R 3 isoRecv3 RSC Isochronous receive channel 3 caused the interrupt event register bit 7 (isochRx) interrupt. 2 isoRecv2 RSC Isochronous receive channel 2 caused the interrupt event register bit 7 (isochRx) interrupt. 1 isoRecv1 RSC Isochronous receive channel 1 caused the interrupt event register bit 7 (isochRx) interrupt. 0 isoRecv0 RSC Isochronous receive channel 0 caused the interrupt event register bit 7 (isochRx) interrupt. 8−24 Reserved. Bits 31−4 return 0s when read. 8.26 Isochronous Receive Interrupt Mask Register The isochronous receive interrupt mask set/clear register enables the isochRx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous receive interrupt mask register. In all cases the enables for each interrupt event align with the isochronous receive interrupt event register bits detailed in Table 8−18. Bit 31 30 29 28 27 26 Name 25 24 23 22 21 20 19 18 17 16 Isochronous receive interrupt mask Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Isochronous receive interrupt mask Type R R R R R R R R R R R R RSC RSC RSC RSC Default 0 0 0 0 0 0 0 0 0 0 0 0 X X X X Register: Offset: Type: Default: Isochronous receive interrupt mask A8h set register ACh clear register Read/Set/Clear, Read-only 0000 000Xh 8.27 Initial Bandwidth Available Register The initial bandwidth available register value is loaded into the corresponding bus management CSR register on a system (hardware) or software reset. See Table 8−19 for a complete description of the register contents. Bit 31 30 29 28 27 26 Name 25 24 23 22 21 20 19 18 17 16 Initial bandwidth available Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Initial bandwidth available Type R R R RW RW RW RW RW RW RW RW RW RW RW RW RW Default 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 Register: Offset: Type: Default: Initial bandwidth available B0h Read-only, Read/Write 0000 1333h Table 8−19. Initial Bandwidth Available Register Description BIT FIELD NAME TYPE 31−13 RSVD R 12−0 InitBWAvailable RW DESCRIPTION Reserved. Bits 31−13 return 0s when read. This field is reset to 1333h on a system (hardware) or software reset, and is not affected by a 1394 bus reset. The value of this field is loaded into the BANDWIDTH_AVAILABLE CSR register upon a GRST, PRST, or a 1394 bus reset. 8−25 8.28 Initial Channels Available High Register The initial channels available high register value is loaded into the corresponding bus management CSR register on a system (hardware) or software reset. See Table 8−20 for a complete description of the register contents. Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Initial channels available high RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Initial channels available high RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Register: Offset: Type: Default: Initial channels available high B4h Read/Write FFFF FFFFh Table 8−20. Initial Channels Available High Register Description BIT FIELD NAME TYPE DESCRIPTION 31−0 InitChanAvailHi RW This field is reset to FFFF_FFFFh on a system (hardware) or software reset, and is not affected by a 1394 bus reset. The value of this field is loaded into the CHANNELS_AVAILABLE_HI CSR register upon a GRST, PRST, or a 1394 bus reset. 8.29 Initial Channels Available Low Register The initial channels available low register value is loaded into the corresponding bus management CSR register on a system (hardware) or software reset. See Table 8−21 for a complete description of the register contents. Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Initial channels available low RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Initial channels available low RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Register: Offset: Type: Default: Initial channels available low B8h Read/Write FFFF FFFFh Table 8−21. Initial Channels Available Low Register Description BIT FIELD NAME TYPE DESCRIPTION 31−0 InitChanAvailLo RW This field is reset to FFFF_FFFFh on a system (hardware) or software reset, and is not affected by a 1394 bus reset. The value of this field is loaded into the CHANNELS_AVAILABLE_LO CSR register upon a GRST, PRST, or a 1394 bus reset. 8−26 8.30 Fairness Control Register The fairness control register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval. See Table 8−22 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 Fairness control Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Fairness control Type R R R R R R R R RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Fairness control DCh Read-only 0000 0000h Table 8−22. Fairness Control Register Description BIT FIELD NAME TYPE 31−8 RSVD R 7−0 pri_req RW DESCRIPTION Reserved. Bits 31−8 return 0s when read. This field specifies the maximum number of priority arbitration requests for asynchronous request packets that the link is permitted to make of the PHY layer during a fairness interval. 8−27 8.31 Link Control Register The link control set/clear register provides the control flags that enable and configure the link core protocol portions of the PCI4510 device. It contains controls for the receiver and cycle timer. See Table 8−23 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 Link control Type R R R R R R R R R RSC RSCU RSC R R R R Default 0 0 0 0 0 0 0 0 0 X X X 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Link control Type R R R R R RSC RSC R R RS R R R R R R Default 0 0 0 0 0 X X 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Link control E0h set register E4h clear register Read/Set/Clear/Update, Read/Set/Clear, Read-only 00X0 0X00h Table 8−23. Link Control Register Description BIT FIELD NAME TYPE 31−23 RSVD R DESCRIPTION 22 cycleSource RSC When bit 22 is set to 1, the cycle timer uses an external source (CYCLEIN) to determine when to roll over the cycle timer. When this bit is cleared, the cycle timer rolls over when the timer reaches 3072 cycles of the 24.576-MHz clock (125 µs). 21 cycleMaster RSCU When bit 21 is set to 1, the PCI4510 device is root and it generates a cycle start packet every time the cycle timer rolls over, based on the setting of bit 22 (cycleSource). When bit 21 is cleared, the OHCI-Lynx accepts received cycle start packets to maintain synchronization with the node which is sending them. Bit 21 is automatically cleared when bit 25 (cycleTooLong) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) is set to 1. Bit 21 cannot be set to 1 until bit 25 (cycleTooLong) is cleared. 20 CycleTimerEnable RSC When bit 20 is set to 1, the cycle timer offset counts cycles of the 24.576-MHz clock and rolls over at the appropriate time, based on the settings of the above bits. When this bit is cleared, the cycle timer offset does not count. Reserved. Bits 31−23 return 0s when read. 19−11 RSVD R 10 RcvPhyPkt RSC When bit 10 is set to 1, the receiver accepts incoming PHY packets into the AR request context if the AR request context is enabled. This bit does not control receipt of self-identification packets. 9 RcvSelfID RSC When bit 9 is set to 1, the receiver accepts incoming self-identification packets. Before setting this bit to 1, software must ensure that the self-ID buffer pointer register contains a valid address. 8−7 RSVD R 6 tag1SyncFilterLock RS 5−0 RSVD R 8−28 Reserved. Bits 19−11 return 0s when read. Reserved. Bits 8 and 7 return 0s when read. When bit 6 is set to 1, bit 6 (tag1SyncFilter) in the isochronous receive context match register (see Section 8.46) is set to 1 for all isochronous receive contexts. When bit 6 is cleared, bit 6 (tag1SyncFilter) in the isochronous receive context match register has read/write access. This bit is cleared when GRST is asserted. Reserved. Bits 5−0 return 0s when read. 8.32 Node Identification Register The node identification register contains the address of the node on which the OHCI-Lynx chip resides, and indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15−6) and the NodeNumber field (bits 5−0) is referred to as the node ID. See Table 8−24 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 Node identification RU RU R R RU R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Node identification RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RU RU RU RU RU RU 1 1 1 1 1 1 1 1 1 1 X X X X X X Register: Offset: Type: Default: Node identification E8h Read/Write/Update, Read/Update, Read-only 0000 FFXXh Table 8−24. Node Identification Register Description BIT FIELD NAME TYPE DESCRIPTION 31 iDValid RU Bit 31 indicates whether or not the PCI4510 device has a valid node number. It is cleared when a 1394 bus reset is detected and set to 1 when the PCI4510 device receives a new node number from its PHY layer. 30 root RU Bit 30 is set to 1 during the bus reset process if the attached PHY layer is root. 29−28 RSVD R 27 CPS RU 26−16 RSVD R 15−6 busNumber RWU This field identifies the specific 1394 bus the PCI4510 device belongs to when multiple 1394-compatible buses are connected via a bridge. 5−0 NodeNumber RU This field is the physical node number established by the PHY layer during self-identification. It is automatically set to the value received from the PHY layer after the self-identification phase. If the PHY layer sets the nodeNumber to 63, then software must not set bit 15 (run) in the asynchronous context control register (see Section 8.40) for either of the AT DMA contexts. Reserved. Bits 29 and 28 return 0s when read. Bit 27 is set to 1 if the PHY layer is reporting that cable power status is OK. Reserved. Bits 26−16 return 0s when read. 8−29 8.33 PHY Layer Control Register The PHY layer control register reads from or writes to a PHY register. See Table 8−25 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 PHY layer control RU R R R RU RU RU RU RU RU RU RU RU RU RU RU Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default PHY layer control RWU RWU R R RW RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: PHY layer control ECh Read/Write/Update, Read/Write, Read/Update, Read-only 0000 0000h Table 8−25. PHY Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31 rdDone RU Bit 31 is cleared to 0 by the PCI4510 device when either bit 15 (rdReg) or bit 14 (wrReg) is set to 1. This bit is set to 1 when a register transfer is received from the PHY layer. 30−28 RSVD R 27−24 rdAddr RU Reserved. Bits 30−28 return 0s when read. This field is the address of the register most recently received from the PHY layer. 23−16 rdData RU This field is the contents of a PHY register that has been read. 15 rdReg RWU Bit 15 is set to 1 by software to initiate a read request to a PHY register, and is cleared by hardware when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set to 1 simultaneously. 14 wrReg RWU Bit 14 is set to 1 by software to initiate a write request to a PHY register, and is cleared by hardware when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set to 1 simultaneously. 13−12 RSVD R 11−8 regAddr RW This field is the address of the PHY register to be written or read. 7−0 wrData RW This field is the data to be written to a PHY register and is ignored for reads. 8−30 Reserved. Bits 13 and 12 return 0s when read. 8.34 Isochronous Cycle Timer Register The isochronous cycle timer register indicates the current cycle number and offset. When the PCI4510 device is cycle master, this register is transmitted with the cycle start message. When the PCI4510 device is not cycle master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start message is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference. See Table 8−26 for a complete description of the register contents. Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Isochronous cycle timer RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU Default X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Isochronous cycle timer RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU X X X X X X X X X X X X X X X X Register: Offset: Type: Default: Isochronous cycle timer F0h Read/Write/Update XXXX XXXXh Table 8−26. Isochronous Cycle Timer Register Description BIT FIELD NAME TYPE 31−25 cycleSeconds RWU This field counts seconds [rollovers from bits 24−12 (cycleCount field)] modulo 128. DESCRIPTION 24−12 cycleCount RWU This field counts cycles [rollovers from bits 11−0 (cycleOffset field)] modulo 8000. 11−0 cycleOffset RWU This field counts 24.576-MHz clocks modulo 3072, that is, 125 µs. If an external 8-kHz clock configuration is being used, then this field must be cleared to 0s at each tick of the external clock. 8−31 8.35 Asynchronous Request Filter High Register The asynchronous request filter high set/clear register enables asynchronous receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for either the physical request context or the ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is not set to 1 in this register, then the packet is not acknowledged and the request is not queued. The node ID comparison is done if the source node is on the same bus as the PCI4510 device. Nonlocal bus-sourced packets are not acknowledged unless bit 31 in this register is set to 1. See Table 8−27 for a complete description of the register contents. Bit 31 30 29 28 27 26 RSC RSC RSC RSC RSC RSC RSC RSC RSC Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 RSC RSC RSC RSC RSC RSC RSC RSC RSC 0 0 0 0 0 0 0 0 0 Name Type Default 24 23 22 21 20 19 18 17 16 RSC RSC RSC RSC RSC RSC RSC 0 0 0 0 0 0 0 6 5 4 3 2 1 0 RSC RSC RSC RSC RSC RSC RSC 0 0 0 0 0 0 0 Asynchronous request filter high Name Type 25 Asynchronous request filter high Register: Offset: Type: Default: Asynchronous request filter high 100h set register 104h clear register Read/Set/Clear 0000 0000h Table 8−27. Asynchronous Request Filter High Register Description 8−32 BIT FIELD NAME TYPE DESCRIPTION 31 asynReqAllBuses RSC If bit 31 is set to 1, all asynchronous requests received by the PCI4510 device from nonlocal bus nodes are accepted. 30 asynReqResource62 RSC If bit 30 is set to 1 for local bus node number 62, asynchronous requests received by the PCI4510 device from that node are accepted. 29 asynReqResource61 RSC If bit 29 is set to 1 for local bus node number 61, asynchronous requests received by the PCI4510 device from that node are accepted. 28 asynReqResource60 RSC If bit 28 is set to 1 for local bus node number 60, asynchronous requests received by the PCI4510 device from that node are accepted. 27 asynReqResource59 RSC If bit 27 is set to 1 for local bus node number 59, asynchronous requests received by the PCI4510 device from that node are accepted. 26 asynReqResource58 RSC If bit 26 is set to 1 for local bus node number 58, asynchronous requests received by the PCI4510 device from that node are accepted. 25 asynReqResource57 RSC If bit 25 is set to 1 for local bus node number 57, asynchronous requests received by the PCI4510 device from that node are accepted. 24 asynReqResource56 RSC If bit 24 is set to 1 for local bus node number 56, asynchronous requests received by the PCI4510 device from that node are accepted. 23 asynReqResource55 RSC If bit 23 is set to 1 for local bus node number 55, asynchronous requests received by the PCI4510 device from that node are accepted. 22 asynReqResource54 RSC If bit 22 is set to 1 for local bus node number 54, asynchronous requests received by the PCI4510 device from that node are accepted. 21 asynReqResource53 RSC If bit 21 is set to 1 for local bus node number 53, asynchronous requests received by the PCI4510 device from that node are accepted. 20 asynReqResource52 RSC If bit 20 is set to 1 for local bus node number 52, asynchronous requests received by the PCI4510 device from that node are accepted. 19 asynReqResource51 RSC If bit 19 is set to 1 for local bus node number 51, asynchronous requests received by the PCI4510 device from that node are accepted. Table 8−27. Asynchronous Request Filter High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 18 asynReqResource50 RSC If bit 18 is set to 1 for local bus node number 50, asynchronous requests received by the PCI4510 device from that node are accepted. 17 asynReqResource49 RSC If bit 17 is set to 1 for local bus node number 49, asynchronous requests received by the PCI4510 device from that node are accepted. 16 asynReqResource48 RSC If bit 16 is set to 1 for local bus node number 48, asynchronous requests received by the PCI4510 device from that node are accepted. 15 asynReqResource47 RSC If bit 15 is set to 1 for local bus node number 47, asynchronous requests received by the PCI4510 device from that node are accepted. 14 asynReqResource46 RSC If bit 14 is set to 1 for local bus node number 46, asynchronous requests received by the PCI4510 device from that node are accepted. 13 asynReqResource45 RSC If bit 13 is set to 1 for local bus node number 45, asynchronous requests received by the PCI4510 device from that node are accepted. 12 asynReqResource44 RSC If bit 12 is set to 1 for local bus node number 44, asynchronous requests received by the PCI4510 device from that node are accepted. 11 asynReqResource43 RSC If bit 11 is set to 1 for local bus node number 43, asynchronous requests received by the PCI4510 device from that node are accepted. 10 asynReqResource42 RSC If bit 10 is set to 1 for local bus node number 42, asynchronous requests received by the PCI4510 device from that node are accepted. 9 asynReqResource41 RSC If bit 9 is set to 1 for local bus node number 41, asynchronous requests received by the PCI4510 device from that node are accepted. 8 asynReqResource40 RSC If bit 8 is set to 1 for local bus node number 40, asynchronous requests received by the PCI4510 device from that node are accepted. 7 asynReqResource39 RSC If bit 7 is set to 1 for local bus node number 39, asynchronous requests received by the PCI4510 device from that node are accepted. 6 asynReqResource38 RSC If bit 6 is set to 1 for local bus node number 38, asynchronous requests received by the PCI4510 device from that node are accepted. 5 asynReqResource37 RSC If bit 5 is set to 1 for local bus node number 37, asynchronous requests received by the PCI4510 device from that node are accepted. 4 asynReqResource36 RSC If bit 4 is set to 1 for local bus node number 36, asynchronous requests received by the PCI4510 device from that node are accepted. 3 asynReqResource35 RSC If bit 3 is set to 1 for local bus node number 35, asynchronous requests received by the PCI4510 device from that node are accepted. 2 asynReqResource34 RSC If bit 2 is set to 1 for local bus node number 34, asynchronous requests received by the PCI4510 device from that node are accepted. 1 asynReqResource33 RSC If bit 1 is set to 1 for local bus node number 33, asynchronous requests received by the PCI4510 device from that node are accepted. 0 asynReqResource32 RSC If bit 0 is set to 1 for local bus node number 32, asynchronous requests received by the PCI4510 device from that node are accepted. 8−33 8.36 Asynchronous Request Filter Low Register The asynchronous request filter low set/clear register enables asynchronous receive requests on a per-node basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to the asynchronous request filter high register. See Table 8−28 for a complete description of the register contents. Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Asynchronous request filter low RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Asynchronous request filter low RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Asynchronous request filter low 108h set register 10Ch clear register Read/Set/Clear 0000 0000h Table 8−28. Asynchronous Request Filter Low Register Description BIT FIELD NAME TYPE DESCRIPTION 31 asynReqResource31 RSC If bit 31 is set to 1 for local bus node number 31, asynchronous requests received by the PCI4510 device from that node are accepted. 30 asynReqResource30 RSC If bit 30 is set to 1 for local bus node number 30, asynchronous requests received by the PCI4510 device from that node are accepted. 29−2 asynReqResourcen RSC Bits 29 through 2 (asynReqResourcen, where n = 29, 28, 27, …, 2) follow the same pattern as bits 31 and 30. 1 asynReqResource1 RSC If bit 1 is set to 1 for local bus node number 1, asynchronous requests received by the PCI4510 device from that node are accepted. 0 asynReqResource0 RSC If bit 0 is set to 1 for local bus node number 0, asynchronous requests received by the PCI4510 device from that node are accepted. 8−34 8.37 Physical Request Filter High Register The physical request filter high set/clear register enables physical receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for the physical request context, and the node ID has been compared against the ARRQ registers, then the comparison is done again with this register. If the bit corresponding to the node ID is not set to 1 in this register, then the request is handled by the ARRQ context instead of the physical request context. The node ID comparison is done if the source node is on the same bus as the PCI4510 device. Nonlocal bus-sourced packets are not acknowledged unless bit 31 in this register is set to 1. See Table 8−29 for a complete description of the register contents. Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Physical request filter high RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name Type Default Physical request filter high Register: Offset: Type: Default: Physical request filter high 110h set register 114h clear register Read/Set/Clear 0000 0000h Table 8−29. Physical Request Filter High Register Description BIT FIELD NAME TYPE DESCRIPTION 31 physReqAllBusses RSC If bit 31 is set to 1, all asynchronous requests received by the PCI4510 device from nonlocal bus nodes are accepted. Bit 31 is not cleared by a PRST. 30 physReqResource62 RSC If bit 30 is set to 1 for local bus node number 62, physical requests received by the PCI4510 device from that node are handled through the physical request context. 29 physReqResource61 RSC If bit 29 is set to 1 for local bus node number 61, physical requests received by the PCI4510 device from that node are handled through the physical request context. 28 physReqResource60 RSC If bit 28 is set to 1 for local bus node number 60, physical requests received by the PCI4510 device from that node are handled through the physical request context. 27 physReqResource59 RSC If bit 27 is set to 1 for local bus node number 59, physical requests received by the PCI4510 device from that node are handled through the physical request context. 26 physReqResource58 RSC If bit 26 is set to 1 for local bus node number 58, physical requests received by the PCI4510 device from that node are handled through the physical request context. 25 physReqResource57 RSC If bit 25 is set to 1 for local bus node number 57, physical requests received by the PCI4510 device from that node are handled through the physical request context. 24 physReqResource56 RSC If bit 24 is set to 1 for local bus node number 56, physical requests received by the PCI4510 device from that node are handled through the physical request context. 23 physReqResource55 RSC If bit 23 is set to 1 for local bus node number 55, physical requests received by the PCI4510 device from that node are handled through the physical request context. 22 physReqResource54 RSC If bit 22 is set to 1 for local bus node number 54, physical requests received by the PCI4510 device from that node are handled through the physical request context. 21 physReqResource53 RSC If bit 21 is set to 1 for local bus node number 53, physical requests received by the PCI4510 device from that node are handled through the physical request context. 20 physReqResource52 RSC If bit 20 is set to 1 for local bus node number 52, physical requests received by the PCI4510 device from that node are handled through the physical request context. 19 physReqResource51 RSC If bit 19 is set to 1 for local bus node number 51, physical requests received by the PCI4510 device from that node are handled through the physical request context. 8−35 Table 8−29. Physical Request Filter High Register Description (Continued) 8−36 BIT FIELD NAME TYPE DESCRIPTION 18 physReqResource50 RSC If bit 18 is set to 1 for local bus node number 50, physical requests received by the PCI4510 device from that node are handled through the physical request context. 17 physReqResource49 RSC If bit 17 is set to 1 for local bus node number 49, physical requests received by the PCI4510 device from that node are handled through the physical request context. 16 physReqResource48 RSC If bit 16 is set to 1 for local bus node number 48, physical requests received by the PCI4510 device from that node are handled through the physical request context. 15 physReqResource47 RSC If bit 15 is set to 1 for local bus node number 47, physical requests received by the PCI4510 device from that node are handled through the physical request context. 14 physReqResource46 RSC If bit 14 is set to 1 for local bus node number 46, physical requests received by the PCI4510 device from that node are handled through the physical request context. 13 physReqResource45 RSC If bit 13 is set to 1 for local bus node number 45, physical requests received by the PCI4510 device from that node are handled through the physical request context. 12 physReqResource44 RSC If bit 12 is set to 1 for local bus node number 44, physical requests received by the PCI4510 device from that node are handled through the physical request context. 11 physReqResource43 RSC If bit 11 is set to 1 for local bus node number 43, physical requests received by the PCI4510 device from that node are handled through the physical request context. 10 physReqResource42 RSC If bit 10 is set to 1 for local bus node number 42, physical requests received by the PCI4510 device from that node are handled through the physical request context. 9 physReqResource41 RSC If bit 9 is set to 1 for local bus node number 41, physical requests received by the PCI4510 device from that node are handled through the physical request context. 8 physReqResource40 RSC If bit 8 is set to 1 for local bus node number 40, physical requests received by the PCI4510 device from that node are handled through the physical request context. 7 physReqResource39 RSC If bit 7 is set to 1 for local bus node number 39, physical requests received by the PCI4510 device from that node are handled through the physical request context. 6 physReqResource38 RSC If bit 6 is set to 1 for local bus node number 38, physical requests received by the PCI4510 device from that node are handled through the physical request context. 5 physReqResource37 RSC If bit 5 is set to 1 for local bus node number 37, physical requests received by the PCI4510 device from that node are handled through the physical request context. 4 physReqResource36 RSC If bit 4 is set to 1 for local bus node number 36, physical requests received by the PCI4510 device from that node are handled through the physical request context. 3 physReqResource35 RSC If bit 3 is set to 1 for local bus node number 35, physical requests received by the PCI4510 device from that node are handled through the physical request context. 2 physReqResource34 RSC If bit 2 is set to 1 for local bus node number 34, physical requests received by the PCI4510 device from that node are handled through the physical request context. 1 physReqResource33 RSC If bit 1 is set to 1 for local bus node number 33, physical requests received by the PCI4510 device from that node are handled through the physical request context. 0 physReqResource32 RSC If bit 0 is set to 1 for local bus node number 32, physical requests received by the PCI4510 device from that node are handled through the physical request context. 8.38 Physical Request Filter Low Register The physical request filter low set/clear register enables physical receive requests on a per-node basis, and handles the lower node IDs. When a packet is destined for the physical request context, and the node ID has been compared against the asynchronous request filter registers, then the node ID comparison is done again with this register. If the bit corresponding to the node ID is not set to 1 in this register, then the request is handled by the asynchronous request context instead of the physical request context. See Table 8−30 for a complete description of the register contents. Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Physical request filter low RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Physical request filter low RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Physical request filter low 118h set register 11Ch clear register Read/Set/Clear 0000 0000h Table 8−30. Physical Request Filter Low Register Description BIT FIELD NAME TYPE DESCRIPTION 31 physReqResource31 RSC If bit 31 is set to 1 for local bus node number 31, physical requests received by the PCI4510 device from that node are handled through the physical request context. 30 physReqResource30 RSC If bit 30 is set to 1 for local bus node number 30, physical requests received by the PCI4510 device from that node are handled through the physical request context. 29−2 physReqResourcen RSC Bits 29 through 2 (physReqResourcen, where n = 29, 28, 27, …, 2) follow the same pattern as bits 31 and 30. 1 physReqResource1 RSC If bit 1 is set to 1 for local bus node number 1, physical requests received by the PCI4510 device from that node are handled through the physical request context. 0 physReqResource0 RSC If bit 0 is set to 1 for local bus node number 0, physical requests received by the PCI4510 device from that node are handled through the physical request context. 8.39 Physical Upper Bound Register (Optional Register) The physical upper bound register is an optional register and is not implemented. This register returns all 0s when read. Bit 31 30 29 28 27 26 25 Name 24 23 22 21 20 19 18 17 16 Physical upper bound Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Physical upper bound Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Physical upper bound 120h Read-only 0000 0000h 8−37 8.40 Asynchronous Context Control Register The asynchronous context control set/clear register controls the state and indicates status of the DMA context. See Table 8−31 for a complete description of the register contents. Bit 31 30 29 28 27 26 Name 25 24 23 22 21 20 19 18 17 16 Asynchronous context control Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Asynchronous context control RSCU R R RSU RU RU R R RU RU RU RU RU RU RU RU 0 0 0 X 0 0 0 0 X X X X X X X X Register: Offset: Type: Default: Asynchronous context control 180h set register [ATRQ] 184h clear register [ATRQ] 1A0h set register [ATRS] 1A4h clear register [ATRS] 1C0h set register [ARRQ] 1C4h clear register [ARRQ] 1E0h set register [ARRS] 1E4h clear register [ARRS] Read/Set/Clear/Update, Read/Set/Update, Read/Update, Read-only 0000 X0XXh Table 8−31. Asynchronous Context Control Register Description BIT FIELD NAME TYPE 31−16 RSVD R 15 run RSCU 14−13 RSVD R 12 wake RSU Software sets bit 12 to 1 to cause the PCI4510 device to continue or resume descriptor processing. The PCI4510 device clears this bit on every descriptor fetch. 11 dead RU The PCI4510 device sets bit 11 to 1 when it encounters a fatal error, and clears the bit when software clears bit 15 (run). Asynchronous contexts supporting out-of-order pipelining provide unique ContextControl.dead functionality. See Section 7.7 in the 1394 Open Host Controller Interface Specification (Release 1.1) for more information. The PCI4510 device sets bit 10 to 1 when it is processing descriptors. 10 active RU 9−8 RSVD R 7−5 spd RU DESCRIPTION Reserved. Bits 31−16 return 0s when read. Bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. The PCI4510 device changes this bit only on a system (hardware) or software reset. Reserved. Bits 14 and 13 return 0s when read. Reserved. Bits 9 and 8 return 0s when read. This field indicates the speed at which a packet was received or transmitted and only contains meaningful information for receive contexts. This field is encoded as: 000 = 100M bits/sec 001 = 200M bits/sec 010 = 400M bits/sec All other values are reserved. 4−0 8−38 eventcode RU This field holds the acknowledge sent by the link core for this packet or an internally generated error code if the packet was not transferred successfully. 8.41 Asynchronous Context Command Pointer Register The asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the PCI4510 device accesses when software enables the context by setting bit 15 (run) in the asynchronous context control register (see Section 8.40) to 1. See Table 8−32 for a complete description of the register contents. Bit 31 30 29 28 27 Name Type 26 25 24 23 22 21 20 19 18 17 16 Asynchronous context command pointer RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU Default X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Asynchronous context command pointer RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU X X X X X X X X X X X X X X X X Register: Offset: Type: Default: Asynchronous context command pointer 18Ch [ATRQ] 1ACh [ATRS] 1CCh [ARRQ] 1ECh [ARRS] Read/Write/Update XXXX XXXXh Table 8−32. Asynchronous Context Command Pointer Register Description BIT FIELD NAME TYPE DESCRIPTION 31−4 descriptorAddress RWU Contains the upper 28 bits of the address of a 16-byte aligned descriptor block. 3−0 Z RWU Indicates the number of contiguous descriptors at the address pointed to by the descriptor address. If Z is 0, then it indicates that the descriptorAddress field (bits 31−4) is not valid. 8−39 8.42 Isochronous Transmit Context Control Register The isochronous transmit context control set/clear register controls options, state, and status for the isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, …, 7). See Table 8−33 for a complete description of the register contents. Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Isochronous transmit context control RSCU RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Isochronous transmit context control RSC R R RSU RU RU R R RU RU RU RU RU RU RU RU 0 0 0 X 0 0 0 0 X X X X X X X X Register: Offset: Type: Default: Isochronous transmit context control 200h + (16 * n) set register 204h + (16 * n) clear register Read/Set/Clear/Update, Read/Set/Clear, Read/Set/Update, Read/Update, Read-only XXXX X0XXh Table 8−33. Isochronous Transmit Context Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31 cycleMatchEnable RSCU When bit 31 is set to 1, processing occurs such that the packet described by the context first descriptor block is transmitted in the cycle whose number is specified in the cycleMatch field (bits 30−16). The cycleMatch field (bits 30−16) must match the low-order two bits of cycleSeconds and the 13-bit cycleCount field in the cycle start packet that is sent or received immediately before isochronous transmission begins. Since the isochronous transmit DMA controller may work ahead, the processing of the first descriptor block may begin slightly in advance of the actual cycle in which the first packet is transmitted. The effects of this bit, however, are impacted by the values of other bits in this register and are explained in the 1394 Open Host Controller Interface Specification. Once the context has become active, hardware clears this bit. 30−16 cycleMatch RSC This field contains a 15-bit value, corresponding to the low-order two bits of the isochronous cycle timer register at OHCI offset F0h (see Section 8.34) cycleSeconds field (bits 31−25) and the cycleCount field (bits 24−12). If bit 31 (cycleMatchEnable) is set to 1, then this isochronous transmit DMA context becomes enabled for transmits when the low-order two bits of the isochronous cycle timer register at OHCI offset F0h cycleSeconds field (bits 31−25) and the cycleCount field (bits 24−12) value equal this field (cycleMatch) value. 15 run RSC Bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. The PCI4510 device changes this bit only on a system (hardware) or software reset. 14−13 RSVD R 12 wake RSU Software sets bit 12 to 1 to cause the PCI4510 device to continue or resume descriptor processing. The PCI4510 device clears this bit on every descriptor fetch. 11 dead RU The PCI4510 device sets bit 11 to 1 when it encounters a fatal error, and clears the bit when software clears bit 15 (run) to 0. 10 active RU The PCI4510 device sets bit 10 to 1 when it is processing descriptors. 9−8 RSVD R 7−5 spd RU This field in not meaningful for isochronous transmit contexts. 4−0 event code RU Following an OUTPUT_LAST* command, the error code is indicated in this field. Possible values are: ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown. Reserved. Bits 14 and 13 return 0s when read. Reserved. Bits 9 and 8 return 0s when read. † On an overflow for each running context, the isochronous transmit DMA supports up to 7 cycle skips, when the following are true: 1. Bit 11 (dead) in either the isochronous transmit or receive context control register is set to 1. 2. Bits 4−0 (eventcode field) in either the isochronous transmit or receive context control register is set to evt_timeout. 3. Bit 24 (unrecoverableError) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) is set to 1. 8−40 8.43 Isochronous Transmit Context Command Pointer Register The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the PCI4510 device accesses when software enables an isochronous transmit context by setting bit 15 (run) in the isochronous transmit context control register (see Section 8.42) to 1. The isochronous transmit DMA context command pointer can be read when a context is active. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, …, 7). Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Isochronous transmit context command pointer R R R R R R R R R R R R R R R R Default X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Type R R R R R R R R R R R R R R R R Default X X X X X X X X X X X X X X X X Name Isochronous transmit context command pointer Register: Offset: Type: Default: Isochronous transmit context command pointer 20Ch + (16 * n) Read-only XXXX XXXXh 8.44 Isochronous Receive Context Control Register The isochronous receive context control set/clear register controls options, state, and status for the isochronous receive DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). See Table 8−34 for a complete description of the register contents. Bit 31 30 29 28 27 26 RSC RSC RSCU RSC RSC R R R R Default X X X X X 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name Type Default 24 23 22 21 20 19 18 17 16 R R R R R R R 0 0 0 0 0 0 0 6 5 4 3 2 1 0 Isochronous receive context control Name Type 25 Isochronous receive context control RSCU R R RSU RU RU R R RU RU RU RU RU RU RU RU 0 0 0 X 0 0 0 0 X X X X X X X X Register: Offset: Isochronous receive context control 400h + (32 * n) set register 404h + (32 * n) clear register Read/Set/Clear/Update, Read/Set/Clear, Read/Set/Update, Read/Update, Read-only XX00 X0XXh Type: Default: Table 8−34. Isochronous Receive Context Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31 bufferFill RSC When bit 31 is set to 1, received packets are placed back-to-back to completely fill each receive buffer. When this bit is cleared, each received packet is placed in a single buffer. If bit 28 (multiChanMode) is set to 1, then this bit must also be set to 1. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1. 30 isochHeader RSC When bit 30 is set to 1, received isochronous packets include the complete 4-byte isochronous packet header seen by the link layer. The end of the packet is marked with a xferStatus in the first doublet, and a 16-bit timeStamp indicating the time of the most recently received (or sent) cycleStart packet. When this bit is cleared, the packet header is stripped from received isochronous packets. The packet header, if received, immediately precedes the packet payload. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1. 8−41 Table 8−34. Isochronous Receive Context Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 29 cycleMatchEnable RSCU When bit 29 is set to 1 and the 13-bit cycleMatch field (bits 24−12) in the isochronous receive context match register (See Section 8.46) matches the 13-bit cycleCount field in the cycleStart packet, the context begins running. The effects of this bit, however, are impacted by the values of other bits in this register. Once the context has become active, hardware clears this bit. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1. 28 multiChanMode RSC When bit 28 is set to 1, the corresponding isochronous receive DMA context receives packets for all isochronous channels enabled in the isochronous receive channel mask high register at OHCI offset 70h/74h (see Section 8.19) and isochronous receive channel mask low register at OHCI offset 78h/7Ch (see Section 8.20). The isochronous channel number specified in the isochronous receive context match register (see Section 8.46) is ignored. When this bit is cleared, the isochronous receive DMA context receives packets for the single channel specified in the isochronous receive context match register (see Section 8.46). Only one isochronous receive DMA context may use the isochronous receive channel mask registers (see Sections 8.19, and 8.20). If more than one isochronous receive context control register has this bit set, then the results are undefined. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1. 27 dualBufferMode RSC When bit 27 is set to 1, receive packets are separated into first and second payload and streamed independently to the firstBuffer series and secondBuffer series as described in Section 10.2.3 in the 1394 Open Host Controller Interface Specification. Also, when bit 27 is set to 1, both bits 28 (multiChanMode) and 31 (bufferFill) are cleared to 0. The value of this bit does not change when either bit 10 (active) or bit 15 (run) is set to 1. 26−16 RSVD R 15 run RSCU 14−13 RSVD R 12 wake RSU Software sets bit 12 to 1 to cause the PCI4510 device to continue or resume descriptor processing. The PCI4510 device clears this bit on every descriptor fetch. 11 dead RU The PCI4510 device sets bit 11 to 1 when it encounters a fatal error, and clears the bit when software clears bit 15 (run). 10 active RU The PCI4510 device sets bit 10 to 1 when it is processing descriptors. 9−8 RSVD R 7−5 spd RU Reserved. Bits 26−16 return 0s when read. Bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. The PCI4510 device changes this bit only on a system (hardware) or software reset. Reserved. Bits 14 and 13 return 0s when read. Reserved. Bits 9 and 8 return 0s when read. This field indicates the speed at which the packet was received. 000 = 100M bits/sec 001 = 200M bits/sec 010 = 400M bits/sec All other values are reserved. 4−0 8−42 event code RU For bufferFill mode, possible values are: ack_complete, evt_descriptor_read, evt_data_write, and evt_unknown. Packets with data errors (either dataLength mismatches or dataCRC errors) and packets for which a FIFO overrun occurred are backed out. For packet-per-buffer mode, possible values are: ack_complete, ack_data_error, evt_long_packet, evt_overrun, evt_descriptor_read, evt_data_write, and evt_unknown. 8.45 Isochronous Receive Context Command Pointer Register The isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the PCI4510 device accesses when software enables an isochronous receive context by setting bit 15 (run) in the isochronous receive context control register (see Section 8.44) to 1. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). Bit 31 30 29 28 27 Name 26 25 24 23 22 21 20 19 18 17 16 Isochronous receive context command pointer Type R R R R R R R R R R R R R R R R Default X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Isochronous receive context command pointer Type R R R R R R R R R R R R R R R R Default X X X X X X X X X X X X X X X X Register: Offset: Type: Default: Isochronous receive context command pointer 40Ch + (32 * n) Read-only XXXX XXXXh 8−43 8.46 Isochronous Receive Context Match Register The isochronous receive context match register starts an isochronous receive context running on a specified cycle number, filters incoming isochronous packets based on tag values, and waits for packets with a specified sync value. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). See Table 8−35 for a complete description of the register contents. Bit 31 30 29 28 27 26 Name Type 25 24 23 22 21 20 19 18 17 16 Isochronous receive context match RW RW RW RW R RW RW RW RW RW RW RW RW RW RW RW Default X X X X 0 0 0 X X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Isochronous receive context match RW RW RW RW RW RW RW RW R RW RW RW RW RW RW RW X X X X X X X X 0 X X X X X X X Register: Offset: Type: Default: Isochronous receive context match 410Ch + (32 * n) Read/Write, Read-only XXXX XXXXh Table 8−35. Isochronous Receive Context Match Register Description BIT FIELD NAME TYPE 31 tag3 RW If bit 31 is set to 1, this context matches on isochronous receive packets with a tag field of 11b. 30 tag2 RW If bit 30 is set to 1, this context matches on isochronous receive packets with a tag field of 10b. 29 tag1 RW If bit 29 is set to 1, this context matches on isochronous receive packets with a tag field of 01b. 28 tag0 RW If bit 28 is set to 1, this context matches on isochronous receive packets with a tag field of 00b. 27 RSVD R 26−12 cycleMatch RW This field contains a 15-bit value corresponding to the two low-order bits of cycleSeconds and the 13-bit cycleCount field in the cycleStart packet. If cycleMatchEnable (bit 29) in the isochronous receive context control register (see Section 8.44) is set to 1, then this context is enabled for receives when the two low-order bits of the isochronous cycle timer register at OHCI offset F0h (see Section 8.34) cycleSeconds field (bits 31−25) and cycleCount field (bits 24−12) value equal this field (cycleMatch) value. 11−8 sync RW This 4-bit field is compared to the sync field of each isochronous packet for this channel when the command descriptor w field is set to 11b. 7 RSVD R 6 tag1SyncFilter RW DESCRIPTION Reserved. Bit 27 returns 0 when read. Reserved. Bit 7 returns 0 when read. If bit 6 and bit 29 (tag1) are set to 1, then packets with tag 01b are accepted into the context if the two most significant bits of the packet sync field are 00b. Packets with tag values other than 01b are filtered according to bit 28 (tag0), bit 30 (tag2), and bit 31 (tag3) without any additional restrictions. If this bit is cleared, then this context matches on isochronous receive packets as specified in bits 28−31 (tag0−tag3) with no additional restrictions. 5−0 8−44 channelNumber RW This 6-bit field indicates the isochronous channel number for which this isochronous receive DMA context accepts packets. 9 TI Extension Registers The TI extension base address register provides a method of accessing memory-mapped TI extension registers. See Section 7.9, TI Extension Base Address Register, for register bit field details. See Table 9−1 for the TI extension register listing. Table 9−1. TI Extension Register Map REGISTER NAME OFFSET Reserved 00h−A7Fh Isochronous receive DV enhancement set A80h Isochronous receive DV enhancement clear A84h Link enhancement control set A88h Link enhancement control clear A8Ch Isochronous transmit context 0 timestamp offset A90h Isochronous transmit context 1 timestamp offset A94h Isochronous transmit context 2 timestamp offset A98h Isochronous transmit context 3 timestamp offset A9Ch Isochronous transmit context 4 timestamp offset AA0h Isochronous transmit context 5 timestamp offset AA4h Isochronous transmit context 6 timestamp offset AA8h Isochronous transmit context 7 timestamp offset AA8h 9.1 DV and MPEG2 Timestamp Enhancements The DV timestamp enhancements are enabled by bit 8 (enab_dv_ts) in the link enhancement control register located at PCI offset F4h and are aliased in TI extension register space at offset A88h (set) and A8Ch (clear). The DV and MPEG transmit enhancements are enabled separately by bits in the link enhancement control register located in PCI configuration space at PCI offset F4h. The link enhancement control register is also aliased as a set/clear register in TI extension space at offset A88h (set) and A8Ch (clear). Bit 8 (enab_dv_ts) of the link enhancement control register enables DV timestamp support. When enabled, the link calculates a timestamp based on the cycle timer and the timestamp offset register and substitutes it in the SYT field of the CIP once per DV frame. Bit 10 (enab_mpeg_ts) of the link enhancement control register enables MPEG timestamp support. Two MPEG time stamp modes are supported. The default mode calculates an initial delta that is added to the calculated timestamp in addition to a user-defined offset. The initial offset is calculated as the difference in the intended transmit cycle count and the cycle count field of the timestamp in the first TSP of the MPEG2 stream. The use of the initial delta can be controlled by bit 31 (DisableInitialOffset) in the timestamp offset register (see Section 9.5). The MPEG2 timestamp enhancements are enabled by bit 10 (enab_mpeg_ts) in the link enhancement control register located at PCI offset F4h and aliased in TI extension register space at offset A88h (set) and A8Ch (clear). When bit 10 (enab_mpeg_ts) is set to 1, the hardware applies the timestamp enhancements to isochronous transmit packets that have the tag field equal to 01b in the isochronous packet header and a FMT field equal to 10h. 9−1 9.2 Isochronous Receive Digital Video Enhancements The DV frame sync and branch enhancement provides a mechanism in buffer-fill mode to synchronize 1394 DV data that is received in the correct order to DV frame-sized data buffers described by several INPUT_MORE descriptors (see 1394 Open Host Controller Interface Specification, Release 1.1). This is accomplished by waiting for the start-of-frame packet in a DV stream before transferring the received isochronous stream into the memory buffer described by the INPUT_MORE descriptors. This can improve the DV capture application performance by reducing the amount of processing overhead required to strip the CIP header and copy the received packets into frame-sized buffers. The start of a DV frame is represented in the 1394 packet as a 16-bit pattern of 1FX7h (first byte 1Fh and second byte X7h) received as the first two bytes of the third quadlet in a DV isochronous packet. 9.3 Isochronous Receive Digital Video Enhancements Register The isochronous receive digital video enhancements register enables the DV enhancements in the PCI4510 device. The bits in this register may only be modified when both the active (bit 10) and run (bit 15) bits of the corresponding context control register are 0. See Table 9−2 for a complete description of the register contents. Bit 31 30 29 28 27 R R R R R Name Type 26 25 24 23 22 21 20 19 18 17 16 Isochronous receive digital video enhancements R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Isochronous receive digital video enhancements Type R R RSC RSC R R RSC RSC R R RSC RSC R R RSC RSC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Isochronous receive digital video enhancements A80h set register A84h clear register Read/Set/Clear, Read-only 0000 0000h Table 9−2. Isochronous Receive Digital Video Enhancements Register Description BIT FIELD NAME TYPE DESCRIPTION 31−14 RSVD R 13 DV_Branch3 RSC Reserved. Bits 31−14 return 0s when read. When bit 13 is set to 1, the isochronous receive context 3 synchronizes reception to the DV frame start tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 12 (CIP_Strip3) is set to 1 and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 460h/464h (see Section 8.44) is cleared to 0. 12 CIP_Strip3 RSC When bit 12 is set to 1, the isochronous receive context 3 strips the first two quadlets of payload. This bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 460h/464h (see Section 8.44) is cleared to 0. 11−10 RSVD R 9 DV_Branch2 RSC When bit 9 is set to 1, the isochronous receive context 2 synchronizes reception to the DV frame start tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 8 (CIP_Strip2) is set to 1 and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 440h/444h (see Section 8.44) is cleared to 0. 8 CIP_Strip2 RSC When bit 8 is set to 1, the isochronous receive context 2 strips the first two quadlets of payload. This bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 440h/444h (see Section 8.44) is cleared to 0. 9−2 Reserved. Bits 11 and 10 return 0s when read. Table 9−2. Isochronous Receive Digital Video Enhancements Register Description (Continued) BIT FIELD NAME TYPE 7−6 RSVD R DESCRIPTION 5 DV_Branch1 RSC When bit 5 is set to 1, the isochronous receive context 1 synchronizes reception to the DV frame start tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 4 (CIP_Strip1) is set to 1 and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 420h/424h (see Section 8.44) is cleared to 0. 4 CIP_Strip1 RSC When bit 4 is set to 1, the isochronous receive context 1 strips the first two quadlets of payload. This bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 420h/424h (see Section 8.44) is cleared to 0. 3−2 RSVD R 1 DV_Branch0 RSC When bit 1 is set to 1, the isochronous receive context 0 synchronizes reception to the DV frame start tag in bufferfill mode if input_more.b = 01b and jumps to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 0 (CIP_Strip0) is set to 1 and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 400h/404h (see Section 8.44) is cleared to 0. 0 CIP_Strip0 RSC When bit 0 is set to 1, the isochronous receive context 0 strips the first two quadlets of payload. This bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 400h/404h (see Section 8.44) is cleared to 0. Reserved. Bits 7 and 6 return 0s when read. Reserved. Bits 3 and 2 return 0s when read. 9−3 9.4 Link Enhancement Register This register is a memory-mapped set/clear register that is an alias of the link enhancement control register at PCI offset F4h. These bits may be initialized by software. Some of the bits may also be initialized by a serial EEPROM, if one is present, as noted in the bit descriptions below. If the bits are to be initialized by software, then the bits must be initialized prior to setting bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see Section 8.16). See Table 9−3 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name Default 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Link enhancement Name Type 24 Link enhancement RSC R RSC RSC R RSC R RSC RSC R R R R R RSC R 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Link enhancement A88h set register A8Ch clear register Read/Set/Clear, Read-only 0000 0000h Table 9−3. Link Enhancement Register Description BIT FIELD NAME TYPE 31−16 RSVD R 15 dis_at_pipeline RSC 14 RSVD R 13−12 atx_thresh RSC DESCRIPTION Reserved. Bits 31−16 return 0s when read. Disable AT pipelining. When bit 15 is set to 1, out-of-order AT pipelining is disabled. Reserved. This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the PCI4510 device retries the packet, it uses a 2K-byte threshold, resulting in a store-and-forward operation. 00 = Threshold ~ 2K bytes resulting in a store-and-forward operation 01 = Threshold ~ 1.7K bytes (default) 10 = Threshold ~ 1K bytes 11 = Threshold ~ 512 bytes These bits fine-tune the asynchronous transmit threshold. For most applications the 1.7K-byte threshold is optimal. Changing this value may increase or decrease the 1394 latency depending on the average PCI bus latency. Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than the AT threshold, then the remaining data must be received before the AT FIFO is emptied; otherwise, an underrun condition occurs, resulting in a packet error at the receiving node. As a result, the link then commences store-and-forward operation. Wait until it has the complete packet in the FIFO before retransmitting it on the second attempt, to ensure delivery. An AT threshold of 2K results in store-and-forward operation, which means that asynchronous data will not be transmitted until an end-of-packet token is received. Restated, setting the AT threshold to 2K results in only complete packets being transmitted. Note that this device always uses store-and-forward when the asynchronous transmit retries register at OHCI offset 08h (see Section 8.3) is cleared. 9−4 11 RSVD R 10 enab_mpeg_ts RSC 9 RSVD R 8 enab_dv_ts RSC Reserved. Bit 11 returns 0 when read. Enable MPEG timestamp enhancements. When bit 10 is set to 1, the enhancement is enabled for MPEG transmit streams (FMT = 20h). Reserved. Bit 9 returns 0 when read. Enable DV CIP timestamp enhancement. When bit 8 is set to 1, the enhancement is enabled for DV CIP transmit streams (FMT = 00h). Table 9−3. Link Enhancement Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 7 enab_unfair RSC Enable asynchronous priority requests. OHCI-Lynx compatible. Setting bit 7 to 1 enables the link to respond to requests with priority arbitration. It is recommended that this bit be set to 1. 6 RSVD R This bit is not assigned in the PCI4510 follow-on products, since this bit location loaded by the serial EEPROM from the enhancements field corresponds to bit 23 (programPhyEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16). Reserved. Bits 5−2 return 0s when read. 5−2 RSVD R 1 enab_accel RSC 0 RSVD R Enable acceleration enhancements. OHCI-Lynx compatible. When bit 1 is set to 1, the PHY layer is notified that the link supports the IEEE Std 1394a-2000 acceleration enhancements, that is, ack-accelerated, fly-by concatenation, etc. It is recommended that this bit be set to 1. Reserved. Bit 0 returns 0 when read. 9.5 Timestamp Offset Register The value of this register is added as an offset to the cycle timer value when using the MPEG, DV, and CIP enhancements. A timestamp offset register is implemented per isochronous transmit context. The n value following the offset indicates the context number (n = 0, 1, 2, 3, …, 7). These registers are programmed by software as appropriate. See Table 9−4 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 Timestamp offset RW R R R R R R RW RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name Type Default Timestamp offset Register: Offset: Type: Default: Timestamp offset A90h + (4*n) Read/Write, Read-only 0000 0000h Table 9−4. Timestamp Offset Register Description BIT FIELD NAME TYPE DESCRIPTION 31 DisableInitialOffset RW Bit 31 disables the use of the initial timestamp offset when the MPEG2 enhancements are enabled. A value of 0 indicates the use of the initial offset, a value of 1 indicates that the initial offset must not be applied to the calculated timestamp. This bit has no meaning for the DV timestamp enhancements. 30−25 RSVD R 24−12 CycleCount RW Reserved. Bits 30−25 return 0s when read. This field adds an offset to the cycle count field in the timestamp when the DV or MPEG2 enhancements are enabled. The cycle count field is incremented modulo 8000; therefore, values in this field must be limited between 0 and 7999. 11−0 CycleOffset RW This field adds an offset to the cycle offset field in the timestamp when the DV or MPEG2 enhancements are enabled. The cycle offset field is incremented modulo 3072; therefore, values in this field must be limited between 0 and 3071. 9−5 9−6 10 PHY Register Configuration There are 16 accessible internal registers in the PCI4510 device. The configuration of the registers at addresses 0h through 7h (the base registers) is fixed, whereas the configuration of the registers at addresses 8h through Fh (the paged registers) is dependent upon which one of eight pages, numbered 0h through 7h, is currently selected. The selected page is set in base register 7h. 10.1 Base Registers Table 10−1 shows the configuration of the base registers, and Table 10−2 shows the corresponding field descriptions. The base register field definitions are unaffected by the selected page number. A reserved register or register field (marked as Reserved in the following register configuration tables) is read as 0, but is subject to future usage. All registers in address pages 2 through 6 are reserved. Table 10−1. Base Register Configuration BIT POSITION ADDRESS 0 1 0000 0001 2 3 4 5 Physical ID RHB IBR 6 7 R CPS Gap_Count 0010 Extended (111b) Reserved Total_Ports (0010b) 0011 Max_Speed (010b) Reserved Delay (0000b) 0100 LCtrl C 0101 Watchdog ISBR 0110 0111 Jitter (000b) Loop Pwr_fail Pwr_Class Timeout Port_event Enab_accel Enab_multi Reserved Page_Select Reserved Port_Select 10−1 Table 10−2. Base Register Field Descriptions FIELD SIZE TYPE DESCRIPTION Physical ID 6 R This field contains the physical address ID of this node determined during self-ID. The physical ID is invalid after a bus reset until self-ID has completed as indicated by an unsolicited register-0 status transfer. R 1 R Root. This bit indicates that this node is the root node. The R bit is cleared to 0 by bus reset and is set to 1 during tree-ID if this node becomes root. CPS 1 R Cable-power-status. This bit indicates the state of the CPS input terminal. The CPS terminal is normally tied to serial bus cable power through a 400-kΩ resistor. A 0 in this bit indicates that the cable power voltage has dropped below its threshold for ensured reliable operation. RHB 1 R/W Root-holdoff bit. This bit instructs the PHY layer to attempt to become root after the next bus reset. The RHB bit is cleared to 0 by a system (hardware) reset and is unaffected by a bus reset. IBR 1 R/W Initiate bus reset. This bit instructs the PHY layer to initiate a long (166 µs) bus reset at the next opportunity. Any receive or transmit operation in progress when this bit is set completes before the bus reset is initiated. The IBR bit is cleared to 0 after a system (hardware) reset or a bus reset. Gap_Count 6 R/W Arbitration gap count. This value sets the subaction (fair) gap, arb-reset gap, and arb-delay times. The gap count can be set either by a write to the register, or by reception or transmission of a PHY_CONFIG packet. The gap count is reset to 3Fh by system (hardware) reset or after two consecutive bus resets without an intervening write to the gap count register (either by a write to the PHY register or by a PHY_CONFIG packet). Extended 3 R Extended register definition. For the PCI4510 device, this field is 111b, indicating that the extended register set is implemented. Total_Ports 4 R Number of ports. This field indicates the number of ports implemented in the PHY layer. For the PCI4510 device this field is 2. Max_Speed 3 R PHY speed capability. For the PCI4510 PHY layer this field is 010b, indicating S400 speed capability. Delay 4 R PHY repeater data delay. This field indicates the worst case repeater data delay of the PHY layer, expressed as 144+(delay × 20) ns. For the PCI4510 device this field is 0. LCtrl 1 R/W Link-active status control. This bit controls the active status of the LLC as indicated during self-ID. The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet. The LLC is considered active only if both the LPS input is active and the LCtrl bit is set. The LCtrl bit provides a software controllable means to indicate the LLC active/status in lieu of using the LPS input. The LCtrl bit is set to 1 by a system (hardware) reset and is unaffected by a bus reset. NOTE: The state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state of the LCtrl bit. If the PHY-LLC interface is operational as determined by the LPS input being active, received packets and status information continue to be presented on the interface, and any requests indicated on the LREQ input are processed, even if the LCtrl bit is cleared to 0. C 1 R/W Contender status. This bit indicates that this node is a contender for the bus or isochronous resource manager. This bit is replicated in the c field (bit 20) of the self-ID packet. Jitter 3 R PHY repeater jitter. This field indicates the worst case difference between the fastest and slowest repeater data delay, expressed as (Jitter+1) × 20 ns. For the PCI4510 device, this field is 0. Pwr_Class 3 R/W Node power class. This field indicates this node power consumption and source characteristics and is replicated in the pwr field (bits 21−23) of the self-ID packet. This field is reset to the state specified by the PC0−PC2 input terminals upon a system (hardware) reset and is unaffected by a bus reset. See Table 10−9. Watchdog 1 R/W Watchdog enable. This bit, if set to 1, enables the port event interrupt (Port_event) bit to be set whenever resume operations begin on any port. This bit is cleared to 0 by system (hardware) reset and is unaffected by bus reset. 10−2 Table 10−2. Base Register Field Descriptions (Continued) FIELD ISBR SIZE TYPE DESCRIPTION 1 R/W Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY layer to initiate a short (1.3 µs) arbitrated bus reset at the next opportunity. This bit is cleared to 0 by a bus reset. NOTE: Legacy IEEE Std 1394-1995 compliant PHY layers can not be capable of performing short bus resets. Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long bus reset being performed. Loop 1 R/W Loop detect. This bit is set to 1 when the arbitration controller times out during tree-ID start and may indicate that the bus is configured in a loop. This bit is cleared to 0 by system (hardware) reset or by writing a 1 to this register bit. If the loop and watchdog bits are both set and the LLC is or becomes inactive, the PHY layer activates the LLC to service the interrupt. NOTE: If the network is configured in a loop, only those nodes which are part of the loop generate a configuration-timeout interrupt. All other nodes instead time out waiting for the tree-ID and/or self-ID process to complete and then generate a state time-out interrupt and bus-reset. Pwr_fail 1 R/W Cable power failure detect. This bit is set to 1 whenever the CPS input transitions from high to low indicating that cable power may be too low for reliable operation. This bit is cleared to 0 by system (hardware) reset or by writing a 1 to this register bit. Timeout 1 R/W State time-out interrupt. This bit indicates that a state time-out has occurred (which also causes a bus reset to occur). This bit is cleared to 0 by system (hardware) reset or by writing a 1 to this register bit. Port_event 1 R/W Port event detect. This bit is set to 1 upon a change in the bias (unless disabled) connected, disabled, or fault bits for any port for which the port interrupt enable (Int_enable) bit is set. Additionally, if the watchdog bit is set, the Port_event bit is set to 1 at the start of resume operations on any port. This bit is cleared to 0 by system (hardware) reset or by writing a 1 to this register bit. Enab_accel 1 R/W Enable accelerated arbitration. This bit enables the PHY layer to perform the various arbitration acceleration enhancements defined in IEEE Std 1394a-2000 (ACK-accelerated arbitration, asynchronous fly-by concatenation, and isochronous fly-by concatenation). This bit is cleared to 0 by system (hardware) reset and is unaffected by bus reset. Enab_multi 1 R/W Enable multispeed concatenated packets. This bit enables the PHY layer to transmit concatenated packets of differing speeds in accordance with the protocols defined in IEEE Std 1394a-2000. This bit is cleared to 0 by system (hardware) reset and is unaffected by bus reset. Page_Select 3 R/W Page_Select. This field selects the register page to use when accessing register addresses 8 through 15. This field is cleared to 0 by a system (hardware) reset and is unaffected by bus reset. Port_Select 4 R/W Port_Select. This field selects the port when accessing per-port status or control (for example, when one of the port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is cleared to 0 by system (hardware) reset and is unaffected by bus reset. 10−3 10.2 Port Status Register The port status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. Table 10−3 shows the configuration of the port status page registers and Table 10−4 shows the corresponding field descriptions. If the selected port is not implemented, all registers in the port status page are read as 0. Table 10−3. Page 0 (Port Status) Register Configuration BIT POSITION ADDRESS 0 1 1000 AStat 1001 Peer_Speed 2 3 4 5 Ch Con Int_enable Fault BStat 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved 6 7 Bias Dis Reserved Table 10−4. Page 0 (Port Status) Register Field Descriptions FIELD SIZE TYPE DESCRIPTION AStat 2 R TPA line state. This field indicates the TPA line state of the selected port, encoded as follows: Code Arb Value 11 Z 10 0 01 1 00 invalid BStat 2 R TPB line state. This field indicates the TPB line state of the selected port. This field has the same encoding as the AStat field. Ch 1 R Child/parent status. A 1 indicates that the selected port is a child port. A 0 indicates that the selected port is the parent port. A disconnected, disabled, or suspended port is reported as a child port. The Ch bit is invalid after a bus reset until tree-ID has completed. Con 1 R Debounced port connection status. This bit indicates that the selected port is connected. The connection must be stable for the debounce time of approximately 341 ms for the con bit to be set to 1. The Con bit is cleared to 0 by system (hardware) reset and is unaffected by bus reset. NOTE: The Con bit indicates that the port is physically connected to a peer PHY device, but the port is not necessarily active. Bias 1 R Debounced incoming cable bias status. A 1 indicates that the selected port is detecting incoming cable bias. The incoming cable bias must be stable for the debounce time of 52 µs for the bias bit to be set to 1. Dis 1 RW Port disabled control. If the dis bit is set to 1, the selected port is disabled. The dis bit is cleared to 0 by system (hardware) reset (all ports are enabled for normal operation following system (hardware) reset). The dis bit is not affected by bus reset. Peer_Speed 3 R Port peer speed. This field indicates the highest speed capability of the peer PHY device connected to the selected port, encoded as follows: Peer Speed Code 000 S100 001 S200 010 S400 011−111 invalid The Peer_Speed field is invalid after a bus reset until self-ID has completed. NOTE: Peer speed codes higher than 010b (S400) are defined in IEEE Std 1394a-2000. However, the PCI4510 device is only capable of detecting peer speeds up to S400. 10−4 Table 10−4. Page 0 (Port Status) Register Field Descriptions (Continued) FIELD SIZE TYPE DESCRIPTION Int_enable 1 RW Port event interrupt enable. When the Int_enable bit is set to 1, a port event on the selected port sets the port event interrupt (Port_event) bit and notifies the link. This bit is cleared to 0 by a system (hardware) reset and is unaffected by bus reset. Fault 1 RW Fault. This bit indicates that a resume-fault or suspend-fault has occurred on the selected port, and that the port is in the suspended state. A resume-fault occurs when a resuming port fails to detect incoming cable bias from its attached peer. A suspend-fault occurs when a suspending port continues to detect incoming cable bias from its attached peer. Writing 1 to this bit clears the fault bit to 0. This bit is cleared to 0 by system (hardware) reset and is unaffected by bus reset. 10.3 Vendor Identification Register The vendor identification page identifies the vendor/manufacturer and compliance level. The page is selected by writing 1 to the Page_Select field in base register 7. Table 10−5 shows the configuration of the vendor identification page, and Table 10−6 shows the corresponding field descriptions. Table 10−5. Page 1 (Vendor ID) Register Configuration BIT POSITION ADDRESS 0 1 2 3 4 1000 Compliance 1001 Reserved 1010 Vendor_ID[0] 1011 Vendor_ID[1] 1100 Vendor_ID[2] 1101 Product_ID[0] 1110 Product_ID[1] 1111 Product_ID[2] 5 6 7 Table 10−6. Page 1 (Vendor ID) Register Field Descriptions FIELD SIZE TYPE DESCRIPTION Compliance 8 R Compliance level. For the PCI4510 device this field is 01h, indicating compliance with IEEE Std 1394a-2000. Vendor_ID 24 R Manufacturer’s organizationally unique identifier (OUI). For the PCI4510 device this field is 08 0028h (Texas Instruments) (the MSB is at register address 1010b). Product_ID 24 R Product identifier. For the PCI4510 device this field is 42 4499h (the MSB is at register address 1101b). 10−5 10.4 Vendor-Dependent Register The vendor-dependent page provides access to the special control features of the PCI4510 device, as well as to configuration and status information used in manufacturing test and debug. This page is selected by writing 7 to the Page_Select field in base register 7. Table 10−7 shows the configuration of the vendor-dependent page, and Table 10−8 shows the corresponding field descriptions. Table 10−7. Page 7 (Vendor-Dependent) Register Configuration BIT POSITION ADDRESS 0 1000 NPA 1 2 3 4 Reserved 5 6 7 Link_Speed 1001 Reserved for test 1010 Reserved for test 1011 Reserved for test 1100 Reserved for test 1101 Reserved for test 1110 Reserved for test 1111 Reserved for test Table 10−8. Page 7 (Vendor-Dependent) Register Field Descriptions FIELD SIZE TYPE DESCRIPTION NPA 1 RW Null-packet actions flag. This bit instructs the PHY layer to not clear fair and priority requests when a null packet is received with arbitration acceleration enabled. If this bit is set to 1, fair and priority requests are cleared only when a packet of more than 8 bits is received; ACK packets (exactly 8 data bits), null packets (no data bits), and malformed packets (less than 8 data bits) do not clear fair and priority requests. If this bit is cleared to 0, fair and priority requests are cleared when any non-ACK packet is received, including null packets or malformed packets of less than 8 bits. This bit is cleared to 0 by system (hardware) reset and is unaffected by bus reset. Link_Speed 2 RW Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows: Code Speed 00 S100 01 S200 10 S400 11 illegal This field is replicated in the sp field of the self-ID packet to indicate the speed capability of the node (PHY and LLC in combination). However, this field does not affect the PHY speed capability indicated to peer PHYs during self-ID; the PCI4510 PHY layer identifies itself as S400 capable to its peers regardless of the value in this field. This field is set to 10b (S400) by system (hardware) reset and is unaffected by bus reset. 10−6 10.5 Power-Class Programming The PC0–PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field (bits 21–23) of the transmitted self-ID packet. Table 10−9 shows the descriptions of the various power classes. The default power-class value is loaded following a system (hardware) reset, but is overridden by any value subsequently loaded into the Pwr_Class field in register 4. Table 10−9. Power Class Descriptions PC0–PC2 DESCRIPTION 000 Node does not need power and does not repeat power. 001 Node is self-powered and provides a minimum of 15 W to the bus. 010 Node is self-powered and provides a minimum of 30 W to the bus. 011 Node is self-powered and provides a minimum of 45 W to the bus. 100 Node may be powered from the bus and is using up to 3 W. No additional power is needed to enable the link. 101 Reserved 110 Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link. 111 Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link. 10−7 10−8 11 Electrical Characteristics 11.1 Absolute Maximum Ratings Over Operating Temperature Ranges† Supply voltage range: VR_PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.2 V to 2.2 V ANALOGVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V PLLVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V VCCCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V Clamping voltage range for VCCP and VCCCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to 6 V Input voltage range for PCI, VI, CardBus, PHY, and Miscellaneous . . . . . . . . . . . . . . . . . −0.5 to VCC + 0.5 V Output voltage range for PCI, VO, CardBus, PHY, and Miscellaneous . . . . . . . . . . . . . . . −0.5 to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Operating free-air temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C † Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Applies for external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. PCI terminals and miscellaneous terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to VCCCB. The limit specified applies for a dc condition. 2. Applies for external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. PCI terminals and miscellaneous terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to VCCCB. The limit specified applies for a dc condition. 11−1 11.2 Recommended Operating Conditions OPERATION MIN NOM MAX UNIT VR_PORT (see Table 2−6 for description) 1.8 V 1.6 1.8 2 V ANALOGVCC VCC 3.3 V 3 3.3 3.6 V 3.3 V 3 3.3 3.6 V PLLVCC 3.3 V 3 3.3 3.6 V PCI I/O clamping voltage, VCCP VCCP = 3.3 V VCCP = 5 V 3 3.3 3.6 4.75 5 5.25 VCCCB PC Card I/O clamping voltage VCCCB = 3.3 V VCCCB = 5 V 3 3.3 3.6 4.75 5 5.25 3.3 V CardBus PC Card High-level input voltage, VIH† PCI Input voltage, VI Output voltage, VO§ Input transition time (tr and tf), tt Output current, IO Differential input voltage, VID Common-mode input voltage, VIC Power up reset time, tpu PCI Operating ambient temperature range, TA Virtual juction temperature, TJ# VCCCB V 2.4 VCCCB VCCP V 3.3 V 5V 0.5VCCP 2 VCCP VCC 0.7VCC 2 VCC 0.325VCCCB V V 3.3 V CardBus 0 3.3 V 16-bit 0 0.8 V 5 V 16-bit 0 0.8 V 3.3 V 0 5V 0 0.3VCCP 0.8 PC(0−2) 0 Miscellaneous‡ 0 PC Card 0 PCI 0 Miscellaneous‡ 0 PC Card 0 PCI 0 Miscellaneous‡ 0 PCI and PC Card Miscellaneous‡ 1 0.2VCC 0.8 V VCCCB VCCP V VCC VCC V VCC VCC V V V V 4 ns 0 6 ns −5.6 1.3 mA Cable inputs, during data reception 118 260 Cable inputs, during arbitration 168 265 TPB cable inputs, source power node 0.4706 TPB cable inputs, nonsource power node 0.4706 2.515 2.015¶ TPBIAS outputs GRST input 2 V ms TPA, TPB cable inputs, S200 operation ± 0.5 TPA, TPB cable inputs, S400 operation ± 0.315 GRST input mV ± 1.08 ns 0 25 70 °C 0 25 115 °C NOTE: Unused terminals (input or I/O) must be held high or low to prevent them from floating. † Applies to external inputs and bidirectional buffers without hysteresis. ‡ Miscellaneous terminals are: SDA, SCL, SUSPEND, GRST, CDx, VSx, CNA, and PHY_TEST_MA. § Applies to external output buffers. ¶ For a node that does not source power; see Section 4.2.2.2 in IEEE Std 1394a-2000. # This junction temperature reflects simulation, the customer is responsible for verifying junction temperature. 11−2 V 2.0 TPA, TPB cable inputs, S100 operation Receive input jitter VCCCB 5 V 16-bit Miscellaneous‡ Low-level input voltage, VIL† V 3.3 V 16-bit PC(0−2) PC Card 0.475VCCCB V Recommended Operating Conditions (Continued) OPERATION Receive input skew MIN NOM MAX UNIT Between TPA and TPB cable inputs, S100 operation ± 0.8 Between TPA and TPB cable inputs, S200 operation ± 0.55 Between TPA and TPB cable inputs, S400 operation ± 0.5 ns 11.3 Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted) PARAMETER OPERATION 3.3 V PCI VOH High-level output voltage PC Card Low-level output voltage PC Card 3-state output high-impedance Output terminals IOZL High-impedance, low-level output current Output terminals IOZH High-impedance, high-level output current Output terminals IIL Low-level input current V 3.3 V CardBus IOH = −0.15 mA 0.9VCC V 3.3 V 16-bit IOH = −0.15 mA 2.4 V 5 V 16-bit IOH = −0.15 mA IOH = − 4 mA 2.8 V High-level input current 5V V 3.3 V CardBus IOL = 0.7 mA 0.1VCC V 3.3 V 16-bit IOL = 0.7 mA 0.4 V 5 V 16-bit IOL = 0.7 mA IOL = 4 mA 0.55 V 0.5 V ± 20 µA 3.6 V 3.6 V VO = VCC or GND VI = VCC 5.25 V VI = VCC −1 3.6 V VI = VCC† VI = VCC† 10 5.25 V Input terminals 3.6 V 3.6 V Others† 3.6 V 3.6 V 5.25 V 3.6 V I/O terminals V 0.1VCC 0.55 I/O terminals† PCI† Input terminals VCC −0.6 IOL = 1.5 mA IOL = 6 mA 3.6 V IIH UNIT 5V Miscellaneous‡ IOZ MAX 0.9VCC 2.4 3.3 V VOL MIN IOH = − 0.5 mA IOH = − 2 mA Miscellaneous‡ PCI TEST CONDITIONS −1 25 ± 20 VI = GND VI = GND ± 20 VI = VCC VI = VCC ± 20 ± 20 VI = VCC‡ VI = VCC‡ 10 VI = VCC‡ VI = VCC‡ 10 5.25 V † For I/O terminals, input leakage (IIL and IIH) includes IOZ of the disabled output. ‡ Miscellaneous terminals are: SDA, SCL, SUSPEND, GRST, CDx, VSx, CNA, and PHY_TEST_MA. 20 µA A µA A µA A µA A µA 25 11−3 11.4 Electrical Characteristics Over Recommended Ranges of Operating Conditions (unless otherwise noted) 11.4.1 Device PARAMETER VTH VO TEST CONDITIONS Power status threshold, CPS input† 400-kΩ resistor† TPBIAS output voltage At rated IO current II Input current (PC0 −PC2 inputs) † Measured at cable power side of resistor. MIN TYP MAX UNIT 4.7 7.5 1.665 2.015 V 5 µA VCC = 3.6 V V 11.4.2 Driver PARAMETER TEST CONDITIONS MIN MAX 265 1.05‡ −2.53§ mV −8.1§ mA VOD IDIFF Differential output voltage 56 Ω , see Figure 11−1 Driver difference current, TPA+, TPA−, TPB+, TPB − Drivers enabled, speed signaling off ISP200 ISP400 Common-mode speed signaling current, TPB+, TPB − S200 speed signaling enabled 172 −1.05‡ −4.84§ Common-mode speed signaling current, TPB+, TPB − S400 speed signaling enabled −12.4§ UNIT mA mA VOFF Off state differential voltage Drivers disabled, see Figure 11−1 20 mV ‡ Limits defined as algebraic sum of TPA+ and TPA− driver currents. Limits also apply to TPB+ and TPB − algebraic sum of driver currents. § Limits defined as absolute limit of each of TPB+ and TPB − driver currents. TPAx+ TPBx+ 56 Ω TPAx− TPBx− Figure 11−1. Test Load Diagram 11.4.3 Receiver PARAMETER TEST CONDITIONS MIN TYP 4 7 MAX UNIT kΩ ZID Differential impedance Drivers disabled ZIC Common-mode impedance Drivers disabled VTH-R VTH-CB Receiver input threshold voltage Drivers disabled −30 Cable bias detect threshold, TPBx cable inputs Drivers disabled 0.6 1 VTH+ VTH− Positive arbitration comparator threshold voltage Drivers disabled 89 168 mV Negative arbitration comparator threshold voltage Drivers disabled −168 −89 mV VTH−SP200 Speed signal threshold TPBIAS−TPA common mode voltage, drivers disabled 49 131 mV VTH−SP400 Speed signal threshold TPBIAS−TPA common mode voltage, drivers disabled 314 396 mV 4 20 11−4 pF kΩ 24 pF 30 mV V 11.5 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature ALTERNATE SYMBOL PARAMETER tc tw(H) Cycle time, PCLK tw(L) tr, tf Pulse duration (width), PCLK low tw tsu Pulse duration (width), GRST Pulse duration (width), PCLK high Slew rate, PCLK Setup time, PCLK active at end of PRST TEST CONDITIONS MIN MAX UNIT tcyc thigh 30 ns 11 ns tlow ∆v/∆t 11 ns trst 1 ms 100 ms 1 trst-clk 4 V/ns 11.6 Switching Characteristics for PHY Port Interface PARAMETER tr tf TEST CONDITIONS MIN Jitter, transmit Between TPA and TPB Skew, transmit Between TPA and TPB TP differential rise time, transmit 10% to 90%, at 1394 connector 0.5 TP differential fall time, transmit 90% to 10%, at 1394 connector 0.5 TYP MAX UNIT ± 0.15 ns ± 0.1 ns 1.2 ns 1.2 ns 11.7 Operating, Timing, and Switching Characteristics of XI PARAMETER VCC VIH High-level input voltage VIL Low-level input voltage MIN TYP MAX 3 3.3 3.6 UNIT V (PLLVCC) 0.63VCC V 0.33VCC Input clock frequency V 24.576 MHz Input clock frequency tolerance Input slew rate Input clock duty cycle <100 PPM 0.2 4 V/ns 40% 60% 11.8 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature This data manual uses the following conventions to describe time ( t ) intervals. The format is tA, where subscript A indicates the type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td (ten, tdis) = delay time, tsu = setup time, and th = hold time. ALTERNATE SYMBOL PARAMETER tpd Propagation delay time, See Note 3 PCLK-to-shared signal valid delay time tval PCLK-to-shared signal invalid delay time tinv ten tdis Enable time, high impedance-to-active delay time from PCLK tsu th Setup time before PCLK valid Disable time, active-to-high impedance delay time from PCLK Hold time after PCLK high TEST CONDITIONS MIN CL = 50 pF, See Note 3 MAX UNIT 11 ns 2 ton toff 2 ns tsu th 7 ns 0 ns 28 ns NOTE 3: PCI shared signals are AD31−AD0, C/BE3−C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR. 11−5 11.8.1 CardBus PC Card Clock Specifications MIN MAX tcyc thigh CCLK cycle time (see Note 4) PARAMETER 30 R CCLK high time 12 tlow CCLK low time 12 CCLK slew rate (see Note 5) UNIT ns ns ns 1 4 V/ns UNIT − NOTES: 4. In general, all CardBus PC Card components must work with any clock frequency up to 33 MHz. The clock frequency may be changed at any time during the operation of the system so long as the clock edges remain clean (monotonic) and the minimum cycle and high and low times are not violated. If the clock is stopped, it must be in a low state. A variance on this specification is allowed for the CardBus PC Card adapter which may operate the CardBus PC Card interface at any single fixed frequency up to 33 MHz, and may enforce a policy of no frequency changes. 5. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform (see Figure 11−2). tcyc thigh 0.6 VCC 0.475 VCC 0.4 VCC 0.325 VCC tlow 0.4 VCC, p-to-p (Minimum) 0.2 VCC Figure 11−2. CardBus PC Card Clock Waveform 11.8.2 3.3-V Timing Parameters MIN MAX tval ton CCLK-to-signal-valid delay (see Notes 6 and 7) 2 18 Float-to-active delay (see Note 6) 2 toff tsu Active-to-float delay (see Note 6) Input set up time to CCLK (see Note 8) 7 th trst Input hold time from CCLK (see Note 8) 0 ns Reset active time after power stable (see Note 9) 1 ms trst-clk trst-off Reset active time after CCLK stable (see Note 9) 100 Reset-active-to-output-float delay (see Notes 9 and 10) ns ns 28 ns ns clocks 40 ns tpulse CSTSCHG remote wakeup pulse width (see Note 11) 1 ms NOTES: 6. tval includes the time to propagate data from internal registers to the output buffer and drive the output to a valid level. Minimum tval is measured from CCLK crossing Vtest to the signal crossing VIH on falling edges and VIL on rising edges. Maximum tval is measured from CCLK crossing Vtest to the signal’s last transition out of the threshold region (VIL for falling edges, VIH for rising edges). 7. Minimum times are specified with 0-pF equivalent load; maximum times are specified with 30-pF equivalent load. Actual test capacitance may vary, but results must be correlated to these specifications. Systems which exceed this capacitance, due to long traces between the socket and adaptor, must reduce the CCLK frequency appropriately. 8. tsu and th are measured at VTH for rising edges and VTL for falling edges. 9. CRST is asserted asynchronously and negated synchronously with respect to CCLK. CCLK Stable means that Vcc is within tolerances and CCLK is meeting specifications. 10. See PC Card Standard— Electrical Specification for the CardBus PC Card and adapter signals which must be in a high-impedance state. 11. This parameter only applies when signaling remote wakeup over the CSTSCHG terminal. All other status change information must be signaled by asserting CSTSCHG until the resultant interrupt is serviced. 11−6 12 Mechanical Information The PCI4510 is packaged either in a GHK or ZHK 209-ball BGA, a 208-pin PDV package, or an RGVF or RZVF 224-ball MicroStar BGA. The following shows the mechanical dimensions for the GHK, PDV, RGVF, RZVF, and ZHK packages. GHK (S−PBGA−N209) PLASTIC BALL GRID ARRAY 16,10 15,90 SQ 14,40 TYP 0,80 W V U T R P N M L K J H G F E D C B A 0,80 3 1 A1 Corner 2 5 4 7 6 0,95 9 8 11 10 13 12 15 14 17 16 19 18 Bottom View 0,85 1,40 MAX Seating Plane 0,55 0,45 0,08 0,45 0,12 0,35 4145273 − 2/E 08/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice C. MicroStar BGA configuration MicroStar BGA is a trademark of Texas Instruments. 12−1 PDV (S-PQFP-G208) PLASTIC QUAD FLATPACK 156 105 157 104 0,27 0,17 0,08 M 0,50 0,13 NOM 208 53 1 52 Gage Plane 25,50 TYP 28,05 SQ 27,95 0,25 0,05 MIN 0°−ā 7° 30,20 SQ 29,80 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4087729/D 11/98 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 12−2 RGVF (S−PBGA−N224) PLASTIC BALL GRID ARRAY NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. 12−3 RZVF (S−PBGA−N224) NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. 12−4 PLASTIC BALL GRID ARRAY 12−5 12−6