TI TSB43AB23PGE

Data Manual
February 2003
1394 Host Controller Solutions
SLLS450A
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
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Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright  2003, Texas Instruments Incorporated
Contents
Section
1
2
3
4
Title
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSB43AB23 1394 OHCI Controller Programming Model . . . . . . . . . . . . . .
3.1
PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
Class Code and Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7
Latency Timer and Class Cache Line Size Register . . . . . . . . . . . . . .
3.8
Header Type and BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9
OHCI Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 TI Extension Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Subsystem Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12 Power Management Capabilities Pointer Register . . . . . . . . . . . . . . .
3.13 Interrupt Line and Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14 MIN_GNT and MAX_LAT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15 OHCI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.16 Capability ID and Next Item Pointer Registers . . . . . . . . . . . . . . . . . . .
3.17 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . .
3.18 Power Management Control and Status Register . . . . . . . . . . . . . . . .
3.19 Power Management Extension Registers . . . . . . . . . . . . . . . . . . . . . . .
3.20 PCI PHY Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.21 Miscellaneous Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . .
3.22 Link Enhancement Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.23 Subsystem Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.24 GPIO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OHCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
OHCI Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
GUID ROM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
Asynchronous Transmit Retries Register . . . . . . . . . . . . . . . . . . . . . . .
4.4
CSR Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
1–1
1–1
1–3
1–4
1–4
1–4
2–1
3–1
3–3
3–3
3–4
3–4
3–5
3–6
3–6
3–7
3–7
3–8
3–9
3–9
3–10
3–10
3–11
3–11
3–12
3–13
3–13
3–14
3–15
3–16
3–17
3–18
4–1
4–4
4–5
4–6
4–6
iii
5
iv
4.5
CSR Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6
CSR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7
Configuration ROM Header Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8
Bus Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9
Bus Options Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 GUID High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 GUID Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 Configuration ROM Mapping Register . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13 Posted Write Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 Posted Write Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 Host Controller Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.17 Self-ID Buffer Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18 Self-ID Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19 Isochronous Receive Channel Mask High Register . . . . . . . . . . . . . .
4.20 Isochronous Receive Channel Mask Low Register . . . . . . . . . . . . . . .
4.21 Interrupt Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.22 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.23 Isochronous Transmit Interrupt Event Register . . . . . . . . . . . . . . . . . .
4.24 Isochronous Transmit Interrupt Mask Register . . . . . . . . . . . . . . . . . . .
4.25 Isochronous Receive Interrupt Event Register . . . . . . . . . . . . . . . . . . .
4.26 Isochronous Receive Interrupt Mask Register . . . . . . . . . . . . . . . . . . .
4.27 Initial Bandwidth Available Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.28 Initial Channels Available High Register . . . . . . . . . . . . . . . . . . . . . . . .
4.29 Initial Channels Available Low Register . . . . . . . . . . . . . . . . . . . . . . . . .
4.30 Fairness Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.31 Link Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.32 Node Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.33 PHY Layer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.34 Isochronous Cycle Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.35 Asynchronous Request Filter High Register . . . . . . . . . . . . . . . . . . . . .
4.36 Asynchronous Request Filter Low Register . . . . . . . . . . . . . . . . . . . . .
4.37 Physical Request Filter High Register . . . . . . . . . . . . . . . . . . . . . . . . . .
4.38 Physical Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . .
4.39 Physical Upper Bound Register (Optional Register) . . . . . . . . . . . . . .
4.40 Asynchronous Context Control Register . . . . . . . . . . . . . . . . . . . . . . . .
4.41 Asynchronous Context Command Pointer Register . . . . . . . . . . . . . .
4.42 Isochronous Transmit Context Control Register . . . . . . . . . . . . . . . . . .
4.43 Isochronous Transmit Context Command Pointer Register . . . . . . . .
4.44 Isochronous Receive Context Control Register . . . . . . . . . . . . . . . . . .
4.45 Isochronous Receive Context Command Pointer Register . . . . . . . .
4.46 Isochronous Receive Context Match Register . . . . . . . . . . . . . . . . . . .
TI Extension Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
DV and MPEG2 Timestamp Enhancements . . . . . . . . . . . . . . . . . . . . .
4–7
4–7
4–8
4–8
4–9
4–10
4–10
4–11
4–11
4–12
4–12
4–13
4–14
4–15
4–16
4–17
4–18
4–20
4–22
4–23
4–23
4–24
4–24
4–25
4–25
4–26
4–27
4–28
4–29
4–30
4–31
4–33
4–34
4–36
4–36
4–37
4–38
4–39
4–40
4–40
4–42
4–43
5–1
5–1
5.2
Isochronous Receive Digital Video Enhancements . . . . . . . . . . . . . . . 5–2
5.3
Isochronous Receive Digital Video Enhancements Register . . . . . . . 5–2
5.4
Link Enhancement Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
5.5
Timestamp Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
6 Serial EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
7 PHY Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1
7.1
Base Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1
7.2
Port Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
7.3
Vendor Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
7.4
Vendor-Dependent Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6
7.5
Power-Class Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7
8 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1
8.1
PHY Port Cable Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1
8.2
Crystal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2
8.3
Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3
8.4
EMI Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4
9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1
9.1
Absolute Maximum Ratings Over Operating Temperature Ranges . 9–1
9.2
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2
9.3
Electrical Characteristics Over Recommended
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3
9.4
Electrical Characteristics Over Recommended Ranges of
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4
9.4.1
Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4
9.4.2
Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4
9.4.3
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–5
9.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–5
9.6
Switching Characteristics for PHY Port Interface . . . . . . . . . . . . . . . . . 9–5
9.7
Operating, Timing, and Switching Characteristics of XI . . . . . . . . . . . 9–5
9.8
Switching Characteristics for PCI Interface . . . . . . . . . . . . . . . . . . . . . . 9–5
10 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1
v
List of Illustrations
Figure
2–1
2–2
3–1
8–1
8–2
8–3
8–4
8–5
9–1
vi
Title
Page
PDT Package Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
PGE Package Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
TSB43AB23 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
TP Cable Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1
Typical Compliant DC Isolated Outer Shield Termination . . . . . . . . . . . . . 8–2
Non-DC Isolated Outer Shield Termination . . . . . . . . . . . . . . . . . . . . . . . . . 8–2
Load Capacitance for the TSB43AB23 PHY . . . . . . . . . . . . . . . . . . . . . . . . 8–3
Recommended Crystal and Capacitor Layout . . . . . . . . . . . . . . . . . . . . . . . 8–3
Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4
List of Tables
Table
2–1
2–2
2–3
2–4
2–5
2–6
2–7
2–8
2–9
3–1
3–2
3–3
3–4
3–5
3–6
3–7
3–8
3–9
3–10
3–11
3–12
3–13
3–14
3–15
3–16
3–17
3–18
3–19
3–20
3–21
3–22
4–1
4–2
4–3
4–4
4–5
4–6
Title
PDT Package Signals Sorted by Terminal Number . . . . . . . . . . . . . . . . . .
PGE Package Signals Sorted by Terminal Number . . . . . . . . . . . . . . . . . .
Signal Names Sorted Alphanumerically to Terminal Number . . . . . . . . . .
PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Layer Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Field Access Tag Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Class Code and Revision ID Register Description . . . . . . . . . . . . . . . . . . .
Latency Timer and Class Cache Line Size Register Description . . . . . . .
Header Type and BIST Register Description . . . . . . . . . . . . . . . . . . . . . . . .
OHCI Base Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .
TI Base Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subsystem Identification Register Description . . . . . . . . . . . . . . . . . . . . . .
Interrupt Line and Pin Registers Description . . . . . . . . . . . . . . . . . . . . . . . .
MIN_GNT and MAX_LAT Register Description . . . . . . . . . . . . . . . . . . . . .
OHCI Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capability ID and Next Item Pointer Registers Description . . . . . . . . . . . .
Power Management Capabilities Register Description . . . . . . . . . . . . . . .
Power Management Control and Status Register Description . . . . . . . . .
Power Management Extension Registers Description . . . . . . . . . . . . . . . .
PCI PHY Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Miscellaneous Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Enhancement Control Register Description . . . . . . . . . . . . . . . . . . . .
Subsystem Access Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose Input/Output Control Register Description . . . . . . . . . .
OHCI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OHCI Version Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GUID ROM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Transmit Retries Register Description . . . . . . . . . . . . . . . .
CSR Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration ROM Header Register Description . . . . . . . . . . . . . . . . . . . .
Page
2–4
2–5
2–6
2–7
2–7
2–8
2–9
2–10
2–11
3–1
3–3
3–4
3–5
3–6
3–6
3–7
3–7
3–8
3–9
3–10
3–10
3–11
3–11
3–12
3–13
3–13
3–14
3–15
3–16
3–17
3–18
4–1
4–4
4–5
4–6
4–7
4–8
vii
4–7
4–8
4–9
4–10
4–11
4–12
4–13
4–14
4–15
4–16
4–17
4–18
4–19
4–20
4–21
4–22
4–23
4–24
4–25
4–26
4–27
4–28
4–29
4–30
4–31
4–32
4–33
4–34
4–35
5–1
5–2
5–3
5–4
6–1
6–2
7–1
7–2
7–3
7–4
7–5
7–6
7–7
7–8
7–9
viii
Bus Options Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration ROM Mapping Register Description . . . . . . . . . . . . . . . . . . .
Posted Write Address Low Register Description . . . . . . . . . . . . . . . . . . . .
Posted Write Address High Register Description . . . . . . . . . . . . . . . . . . . .
Host Controller Control Register Description . . . . . . . . . . . . . . . . . . . . . . . .
Self-ID Count Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Isochronous Receive Channel Mask High Register Description . . . . . . .
Isochronous Receive Channel Mask Low Register Description . . . . . . . .
Interrupt Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Isochronous Transmit Interrupt Event Register Description . . . . . . . . . . .
Isochronous Receive Interrupt Event Register Description . . . . . . . . . . .
Initial Bandwidth Available Register Description . . . . . . . . . . . . . . . . . . . . .
Initial Channels Available High Register Description . . . . . . . . . . . . . . . . .
Initial Channels Available Low Register Description . . . . . . . . . . . . . . . . .
Fairness Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Node Identification Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . .
PHY Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Isochronous Cycle Timer Register Description . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Request Filter High Register Description . . . . . . . . . . . . .
Asynchronous Request Filter Low Register Description . . . . . . . . . . . . . .
Physical Request Filter High Register Description . . . . . . . . . . . . . . . . . . .
Physical Request Filter Low Register Description . . . . . . . . . . . . . . . . . . .
Asynchronous Context Control Register Description . . . . . . . . . . . . . . . . .
Asynchronous Context Command Pointer Register Description . . . . . . .
Isochronous Transmit Context Control Register Description . . . . . . . . . .
Isochronous Receive Context Control Register Description . . . . . . . . . . .
Isochronous Receive Context Match Register Description . . . . . . . . . . . .
TI Extension Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Isochronous Receive Digital Video Enhancements Register Description
Link Enhancement Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timestamp Offset Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers and Bits Loadable Through Serial EEPROM . . . . . . . . . . . . . . .
Serial EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Base Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Base Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page 0 (Port Status) Register Configuration . . . . . . . . . . . . . . . . . . . . . . . .
Page 0 (Port Status) Register Field Descriptions . . . . . . . . . . . . . . . . . . . .
Page 1 (Vendor ID) Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . .
Page 1 (Vendor ID) Register Field Descriptions . . . . . . . . . . . . . . . . . . . . .
Page 7 (Vendor-Dependent) Register Configuration . . . . . . . . . . . . . . . . .
Page 7 (Vendor-Dependent) Register Field Descriptions . . . . . . . . . . . . .
Power Class Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–9
4–11
4–11
4–12
4–13
4–15
4–16
4–17
4–18
4–20
4–22
4–23
4–24
4–25
4–25
4–26
4–27
4–28
4–29
4–30
4–31
4–33
4–34
4–36
4–37
4–38
4–39
4–40
4–43
5–1
5–2
5–4
5–5
6–1
6–2
7–1
7–2
7–4
7–4
7–5
7–5
7–6
7–6
7–7
1 Introduction
This chapter provides an overview of the Texas Instruments TSB43AB23 device and its features.
1.1 Description
The Texas Instruments TSB43AB23 device is an integrated 1394a-2000 OHCI PHY/link-layer controller (LLC) device
that is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management Interface Specification
(Revision 1.1), IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller Interface
Specification (Release 1.1). It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at
100M bits/s, 200M bits/s, and 400M bits/s. The TSB43AB23 device provides three 1394 ports that have separate
cable bias (TPBIAS). The TSB43AB23 device also supports the IEEE Std 1394a-2000 power-down features for
battery-operated applications and arbitration enhancements.
As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal
control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through
configuration cycles specified by PCI, and it provides plug-and-play (PnP) compatibility. Furthermore, the
TSB43AB23 device is compliant with the PCI Bus Power Management Interface Specification as specified by the
PC 2001 Design Guide requirements. The TSB43AB23 device supports the D0, D1, D2, and D3 power states.
The TSB43AB23 design provides PCI bus master bursting, and it is capable of transferring a cacheline of data at
132M bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are provided
to buffer the 1394 data.
The TSB43AB23 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2
performance. The TSB43AB23 device also provides multiple isochronous contexts, multiple cacheline burst
transfers, and advanced internal arbitration.
An advanced CMOS process achieves low power consumption and allows the TSB43AB23 device to operate at PCI
clock rates up to 33 MHz.
The TSB43AB23 PHY-layer provides the digital and analog transceiver functions needed to implement a three-port
node in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. The transceivers
include circuitry to monitor the line conditions as needed for determining connection status, for initialization and
arbitration, and for packet reception and transmission.
The TSB43AB23 PHY-layer requires only an external 24.576-MHz crystal as a reference for the cable ports. An
external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL),
which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the
clock signals that control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock
signal is supplied to the integrated LLC for synchronization and is used for resynchronization of the received data.
Data bits to be transmitted through the cable ports are received from the integrated LLC and are latched internally
in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted
at 98.304M, 196.608M, or 393.216M bits/s (referred to as S100, S200, or S400 speeds, respectively) as the outbound
data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the
twisted-pair B (TPB) cable pair(s), and the encoded strobe information is transmitted differentially on the twisted-pair
A (TPA) cable pair(s).
During packet reception, the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers
for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe
information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive
clock signal and the serial data bits. The serial data bits are resynchronized to the local 49.152-MHz system clock
and sent to the integrated LLC. The received data is also transmitted (repeated) on the other active (connected) cable
ports.
1–1
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during
initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the
arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this
common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the
TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely
supplied twisted-pair bias voltage.
The TSB43AB23 device provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY
layer contains two independent TPBIAS circuits. This bias voltage, when seen through a cable by a remote receiver,
indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter
capacitor of 1.0 µF.
The line drivers in the TSB43AB23 device operate in a high-impedance current mode and are designed to work with
external 112-Ω line-termination resistor networks in order to match the 110-Ω cable impedance. One network is
provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56-Ω resistors.
The midpoint of the pair of resistors that is directly connected to the TPA terminals is connected to its corresponding
TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the TPB terminals is
coupled to ground through a parallel R-C network with recommended values of 5 kΩ and 220 pF. The values of the
external line-termination resistors are designed to meet the standard specifications when connected in parallel with
the internal receiver circuits. An external resistor connected between the R0 and R1 terminals sets the driver output
current and other internal operating currents. This current-setting resistor has a value of 6.34 kΩ ±1%.
When the power supply of the TSB43AB23 device is off and the twisted-pair cables are connected, the TSB43AB23
transmitter and receiver circuitry present a high impedance to the cable and do not load the TPBIAS voltage at the
other end of the cable.
When the device is in a low-power state (for example, D2 or D3) the TSB43AB23 device automatically enters a
low-power mode if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the
TSB43AB23 device disables its internal clock generators and also disables various voltage and current reference
circuits, depending on the state of the ports (some reference circuitry must remain active in order to detect new cable
connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the ultralow-power
sleep mode) is attained when all ports are either disconnected or disabled with the port interrupt enable bit cleared.
The TSB43AB23 device exits the low-power mode when bit 19 (LPS) in the host controller control register at OHCI
offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1 or when a port event occurs which
requires that the TSB43AB23 device to become active in order to respond to the event or to notify the LLC of the event
(for example, incoming bias is detected on a suspended port, a disconnection is detected on a suspended port, or
a new connection is detected on a nondisabled port). When the TSB43AB23 device is in the low-power mode, the
internal 49.153-MHz clock becomes active (and the integrated PHY layer becomes operative) within 2 ms after bit 19
(LPS) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control
Register) is set to 1.
The TSB43AB23 device supports hardware enhancements to better support digital video (DV) and MPEG data
stream reception and transmission. These enhancements are enabled through the isochronous receive digital video
enhancements register at OHCI offset A88h (see Chapter 5, TI Extension Registers). The enhancements include
automatic timestamp insertion for transmitted DV and MPEG-formatted streams and common isochronous packet
(CIP) header stripping for received DV streams.
The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the isochronous data
contexts are implemented as hardware support for the synchronization timestamp for both DV and MPEG CIP
formats. The TSB43AB23 device supports modification of the synchronization timestamp field to ensure that the
value inserted via software is not stale—that is, the value is less than the current cycle timer when the packet is
transmitted.
1–2
1.2 Features
The TSB43AB23 device supports the following features:
•
Fully compliant with 1394 Open Host Controller Interface Specification (Release 1.1)
•
Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus† and IEEE Std
1394a-2000
•
Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394
•
Compliant with Intel Mobile Power Guideline 2000
•
Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed
concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume
•
Power-down features to conserve energy in battery-powered applications include: automatic device power
down during suspend, PCI power management for link-layer, and inactive ports powered down
•
Ultralow-power sleep mode
•
Three IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and 400M bits/s
•
Cable ports monitor line conditions for active connection to remote node
•
Cable power presence monitoring
•
Separate cable bias (TPBIAS) for each port
•
1.8-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
•
Physical write posting of up to three outstanding transactions
•
PCI burst transfers and deep FIFOs to tolerate large host latency
•
PCI_CLKRUN protocol
•
External cycle timer control for customized synchronization
•
Extended resume signaling for compatibility with legacy DV components
•
PHY-link logic performs system initialization and arbitration functions
•
PHY-link encode and decode functions included for data-strobe bit level encoding
•
PHY-link incoming data resynchronized to local clock
•
Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, and
400M bits/s
•
Node power class information signaling for system power management
•
Serial ROM interface supports 2-wire serial EEPROM devices
•
Two general-purpose I/Os
•
Register bits give software control of contender bit, power class bits, link active control bit, and IEEE Std
1394a-2000 features
•
Fabricated in advanced low-power CMOS process
•
Isochronous receive dual-buffer mode
•
Out-of-order pipelining for asynchronous transmit requests
•
Register access fail interrupt when the PHY SCLK is not active
† Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
1–3
•
PCI power-management D0, D1, D2, and D3 power states
•
Initial bandwidth available and initial channels available registers
•
PME support per 1394 Open Host Controller Interface Specification
1.3 Related Documents
•
1394 Open Host Controller Interface Specification (Release 1.1)
•
IEEE Standard for a High Performance Serial Bus (IEEE Std 1394-1995)
•
IEEE Standard for a High Performance Serial Bus—Amendment 1 (IEEE Std 1394a-2000)
•
PC Card Standard—Electrical Specification
•
PC 2001 Design Guide
•
PCI Bus Power Management Interface Specification (Revision 1.1)
•
PCI Local Bus Specification (Revision 2.2)
•
Mobile Power Guideline 2000
•
Serial Bus Protocol 2 (SBP-2)
•
IEC 61883-1:1998 Consumer Audio/Video Equipment Digital Interface Part 1: General
1.4 Trademarks
iOHCI-Lynx and TI are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
1.5 Ordering Information
1–4
ORDERING NUMBER
NAME
VOLTAGE
PACKAGE
TSB43AB23PDT
iOHCI-Lynx
3.3 V
PDT
TSB43AB23PGE
iOHCI-Lynx
3.3 V
PGE
2 Terminal Descriptions
This section provides the terminal descriptions for the TSB43AB23 device. Figure 2–2 shows the signal assigned to
each terminal in the package. Table 2–1 and Table 2–3 provide a cross-reference between each terminal number and
the signal name on that terminal. Table 2–1 is arranged in terminal number order, and Table 2–3 lists signals in
alphabetical order.
2–1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
TSB43AB23
30
31
32
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
PCI_AD13
PCI_AD12
PCI_AD11
DGND
PCI_AD10
PCI_AD9
PCI_AD8
DVDD
PCI_C/BE0
PCI_AD7
DGND
PCI_AD6
PCI_AD5
VDDP
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
DGND
PCI_AD0
PCI_RST
CYCLEOUT
CYCLEIN
DVDD
GPIO3/TEST1
GPIO2/TEST0
SCL
SDA
REG18
PC2
PC1
PC0
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
DGND
PCI_C/BE3
VDDP
PCI_IDSEL
PCI_AD23
PCI_AD22
DVDD
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
DGND
PCI_AD17
PCI_AD16
PCI_C/BE2
VDDP
PCI_FRAME
PCI_IRDY
DVDD
PCI_TRDY
PCI_DEVSEL
PCI_STOP
DGND
PCI_PERR
PCI_SERR
PCI_PAR
DVDD
PCI_C/BE1
PCI_AD15
VDDP
PCI_AD14
DGND
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
PCI_AD24
PCI_AD25
REG18
PCI_AD26
PCI_AD27
DVDD
PCI_AD28
PCI_AD29
PCI_AD30
DGND
PCI_AD31
PCI_PME
VDDP
PCI_REQ
PCI_GNT
DGND
PCI_PCLK
DVDD
G_RST
PCI_INTA
PCI_CLKRUN
REG_EN
XO
XI
PLLGND
PLLVDD
FILTER1
FILTER0
R0
R1
AVDD
AGND
PDT PACKAGE
(TOP VIEW)
Figure 2–1. PDT Package Terminal Assignments
2–2
TPBIAS2
TPA2+
TPA2–
AVDD
TPB2+
TPB2–
AVDD
AGND
TPBIAS1
TPA1+
TPA1–
AVDD
AGND
TPB1+
TPB1–
AVDD
AGND
TPBIAS0
TPA0+
TPA0–
AGND
TPB0+
TPB0–
AGND
AVDD
AGND
AVDD
CPS
PHY_TEST_MA
CNA
DGND
DVDD
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
NC
NC
TPBIAS2
TPA2+
TPA2–
AVDD
TPB2+
TPB2–
AVDD
AGND
TPBIAS1
TPA1+
TPA1–
AVDD
AGND
TPB1+
TPB1–
AVDD
AGND
TPBIAS0
TPA0+
TPA0–
AGND
TPB0+
TPB0–
AGND
AVDD
AGND
AVDD
CPS
PHY_TEST_MA
CNA
DGND
DVDD
NC
NC
PGE PACKAGE
(TOP VIEW)
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
TSB43AB23
131
132
133
134
135
136
137
138
139
140
141
142
NC
NC
PC0
PC1
PC2
REG18
SDA
SCL
GPIO2/TEST0
GPIO3/TEST1
DVDD
CYCLEIN
CYCLEOUT
PCI_RST
PCI_AD0
DGND
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
VDDP
PCI_AD5
PCI_AD6
DGND
PCI_AD7
PCI_C/BE0
DVDD
PCI_AD8
PCI_AD9
PCI_AD10
DGND
PCI_AD11
PCI_AD12
PCI_AD13
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
143
144
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
NC
NC
DGND
PCI_C/BE3
VDDP
PCI_IDSEL
PCI_AD23
PCI_AD22
DVDD
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
DGND
PCI_AD17
PCI_AD16
PCI_C/BE2
VDDP
PCI_FRAME
PCI_IRDY
DVDD
PCI_TRDY
PCI_DEVSEL
PCI_STOP
DGND
PCI_PERR
PCI_SERR
PCI_PAR
DVDD
PCI_C/BE1
PCI_AD15
VDDP
PCI_AD14
DGND
NC
NC
NC
NC
AGND
AVDD
R1
R0
FILTER0
FILTER1
PLLVDD
PLLGND
XI
XO
REG_EN
PCI_CLKRUN
PCI_INTA
G_RST
DVDD
PCI_PCLK
DGND
PCI_GNT
PCI_REQ
VDDP
PCI_PME
PCI_AD31
DGND
PCI_AD30
PCI_AD29
PCI_AD28
DVDD
PCI_AD27
PCI_AD26
REG18
PCI_AD25
PCI_AD24
NC
NC
Figure 2–2. PGE Package Terminal Assignments
2–3
Table 2–1. PDT Package Signals Sorted by Terminal Number
NO.
2–4
TERMINAL NAME
NO.
TERMINAL NAME
NO.
TERMINAL NAME
NO.
TERMINAL NAME
1
DGND
33
PCI_AD13
65
AGND
PCI_C/BE3
34
PCI_AD12
66
DVDD
DGND
97
2
98
3
35
PCI_AD11
67
CNA
99
AVDD
R1
4
VDDP
PCI_IDSEL
36
DGND
68
PHY_TEST_MA
100
R0
5
PCI_AD23
37
PCI_AD10
69
CPS
101
FILTER0
6
PCI_AD22
38
PCI_AD9
70
FILTER1
DVDD
39
PCI_AD8
71
AVDD
AGND
102
7
103
8
PCI_AD21
40
72
104
9
PCI_AD20
41
DVDD
PCI_C/BE0
73
AVDD
AGND
105
PLLVDD
PLLGND
XI
10
PCI_AD19
42
PCI_AD7
74
TPB0–
106
XO
11
PCI_AD18
43
DGND
75
TPB0+
107
REG_EN
12
DGND
44
PCI_AD6
76
AGND
108
PCI_CLKRUN
13
PCI_AD17
45
PCI_AD5
77
TPA0–
109
PCI_INTA
14
PCI_AD16
46
TPA0+
110
G_RST
PCI_C/BE2
47
VDDP
PCI_AD4
78
15
79
TPBIAS0
111
DVDD
16
VDDP
PCI_FRAME
48
PCI_AD3
80
AGND
112
PCI_PCLK
17
49
PCI_AD2
81
113
DGND
18
PCI_IRDY
50
PCI_AD1
82
AVDD
TPB1–
114
PCI_GNT
19
DVDD
PCI_TRDY
51
DGND
83
TPB1+
115
PCI_REQ
20
52
PCI_AD0
84
AGND
116
21
PCI_DEVSEL
53
PCI_RST
85
117
VDDP
PCI_PME
22
PCI_STOP
54
CYCLEOUT
86
AVDD
TPA1–
118
PCI_AD31
23
DGND
55
CYCLEIN
87
TPA1+
119
DGND
24
PCI_PERR
56
TPBIAS1
120
PCI_AD30
PCI_SERR
57
DVDD
GPIO3/TEST1
88
25
89
AGND
121
PCI_AD29
26
PCI_PAR
58
GPIO2/TEST0
90
122
PCI_AD28
27
59
SCL
91
123
28
DVDD
PCI_C/BE1
AVDD
TPB2–
60
SDA
92
TPB2+
124
DVDD
PCI_AD27
29
PCI_AD15
61
REG18
93
PCI_AD26
62
PC2
94
126
REG18
31
VDDP
PCI_AD14
AVDD
TPA2–
125
30
63
PC1
95
TPA2+
127
PCI_AD25
32
DGND
64
PC0
96
TPBIAS2
128
PCI_AD24
Table 2–2. PGE Package Signals Sorted by Terminal Number
NO.
TERMINAL NAME
NO.
TERMINAL NAME
NO.
TERMINAL NAME
NO.
TERMINAL NAME
1
NC
37
NC
73
NC
109
NC
2
NC
38
NC
74
NC
110
NC
3
DGND
39
PCI_AD13
75
DVDD
111
AGND
4
PCI_C/BE3
40
PCI_AD12
76
DGND
112
5
41
PCI_AD11
77
CNA
113
AVDD
R1
6
VDDP
PCI_IDSEL
42
DGND
78
PHY_TEST_MA
114
R0
7
PCI_AD23
43
PCI_AD10
79
CPS
115
FILTER0
8
PCI_AD22
44
PCI_AD9
80
116
FILTER1
9
45
PCI_AD8
81
117
10
DVDD
PCI_AD21
AVDD
AGND
46
DVDD
82
118
PLLVDD
PLLGND
11
PCI_AD20
47
PCI_C/BE0
83
AVDD
AGND
119
XI
12
PCI_AD19
48
PCI_AD7
84
TPB0–
120
XO
13
PCI_AD18
49
DGND
85
TPB0+
121
REG_EN
14
DGND
50
PCI_AD6
86
AGND
122
PCI_CLKRUN
15
PCI_AD17
51
PCI_AD5
87
TPA0–
123
PCI_INTA
16
PCI_AD16
52
TPA0+
124
G_RST
PCI_C/BE2
53
VDDP
PCI_AD4
88
17
89
TPBIAS0
125
18
54
PCI_AD3
90
AGND
126
DVDD
PCI_PCLK
19
VDDP
PCI_FRAME
55
PCI_AD2
91
DGND
PCI_RDY
56
PCI_AD1
92
AVDD
TPB1–
127
20
128
PCI_GNT
21
57
DGND
93
TPB1+
129
PCI_REQ
22
DVDD
PCI_TRDY
58
PCI_AD0
94
AGND
130
23
PCI_DEVSEL
59
PCI_RST
95
131
VDDP
PCI_PME
24
PCI_STOP
60
CYCLEOUT
96
AVDD
TPA1–
132
PCI_AD31
25
DGND
61
CYCLEIN
97
TPA1+
133
DGND
26
PCI_PERR
62
DVDD
98
TPBIAS1
134
PCI_AD30
27
PCI_SERR
63
GPIO3/TEST1
99
AGND
135
PCI_AD29
28
PCI_PAR
64
GPIO2/TEST0
100
136
PCI_AD28
29
65
SCL
101
137
30
DVDD
PCI_C/BE1
AVDD
TPB2–
66
SDA
102
TPB2+
138
DVDD
PCI_AD27
31
PCI_AD15
67
REG18
103
139
PCI_AD26
32
VDDP
68
PC2
104
AVDD
TPA2–
140
REG18
33
PCI_AD14
69
PC1
105
TPA2+
141
PCI_AD25
34
DGND
70
PC0
106
TPBIAS2
142
PCI_AD24
35
NC
71
NC
107
NC
143
NC
36
NC
72
NC
108
NC
144
NC
2–5
Table 2–3. Signal Names Sorted Alphanumerically to Terminal Number
2–6
TERMINAL
NAME
PDT
NO.
PGE
NO.
TERMINAL
NAME
PDT
NO.
PGENO.
TERMINAL
NAME
PDT
NO.
PGENO.
TERMINAL
NAME
AGND
71
81
62
PCI_AD23
73
83
DVDD
DVDD
56
AGND
65
75
PCI_AD24
AGND
76
86
125
PCI_AD25
127
80
90
DVDD
DVDD
111
AGND
123
137
PCI_AD26
125
AGND
84
94
FILTER0
101
115
PCI_AD27
AGND
89
99
FILTER1
102
116
AGND
97
111
GPIO2/TEST0
58
64
AVDD
AVDD
70
80
GPIO3/TEST1
57
72
82
G_RST
110
AVDD
AVDD
81
91
PCI_AD0
52
85
95
PCI_AD1
AVDD
AVDD
90
100
PCI_AD2
93
103
AVDD
CNA
98
112
67
PDT
NO.
PGENO.
5
7
PHY_TEST_MA
68
78
128
142
104
118
141
PLLGND
PLLVDD
103
117
139
REG18
61
67
124
138
REG18
126
140
PCI_AD28
122
136
REG_EN
107
121
PCI_AD29
121
135
R1
99
113
63
PCI_AD30
120
134
R0
100
114
124
PCI_AD31
118
132
SCL
59
65
58
PCI_C/BE0
41
47
SDA
60
66
50
56
PCI_C/BE1
28
30
TPA0–
77
87
49
55
PCI_C/BE2
15
17
TPA0+
78
88
PCI_AD3
48
54
PCI_C/BE3
2
4
TPA1–
86
96
PCI_AD4
47
53
PCI_CLKRUN
108
122
TPA1+
87
97
77
PCI_AD5
45
51
PCI_DEVSEL
21
23
TPA2–
94
104
CPS
69
79
PCI_AD6
44
50
PCI_FRAME
17
19
TPA2+
95
105
CYCLEIN
55
61
PCI_AD7
42
48
PCI_GNT
114
128
TPBIAS0
79
89
CYCLEOUT
54
60
PCI_AD8
39
45
PCI_IDSEL
4
6
TPBIAS1
88
98
DGND
1
3
PCI_AD9
38
44
PCI_INTA
109
123
TPBIAS2
96
106
DGND
12
14
PCI_AD10
37
43
PCI_IRDY
18
20
TPB0–
74
84
DGND
23
25
PCI_AD11
35
41
PCI_PAR
26
28
TPB0+
75
85
DGND
32
34
PCI_AD12
34
40
PCI_PCLK
112
126
TPB1–
82
92
DGND
36
42
PCI_AD13
33
39
PCI_PERR
24
26
TPB1+
83
93
DGND
43
49
PCI_AD14
31
33
PCI_PME
117
131
TPB2–
91
101
DGND
51
57
PCI_AD15
29
31
PCI_REQ
115
129
TPB2+
92
102
VDDP
VDDP
3
5
16
18
VDDP
VDDP
30
32
46
52
116
130
105
119
106
120
DGND
66
76
PCI_AD16
14
16
PCI_RST
53
59
DGND
113
127
PCI_AD17
13
15
PCI_SERR
25
27
DGND
119
133
PCI_AD18
11
13
PCI_STOP
22
24
DVDD
7
9
PCI_AD19
10
12
PCI_TRDY
20
22
DVDD
19
21
PCI_AD20
9
11
PC0
64
70
DVDD
27
29
PCI_AD21
8
10
PC1
63
69
VDDP
XI
DVDD
40
46
PCI_AD22
6
8
PC2
62
68
XO
The terminals are grouped in tables by functionality, such as PCI system function and power supply function (see
Table 2–4 through Table 2–9). The terminal numbers are also listed for convenient reference.
Table 2–4. PCI System Terminals
TERMINAL
NAME
PDT
NO.
PGE
NO.
I/O
DESCRIPTION
G_RST
110
124
I
Global power reset. This reset brings all of the TSB43AB23 internal registers to their default states,
including those registers not reset by PCI_RST. When G_RST is asserted, the device is completely
nonfunctional, placing all output buffers in a high impedance state.
When implementing wake capabilities from the 1394 host controller, it is necessary to implement two
resets to the TSB43AB23 device. G_RST is designed to be a one-time power-on reset, and PCI_RST
must be connected to the PCI bus RST. G_RST must be asserted for a minimum of 2 ms.
PCI_PCLK
112
126
I
PCI bus clock. Provides timing for all transactions on the PCI bus. All PCI signals are sampled at the
rising edge of PCI_CLK.
PCI_INTA
109
123
O
Interrupt signal. This output indicates interrupts from the TSB43AB23 device to the host. This terminal
is implemented as open-drain.
I
PCI reset. When this bus reset is asserted, the TSB43AB23 device places all output buffers in a
high-impedance state and resets all internal registers except device power management context- and
vendor-specific bits initialized by host power-on software. When PCI_RST is asserted, the device is
completely nonfunctional. Connect this terminal to PCI bus RST.
PCI_RST
53
59
Table 2–5. PCI Address and Data Terminals
TERMINAL
NAME
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PDT
NO.
PGE
NO.
118
120
121
122
124
125
127
128
5
6
8
9
10
11
13
14
29
31
33
34
35
37
38
39
42
44
45
47
48
49
50
52
132
134
135
136
138
139
141
142
7
8
10
11
12
13
15
16
31
33
39
40
41
43
44
45
48
50
51
53
54
55
56
58
I/O
DESCRIPTION
I/O
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the PCI
interface. During the address phase of a PCI cycle, AD31–AD0 contain a 32-bit address or other
destination information. During the data phase, AD31–AD0 contain data.
2–7
Table 2–6. PCI Interface Control Terminals
TERMINAL
NAME
PDT
NO.
PGE
NO.
I/O
DESCRIPTION
PCI_CLKRUN
108
122
I/O
Clock run. This terminal provides clock control through the CLKRUN protocol. This terminal is
implemented as open-drain and must be pulled low through a 10-kΩ nominal resistor for designs where
CLKRUN is not implemented. For mobile applications where CLKRUN is implemented, the pullup
resistor is typically provided by the system central resource.
PCI_C/BE0
PCI_C/BE1
PCI_C/BE2
PCI_C/BE3
41
28
15
2
47
30
17
4
I/O
PCI bus commands and byte enables. The command and byte enable signals are multiplexed on the
same PCI terminals. During the address phase of a bus cycle, PCI_C/BE3–PCI_C/BE0 define the bus
command. During the data phase, this 4-bit bus is used for byte enables.
PCI_DEVSEL
21
23
I/O
PCI device select. The TSB43AB23 device asserts this signal to claim a PCI cycle as the target device.
As a PCI initiator, the TSB43AB23 device monitors this signal until a target responds. If no target
responds before time-out occurs, the TSB43AB23 device terminates the cycle with an initiator abort.
PCI_FRAME
17
19
I/O
PCI cycle frame. This signal is driven by the initiator of a PCI bus cycle. PCI_FRAME is asserted to
indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted.
When PCI_FRAME is deasserted, the PCI bus transaction is in the final data phase.
PCI_GNT
114
128
I
PCI bus grant. This signal is driven by the PCI bus arbiter to grant the TSB43AB23 device access to
the PCI bus after the current data transaction has completed. This signal may or may not follow a PCI
bus request, depending upon the PCI bus parking algorithm.
PCI_IDSEL
4
6
I
Initialization device select. PCI_IDSEL selects the TSB43AB23 device during configuration space
accesses. PCI_IDSEL can be connected to 1 of the upper 21 PCI address lines on the PCI bus.
PCI_IRDY
18
20
I/O
PCI initiator ready. PCI_IRDY indicates the ability of the PCI bus initiator to complete the current data
phase of the transaction. A data phase is completed upon a rising edge of PCI_CLK where both
PCI_IRDY and PCI_TRDY are asserted.
PCI_PAR
26
28
I/O
PCI parity. In all PCI bus read and write cycles, the TSB43AB23 device calculates even parity across
the PCI_AD and PCI_C/BE buses. As an initiator during PCI cycles, the TSB43AB23 device outputs
this parity indicator with a one-PCI_CLK delay. As a target during PCI cycles, the calculated parity is
compared to the initiator parity indicator; a miscompare can result in a parity error assertion
(PCI_PERR).
PCI_PERR
24
26
I/O
PCI parity error indicator. This signal is driven by a PCI device to indicate that calculated parity does
not match PCI_PAR when bit 6 (PERR_ENB) is set to 1 in the command register at offset 04h in the
PCI configuration space (see Section 3.4, Command Register).
PCI_PME
117
131
O
Power management event. This terminal indicates wake events to the host and is implemented as an
open-drain output.
PCI_REQ
115
129
O
PCI bus request. Asserted by the TSB43AB23 device to request access to the bus as an initiator. The
host arbiter asserts PCI_GNT when the TSB43AB23 device has been granted access to the bus.
PCI_SERR
25
27
O
PCI system error. When bit 8 (SERR_ENB) in the command register at offset 04h in the PCI
configuration space (see Section 3.4, Command Register) is set to 1, the output is pulsed, indicating
an address parity error has occurred. The TSB43AB23 device need not be the target of the PCI cycle
to assert this signal. This terminal is implemented as open-drain.
PCI_STOP
22
24
I/O
PCI cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current PCI
bus transaction. This signal is used for target disconnects, and is commonly asserted by target devices
which do not support burst data transfers.
PCI_TRDY
20
22
I/O
PCI target ready. PCI_TRDY indicates the ability of the PCI bus target to complete the current data
phase of the transaction. A data phase is completed upon a rising edge of PCI_CLK where both
PCI_IRDY and PCI_TRDY are asserted.
2–8
Table 2–7. Miscellaneous Terminals
TERMINAL
NAME
CYCLEIN
PDT
NO.
PGE
NO.
I/O
DESCRIPTION
55
61
I/O
The CYCLEIN terminal allows an external 8-kHz clock to be used as a cycle timer for synchronization
with other system devices.
If this terminal is not implemented, it must be pulled high to DVDD through a pullup resistor.
CYCLEOUT
54
60
I/O
The CYCLEOUT terminal provides an 8-kHz cycle timer synchronization signal. If CYCLEOUT is not
implemented, this terminal must be pulled down to ground through a pulldown resistor.
REG_EN
107
121
I
Regulator enable. This terminal must be tied to ground to enable the internal voltage regulator. When
using a single 3.3-V supply, this terminal must be tied to ground to enable the internal voltage regulator.
When using a dual 1.8-V/3.3-V supply to provide power to the device, REG_EN must be pulled to DVDD
to disable the internal voltage regulator.
GPIO2/TEST0
58
64
I/O
General-purpose I/O [2]. This terminal defaults as an input and if it is not implemented, it is
recommended that it be pulled low to ground with a 220-Ω resistor.
GPIO3/TEST1
57
63
I/O
General-purpose I/O [3]. This terminal defaults as an input and if it is not implemented, it is
recommended that it be pulled low to ground with a 220-Ω resistor.
SCL
59
65
I/O
Serial clock. This terminal provides the serial clock signaling and is implemented as open-drain. For
normal operation (a ROM is implemented in the design), this terminal must be pulled high to the ROM
DVDD with a 2.7-kΩ resistor. Otherwise, it must be pulled low to ground with a 220-Ω resistor.
Serial data. At PCI_RST, the SDA signal is sampled to determine if a two-wire serial ROM is present.
If the serial ROM is detected, this terminal provides the serial data signaling.
SDA
60
66
I/O
This terminal is implemented as open-drain, and for normal operation (a ROM is implemented in the
design), this terminal must be pulled high to the ROM DVDD with a 2.7-kΩ resistor. Otherwise, it must
be pulled low to ground with a 220-Ω resistor.
2–9
Table 2–8. Physical Layer Terminals
TERMINAL
NAME
PDT
NO.
PGE
NO.
TYPE
I/O
DESCRIPTION
Cable not active. This terminal is asserted high when there are no ports receiving incoming
bias voltage. If not used, this terminal must be strapped either to DVDD or to GND through
a resistor. To enable the CNA terminal, the BIOS must set bit 7 (CNAOUT) of the PCI PHY
control register at offset ECh in the PCI configuration space (see Section 3.20, PCI PHY
Control Register). If an EEPROM is implemented and CNA functionality is needed, bit 7 of
byte offset 16h in the serial EEPROM must be set. This sets the bit in the PCI configuration
space at power up via the EEPROM.
CNA
67
77
CMOS
I/O
CPS
69
79
CMOS
I
FILTER0
FILTER1
101
102
115
116
CMOS
I/O
PC0
PC1
PC2
64
63
62
70
69
68
CMOS
I
Power class programming inputs. On hardware reset, these inputs set the default value of
the power class indicated during self-ID. Programming is done by tying these terminals high
or low.
R0
R1
100
99
114
113
Bias
–
Current-setting resistor terminals. These terminals are connected to an external resistance
to set the internal operating currents and cable driver output currents. A resistance of
6.34 kΩ ±1% is required to meet the IEEE Std 1394-1995 output voltage limits.
TPA0+
TPA0–
78
77
88
87
Cable
I/O
TPA1+
TPA1–
87
86
97
96
Cable
I/O
TPA2+
TPA2–
95
94
105
104
Cable
I/O
TPB0+
TPB0–
75
74
85
84
Cable
I/O
TPB1+
TPB1–
83
82
93
92
Cable
I/O
TPB2+
TPB2–
92
91
102
101
Cable
I/O
TPBIAS0
TPBIAS1
TPBIAS2
79
88
96
89
98
106
XI
XO
2–10
105
106
119
120
Cable
Crystal
Cable power status input. This terminal is normally connected to cable power through a
400-kΩ resistor. This circuit drives an internal comparator that detects the presence of cable
power. If CPS does not detect cable power, this terminal must be pulled to AVDD.
PLL filter terminals. These terminals are connected to an external capacitance to form a
lag-lead filter required for stable operation of the internal frequency multiplier PLL running
off of the crystal oscillator. A 0.1-µF ±10% capacitor is the only external component required
to complete this filter.
Twisted-pair cable A differential signal terminals. Board trace lengths from each pair of
positive and negative differential signal pins must be matched and as short as possible to
the external load resistors and to the cable connector.
connector
Twisted-pair cable B differential signal terminals. Board trace lengths from each pair of
positive and negative differential signal pins must be matched and as short as possible to
the external load resistors and to the cable connector.
connector
I/O
Twisted-pair bias output. This provides the 1.86-V nominal bias voltage needed for proper
operation of the twisted-pair cable drivers and receivers and for signaling to the remote
nodes that there is an active cable connection. Each of these pins must be decoupled with
a 1.0-µF capacitor to ground.
–
Crystal oscillator inputs. These pins connect to a 24.576-MHz parallel resonant fundamental
mode crystal. The optimum values for the external shunt capacitors are dependent on the
specifications of the crystal used (see Section 8.2, Crystal Selection). Terminal 5 has an
internal 10-kΩ (nominal value) pulldown resistor. An external clock input can be connected
to the XI terminal. When using an external clock input, the XO terminal must be left
unconnected. Refer to Section 9.7 for the operating characteristics of the XI terminal.
Table 2–9. Power Supply Terminals
TERMINAL
NAME
AGND
PDT
NO.
PGE
NO.
71, 73, 76, 80,
84, 89, 97
81, 83, 86, 90,
94, 99, 111
TYPE
I/O
DESCRIPTION
Supply
–
Analog circuit ground terminals. These terminals must be tied together
to the low-impedance circuit board ground plane.
AVDD
70, 72, 81, 85,
90, 93, 98
80, 82, 91, 95,
100, 103, 112
Supply
–
Analog circuit power terminals. A parallel combination of high
frequency decoupling capacitors near each terminal is suggested,
such as 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering
capacitors are also recommended. These supply terminals are
separated from PLLVDD and DVDD internal to the device to provide
noise isolation. They must be tied at a low-impedance point on the
circuit board.
DGND
1, 12, 23, 32,
36, 43, 51, 66,
113, 119
3, 14, 25, 34,
42, 49, 57, 76,
127, 133
Supply
–
Digital circuit ground terminals. These terminals must be tied together
to the low-impedance circuit board ground plane.
7, 19, 27, 40,
56, 65, 111,
123
9, 21, 29, 46,
62, 75, 125,
137
Supply
–
Digital circuit power terminals. A parallel combination of high frequency
decoupling capacitors near each DVDD terminal is suggested, such as
0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are
also recommended. These supply terminals are separated from
PLLVDD and AVDD internal to the device to provide noise isolation. They
must be tied at a low-impedance point on the circuit board.
PHY_TEST_MA
68
78
–
–
Test control input. This input is used in the manufacturing test of the
TSB43AB23 device. For normal use, the terminal must be tied to DVDD.
PLLGND
104
118
Supply
–
PLL circuit ground terminal. This terminal must be tied to the
low-impedance circuit board ground plane.
–
PLL circuit power terminal. A parallel combination of high frequency
decoupling capacitors near the terminal is suggested, such as 0.1 µF
and 0.001 µF. Lower frequency 10-µF filtering capacitors are also
recommended. This supply terminal is separated from DVDD and AVDD
internal to the device to provide noise isolation. It must be tied to a
low-impedance point on the circuit board.
DVDD
PLLVDD
103
117
Supply
REG18
61, 126
67, 140
Supply
–
REG18. 1.8-V power supply for the device core. The internal voltage
regulator provides 1.8 V from DVDD. When the internal regulator is
disabled (REG_EN is high), the REG18 terminals can be used to supply
an external 1.8-V supply to the TSB43AB23 core. It is recommended
that 0.1-µF bypass capacitors be used and placed close to these
terminals.
VDDP
3, 16, 30, 46,
116
5, 18, 32, 52,
130
Supply
–
PCI signaling clamp voltage power input. PCI signals are clamped per
the PCI Local Bus Specification. In addition, if a 5-V ROM is used, the
VDDP must be connected to 5 V.
2–11
3 TSB43AB23 1394 OHCI Controller Programming Model
This section describes the internal PCI configuration registers used to program the TSB43AB23 1394 open host
controller interface. All registers are detailed in the same format: a brief description for each register is followed by
the register offset and a bit table describing the reset state for each register.
A bit description table, typically included when the register contains bits of more than one type or purpose, indicates
bit field names, a detailed field description, and field access tags which appear in the type column. Table 3–1
describes the field access tags.
Table 3–1. Bit Field Access Tag Descriptions
ACCESS TAG
NAME
R
Read
Field can be read by software.
MEANING
W
Write
Field can be written by software to any value.
S
Set
C
Clear
Field can be cleared by a write of 1. Writes of 0 have no effect.
U
Update
Field can be autonomously updated by the TSB43AB23 device.
Field can be set by a write of 1. Writes of 0 have no effect.
Figure 3–1 shows a simplified block diagram of the TSB43AB23 device.
3–1
PCI
Target
SM
Internal
Registers
Serial
ROM
OHCI PCI Power
Mgmt and CLKRUN
GPIOs
Isochronous
Transmit
Contexts
Asynchronous
Transmit
Contexts
Misc
Interface
Transmit
FIFO
Physical DMA
and Response
Resp
Time-out
PCI
Host
Bus
Interface
Central
Arbiter
and
PCI
Initiator
SM
Link
Transmit
Receive
Acknowledge
PHY
Register
Access
and
Status
Monitor
Cycle Start
Generator and
Cycle Monitor
Request
Filters
Synthesized
Bus Reset
Link
Receive
General
Request Receive
Asynchronous
Response
Receive
PHY/
Link
Interface
Receive
FIFO
Isochronous
Receive
Contexts
Cable Port 0
Received Data
Decoder/Retimer
Cable Port 1
Arbitration
and Control
State Machine
Logic
Cable Port 2
Crystal
Oscillator,
PLL System,
and Clock
Generator
Bias Voltage
and
Current Generator
Transmit Data
Encoder
Figure 3–1. TSB43AB23 Block Diagram
3–2
CRC
3.1 PCI Configuration Registers
The TSB43AB23 device is a single-function PCI device. The configuration header is compliant with the PCI Local Bus
Specification as a standard header. Table 3–2 illustrates the PCI configuration header that includes both the
predefined portion of the configuration space and the user-definable registers.
Table 3–2. PCI Configuration Register Map
REGISTER NAME
OFFSET
Device ID
Vendor ID
00h
Status
Command
04h
Class code
BIST
Header type
Latency timer
Revision ID
08h
Cache line size
0Ch
OHCI base address
10h
TI extension base address
14h
Reserved
18h–2Bh
Subsystem ID
Subsystem vendor ID
2Ch
Reserved
30h
Reserved
PCI power
management
capabilities pointer
34h
Interrupt line
3Ch
Reserved
Maximum latency
Minimum grant
38h
Interrupt pin
OHCI control
Power management capabilities
PM data
PMCSR_BSE
Capability ID
44h
Power management control and status
48h
Reserved
4Ch–EBh
PCI PHY control
ECh
Miscellaneous configuration
F0h
Link enhancement control
F4h
Subsystem device ID alias
GPIO3
40h
Next item pointer
Subsystem vendor ID alias
F8h
Reserved
FCh
GPIO2
3.2 Vendor ID Register
The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device.
The vendor ID assigned to Texas Instruments is 104Ch.
Bit
15
14
13
12
11
10
9
Name
8
7
6
5
4
3
2
1
0
Vendor ID
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
1
0
0
0
0
0
1
0
0
1
1
0
0
Register:
Offset:
Type:
Default:
Vendor ID
00h
Read-only
104Ch
3–3
3.3 Device ID Register
The device ID register contains a value assigned to the TSB43AB23 device by Texas Instruments. The device
identification for the TSB43AB23 device is 8024h.
Bit
15
14
13
12
11
10
9
Type
R
R
R
R
R
R
R
R
Default
1
0
0
0
0
0
0
0
Name
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
0
0
1
0
0
1
0
0
Device ID
Register:
Offset:
Type:
Default:
Device ID
02h
Read-only
8024h
3.4 Command Register
The command register provides control over the TSB43AB23 interface to the PCI bus. All bit functions adhere to the
definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 3–3 for a complete
description of the register contents.
Bit
15
14
13
12
11
10
9
Name
8
7
6
5
4
3
2
1
0
Command
Type
R
R
R
R
R
R
R
R/W
R
R/W
R
R/W
R
R/W
R/W
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Command
04h
Read/Write, Read-only
0000h
Table 3–3. Command Register Description
BIT
FIELD NAME
TYPE
15–10
RSVD
R
Reserved. Bits 15–10 return 0s when read.
9
FBB_ENB
R
Fast back-to-back enable. The TSB43AB23 device does not generate fast back-to-back transactions;
therefore, bit 9 returns 0 when read.
8
SERR_ENB
R/W
PCI_SERR enable. When bit 8 is set to 1, the TSB43AB23 PCI_SERR driver is enabled. PCI_SERR
can be asserted after detecting an address parity error on the PCI bus.
7
STEP_ENB
R
Address/data stepping control. The TSB43AB23 device does not support address/data stepping;
therefore, bit 7 is hardwired to 0.
6
PERR_ENB
R/W
Parity error enable. When bit 6 is set to 1, the TSB43AB23 device is enabled to drive PCI_PERR
response to parity errors through the PCI_PERR signal.
5
VGA_ENB
R
VGA palette snoop enable. The TSB43AB23 device does not feature VGA palette snooping; therefore,
bit 5 returns 0 when read.
4
MWI_ENB
R/W
Memory write and invalidate enable. When bit 4 is set to 1, the TSB43AB23 device is enabled to
generate MWI PCI bus commands. If this bit is cleared, the TSB43AB23 device generates memory
write commands instead.
3
SPECIAL
R
Special cycle enable. The TSB43AB23 function does not respond to special cycle transactions;
therefore, bit 3 returns 0 when read.
2
MASTER_ENB
R/W
Bus master enable. When bit 2 is set to 1, the TSB43AB23 device is enabled to initiate cycles on the
PCI bus.
1
MEMORY_ENB
R/W
Memory response enable. Setting bit 1 to 1 enables the TSB43AB23 device to respond to memory
cycles on the PCI bus. This bit must be set to access OHCI registers.
0
IO_ENB
R
I/O space enable. The TSB43AB23 device does not implement any I/O-mapped functionality;
therefore, bit 0 returns 0 when read.
3–4
DESCRIPTION
3.5 Status Register
The status register provides status over the TSB43AB23 interface to the PCI bus. All bit functions adhere to the
definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 3–4 for a complete
description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RCU
RCU
RCU
RCU
RCU
R
R
RCU
0
0
0
0
0
0
1
R
R
R
R
R
R
R
R
0
0
0
0
1
0
0
0
0
Name
Type
Default
Status
Register:
Offset:
Type:
Default:
Status
06h
Read/Clear/Update, Read-only
0210h
Table 3–4. Status Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15
PAR_ERR
RCU
Detected parity error. Bit 15 is set to 1 when either an address parity or data parity error is detected.
14
SYS_ERR
RCU
Signaled system error. Bit 14 is set to 1 when PCI_SERR is enabled and the TSB43AB23 device has
signaled a system error to the host.
13
MABORT
RCU
Received master abort. Bit 13 is set to 1 when a cycle initiated by the TSB43AB23 device on the PCI
bus has been terminated by a master abort.
12
TABORT_REC
RCU
Received target abort. Bit 12 is set to 1 when a cycle initiated by the TSB43AB23 device on the PCI
bus was terminated by a target abort.
11
TABORT_SIG
RCU
Signaled target abort. Bit 11 is set to 1 by the TSB43AB23 device when it terminates a transaction on
the PCI bus with a target abort.
10–9
PCI_SPEED
R
DEVSEL timing. Bits 10 and 9 encode the timing of PCI_DEVSEL and are hardwired to 01b, indicating
that the TSB43AB23 device asserts this signal at a medium speed on nonconfiguration cycle
accesses.
8
DATAPAR
RCU
Data parity error detected. Bit 8 is set to 1 when the following conditions have been met:
a. PCI_PERR was asserted by any PCI device including the TSB43AB23 device.
b. The TSB43AB23 device was the bus master during the data parity error.
c. Bit 6 (PERR_EN) in the command register at offset 04h in the PCI configuration space
(see Section 3.4, Command Register) is set to 1.
7
FBB_CAP
R
Fast back-to-back capable. The TSB43AB23 device cannot accept fast back-to-back transactions;
therefore, bit 7 is hardwired to 0.
6
UDF
R
User-definable features (UDF) supported. The TSB43AB23 device does not support the UDF;
therefore, bit 6 is hardwired to 0.
5
66MHZ
R
66-MHz capable. The TSB43AB23 device operates at a maximum PCI_CLK frequency of 33 MHz;
therefore, bit 5 is hardwired to 0.
4
CAPLIST
R
Capabilities list. Bit 4 returns 1 when read, indicating that capabilities additional to standard PCI are
implemented. The linked list of PCI power-management capabilities is implemented in this function.
3–0
RSVD
R
Reserved. Bits 3–0 return 0s when read.
3–5
3.6 Class Code and Revision ID Register
The class code and revision ID register categorizes the TSB43AB23 device as a serial bus controller (0Ch),
controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is
indicated in the least significant byte. See Table 3–5 for a complete description of the register contents.
Bit
31
30
29
28
27
26
Name
25
24
23
22
21
20
19
18
17
16
Class code and revision ID
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Class code and revision ID
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Class code and revision ID
08h
Read-only
0C00 1000h
Table 3–5. Class Code and Revision ID Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31–24
BASECLASS
R
Base class. This field returns 0Ch when read, which broadly classifies the function as a serial bus
controller.
23–16
SUBCLASS
R
Subclass. This field returns 00h when read, which specifically classifies the function as controlling an
IEEE 1394 serial bus.
15–8
PGMIF
R
Programming interface. This field returns 10h when read, which indicates that the programming model
is compliant with the 1394 Open Host Controller Interface Specification.
7–0
CHIPREV
R
Silicon revision. This field returns 00h when read, which indicates the silicon revision of the
TSB43AB23 device.
3.7 Latency Timer and Class Cache Line Size Register
The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size
and the latency timer associated with the TSB43AB23 device. See Table 3–6 for a complete description of the register
contents.
Bit
15
14
13
12
11
10
Name
Type
Default
9
8
7
6
5
4
3
2
1
0
Latency timer and class cache line size
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Latency timer and class cache line size
0Ch
Read/Write
0000h
Table 3–6. Latency Timer and Class Cache Line Size Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15–8
LATENCY_TIMER
R/W
PCI latency timer. The value in this register specifies the latency timer for the TSB43AB23 device, in
units of PCI clock cycles. When the TSB43AB23 device is a PCI bus initiator and asserts PCI_FRAME,
the latency timer begins counting from zero. If the latency timer expires before the TSB43AB23
transaction has terminated, the TSB43AB23 device terminates the transaction when its PCI_GNT is
deasserted.
7–0
CACHELINE_SZ
R/W
Cache line size. This value is used by the TSB43AB23 device during memory write and invalidate,
memory-read line, and memory-read multiple transactions.
3–6
3.8 Header Type and BIST Register
The header type and built-in self-test (BIST) register indicates the TSB43AB23 PCI header type and no built-in
self-test. See Table 3–7 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
Name
8
7
6
5
4
3
2
1
0
Header type and BIST
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Header type and BIST
0Eh
Read-only
0000h
Table 3–7. Header Type and BIST Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15–8
BIST
R
Built-in self-test. The TSB43AB23 device does not include a BIST; therefore, this field returns 00h when
read.
7–0
HEADER_TYPE
R
PCI header type. The TSB43AB23 device includes the standard PCI header, which is communicated
by returning 00h when this field is read.
3.9 OHCI Base Address Register
The OHCI base address register is programmed with a base address referencing the memory-mapped OHCI control.
When BIOS writes all 1s to this register, the value read back is FFFF F800h, indicating that at least 2K bytes of
memory address space are required for the OHCI registers. See Table 3–8 for a complete description of the register
contents.
Bit
31
30
29
28
27
26
25
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Type
24
23
22
21
20
19
18
17
16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OHCI base address
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
OHCI base address
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
OHCI base address
10h
Read/Write, Read-only
0000 0000h
Table 3–8. OHCI Base Address Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31–11
OHCIREG_PTR
R/W
OHCI register pointer. This field specifies the upper 21 bits of the 32-bit OHCI base address register.
10–4
OHCI_SZ
R
OHCI register size. This field returns 0s when read, indicating that the OHCI registers require a
2K-byte region of memory.
3
OHCI_PF
R
OHCI register prefetch. Bit 3 returns 0 when read, indicating that the OHCI registers are
nonprefetchable.
2–1
OHCI_MEMTYPE
R
OHCI memory type. This field returns 0s when read, indicating that the OHCI base address register
is 32 bits wide and mapping can be done anywhere in the 32-bit memory space.
0
OHCI_MEM
R
OHCI memory indicator. Bit 0 returns 0 when read, indicating that the OHCI registers are mapped
into system memory space.
3–7
3.10 TI Extension Base Address Register
The TI extension base address register is programmed with a base address referencing the memory-mapped TI
extension registers. When BIOS writes all 1s to this register, the value read back is FFFF C000h, indicating that at
least 16K bytes of memory address space are required for the TI registers. See Table 3–9 for a complete description
of the register contents.
Bit
31
30
29
28
27
26
25
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
Name
Type
Default
23
22
21
20
19
18
17
16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
6
5
4
3
2
1
0
TI extension base address
Name
Type
24
TI extension base address
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
TI extension base address
14h
Read/Write, Read-only
0000 0000h
Table 3–9. TI Base Address Register Description
BIT
FIELD NAME
TYPE
31–14
TIREG_PTR
R/W
13–4
TI_SZ
R
TI register size. This field returns 0s when read, indicating that the TI registers require a 16K-byte
region of memory.
3–8
DESCRIPTION
TI register pointer. This field specifies the upper 18 bits of the 32-bit TI base address register.
3
TI_PF
R
TI register prefetch. Bit 3 returns 0 when read, indicating that the TI registers are nonprefetchable.
2–1
TI_MEMTYPE
R
TI memory type. This field returns 0s when read, indicating that the TI base address register is 32 bits
wide and mapping can be done anywhere in the 32-bit memory space.
0
TI_MEM
R
TI memory indicator. Bit 0 returns 0 when read, indicating that the TI registers are mapped into system
memory space.
3.11 Subsystem Identification Register
The subsystem identification register is used for system and option card identification purposes. This register can
be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCI
configuration space (see Section 3.23, Subsystem Access Register). See Table 3–10 for a complete description of
the register contents.
Bit
31
30
29
28
27
26
25
RU
RU
RU
RU
RU
RU
RU
RU
RU
Default
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
Name
Type
Default
23
22
21
20
19
18
17
16
RU
RU
RU
RU
RU
RU
RU
0
0
0
0
0
0
0
6
5
4
3
2
1
0
Subsystem identification
Name
Type
24
Subsystem identification
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Subsystem identification
2Ch
Read/Update
0000 0000h
Table 3–10. Subsystem Identification Register Description
BIT
FIELD NAME
TYPE
31–16
OHCI_SSID
RU
Subsystem device ID. This field indicates the subsystem device ID.
DESCRIPTION
15–0
OHCI_SSVID
RU
Subsystem vendor ID. This field indicates the subsystem vendor ID.
3.12 Power Management Capabilities Pointer Register
The power management capabilities pointer register provides a pointer into the PCI configuration header where the
power-management register block resides. The TSB43AB23 configuration header doublewords at offsets 44h and
48h provide the power-management registers. This register is read-only and returns 44h when read.
Bit
7
6
5
Name
4
3
2
1
0
Power management capabilities pointer
Type
R
R
R
R
R
R
R
R
Default
0
1
0
0
0
1
0
0
Register:
Offset:
Type:
Default:
Power management capabilities pointer
34h
Read-only
44h
3–9
3.13 Interrupt Line and Pin Register
The interrupt line and pin register communicates interrupt line routing information. See Table 3–11 for a complete
description of the register contents.
Bit
15
14
13
12
11
10
9
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
1
Name
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Interrupt line and pin
Register:
Offset:
Type:
Default:
Interrupt line and pin
3Ch
Read/Write
0100h
Table 3–11. Interrupt Line and Pin Registers Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15–8
INTR_PIN
R
Interrupt pin. This field returns 01h when read, indicating that the TSB43AB23 PCI function signals
interrupts on the PCI_INTA terminal.
7–0
INTR_LINE
R/W
Interrupt line. This field is programmed by the system and indicates to software which interrupt line the
TSB43AB23 PCI_INTA is connected to.
3.14 MIN_GNT and MAX_LAT Register
The MIN_GNT and MAX_LAT register communicates to the system the desired setting of bits 15–8 in the latency timer
and class cache line size register at offset 0Ch in the PCI configuration space (see Section 3.7, Latency Timer and
Class Cache Line Size Register). If a serial EEPROM is detected, the contents of this register are loaded through
the serial EEPROM interface after a G_RST. If no serial EEPROM is detected, this register returns a default value
that corresponds to the MAX_LAT = 4, MIN_GNT = 2. See Table 3–12 for a complete description of the register
contents.
Bit
15
14
13
12
11
10
Name
Type
Default
9
8
7
6
5
4
3
2
1
0
MIN_GNT and MAX_LAT
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
Register:
Offset:
Type:
Default:
MIN_GNT and MAX_LAT
3Eh
Read/Update
0402h
Table 3–12. MIN_GNT and MAX_LAT Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15–8
MAX_LAT
RU
Maximum latency. The contents of this field may be used by host BIOS to assign an arbitration priority level
to the TSB43AB23 device. The default for this register indicates that the TSB43AB23 device may need to
access the PCI bus as often as every 0.25 µs; thus, an extremely high priority level is requested. The
contents of this field may also be loaded through the serial EEPROM.
7–0
MIN_GNT
RU
Minimum grant. The contents of this field may be used by host BIOS to assign a latency timer register value
to the TSB43AB23 device. The default for this register indicates that the TSB43AB23 device may need to
sustain burst transfers for nearly 64 µs and thus request a large value be programmed in bits 15–8 of the
TSB43AB23 latency timer and class cache line size register at offset 0Ch in the PCI configuration space
(see Section 3.7, Latency Timer and Class Cache Line Size Register).
3–10
3.15 OHCI Control Register
The PCI OHCI control register is defined by the 1394 Open Host Controller Interface Specification and provides a
bit for big endian PCI support. See Table 3–13 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
OHCI control
Name
OHCI control
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
OHCI control
40h
Read/Write, read-only
0000 0000h
Table 3–13. OHCI Control Register Description
BIT
FIELD NAME
TYPE
31–1
RSVD
R
0
GLOBAL_SWAP
R/W
DESCRIPTION
Reserved. Bits 31–1 return 0s when read.
When bit 0 is set to 1, all quadlets read from and written to the PCI interface are byte-swapped (big
endian).
3.16 Capability ID and Next Item Pointer Registers
The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the
next capability item. See Table 3–14 for a complete description of the register contents.
Bit
15
14
13
12
11
10
Name
9
8
7
6
5
4
3
2
1
0
Capability ID and next item pointer
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Register:
Offset:
Type:
Default:
Capability ID and next item pointer
44h
Read-only
0001h
Table 3–14. Capability ID and Next Item Pointer Registers Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15–8
NEXT_ITEM
R
Next item pointer. The TSB43AB23 device supports only one additional capability that is
communicated to the system through the extended capabilities list; therefore, this field returns 00h
when read.
7–0
CAPABILITY_ID
R
Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI
SIG for PCI power-management capability.
3–11
3.17 Power Management Capabilities Register
The power management capabilities register indicates the capabilities of the TSB43AB23 device related to PCI power
management. See Table 3–15 for a complete description of the register contents.
Bit
15
14
13
12
11
10
RU
R
R
R
R
R
R
R
R
0
1
1
1
1
1
1
0
0
Name
Type
Default
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
0
0
0
0
0
1
0
Power management capabilities
Register:
Offset:
Type:
Default:
Power management capabilities
46h
Read/Update, Read-only
7E02h
Table 3–15. Power Management Capabilities Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15
PME_D3COLD
RU
PCI_PME support from D3cold. This bit can be set to 1 or cleared to 0 via bit 15 (PME_D3COLD) in
the miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 3.21,
Miscellaneous Configuration Register). The miscellaneous configuration register is loaded from ROM.
When this bit is set to 1, it indicates that the TSB43AB23 device is capable of generating a PCI_PME
wake event from D3cold. This bit state is dependent upon the TSB43AB23 VAUX implementation and
may be configured by using bit 15 (PME_D3COLD) in the miscellaneous configuration register (see
Section 3.21).
14–11
PME_SUPPORT
R
10
D2_SUPPORT
R
PCI_PME support. This 4-bit field indicates the power states from which the TSB43AB23 device may
assert PCI_PME. This field returns a value of 1111b by default, indicating that PCI_PME may be
asserted from the D3hot, D2, D1, and D0 power states.
D2 support. Bit 10 is hardwired to 1, indicating that the TSB43AB23 device supports the D2 power
state.
9
D1_SUPPORT
R
D1 support. Bit 9 is hardwired to 1, indicating that the TSB43AB23 device supports the D1 power state.
8–6
AUX_CURRENT
R
Auxiliary current. This 3-bit field reports the 3.3-VAUX auxiliary current requirements. When bit 15
(PME_D3COLD) is cleared, this field returns 000b; otherwise, it returns 001b.
000b = Self-powered
001b = 55 mA (3.3-VAUX maximum current required)
5
3–12
DSI
R
Device-specific initialization. This bit returns 0 when read, indicating that the TSB43AB23 device does
not require special initialization beyond the standard PCI configuration header before a generic class
driver is able to use it.
4
RSVD
R
Reserved. Bit 4 returns 0 when read.
3
PME_CLK
R
PCI_PME clock. This bit returns 0 when read, indicating that no host bus clock is required for the
TSB43AB23 device to generate PCI_PME.
2–0
PM_VERSION
R
Power-management version. This field returns 010b when read, indicating that the TSB43AB23 device
is compatible with the registers described in the PCI Bus Power Management Interface Specification
(Revision 1.1).
3.18 Power Management Control and Status Register
The power management control and status register implements the control and status of the PCI power management
function. This register is not affected by the internally generated reset caused by the transition from the D3hot to D0
state. See Table 3–16 for a complete description of the register contents.
Bit
15
14
13
12
11
10
Name
Type
Default
9
8
7
6
5
4
3
2
1
0
Power management control and status
RWC
R
R
R
R
R
R
R/W
R
R
R
R
R
R
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Power management control and status
48h
Read/Clear, Read/Write, Read-only
0000h
Table 3–16. Power Management Control and Status Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15
PME_STS
RWC
Bit 15 is set to 1 when the TSB43AB23 device normally asserts the PCI_PME signal independent of
the state of bit 8 (PME_ENB). This bit is cleared by a writeback of 1, which also clears the PCI_PME
signal driven by the TSB43AB23 device. Writing a 0 to this bit has no effect.
14–13
DATA_SCALE
R
This field returns 0s, because the data register is not implemented.
12–9
DATA_SELECT
R
This field returns 0s, because the data register is not implemented.
8
PME_ENB
R/W
7–2
RSVD
R
1–0
PWR_STATE
R/W
When bit 8 is set to 1, PME assertion is enabled. When bit 8 is cleared, PME assertion is disabled. This
bit defaults to 0 if the function does not support PME generation from D3cold. If the function supports
PME from D3cold, this bit is sticky and must be explicitly cleared by the operating system each time
it is initially loaded.
Reserved. Bits 7–2 return 0s when read.
Power state. This 2-bit field sets the TSB43AB23 device power state and is encoded as follows:
00 = Current power state is D0.
01 = Current power state is D1.
10 = Current power state is D2.
11 = Current power state is D3.
3.19 Power Management Extension Registers
The power management extension register provides extended power-management features not applicable to the
TSB43AB23 device; thus, it is read-only and returns 0 when read. See Table 3–17 for a complete description of the
register contents.
Bit
15
14
13
12
11
10
Name
9
8
7
6
5
4
3
2
1
0
Power management extension
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Power management extension
4Ah
Read-only
0000h
Table 3–17. Power Management Extension Registers Description
BIT
FIELD NAME
TYPE
15–0
RSVD
R
DESCRIPTION
Reserved. Bits 15–0 return 0s when read.
3–13
3.20 PCI PHY Control Register
The PCI PHY control register provides a method for enabling the PHY CNA output. See Table 3–18 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
25
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
PCI PHY control
Name
PCI PHY control
Type
R
R
R
R
R
R
R
R
R/W
R
R
R
R/W
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Register:
Offset:
Type:
Default:
PCI PHY control
ECh
Read/Write, read-only
0000 0008h
Table 3–18. PCI PHY Control Register
3–14
BIT
FIELD NAME
TYPE
31–8
RSVD
R
DESCRIPTION
7
CNAOUT
R/W
When bit 7 is set to 1, the PHY CNA output is routed to terminal 96. When implementing a serial
EEPROM, this bit can be set by programming bit 7 of offset 16h in the EEPROM to 1.
6–4
RSVD
R
Reserved. Bits 6–4 return 0s when read. These bits are affected when implementing a serial
EEPROM; thus, bits 6–4 at EEPROM byte offset 16h must be programmed to 0.
3
RSVD
R
Reserved. Bit 3 defaults to 1 to indicate compliance with IEEE Std 1394a-2000. If a serial
EEPROM is implemented, bit 3 at EEPROM byte offset 16h must be set to 1. See Table 6–2,
Serial EEPROM Map.
2–0
RSVD
R
Reserved. Bits 2–0 return 0s when read. These bits are affected when implementing a serial
EEPROM; thus, bits 2–0 at EEPROM byte offset 16h must be programmed to 0.
Reserved. Bits 31–8 return 0s when read.
3.21 Miscellaneous Configuration Register
The miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 3–19 for a
complete description of the register contents.
Bit
31
30
29
28
27
26
Type
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
Name
Default
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
0
0
0
0
0
0
0
6
5
4
3
2
1
0
Miscellaneous configuration
Name
Type
25
Miscellaneous configuration
R/W
R
R/W
R
R
R/W
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Miscellaneous configuration
F0h
Read/Write, read-only
0000 0000h
Table 3–19. Miscellaneous Configuration Register
BIT
FIELD NAME
TYPE
31–16
RSVD
R
15
PME_D3COLD
R/W
14–5
RSVD
R
4
DIS_TGT_ABT
R/W
DESCRIPTION
Reserved. Bits 31–16 return 0s when read.
PCI_PME support from D3cold. This bit programs bit 15 (PME_D3COLD) in the power
management capabilities register at offset 46h in the PCI configuration space (see Section 3.17,
Power Management Capabilities Register).
Reserved. Bits 14–5 return 0s when read.
Bit 4 defaults to 0, which provides iOHCI-Lynx compatible target abort signaling. When this bit
is set to 1, it enables the no-target-abort mode, in which the TSB43AB23 device returns
indeterminate data instead of signaling target abort.
The TSB43AB23 LLC is divided into the PCI_CLK and SCLK domains. If software tries to access
registers in the link that are not active because the SCLK is disabled, a target abort is issued by
the link. On some systems, this can cause a problem resulting in a fatal system error. Enabling
this bit allows the link to respond to these types of requests by returning FFh.
It is recommended that this bit be set to 1.
3
GP2IIC
R/W
When bit 3 is set to 1, the GPIO3 and GPIO2 signals are internally routed to the SCL and SDA,
respectively. The GPIO3 and GPIO2 terminals are also placed in the high-impedance state.
2
DISABLE_SCLKGATE
R/W
When bit 2 is set to 1, the internal SCLK runs identically with the chip input. This is a test feature
only and must be cleared to 0 (all applications).
1
DISABLE_PCIGATE
R/W
When bit 1 is set to 1, the internal PCI clock runs identically with the chip input. This is a test feature
only and must be cleared to 0 (all applications).
0
KEEP_PCLK
R/W
When bit 0 is set to 1, the PCI clock is always kept running through the PCI_CLKRUN protocol.
When this bit is cleared, the PCI clock can be stopped using PCI_CLKRUN.
3–15
3.22 Link Enhancement Control Register
The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial
EEPROM, if present. After these bits are set to 1, their functionality is enabled only if bit 22 (aPhyEnhanceEnable)
in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is
set to 1. See Table 3–20 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
Type
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
Name
Default
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
0
0
0
0
0
0
0
6
5
4
3
2
1
0
Link enhancement control
Name
Type
24
Link enhancement control
R/W
R
R/W
R/W
R
R/W
R
R/W
R/W
R
R
R
R
R
R/W
R
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Link enhancement control
F4h
Read/Write, read-only
0000 1000h
Table 3–20. Link Enhancement Control Register Description
BIT
FIELD NAME
TYPE
31–16
RSVD
R
15
dis_at_pipeline
R/W
14
RSVD
R
13–12
atx_thresh
R/W
DESCRIPTION
Reserved. Bits 31–16 return 0s when read.
Disable AT pipelining. When bit 15 is set to 1, out-of-order AT pipelining is disabled.
Reserved.
This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the
TSB43AB23 device retries the packet, it uses a 2K-byte threshold, resulting in a store-and-forward
operation.
00 = Threshold ~ 2K bytes resulting in a store-and-forward operation
01 = Threshold ~ 1.7K bytes (default)
10 = Threshold ~ 1K bytes
11 = Threshold ~ 512 bytes
These bits fine-tune the asynchronous transmit threshold. For most applications the 1.7K-byte
threshold is optimal. Changing this value may increase or decrease the 1394 latency depending on
the average PCI bus latency.
Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds
or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than
the AT threshold, the remaining data must be received before the AT FIFO is emptied; otherwise, an
underrun condition occurs, resulting in a packet error at the receiving node. As a result, the link then
commences store-and-forward operation. Wait until it has the complete packet in the FIFO before
retransmitting it on the second attempt to ensure delivery.
An AT threshold of 2K results in store-and-forward operation, which means that asynchronous data
will not be transmitted until an end-of-packet token is received. Restated, setting the AT threshold to
2K results in only complete packets being transmitted.
Note that this device always uses store-and-forward when the asynchronous transmit retries register
at OHCI offset 08h (see Section 4.3, Asynchronous Transmit Retries Register) is cleared.
3–16
11
RSVD
R
10
enab_mpeg_ts
R/W
Reserved. Bit 11 returns 0 when read.
9
RSVD
R
8
enab_dv_ts
R/W
Enable DV CIP timestamp enhancement. When bit 8 is set to 1, the enhancement is enabled for DV
CIP transmit streams (FMT = 00h).
7
enab_unfair
R/W
Enable asynchronous priority requests. iOHCI-Lynx compatible. Setting bit 7 to 1 enables the link
to respond to requests with priority arbitration. It is recommended that this bit be set to 1.
Enable MPEG CIP timestamp enhancement. When bit 9 is set to 1, the enhancement is enabled for
MPEG CIP transmit streams (FMT = 20h).
Reserved. Bit 9 returns 0 when read.
Table 3–20. Link Enhancement Control Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
6
RSVD
R
This bit is not assigned in the TSB43AB23 follow-on products, because this bit location loaded by the
serial EEPROM from the enhancements field corresponds to bit 23 (programPhyEnable) in the host
controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register).
5–2
RSVD
R
Reserved. Bits 5–2 return 0s when read.
1
enab_accel
R/W
0
RSVD
R
Enable acceleration enhancements. iOHCI-Lynx compatible. When bit 1 is set to 1, the PHY layer
is notified that the link supports the IEEE Std 1394a-2000 acceleration enhancements, that is,
ack-accelerated, fly-by concatenation, etc. It is recommended that this bit be set to 1.
Reserved. Bit 0 returns 0 when read.
3.23 Subsystem Access Register
Write access to the subsystem access register updates the subsystem identification registers identically to
iOHCI-Lynx. The system ID value written to this register may also be read back from this register. See Table 3–21
for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
Name
Type
24
23
22
21
20
19
18
17
16
Subsystem access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
Type
Default
Subsystem access
Register:
Offset:
Type:
Default:
Subsystem access
F8h
Read/Write
0000 0000h
Table 3–21. Subsystem Access Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31–16
SUBDEV_ID
R/W
Subsystem device ID alias. This field indicates the subsystem device ID.
15–0
SUBVEN_ID
R/W
Subsystem vendor ID alias. This field indicates the subsystem vendor ID.
3–17
3.24 GPIO Control Register
The GPIO control register has the control and status bits for the GPIO2 and GPIO3 ports. See Table 3–22 for a
complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
R/W
R
R/W
R/W
R
R
R
RWU
Default
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
Type
23
22
21
20
19
18
17
16
R/W
R
R/W
R/W
R
R
R
RWU
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
GPIO control
Name
GPIO control
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
GPIO control
FCh
Read/Write/Update, read/write, read-only
0000 0000h
Table 3–22. General-Purpose Input/Output Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
INT_3EN
R/W
When bit 31 is set to 1, a TSB43AB23 general-purpose interrupt event occurs on a level change of the
GPIO3 input. This event can generate an interrupt, with mask and event status reported through the
interrupt mask register at OHCI offset 88h/8Ch (see Section 4.22, Interrupt Mask Register) and
interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register).
30
RSVD
R
29
GPIO_INV3
R/W
GPIO3 polarity invert. When bit 29 is set to 1, the polarity of GPIO3 is inverted.
28
GPIO_ENB3
R/W
GPIO3 enable control. When bit 28 is set to 1, the output is enabled. Otherwise, the output is high
impedance.
27–25
RSVD
R
24
GPIO_DATA3
RWU
GPIO3 data. Reads from bit 24 return the logical value of the input to GPIO3. Writes to this bit update
the value to drive to GPIO3 when output is enabled.
23
INT_2EN
R/W
When bit 23 is set to 1, a TSB43AB23 general-purpose interrupt event occurs on a level change of the
GPIO2 input. This event can generate an interrupt, with mask and event status reported through the
interrupt mask register at OHCI offset 88h/8Ch (see Section 4.22, Interrupt Mask Register) and
interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register).
22
RSVD
R
21
GPIO_INV2
R/W
GPIO2 polarity invert. When bit 21 is set to 1, the polarity of GPIO2 is inverted.
20
GPIO_ENB2
R/W
GPIO2 enable control. When bit 20 is set to 1, the output is enabled. Otherwise, the output is high
impedance.
19–17
RSVD
R
16
GPIO_DATA2
RWU
15–0
RSVD
R
3–18
Reserved. Bit 30 returns 0 when read.
Reserved. Bits 27–25 return 0s when read.
Reserved. Bit 22 returns 0 when read.
Reserved. Bits 19–17 return 0s when read.
GPIO2 data. Reads from bit 16 return the logical value of the input to GPIO2. Writes to this bit update
the value to drive to GPIO2 when the output is enabled.
Reserved. Bits 15–0 return 0s when read.
4 OHCI Registers
The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a
2K-byte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see
Section 3.9, OHCI Base Address Register). These registers are the primary interface for controlling the TSB43AB23
IEEE 1394 link function.
This section provides the register interface and bit descriptions. Several set/clear register pairs in this programming
model are implemented to solve various issues with typical read-modify-write control registers. There are two
addresses for a set/clear register: RegisterSet and RegisterClear. See Table 4–1 for a register listing. A 1 bit written
to RegisterSet causes the corresponding bit in the set/clear register to be set to 1; a 0 bit leaves the corresponding
bit unaffected. A 1 bit written to RegisterClear causes the corresponding bit in the set/clear register to be cleared;
a 0 bit leaves the corresponding bit in the set/clear register unaffected.
Typically, a read from either RegisterSet or RegisterClear returns the contents of the set or clear register, respectively.
However, sometimes reading the RegisterClear provides a masked version of the set or clear register. The interrupt
event register is an example of this behavior.
Table 4–1. OHCI Register Map
DMA CONTEXT
—
REGISTER NAME
ABBREVIATION
OFFSET
OHCI version
Version
00h
GUID ROM
GUID_ROM
04h
Asynchronous transmit retries
ATRetries
08h
CSR data
CSRData
0Ch
CSR compare
CSRCompareData
10h
CSR control
CSRControl
14h
Configuration ROM header
ConfigROMhdr
18h
Bus identification
BusID
1Ch
Bus options
BusOptions
20h
GUID high
GUIDHi
24h
GUID low
GUIDLo
28h
Reserved
—
Configuration ROM mapping
ConfigROMmap
34h
Posted write address low
PostedWriteAddressLo
38h
Posted write address high
PostedWriteAddressHi
3Ch
Vendor ID
VendorID
40h
Reserved
—
Host controller control
Reserved
2Ch–30h
44h–4Ch
HCControlSet
50h
HCControlClr
54h
—
58h–5Ch
4–1
Table 4–1. OHCI Register Map (Continued)
DMA CONTEXT
Self-ID
REGISTER NAME
OFFSET
—
60h
Self-ID buffer pointer
SelfIDBuffer
64h
Self-ID count
SelfIDCount
68h
Reserved
—
6Ch
IRChannelMaskHiSet
70h
IRChannelMaskHiClear
74h
IRChannelMaskLoSet
78h
IRChannelMaskLoClear
7Ch
IntEventSet
80h
IntEventClear
84h
—
Isochronous receive channel mask high
Isochronous receive channel mask low
Interrupt event
Interrupt mask
Isochronous transmit interrupt event
Isochronous transmit interrupt mask
—
Isochronous receive interrupt event
IntMaskSet
88h
IntMaskClear
8Ch
IsoXmitIntEventSet
90h
IsoXmitIntEventClear
94h
IsoXmitIntMaskSet
98h
IsoXmitIntMaskClear
9Ch
IsoRecvIntEventSet
A0h
IsoRecvIntEventClear
A4h
IsoRecvIntMaskSet
A8h
IsoRecvIntMaskClear
ACh
Initial bandwidth available
InitialBandwidthAvailable
B0h
Initial channels available high
InitialChannelsAvailableHi
B4h
Initial channels available low
InitialChannelsAvailableLo
Reserved
—
Fairness control
FairnessControl
DCh
LinkControlSet
E0h
LinkControlClear
E4h
Isochronous receive interrupt mask
Link control
B8h
BCh–D8h
Node identification
NodeID
E8h
PHY layer control
PhyControl
ECh
Isochronous cycle timer
Isocyctimer
Reserved
—
Asynchronous request filter high
Asynchronous request filter low
Physical request filter high
F0h
F4h–FCh
AsyncRequestFilterHiSet
100h
AsyncRequestFilterHiClear
104h
AsyncRequestFilterLoSet
108h
AsyncRequestFilterLoClear
10Ch
PhysicalRequestFilterHiSet
110h
PhysicalRequestFilterHiClear
114h
PhysicalRequestFilterLoSet
118h
PhysicalRequestFilterLoClear
11Ch
Physical upper bound
PhysicalUpperBound
120h
Reserved
—
Physical request filter low
4–2
ABBREVIATION
Reserved
124h–17Ch
Table 4–1. OHCI Register Map (Continued)
DMA CONTEXT
Asynchronous
Request Transmit
[ ATRQ
Q]
Asynchronous
Response
Res
onse Transmit
[ ATRS ]
Asynchronous
Request Receive
[ ARRQ
Q]
Asynchronous
Response
Res
onse Receive
[ ARRS ]
REGISTER NAME
Asynchronous context control
Transmit Context n
n = 0, 1, 2, 3, …, 7
184h
—
188h
CommandPtr
18Ch
Reserved
—
190h–19Ch
ContextControlSet
1A0h
ContextControlClear
1A4h
Reserved
—
1A8h
Asynchronous context command pointer
CommandPtr
Reserved
—
Asynchronous context control
1ACh
1B0h–1BCh
ContextControlSet
1C0h
ContextControlClear
1C4h
Reserved
—
1C8h
Asynchronous context command pointer
CommandPtr
Reserved
—
Asynchronous context control
Asynchronous context control
1CCh
1D0h–1DCh
ContextControlSet
1E0h
ContextControlClear
1E4h
Reserved
—
1E8h
Asynchronous context command pointer
CommandPtr
1ECh
Reserved
—
1F0h–1FCh
ContextControlSet
200h + 16*n
ContextControlClear
204h + 16*n
Reserved
—
208h + 16*n
Isochronous transmit context command
pointer
CommandPtr
20Ch + 16*n
Reserved
—
210h–3FCh
ContextControlSet
400h + 32*n
ContextControlClear
404h + 32*n
Reserved
—
408h + 32*n
Isochronous receive context command
pointer
CommandPtr
40Ch + 32*n
Isochronous receive context match
ContextMatch
410h + 32*n
Isochronous
n = 0, 1, 2, 3
180h
ContextControlClear
Asynchronous context command pointer
Isochronous receive context control
Receive Context n
OFFSET
Reserved
Isochronous transmit context control
Isochronous
ABBREVIATION
ContextControlSet
4–3
4.1 OHCI Version Register
The OHCI version register indicates the OHCI version support and whether or not the serial EEPROM is present. See
Table 4–2 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
X
Bit
15
14
13
12
11
10
9
8
Name
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
OHCI version
Name
OHCI version
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Register:
Offset:
Type:
Default:
OHCI version
00h
Read-only
0X01 0010h
Table 4–2. OHCI Version Register Description
BIT
FIELD NAME
TYPE
31–25
RSVD
R
Reserved. Bits 31–25 return 0s when read.
24
GUID_ROM
R
The TSB43AB23 device sets bit 24 to 1 if the serial EEPROM is detected. If the serial EEPROM is
present, the Bus_Info_Block is automatically loaded on system (hardware) reset.
23–16
version
R
Major version of the OHCI. The TSB43AB23 device is compliant with the 1394 Open Host Controller
Interface Specification (Revision 1.1); thus, this field reads 01h.
15–8
RSVD
R
Reserved. Bits 15–8 return 0s when read.
7–0
revision
R
Minor version of the OHCI. The TSB43AB23 device is compliant with the 1394 Open Host Controller
Interface Specification (Revision 1.1); thus, this field reads 10h.
4–4
DESCRIPTION
4.2 GUID ROM Register
The GUID ROM register accesses the serial EEPROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI
version register at OHCI offset 00h (see Section 4.1, OHCI Version Register) is set to 1. See Table 4–3 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
25
RSU
R
R
R
R
R
RSU
R
Default
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
Type
24
23
22
21
20
19
18
17
16
RU
RU
RU
RU
RU
RU
RU
RU
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
GUID ROM
Name
GUID ROM
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
GUID ROM
04h
Read/Set/Update, read/update, read-only
00XX 0000h
Table 4–3. GUID ROM Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
addrReset
RSU
Software sets bit 31 to 1 to reset the GUID ROM address to 0. When the TSB43AB23 device completes
the reset, it clears this bit. The TSB43AB23 device does not automatically fill bits 23–16 (rdData field)
with the 0th byte.
30–26
RSVD
R
25
rdStart
RSU
Reserved. Bits 30–26 return 0s when read.
A read of the currently addressed byte is started when bit 25 is set to 1. This bit is automatically cleared
when the TSB43AB23 device completes the read of the currently addressed GUID ROM byte.
24
RSVD
R
23–16
rdData
RU
Reserved. Bit 24 returns 0 when read.
15–8
RSVD
R
Reserved. Bits 15–8 return 0s when read.
7–0
miniROM
R
The miniROM field defaults to 0 indicating that no mini-ROM is implemented. If bit 5 of EEPROM offset
6h is set to 1, this field returns 20h indicating that valid mini-ROM data begins at offset 20h of the GUID
ROM.
This field contains the data read from the GUID ROM.
4–5
4.3 Asynchronous Transmit Retries Register
The asynchronous transmit retries register indicates the number of times the TSB43AB23 device attempts a retry
for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See Table 4–4
for a complete description of the register contents.
Bit
31
30
29
28
27
26
Name
25
24
23
22
21
20
19
18
17
16
Asynchronous transmit retries
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
Asynchronous transmit retries
Register:
Offset:
Type:
Default:
Asynchronous transmit retries
08h
Read/Write, read-only
0000 0000h
Table 4–4. Asynchronous Transmit Retries Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31–29
secondLimit
R
The second limit field returns 0s when read, because outbound dual-phase retry is not
implemented.
28–16
cycleLimit
R
The cycle limit field returns 0s when read, because outbound dual-phase retry is not implemented.
Reserved. Bits 15–12 return 0s when read.
15–12
RSVD
R
11–8
maxPhysRespRetries
R/W
This field tells the physical response unit how many times to attempt to retry the transmit operation
for the response packet when a busy acknowledge or ack_data_error is received from the target
node.
7–4
maxATRespRetries
R/W
This field tells the asynchronous transmit response unit how many times to attempt to retry the
transmit operation for the response packet when a busy acknowledge or ack_data_error is
received from the target node.
3–0
maxATReqRetries
R/W
This field tells the asynchronous transmit DMA request unit how many times to attempt to retry the
transmit operation for the response packet when a busy acknowledge or ack_data_error is
received from the target node.
4.4 CSR Data Register
The CSR data register accesses the bus management CSR registers from the host through compare-swap
operations. This register contains the data to be stored in a CSR if the compare is successful.
Bit
31
30
29
28
27
26
25
R
R
R
R
R
R
R
R
Name
Type
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
CSR data
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
CSR data
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Register:
Offset:
Type:
Default:
4–6
CSR data
0Ch
Read-only
XXXX XXXXh
4.5 CSR Compare Register
The CSR compare register accesses the bus management CSR registers from the host through compare-swap
operations. This register contains the data to be compared with the existing value of the CSR resource.
Bit
31
30
29
28
27
26
25
Type
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
Name
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
CSR compare
Name
CSR compare
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Register:
Offset:
Type:
Default:
CSR compare
10h
Read-only
XXXX XXXXh
4.6 CSR Control Register
The CSR control register accesses the bus management CSR registers from the host through compare-swap
operations. This register controls the compare-swap operation and selects the CSR resource. See Table 4–5 for a
complete description of the register contents.
Bit
31
30
29
28
27
26
25
Name
Type
24
23
22
21
20
19
18
17
16
CSR control
RU
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
Name
CSR control
Register:
Offset:
Type:
Default:
CSR control
14h
Read/Write, Read/Update, Read-only
8000 000Xh
Table 4–5. CSR Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
csrDone
RU
Bit 31 is set to 1 by the TSB43AB23 device when a compare-swap operation is complete. It is cleared
whenever this register is written.
30–2
RSVD
R
1–0
csrSel
R/W
Reserved. Bits 30–2 return 0s when read.
This field selects the CSR resource as follows:
00 = BUS_MANAGER_ID
01 = BANDWIDTH_AVAILABLE
10 = CHANNELS_AVAILABLE_HI
11 = CHANNELS_AVAILABLE_LO
4–7
4.7 Configuration ROM Header Register
The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset
FFFF F000 0400h. See Table 4–6 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
Name
Type
Default
23
22
21
20
19
18
17
16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
6
5
4
3
2
1
0
Configuration ROM header
Name
Type
24
Configuration ROM header
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Register:
Offset:
Type:
Default:
Configuration ROM header
18h
Read/Write
0000 XXXXh
Table 4–6. Configuration ROM Header Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31–24
info_length
R/W
IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control
register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1.
23–16
crc_length
R/W
IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control
register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1.
15–0
rom_crc_value
R/W
IEEE 1394 bus-management field. Must be valid at any time bit 17 (linkEnable) in the host controller
control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to
1. The reset value is undefined if no serial EEPROM is present. If a serial EEPROM is present, this
field is loaded from the serial EEPROM.
4.8 Bus Identification Register
The bus identification register externally maps to the first quadlet in the Bus_Info_Block and contains the constant
3133 3934h, which is the ASCII value of 1394.
Bit
31
30
29
28
27
26
25
Name
24
23
22
21
20
19
18
17
16
Bus identification
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
1
1
0
0
0
1
0
0
1
1
0
0
1
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Bus identification
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
1
1
1
0
0
1
0
0
1
1
0
1
0
0
Register:
Offset:
Type:
Default:
4–8
Bus identification
1Ch
Read-only
3133 3934h
4.9 Bus Options Register
The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 4–7 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
25
R/W
R/W
R/W
R/W
R/W
R
R
R
Default
X
X
X
X
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
Type
Default
23
22
21
20
19
18
17
16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
Bus options
Name
Type
24
Bus options
R/W
R/W
R/W
R/W
R
R
R
R
R/W
R/W
R
R
R
R
R
R
1
0
1
0
0
0
0
0
X
X
0
0
0
0
1
0
Register:
Offset:
Type:
Default:
Bus options
20h
Read/Write, read-only
X0XX A0X2h
Table 4–7. Bus Options Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
irmc
R/W
Isochronous resource-manager capable. IEEE 1394 bus-management field. Must be valid when bit 17
(linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host
Controller Control Register) is set to 1.
30
cmc
R/W
Cycle master capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the
host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control
Register) is set to 1.
29
isc
R/W
Isochronous support capable. IEEE 1394 bus-management field. Must be valid when bit 17
(linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host
Controller Control Register) is set to 1.
28
bmc
R/W
Bus manager capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in
the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control
Register) is set to 1.
27
pmc
R/W
Power-management capable. IEEE 1394 bus-management field. When bit 27 is set to 1, this indicates
that the node is power-management capable. Must be valid when bit 17 (linkEnable) in the host
controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register)
is set to 1.
26–24
RSVD
R
23–16
cyc_clk_acc
R/W
Cycle master clock accuracy, in parts per million. IEEE 1394 bus-management field. Must be valid
when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16,
Host Controller Control Register) is set to 1.
15–12
max_rec
R/W
Maximum request. IEEE 1394 bus-management field. Hardware initializes this field to indicate the
maximum number of bytes in a block request packet that is supported by the implementation. This
value, max_rec_bytes, must be 512 or greater, and is calculated by 2^(max_rec + 1). Software may
change this field; however, this field must be valid at any time bit 17 (linkEnable) in the host controller
control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to
1. A received block write request packet with a length greater than max_rec_bytes may generate an
ack_type_error. This field is not affected by a software reset, and defaults to value indicating
2048 bytes on a system (hardware) reset.
11–8
RSVD
R
7–6
g
R/W
5–3
RSVD
R
Reserved. Bits 5–3 return 0s when read.
2–0
Lnk_spd
R
Link speed. This field returns 010, indicating that the link speeds of 100M bits/s, 200M bits/s, and
400M bits/s are supported.
Reserved. Bits 26–24 return 0s when read.
Reserved. Bits 11–8 return 0s when read.
Generation counter. This field is incremented if any portion of the configuration ROM has been
incremented since the prior bus reset.
4–9
4.10 GUID High Register
The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the third
quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes
to 0s on a system (hardware) reset, which is an illegal GUID value. If a serial EEPROM is detected, the contents of
this register are loaded through the serial EEPROM interface after a G_RST. At that point, the contents of this register
cannot be changed. If no serial EEPROM is detected, the contents of this register are loaded by the BIOS after a
PCI_RST. At that point, the contents of this register cannot be changed.
Bit
31
30
29
28
27
26
25
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
GUID high
Name
GUID high
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
GUID high
24h
Read-only
0000 0000h
4.11 GUID Low Register
The GUID low register represents the lower quadlet in a 64-bit global unique ID (GUID) which maps to chip_ID_lo
in the Bus_Info_Block. This register initializes to 0s on a system (hardware) reset and behaves identical to the GUID
high register at OHCI offset 24h (see Section 4.10, GUID High Register).
Bit
31
30
29
28
27
26
25
Name
24
23
22
21
20
19
18
17
16
GUID low
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
GUID low
Register:
Offset:
Type:
Default:
4–10
GUID low
28h
Read-only
0000 0000h
4.12 Configuration ROM Mapping Register
The configuration ROM mapping register contains the start address within system memory that maps to the start
address of 1394 configuration ROM for this node. See Table 4–8 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
Name
Type
Default
23
22
21
20
19
18
17
16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
6
5
4
3
2
1
0
Configuration ROM mapping
Name
Type
24
Configuration ROM mapping
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Configuration ROM mapping
34h
Read/Write
0000 0000h
Table 4–8. Configuration ROM Mapping Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31–10
configROMaddr
R/W
If a quadlet read request to 1394 offset FFFF F000 0400h through offset FFFF F000 07FFh is
received, the low-order 10 bits of the offset are added to this register to determine the host memory
address of the read request.
9–0
RSVD
R
Reserved. Bits 9–0 return 0s when read.
4.13 Posted Write Address Low Register
The posted write address low register communicates error information if a write request is posted and an error occurs
while the posted data packet is being written. See Table 4–9 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
Name
Type
24
23
22
21
20
19
18
17
16
Posted write address low
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Name
Type
Default
Posted write address low
Register:
Offset:
Type:
Default:
Posted write address low
38h
Read/Update
XXXX XXXXh
Table 4–9. Posted Write Address Low Register Description
BIT
FIELD NAME
TYPE
31–0
offsetLo
RU
DESCRIPTION
The lower 32 bits of the 1394 destination offset of the write request that failed.
4–11
4.14 Posted Write Address High Register
The posted write address high register communicates error information if a write request is posted and an error occurs
while writing the posted data packet. See Table 4–10 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
RU
RU
RU
RU
RU
RU
RU
RU
RU
Default
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
Name
Type
Default
23
22
21
20
19
18
17
16
RU
RU
RU
RU
RU
RU
RU
X
X
X
X
X
X
X
6
5
4
3
2
1
0
Posted write address high
Name
Type
24
Posted write address high
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Register:
Offset:
Type:
Default:
Posted write address high
3Ch
Read/Update
XXXX XXXXh
Table 4–10. Posted Write Address High Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31–16
sourceID
RU
This field is the 10-bit bus number (bits 31–22) and 6-bit node number (bits 21–16) of the node that
issued the write request that failed.
15–0
offsetHi
RU
The upper 16 bits of the 1394 destination offset of the write request that failed.
4.15 Vendor ID Register
The vendor ID register holds the company ID of an organization that specifies any vendor-unique registers. The
TSB43AB23 device implements Texas Instruments unique behavior with regards to OHCI. Thus, this register is
read-only and returns 0108 0028h when read.
Bit
31
30
29
28
27
26
25
R
R
R
R
R
R
R
R
Name
Type
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
Vendor ID
Default
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Vendor ID
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
Register:
Offset:
Type:
Default:
4–12
Vendor ID
40h
Read-only
0108 0028h
4.16 Host Controller Control Register
The host controller control set/clear register pair provides flags for controlling the TSB43AB23 device. See Table 4–11
for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
Name
Type
24
23
22
21
20
19
18
17
16
Host controller control
RSU
RSC
RSC
R
R
R
R
R
R
RSC
R
R
RSC
RSC
RSC
RSCU
Default
0
X
0
0
0
0
0
0
1
0
0
0
0
X
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
Host controller control
Register:
Offset:
Type:
Default:
Host controller control
50h
set register
54h
clear register
Read/Set/Clear/Update, read/set/clear, read/clear, read-only
X08X 0000h
Table 4–11. Host Controller Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
BIBimage Valid
RSU
When bit 31 is set to 1, the TSB43AB23 physical response unit is enabled to respond to block read
requests to host configuration ROM and to the mechanism for atomically updating configuration
ROM. Software creates a valid image of the bus_info_block in host configuration ROM before
setting this bit.
When this bit is cleared, the TSB43AB23 device returns ack_type_error on block read requests
to host configuration ROM. Also, when this bit is cleared and a 1394 bus reset occurs, the
configuration ROM mapping register at OHCI offset 34h (see Section 4.12, Configuration ROM
Mapping Register), configuration ROM header register at OHCI offset 18h (see Section 4.7,
Configuration ROM Header Register), and bus options register at OHCI offset 20h (see
Section 4.9, Bus Options Register) are not updated.
Software can set this bit only when bit 17 (linkEnable) is 0. Once bit 31 is set to 1, it can be cleared
by a system (hardware) reset, a software reset, or if a fetch error occurs when the TSB43AB23
device loads bus_info_block registers from host memory.
30
noByteSwapData
RSC
Bit 30 controls whether physical accesses to locations outside the TSB43AB23 device itself, as
well as any other DMA data accesses are byte swapped.
29
AckTardyEnable
RSC
Bit 29 controls the acknowledgement of ack_tardy. When bit 29 is set to 1, ack_tardy may be
returned as an acknowledgment to accesses from the 1394 bus to the TSB43AB23 device,
including accesses to the bus_info_block. The TSB43AB23 device returns ack_tardy to all other
asynchronous packets addressed to the TSB43AB23 node. When the TSB43AB23 device sends
ack_tardy, bit 27 (ack_tardy) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) is set to 1 to indicate the attempted asynchronous access.
Software ensures that bit 27 (ack_tardy) in the interrupt event register is 0. Software also unmasks
wake-up interrupt events such as bit 19 (phy) and bit 27 (ack_tardy) in the interrupt event register
before placing the TSB43AB23 device into the D1 power mode.
Software must not set this bit if the TSB43AB23 node is the 1394 bus manager.
28–24
RSVD
R
Reserved. Bits 28–24 return 0s when read.
23
programPhyEnable
R
Bit 23 informs upper-level software that lower-level software has consistently configured the IEEE
1394a-2000 enhancements in the link and PHY layers. When this bit is 1, generic software such
as the OHCI driver is responsible for configuring IEEE 1394a-2000 enhancements in the PHY
layer and bit 22 (aPhyEnhanceEnable). When this bit is 0, the generic software may not modify
the IEEE 1394a-2000 enhancements in the PHY layer and cannot interpret the setting of bit 22
(aPhyEnhanceEnable). This bit is initialized from serial EEPROM. This bit defaults to 1.
4–13
Table 4–11. Host Controller Control Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
22
aPhyEnhanceEnable
RSC
When bits 23 (programPhyEnable) and 17 (linkEnable) are 1, the OHCI driver can set bit 22 to
1 to use all IEEE 1394a-2000 enhancements. When bit 23 (programPhyEnable) is cleared to 0,
the software does not change PHY enhancements or this bit.
21–20
RSVD
R
19
LPS
RSC
Reserved. Bits 21 and 20 return 0s when read.
Bit 19 controls the link power status. Software must set this bit to 1 to permit the link-PHY
communication. A 0 prevents link-PHY communication.
The OHCI-link is divided into two clock domains (PCI_CLK and PHY_SCLK). If software tries to
access any register in the PHY_SCLK domain while the PHY_SCLK is disabled, a target abort
is issued by the link. This problem can be avoided by setting bit 4 (DIS_TGT_ABT) to 1 in the
miscellaneous configuration register at offset F0h in the PCI configuration space (see
Section 3.21, Miscellaneous Configuration Register). This allows the link to respond to these
types of request by returning all Fs (hex).
OHCI registers at offsets DCh–F0h and 100h–11Ch are in the PHY_SCLK domain.
After setting LPS, software must wait approximately 10 ms before attempting to access any of
the OHCI registers. This gives the PHY_SCLK time to stabilize.
18
postedWriteEnable
RSC
Bit 18 enables (1) or disables (0) posted writes. Software changes this bit only when bit 17
(linkEnable) is 0.
17
linkEnable
RSC
Bit 17 is cleared to 0 by either a system (hardware) or software reset. Software must set this bit
to 1 when the system is ready to begin operation and then force a bus reset. This bit is necessary
to keep other nodes from sending transactions before the local system is ready. When this bit is
cleared, the TSB43AB23 device is logically and immediately disconnected from the 1394 bus, no
packets are received or processed, nor are packets transmitted.
16
SoftReset
RSCU
When bit 16 is set to 1, all TSB43AB23 states are reset, all FIFOs are flushed, and all OHCI
registers are set to their system (hardware) reset values, unless otherwise specified. PCI
registers are not affected by this bit. This bit remains set to 1 while the software reset is in progress
and reverts back to 0 when the reset has completed.
15–0
RSVD
R
Reserved. Bits 15–0 return 0s when read.
4.17 Self-ID Buffer Pointer Register
The self-ID buffer pointer register points to the 2K-byte aligned base address of the buffer in host memory where the
self-ID packets are stored during bus initialization. Bits 31–11 are read/write accessible. Bits 10–0 are reserved, and
return 0s when read.
Bit
31
30
29
28
27
26
25
Name
Type
24
23
22
21
20
19
18
17
16
Self-ID buffer pointer
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Self-ID buffer pointer
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
4–14
Self-ID buffer pointer
64h
Read/Write, read-only
XXXX XX00h
4.18 Self-ID Count Register
The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-ID
packet errors, and keeps a count of the self-ID data in the self-ID buffer. See Table 4–12 for a complete description
of the register contents.
Bit
31
30
29
28
27
26
25
RU
R
R
R
R
R
R
R
Default
X
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
Type
24
23
22
21
20
19
18
17
16
RU
RU
RU
RU
RU
RU
RU
RU
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
Self-ID count
Name
Self-ID count
Type
R
R
R
R
R
RU
RU
RU
RU
RU
RU
RU
RU
RU
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Self-ID count
68h
Read/Update, read-only
X0XX 0000h
Table 4–12. Self-ID Count Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
selfIDError
RU
When bit 31 is set to 1, an error was detected during the most recent self-ID packet reception. The
contents of the self-ID buffer are undefined. This bit is cleared after a self-ID reception in which no
errors are detected. Note that an error can be a hardware error or a host bus write error.
30–24
RSVD
R
23–16
selfIDGeneration
RU
15–11
RSVD
R
10–2
selfIDSize
RU
1–0
RSVD
R
Reserved. Bits 30–24 return 0s when read.
The value in this field increments each time a bus reset is detected. This field rolls over to 0 after
reaching 255.
Reserved. Bits 15–11 return 0s when read.
This field indicates the number of quadlets that have been written into the self-ID buffer for the current
bits 23–16 (selfIDGeneration field). This includes the header quadlet and the self-ID data. This field
is cleared to 0s when the self-ID reception begins.
Reserved. Bits 1 and 0 return 0s when read.
4–15
4.19 Isochronous Receive Channel Mask High Register
The isochronous receive channel mask high set/clear register enables packet receives from the upper 32
isochronous data channels. A read from either the set register or clear register returns the content of the isochronous
receive channel mask high register. See Table 4–13 for a complete description of the register contents.
Bit
31
30
29
28
27
Name
Type
26
25
24
23
22
21
20
19
18
17
16
Isochronous receive channel mask high
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Name
Type
Default
Isochronous receive channel mask high
Register:
Offset:
Type:
Default:
Isochronous receive channel mask high
70h
set register
74h
clear register
Read/Set/Clear
XXXX XXXXh
Table 4–13. Isochronous Receive Channel Mask High Register Description
4–16
BIT
FIELD NAME
TYPE
DESCRIPTION
31
isoChannel63
RSC
When bit 31 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 63.
30
isoChannel62
RSC
When bit 30 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 62.
29
isoChannel61
RSC
When bit 29 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 61.
28
isoChannel60
RSC
When bit 28 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 60.
27
isoChannel59
RSC
When bit 27 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 59.
26
isoChannel58
RSC
When bit 26 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 58.
25
isoChannel57
RSC
When bit 25 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 57.
24
isoChannel56
RSC
When bit 24 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 56.
23
isoChannel55
RSC
When bit 23 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 55.
22
isoChannel54
RSC
When bit 22 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 54.
21
isoChannel53
RSC
When bit 21 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 53.
20
isoChannel52
RSC
When bit 20 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 52.
19
isoChannel51
RSC
When bit 19 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 51.
18
isoChannel50
RSC
When bit 18 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 50.
17
isoChannel49
RSC
When bit 17 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 49.
16
isoChannel48
RSC
When bit 16 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 48.
15
isoChannel47
RSC
When bit 15 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 47.
14
isoChannel46
RSC
When bit 14 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 46.
13
isoChannel45
RSC
When bit 13 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 45.
12
isoChannel44
RSC
When bit 12 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 44.
11
isoChannel43
RSC
When bit 11 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 43.
10
isoChannel42
RSC
When bit 10 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 42.
9
isoChannel41
RSC
When bit 9 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 41.
8
isoChannel40
RSC
When bit 8 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 40.
7
isoChannel39
RSC
When bit 7 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 39.
Table 4–13. Isochronous Receive Channel Mask High Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
6
isoChannel38
RSC
When bit 6 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 38.
5
isoChannel37
RSC
When bit 5 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 37.
4
isoChannel36
RSC
When bit 4 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 36.
3
isoChannel35
RSC
When bit 3 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 35.
2
isoChannel34
RSC
When bit 2 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 34.
1
isoChannel33
RSC
When bit 1 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 33.
0
isoChannel32
RSC
When bit 0 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 32.
4.20 Isochronous Receive Channel Mask Low Register
The isochronous receive channel mask low set/clear register enables packet receives from the lower 32 isochronous
data channels. See Table 4–14 for a complete description of the register contents.
Bit
31
30
29
28
27
26
Name
Type
25
24
23
22
21
20
19
18
17
16
Isochronous receive channel mask low
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Name
Type
Default
Isochronous receive channel mask low
Register:
Offset:
Type:
Default:
Isochronous receive channel mask low
78h
set register
7Ch
clear register
Read/Set/Clear
XXXX XXXXh
Table 4–14. Isochronous Receive Channel Mask Low Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
isoChannel31
RSC
When bit 31 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 31.
30
isoChannel30
RSC
When bit 30 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 30.
29–2
isoChanneln
RSC
Bits 29 through 2 (isoChanneln, where n = 29, 28, 27, …, 2) follow the same pattern as bits 31 and 30.
1
isoChannel1
RSC
When bit 1 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 1.
0
isoChannel0
RSC
When bit 0 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 0.
4–17
4.21 Interrupt Event Register
The interrupt event set/clear register reflects the state of the various TSB43AB23 interrupt sources. The interrupt bits
are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the
set register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register.
This register is fully compliant with the 1394 Open Host Controller Interface Specification, and the TSB43AB23 device
adds a vendor-specific interrupt function to bit 30. When the interrupt event register is read, the return value is the
bit-wise AND function of the interrupt event and interrupt mask registers. See Table 4–15 for a complete description
of the register contents.
Bit
31
30
29
28
27
26
25
24
Type
R
RSC
RSC
R
RSCU
RSCU
RSCU
RSCU
Default
0
X
0
0
0
X
X
X
Bit
15
14
13
12
11
10
9
8
Name
Default
22
21
20
19
18
17
16
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
X
X
X
X
X
0
X
X
7
6
5
4
3
2
1
0
Interrupt event
Name
Type
23
Interrupt event
RSCU
R
R
R
R
R
RSCU
RSCU
RU
RU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
Register:
Offset:
Type:
Default:
Interrupt event
80h
set register
84h
clear register [returns the content of the interrupt event register bit-wise ANDed with
the interrupt mask register when read]
Read/Set/Clear/Update, read/set/clear, read/update, read-only
XXXX 0XXXh
Table 4–15. Interrupt Event Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
RSVD
R
30
vendorSpecific
RSC
Reserved. Bit 31 returns 0 when read.
This vendor-specific interrupt event is reported when either of the general-purpose interrupts are
asserted. The general-purpose interrupts are enabled by setting the corresponding bits INT_3EN
and INT_2EN (bits 31 and 23, respectively) to 1 in the GPIO control register at offset FCh in the PCI
configuration space (see Section 3.24, GPIO Control Register).
29
SoftInterrupt
RSC
Bit 29 is used by software to generate a TSB43AB23 interrupt for its own use.
28
RSVD
R
27
ack_tardy
RSCU
Reserved. Bit 28 returns 0 when read.
Bit 27 is set to 1 when bit 29 (AckTardyEnable) in the host controller control register at OHCI offset
50h/54h (see Section 4.16, Host Controller Control Register) is set to 1 and any of the following
conditions occur:
a. Data is present in a receive FIFO that is to be delivered to the host.
b. The physical response unit is busy processing requests or sending responses.
c. The TSB43AB23 device sent an ack_tardy acknowledgment.
4–18
26
phyRegRcvd
RSCU
The TSB43AB23 device has received a PHY register data byte which can be read from bits 23–16
in the PHY layer control register at OHCI offset ECh (see Section 4.33, PHY Layer Control Register).
25
cycleTooLong
RSCU
If bit 21 (cycleMaster) in the link control register at OHCI offset E0h/E4h (see Section 4.31, Link
Control Register) is set to 1, this indicates that over 125 µs has elapsed between the start of sending
a cycle start packet and the end of a subaction gap. Bit 21 (cycleMaster) in the link control register
is cleared by this event.
24
unrecoverableError
RSCU
This event occurs when the TSB43AB23 device encounters any error that forces it to stop operations
on any or all of its subunits, for example, when a DMA context sets its dead bit to 1. While bit 24 is
set to 1, all normal interrupts for the context(s) that caused this interrupt are blocked from being set
to 1.
23
cycleInconsistent
RSCU
A cycle start was received that had values for the cycleSeconds and cycleCount fields that are
different from the values in bits 31–25 (cycleSeconds field) and bits 24–12 (cycleCount field) in the
isochronous cycle timer register at OHCI offset F0h (see Section 4.34, Isochronous Cycle Timer
Register).
Table 4–15. Interrupt Event Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
22
cycleLost
RSCU
A lost cycle is indicated when no cycle_start packet is sent or received between two successive
cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately
follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after
a cycleSynch event without an intervening cycle start. Bit 22 may be set to 1 either when a lost cycle
occurs or when logic predicts that one will occur.
21
cycle64Seconds
RSCU
Indicates that the 7th bit of the cycle second counter has changed.
20
cycleSynch
RSCU
Indicates that a new isochronous cycle has started. Bit 20 is set to 1 when the low-order bit of the
cycle count toggles.
19
phy
RSCU
Indicates that the PHY layer requests an interrupt through a status transfer.
18
regAccessFail
RSCU
Indicates that a TSB43AB23 register access has failed due to a missing SCLK clock signal from the
PHY layer. When a register access fails, bit 18 is set to 1 before the next register access.
17
busReset
RSCU
Indicates that the PHY layer has entered bus reset mode.
16
selfIDcomplete
RSCU
A self-ID packet stream has been received. It is generated at the end of the bus initialization process.
Bit 16 is turned off simultaneously when bit 17 (busReset) is turned on.
15
selfIDcomplete2
RSCU
Secondary indication of the end of a self-ID packet stream. Bit 15 is set to 1 by the TSB43AB23 device
when it sets bit 16 (selfIDcomplete), and retains the state, independent of bit 17 (busReset).
14–10
RSVD
R
9
lockRespErr
RSCU
Reserved. Bits 14–10 return 0s when read.
Indicates that the TSB43AB23 device sent a lock response for a lock request to a serial bus register,
but did not receive an ack_complete.
8
postedWriteErr
RSCU
Indicates that a host bus error occurred while the TSB43AB23 device was trying to write a 1394 write
request, which had already been given an ack_complete, into system memory.
7
isochRx
RU
Isochronous receive DMA interrupt. Indicates that one or more isochronous receive contexts have
generated an interrupt. This is not a latched event; it is the logical OR of all bits in the isochronous
receive interrupt event register at OHCI offset A0h/A4h (see Section 4.25, Isochronous Receive
Interrupt Event Register) and isochronous receive interrupt mask register at OHCI offset A8h/ACh
(see Section 4.26, Isochronous Receive Interrupt Mask Register). The isochronous receive interrupt
event register indicates which contexts have been interrupted.
6
isochTx
RU
Isochronous transmit DMA interrupt. Indicates that one or more isochronous transmit contexts have
generated an interrupt. This is not a latched event; it is the logical OR of all bits in the isochronous
transmit interrupt event register at OHCI offset 90h/94h (see Section 4.23, Isochronous Transmit
Interrupt Event Register) and isochronous transmit interrupt mask register at OHCI offset 98h/9Ch
(see Section 4.24, Isochronous Transmit Interrupt Mask Register). The isochronous transmit
interrupt event register indicates which contexts have been interrupted.
5
RSPkt
RSCU
Indicates that a packet was sent to an asynchronous receive response context buffer and the
descriptor xferStatus and resCount fields have been updated.
4
RQPkt
RSCU
Indicates that a packet was sent to an asynchronous receive request context buffer and the
descriptor xferStatus and resCount fields have been updated.
3
ARRS
RSCU
Asynchronous receive response DMA interrupt. Bit 3 is conditionally set to 1 upon completion of an
ARRS DMA context command descriptor.
2
ARRQ
RSCU
Asynchronous receive request DMA interrupt. Bit 2 is conditionally set to 1 upon completion of an
ARRQ DMA context command descriptor.
1
respTxComplete
RSCU
Asynchronous response transmit DMA interrupt. Bit 1 is conditionally set to 1 upon completion of an
ATRS DMA command.
0
reqTxComplete
RSCU
Asynchronous request transmit DMA interrupt. Bit 0 is conditionally set to 1 upon completion of an
ATRQ DMA command.
4–19
4.22 Interrupt Mask Register
The interrupt mask set/clear register enables the various TSB43AB23 interrupt sources. Reads from either the set
register or the clear register always return the contents of the interrupt mask register. In all cases except
masterIntEnable (bit 31) and vendorSpecific (bit 30), the enables for each interrupt event align with the interrupt event
register bits detailed in Table 4–15.
This register is fully compliant with the 1394 Open Host Controller Interface Specification and the TSB43AB23 device
adds an interrupt function to bit 30. See Table 4–16 for a complete description of bits 31 and 30.
Bit
31
30
29
28
27
26
25
Name
Type
24
23
22
21
20
19
18
17
16
Interrupt mask
RSCU
RSC
RSC
R
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
Default
X
X
0
0
0
X
X
X
X
X
X
X
X
0
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSC
R
R
R
R
R
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
Name
Type
Default
Interrupt mask
Register:
Offset:
Type:
Default:
Interrupt mask
88h
set register
8Ch
clear register
Read/Set/Clear/Update, read/set/clear, read/update, read-only
XXXX 0XXXh
Table 4–16. Interrupt Mask Register Description
4–20
BIT
FIELD NAME
TYPE
DESCRIPTION
31
masterIntEnable
RSCU
Master interrupt enable. If bit 31 is set to 1, external interrupts are generated in accordance with the
interrupt mask register. If this bit is cleared, external interrupts are not generated regardless of the
interrupt mask register settings.
30
VendorSpecific
RSC
When this bit and bit 30 (vendorSpecific) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) are set to 1, this vendor-specific interrupt mask enables
interrupt generation.
29
SoftInterrupt
RSC
When this bit and bit 29 (SoftInterrupt) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) are set to 1, this soft-interrupt mask enables interrupt
generation.
28
RSVD
R
27
ack_tardy
RSC
Reserved. Bit 28 returns 0 when read.
When this bit and bit 27 (ack_tardy) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) are set to 1, this acknowledge-tardy interrupt mask enables
interrupt generation.
26
phyRegRcvd
RSC
When this bit and bit 26 (phyRegRcvd) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) are set to 1, this PHY-register interrupt mask enables interrupt
generation.
25
cycleTooLong
RSC
When this bit and bit 25 (cycleTooLong) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) are set to 1, this cycle-too-long interrupt mask enables interrupt
generation.
24
unrecoverableError
RSC
When this bit and bit 24 (unrecoverableError) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) are set to 1, this unrecoverable-error interrupt mask enables
interrupt generation.
23
cycleInconsistent
RSC
When this bit and bit 23 (cycleInconsistent) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) are set to 1, this inconsistent-cycle interrupt mask enables
interrupt generation.
22
cycleLost
RSC
When this bit and bit 22 (cycleLost) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) are set to 1, this lost-cycle interrupt mask enables interrupt
generation.
Table 4–16. Interrupt Mask Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
21
cycle64Seconds
RSC
When this bit and bit 21 (cycle64Seconds) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) are set to 1, this 64-second-cycle interrupt mask enables
interrupt generation.
20
cycleSynch
RSC
When this bit and bit 20 (cycleSynch) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) are set to 1, this isochronous-cycle interrupt mask enables
interrupt generation.
19
phy
RSC
When this bit and bit 19 (phy) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,
Interrupt Event Register) are set to 1, this PHY-status-transfer interrupt mask enables interrupt
generation.
18
regAccessFail
RSC
When this bit and bit 18 (regAccessFail) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) are set to 1, this register-access-failed interrupt mask enables
interrupt generation.
17
busReset
RSC
When this bit and bit 17 (busReset) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) are set to 1, this bus-reset interrupt mask enables interrupt
generation.
16
selfIDcomplete
RSC
When this bit and bit 16 (selfIDcomplete) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) are set to 1, this self-ID-complete interrupt mask enables
interrupt generation.
15
selfIDcomplete2
RSC
When this bit and bit 15 (selfIDcomplete2) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) are set to 1, this second-self-ID-complete interrupt mask
enables interrupt generation.
14–10
RSVD
R
9
lockRespErr
RSC
Reserved. Bits 14–10 return 0s when read.
When this bit and bit 9 (lockRespErr) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) are set to 1, this lock-response-error interrupt mask enables
interrupt generation.
8
postedWriteErr
RSC
When this bit and bit 8 (postedWriteErr) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) are set to 1, this posted-write-error interrupt mask enables
interrupt generation.
7
isochRx
RSC
When this bit and bit 7 (isochRx) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) are set to 1, this isochronous-receive-DMA interrupt mask
enables interrupt generation.
6
isochTx
RSC
When this bit and bit 6 (isochTx) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) are set to 1, this isochronous-transmit-DMA interrupt mask
enables interrupt generation.
5
RSPkt
RSC
When this bit and bit 5 (RSPkt) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,
Interrupt Event Register) are set to 1, this receive-response-packet interrupt mask enables interrupt
generation.
4
RQPkt
RSC
When this bit and bit 4 (RQPkt) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,
Interrupt Event Register) are set to 1, this receive-request-packet interrupt mask enables interrupt
generation.
3
ARRS
RSC
When this bit and bit 3 (ARRS) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,
Interrupt Event Register) are set to 1, this asynchronous-receive-response-DMA interrupt mask
enables interrupt generation.
2
ARRQ
RSC
When this bit and bit 2 (ARRQ) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,
Interrupt Event Register) are set to 1, this asynchronous-receive-request-DMA interrupt mask enables
interrupt generation.
1
respTxComplete
RSC
When this bit and bit 1 (respTxComplete) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) are set to 1, this response-transmit-complete interrupt mask
enables interrupt generation.
0
reqTxComplete
RSC
When this bit and bit 0 (reqTxComplete) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21, Interrupt Event Register) are set to 1, this request-transmit-complete interrupt mask
enables interrupt generation.
4–21
4.23 Isochronous Transmit Interrupt Event Register
The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit
contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* command
completes and its interrupt bits are set to 1. Upon determining that the isochTx (bit 6) interrupt has occurred in the
interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register), software can check this
register to determine which context(s) caused the interrupt. The interrupt bits are set to 1 by an asserting edge of the
corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set register. The only mechanism to
clear a bit in this register is to write a 1 to the corresponding bit in the clear register. See Table 4–17 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
Type
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
Name
25
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
0
0
0
0
0
0
0
6
5
4
3
2
1
0
Isochronous transmit interrupt event
Name
Isochronous transmit interrupt event
Type
R
R
R
R
R
R
R
R
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
Default
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
Register:
Offset:
Isochronous transmit interrupt event
90h
set register
94h
clear register [returns the contents of the isochronous transmit interrupt event
register bit-wise ANDed with the isochronous transmit interrupt mask register
when read]
Read/Set/Clear, read-only
0000 00XXh
Type:
Default:
Table 4–17. Isochronous Transmit Interrupt Event Register Description
BIT
FIELD NAME
TYPE
31–8
RSVD
R
7
isoXmit7
RSC
Isochronous transmit channel 7 caused the interrupt event register bit 6 (isochTx) interrupt.
6
isoXmit6
RSC
Isochronous transmit channel 6 caused the interrupt event register bit 6 (isochTx) interrupt.
5
isoXmit5
RSC
Isochronous transmit channel 5 caused the interrupt event register bit 6 (isochTx) interrupt.
4
isoXmit4
RSC
Isochronous transmit channel 4 caused the interrupt event register bit 6 (isochTx) interrupt.
3
isoXmit3
RSC
Isochronous transmit channel 3 caused the interrupt event register bit 6 (isochTx) interrupt.
2
isoXmit2
RSC
Isochronous transmit channel 2 caused the interrupt event register bit 6 (isochTx) interrupt.
1
isoXmit1
RSC
Isochronous transmit channel 1 caused the interrupt event register bit 6 (isochTx) interrupt.
0
isoXmit0
RSC
Isochronous transmit channel 0 caused the interrupt event register bit 6 (isochTx) interrupt.
4–22
DESCRIPTION
Reserved. Bits 31–8 return 0s when read.
4.24 Isochronous Transmit Interrupt Mask Register
The isochronous transmit interrupt mask set/clear register enables the isochTx interrupt source on a per-channel
basis. Reads from either the set register or the clear register always return the contents of the isochronous transmit
interrupt mask register. In all cases the enables for each interrupt event align with the isochronous transmit interrupt
event register bits detailed in Table 4–17.
Bit
31
30
29
28
27
26
Name
25
24
23
22
21
20
19
18
17
16
Isochronous transmit interrupt mask
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Isochronous transmit interrupt mask
Type
R
R
R
R
R
R
R
R
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
Default
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
Register:
Offset:
Isochronous transmit interrupt mask
98h
set register
9Ch
clear register
Read/Set/Clear, read-only
0000 00XXh
Type:
Default:
4.25 Isochronous Receive Interrupt Event Register
The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive
contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes
and its interrupt bits are set to 1. Upon determining that the isochRx (bit 7) interrupt in the interrupt event register at
OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) has occurred, software can check this register to
determine which context(s) caused the interrupt. The interrupt bits are set to 1 by an asserting edge of the
corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register. The only mechanism to
clear a bit in this register is to write a 1 to the corresponding bit in the clear register. See Table 4–18 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
Name
25
24
23
22
21
20
19
18
17
16
Isochronous receive interrupt event
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Isochronous receive interrupt event
Type
R
R
R
R
R
R
R
R
R
R
R
R
RSC
RSC
RSC
RSC
Default
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
Register:
Offset:
Isochronous receive interrupt event
A0h
set register
A4h
clear register [returns the contents of isochronous receive interrupt event register
bit-wise ANDed with the isochronous receive mask register when read]
Read/Set/Clear, read-only
0000 000Xh
Type:
Default:
Table 4–18. Isochronous Receive Interrupt Event Register Description
BIT
FIELD NAME
TYPE
31–4
RSVD
R
DESCRIPTION
3
isoRecv3
RSC
Isochronous receive channel 3 caused the interrupt event register bit 7 (isochRx) interrupt.
2
isoRecv2
RSC
Isochronous receive channel 2 caused the interrupt event register bit 7 (isochRx) interrupt.
1
isoRecv1
RSC
Isochronous receive channel 1 caused the interrupt event register bit 7 (isochRx) interrupt.
0
isoRecv0
RSC
Isochronous receive channel 0 caused the interrupt event register bit 7 (isochRx) interrupt.
Reserved. Bits 31–4 return 0s when read.
4–23
4.26 Isochronous Receive Interrupt Mask Register
The isochronous receive interrupt mask set/clear register enables the isochRx interrupt source on a per-channel
basis. Reads from either the set register or the clear register always return the contents of the isochronous receive
interrupt mask register. In all cases the enables for each interrupt event align with the isochronous receive interrupt
event register bits detailed in Table 4–18.
Bit
31
30
29
28
27
26
Type
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
Name
25
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
0
0
0
0
0
0
0
6
5
4
3
2
1
0
Isochronous receive interrupt mask
Name
Isochronous receive interrupt mask
Type
R
R
R
R
R
R
R
R
R
R
R
R
RSC
RSC
RSC
RSC
Default
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
Register:
Offset:
Type:
Default:
Isochronous receive interrupt mask
A8h
set register
ACh
clear register
Read/Set/Clear, read-only
0000 000Xh
4.27 Initial Bandwidth Available Register
The initial bandwidth available register value is loaded into the corresponding bus management CSR register on a
system (hardware) or software reset. See Table 4–19 for a complete description of the register contents.
Bit
31
30
29
28
27
26
Name
25
24
23
22
21
20
19
18
17
16
Initial bandwidth available
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
Name
Initial bandwidth available
Register:
Offset:
Type:
Default:
Initial bandwidth available
B0h
Read-only, read/write
0000 1333h
Table 4–19. Initial Bandwidth Available Register Description
BIT
FIELD NAME
TYPE
31–13
RSVD
R
12–0
InitBWAvailable
R/W
4–24
DESCRIPTION
Reserved. Bits 31–13 return 0s when read.
This field is reset to 1333h on a system (hardware) or software reset, and is not affected by a 1394
bus reset. The value of this field is loaded into the BANDWIDTH_AVAILABLE CSR register upon
a G_RST, PCI_RST, or a 1394 bus reset.
4.28 Initial Channels Available High Register
The initial channels available high register value is loaded into the corresponding bus management CSR register on
a system (hardware) or software reset. See Table 4–20 for a complete description of the register contents.
Bit
31
30
29
28
27
26
Name
Type
25
24
23
22
21
20
19
18
17
16
Initial channels available high
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Name
Type
Default
Initial channels available high
Register:
Offset:
Type:
Default:
Initial channels available high
B4h
Read/Write
FFFF FFFFh
Table 4–20. Initial Channels Available High Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31–0
InitChanAvailHi
R/W
This field is reset to FFFF_FFFFh on a system (hardware) or software reset, and is not affected by
a 1394 bus reset. The value of this field is loaded into the CHANNELS_AVAILABLE_HI CSR
register upon a G_RST, PCI_RST, or a 1394 bus reset.
4.29 Initial Channels Available Low Register
The initial channels available low register value is loaded into the corresponding bus management CSR register on
a system (hardware) or software reset. See Table 4–21 for a complete description of the register contents.
Bit
31
30
29
28
27
26
Name
Type
25
24
23
22
21
20
19
18
17
16
Initial channels available low
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Name
Type
Default
Initial channels available low
Register:
Offset:
Type:
Default:
Initial channels available low
B8h
Read/Write
FFFF FFFFh
Table 4–21. Initial Channels Available Low Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31–0
InitChanAvailLo
R/W
This field is reset to FFFF_FFFFh on a system (hardware) or software reset, and is not affected by
a 1394 bus reset. The value of this field is loaded into the CHANNELS_AVAILABLE_LO CSR
register upon a G_RST, PCI_RST, or a 1394 bus reset.
4–25
4.30 Fairness Control Register
The fairness control register provides a mechanism by which software can direct the host controller to transmit
multiple asynchronous requests during a fairness interval. See Table 4–22 for a complete description of the register
contents.
Bit
31
30
29
28
27
26
25
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Fairness control
Name
Fairness control
Type
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Fairness control
DCh
Read-only
0000 0000h
Table 4–22. Fairness Control Register Description
BIT
FIELD NAME
TYPE
31–8
RSVD
R
7–0
pri_req
R/W
4–26
DESCRIPTION
Reserved. Bits 31–8 return 0s when read.
This field specifies the maximum number of priority arbitration requests for asynchronous request
packets that the link is permitted to make of the PHY layer during a fairness interval.
4.31 Link Control Register
The link control set/clear register provides the control flags that enable and configure the link core protocol portions
of the TSB43AB23 device. It contains controls for the receiver and cycle timer. See Table 4–23 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
25
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
24
23
22
21
20
19
18
17
16
R
RSC
RSCU
RSC
R
R
R
R
0
X
X
X
0
0
0
0
7
6
5
4
3
2
1
0
Link control
Name
Link control
Type
R
R
R
R
R
RSC
RSC
R
R
RS
R
R
R
R
R
R
Default
0
0
0
0
0
X
X
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Link control
E0h
set register
E4h
clear register
Read/Set/Clear/Update, read/set/clear, read-only
00X0 0X00h
Table 4–23. Link Control Register Description
BIT
FIELD NAME
TYPE
31–23
RSVD
R
22
cycleSource
RSC
When bit 22 is set to 1, the cycle timer uses an external source (CYCLEIN) to determine when to roll
over the cycle timer. When this bit is cleared, the cycle timer rolls over when the timer reaches
3072 cycles of the 24.576-MHz clock (125 µs).
21
cycleMaster
RSCU
When bit 21 is set to 1, the TSB43AB23 device is root and it generates a cycle start packet every time
the cycle timer rolls over, based on the setting of bit 22 (cycleSource). When bit 21 is cleared, the
iOHCI-Lynx accepts received cycle start packets to maintain synchronization with the node which
is sending them. Bit 21 is automatically cleared when bit 25 (cycleTooLong) in the interrupt event
register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) is set to 1. Bit 21 cannot
be set to 1 until bit 25 (cycleTooLong) is cleared.
20
CycleTimerEnable
RSC
When bit 20 is set to 1, the cycle timer offset counts cycles of the 24.576-MHz clock and rolls over
at the appropriate time, based on the settings of the above bits. When this bit is cleared, the cycle
timer offset does not count.
19–11
RSVD
R
10
RcvPhyPkt
RSC
When bit 10 is set to 1, the receiver accepts incoming PHY packets into the AR request context if
the AR request context is enabled. This bit does not control receipt of self-identification packets.
9
RcvSelfID
RSC
When bit 9 is set to 1, the receiver accepts incoming self-identification packets. Before setting this
bit to 1, software must ensure that the self-ID buffer pointer register contains a valid address.
8–7
RSVD
R
6
tag1SyncFilterLock
RS
5–0
RSVD
R
DESCRIPTION
Reserved. Bits 31–23 return 0s when read.
Reserved. Bits 19–11 return 0s when read.
Reserved. Bits 8 and 7 return 0s when read.
When bit 6 is set to 1, bit 6 (tag1SyncFilter) in the isochronous receive context match register (see
Section 4.46, Isochronous Receive Context Match Register) is set to 1 for all isochronous receive
contexts. When bit 6 is cleared, bit 6 (tag1SyncFilter) in the isochronous receive context match
register has read/write access. This bit is cleared when G_RST is asserted.
Reserved. Bits 5–0 return 0s when read.
4–27
4.32 Node Identification Register
The node identification register contains the address of the node on which the iOHCI-Lynx chip resides and
indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15–6) and the
NodeNumber field (bits 5–0) is referred to as the node ID. See Table 4–24 for a complete description of the register
contents.
Bit
31
30
29
28
27
26
25
RU
RU
R
R
RU
R
R
R
Default
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
Type
Default
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Node identification
Name
Type
24
Node identification
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RU
RU
RU
RU
RU
RU
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
Register:
Offset:
Type:
Default:
Node identification
E8h
Read/Write/Update, read/update, read-only
0000 FFXXh
Table 4–24. Node Identification Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
iDValid
RU
Bit 31 indicates whether or not the TSB43AB23 device has a valid node number. It is cleared when a
1394 bus reset is detected and set to 1 when the TSB43AB23 device receives a new node number
from its PHY layer.
30
root
RU
Bit 30 is set to 1 during the bus reset process if the attached PHY layer is root.
29–28
RSVD
R
27
CPS
RU
Reserved. Bits 29 and 28 return 0s when read.
Bit 27 is set to 1 if the PHY layer is reporting that cable power status is OK.
26–16
RSVD
R
15–6
busNumber
RWU
This field identifies the specific 1394 bus the TSB43AB23 device belongs to when multiple
1394-compatible buses are connected via a bridge.
5–0
NodeNumber
RU
This field is the physical node number established by the PHY layer during self-identification. It is
automatically set to the value received from the PHY layer after the self-identification phase. If the PHY
layer sets the nodeNumber to 63, software must not set bit 15 (run) in the asynchronous context control
register (see Section 4.40, Asynchronous Context Control Register) for either of the AT DMA contexts.
4–28
Reserved. Bits 26–16 return 0s when read.
4.33 PHY Layer Control Register
The PHY layer control register reads from or writes to a PHY register. See Table 4–25 for a complete description of
the register contents.
Bit
31
30
29
28
27
26
25
RU
R
R
R
RU
RU
RU
RU
Default
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
Type
Default
23
22
21
20
19
18
17
16
RU
RU
RU
RU
RU
RU
RU
RU
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
PHY layer control
Name
Type
24
PHY layer control
RWU
RWU
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
PHY layer control
ECh
Read/Write/Update, Read/Write, Read/Update, Read-only
0000 0000h
Table 4–25. PHY Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
rdDone
RU
Bit 31 is cleared to 0 by the TSB43AB23 device when either bit 15 (rdReg) or bit 14 (wrReg) is set to
1. This bit is set to 1 when a register transfer is received from the PHY layer.
30–28
RSVD
R
27–24
rdAddr
RU
Reserved. Bits 30–28 return 0s when read.
This field is the address of the register most recently received from the PHY layer.
23–16
rdData
RU
This field is the contents of a PHY register that has been read.
15
rdReg
RWU
Bit 15 is set to 1 by software to initiate a read request to a PHY register and is cleared by hardware
when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set to 1
simultaneously.
14
wrReg
RWU
Bit 14 is set to 1 by software to initiate a write request to a PHY register and is cleared by hardware
when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set to 1
simultaneously.
13–12
RSVD
R
11–8
regAddr
R/W
This field is the address of the PHY register to be written or read.
7–0
wrData
R/W
This field is the data to be written to a PHY register and is ignored for reads.
Reserved. Bits 13 and 12 return 0s when read.
4–29
4.34 Isochronous Cycle Timer Register
The isochronous cycle timer register indicates the current cycle number and offset. When the TSB43AB23 device
is cycle master, this register is transmitted with the cycle start message. When the TSB43AB23 device is not cycle
master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start message
is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference.
See Table 4–26 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
Default
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
Name
Type
Default
23
22
21
20
19
18
17
16
RWU
RWU
RWU
RWU
RWU
RWU
RWU
X
X
X
X
X
X
X
6
5
4
3
2
1
0
Isochronous cycle timer
Name
Type
24
Isochronous cycle timer
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Register:
Offset:
Type:
Default:
Isochronous cycle timer
F0h
Read/Write/Update
XXXX XXXXh
Table 4–26. Isochronous Cycle Timer Register Description
BIT
FIELD NAME
TYPE
31–25
cycleSeconds
RWU
This field counts seconds [rollovers from bits 24–12 (cycleCount field)] modulo 128.
24–12
cycleCount
RWU
This field counts cycles [rollovers from bits 11–0 (cycleOffset field)] modulo 8000.
11–0
cycleOffset
RWU
This field counts 24.576-MHz clocks modulo 3072, that is, 125 µs. If an external 8-kHz clock
configuration is being used, this field must be cleared to 0s at each tick of the external clock.
4–30
DESCRIPTION
4.35 Asynchronous Request Filter High Register
The asynchronous request filter high set/clear register enables asynchronous receive requests on a per-node basis,
and handles the upper node IDs. When a packet is destined for either the physical request context or the ARRQ
context, the source node ID is examined. If the bit corresponding to the node ID is not set to 1 in this register, the packet
is not acknowledged and the request is not queued. The node ID comparison is done if the source node is on the same
bus as the TSB43AB23 device. Nonlocal bus-sourced packets are not acknowledged unless bit 31 in this register
is set to 1. See Table 4–27 for a complete description of the register contents.
Bit
31
30
29
28
27
26
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
Name
Type
25
24
23
22
21
20
19
18
17
16
RSC
RSC
RSC
RSC
RSC
RSC
RSC
Asynchronous request filter high
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Asynchronous request filter high
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Asynchronous request filter high
100h set register
104h clear register
Read/Set/Clear
0000 0000h
Table 4–27. Asynchronous Request Filter High Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
asynReqAllBuses
RSC
If bit 31 is set to 1, all asynchronous requests received by the TSB43AB23 device from nonlocal
bus nodes are accepted.
30
asynReqResource62
RSC
If bit 30 is set to 1 for local bus node number 62, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
29
asynReqResource61
RSC
If bit 29 is set to 1 for local bus node number 61, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
28
asynReqResource60
RSC
If bit 28 is set to 1 for local bus node number 60, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
27
asynReqResource59
RSC
If bit 27 is set to 1 for local bus node number 59, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
26
asynReqResource58
RSC
If bit 26 is set to 1 for local bus node number 58, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
25
asynReqResource57
RSC
If bit 25 is set to 1 for local bus node number 57, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
24
asynReqResource56
RSC
If bit 24 is set to 1 for local bus node number 56, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
23
asynReqResource55
RSC
If bit 23 is set to 1 for local bus node number 55, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
22
asynReqResource54
RSC
If bit 22 is set to 1 for local bus node number 54, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
21
asynReqResource53
RSC
If bit 21 is set to 1 for local bus node number 53, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
20
asynReqResource52
RSC
If bit 20 is set to 1 for local bus node number 52, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
19
asynReqResource51
RSC
If bit 19 is set to 1 for local bus node number 51, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
4–31
Table 4–27. Asynchronous Request Filter High Register Description (Continued)
4–32
BIT
FIELD NAME
TYPE
DESCRIPTION
18
asynReqResource50
RSC
If bit 18 is set to 1 for local bus node number 50, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
17
asynReqResource49
RSC
If bit 17 is set to 1 for local bus node number 49, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
16
asynReqResource48
RSC
If bit 16 is set to 1 for local bus node number 48, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
15
asynReqResource47
RSC
If bit 15 is set to 1 for local bus node number 47, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
14
asynReqResource46
RSC
If bit 14 is set to 1 for local bus node number 46, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
13
asynReqResource45
RSC
If bit 13 is set to 1 for local bus node number 45, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
12
asynReqResource44
RSC
If bit 12 is set to 1 for local bus node number 44, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
11
asynReqResource43
RSC
If bit 11 is set to 1 for local bus node number 43, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
10
asynReqResource42
RSC
If bit 10 is set to 1 for local bus node number 42, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
9
asynReqResource41
RSC
If bit 9 is set to 1 for local bus node number 41, asynchronous requests received by the TSB43AB23
device from that node are accepted.
8
asynReqResource40
RSC
If bit 8 is set to 1 for local bus node number 40, asynchronous requests received by the TSB43AB23
device from that node are accepted.
7
asynReqResource39
RSC
If bit 7 is set to 1 for local bus node number 39, asynchronous requests received by the TSB43AB23
device from that node are accepted.
6
asynReqResource38
RSC
If bit 6 is set to 1 for local bus node number 38, asynchronous requests received by the TSB43AB23
device from that node are accepted.
5
asynReqResource37
RSC
If bit 5 is set to 1 for local bus node number 37, asynchronous requests received by the TSB43AB23
device from that node are accepted.
4
asynReqResource36
RSC
If bit 4 is set to 1 for local bus node number 36, asynchronous requests received by the TSB43AB23
device from that node are accepted.
3
asynReqResource35
RSC
If bit 3 is set to 1 for local bus node number 35, asynchronous requests received by the TSB43AB23
device from that node are accepted.
2
asynReqResource34
RSC
If bit 2 is set to 1 for local bus node number 34, asynchronous requests received by the TSB43AB23
device from that node are accepted.
1
asynReqResource33
RSC
If bit 1 is set to 1 for local bus node number 33, asynchronous requests received by the TSB43AB23
device from that node are accepted.
0
asynReqResource32
RSC
If bit 0 is set to 1 for local bus node number 32, asynchronous requests received by the TSB43AB23
device from that node are accepted.
4.36 Asynchronous Request Filter Low Register
The asynchronous request filter low set/clear register enables asynchronous receive requests on a per-node basis,
and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to the
asynchronous request filter high register. See Table 4–28 for a complete description of the register contents.
Bit
31
30
29
28
27
26
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
Default
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
Name
Type
Default
24
23
22
21
20
19
18
17
16
RSC
RSC
RSC
RSC
RSC
RSC
RSC
0
0
0
0
0
0
0
6
5
4
3
2
1
0
Asynchronous request filter low
Name
Type
25
Asynchronous request filter low
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Asynchronous request filter low
108h set register
10Ch clear register
Read/Set/Clear
0000 0000h
Table 4–28. Asynchronous Request Filter Low Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
asynReqResource31
RSC
If bit 31 is set to 1 for local bus node number 31, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
30
asynReqResource30
RSC
If bit 30 is set to 1 for local bus node number 30, asynchronous requests received by the
TSB43AB23 device from that node are accepted.
29–2
asynReqResourcen
RSC
Bits 29 through 2 (asynReqResourcen, where n = 29, 28, 27, …, 2) follow the same pattern as
bits 31 and 30.
1
asynReqResource1
RSC
If bit 1 is set to 1 for local bus node number 1, asynchronous requests received by the TSB43AB23
device from that node are accepted.
0
asynReqResource0
RSC
If bit 0 is set to 1 for local bus node number 0, asynchronous requests received by the TSB43AB23
device from that node are accepted.
4–33
4.37 Physical Request Filter High Register
The physical request filter high set/clear register enables physical receive requests on a per-node basis, and handles
the upper node IDs. When a packet is destined for the physical request context, and the node ID has been compared
against the ARRQ registers, then the comparison is done again with this register. If the bit corresponding to the node
ID is not set to 1 in this register, the request is handled by the ARRQ context instead of the physical request context.
The node ID comparison is done if the source node is on the same bus as the TSB43AB23 device. Nonlocal
bus-sourced packets are not acknowledged unless bit 31 in this register is set to 1. See Table 4–29 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
Name
Type
25
24
23
22
21
20
19
18
17
16
Physical request filter high
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Physical request filter high
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Physical request filter high
110h set register
114h clear register
Read/Set/Clear
0000 0000h
Table 4–29. Physical Request Filter High Register Description
4–34
BIT
FIELD NAME
TYPE
DESCRIPTION
31
physReqAllBusses
RSC
If bit 31 is set to 1, all asynchronous requests received by the TSB43AB23 device from nonlocal
bus nodes are accepted. Bit 31 is not cleared by a PCI_RST.
30
physReqResource62
RSC
If bit 30 is set to 1 for local bus node number 62, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
29
physReqResource61
RSC
If bit 29 is set to 1 for local bus node number 61, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
28
physReqResource60
RSC
If bit 28 is set to 1 for local bus node number 60, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
27
physReqResource59
RSC
If bit 27 is set to 1 for local bus node number 59, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
26
physReqResource58
RSC
If bit 26 is set to 1 for local bus node number 58, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
25
physReqResource57
RSC
If bit 25 is set to 1 for local bus node number 57, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
24
physReqResource56
RSC
If bit 24 is set to 1 for local bus node number 56, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
23
physReqResource55
RSC
If bit 23 is set to 1 for local bus node number 55, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
22
physReqResource54
RSC
If bit 22 is set to 1 for local bus node number 54, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
21
physReqResource53
RSC
If bit 21 is set to 1 for local bus node number 53, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
20
physReqResource52
RSC
If bit 20 is set to 1 for local bus node number 52, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
19
physReqResource51
RSC
If bit 19 is set to 1 for local bus node number 51, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
Table 4–29. Physical Request Filter High Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
18
physReqResource50
RSC
If bit 18 is set to 1 for local bus node number 50, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
17
physReqResource49
RSC
If bit 17 is set to 1 for local bus node number 49, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
16
physReqResource48
RSC
If bit 16 is set to 1 for local bus node number 48, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
15
physReqResource47
RSC
If bit 15 is set to 1 for local bus node number 47, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
14
physReqResource46
RSC
If bit 14 is set to 1 for local bus node number 46, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
13
physReqResource45
RSC
If bit 13 is set to 1 for local bus node number 45, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
12
physReqResource44
RSC
If bit 12 is set to 1 for local bus node number 44, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
11
physReqResource43
RSC
If bit 11 is set to 1 for local bus node number 43, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
10
physReqResource42
RSC
If bit 10 is set to 1 for local bus node number 42, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
9
physReqResource41
RSC
If bit 9 is set to 1 for local bus node number 41, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
8
physReqResource40
RSC
If bit 8 is set to 1 for local bus node number 40, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
7
physReqResource39
RSC
If bit 7 is set to 1 for local bus node number 39, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
6
physReqResource38
RSC
If bit 6 is set to 1 for local bus node number 38, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
5
physReqResource37
RSC
If bit 5 is set to 1 for local bus node number 37, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
4
physReqResource36
RSC
If bit 4 is set to 1 for local bus node number 36, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
3
physReqResource35
RSC
If bit 3 is set to 1 for local bus node number 35, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
2
physReqResource34
RSC
If bit 2 is set to 1 for local bus node number 34, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
1
physReqResource33
RSC
If bit 1 is set to 1 for local bus node number 33, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
0
physReqResource32
RSC
If bit 0 is set to 1 for local bus node number 32, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
4–35
4.38 Physical Request Filter Low Register
The physical request filter low set/clear register enables physical receive requests on a per-node basis, and handles
the lower node IDs. When a packet is destined for the physical request context and the node ID has been compared
against the asynchronous request filter registers, then the node ID comparison is done again with this register. If the
bit corresponding to the node ID is not set to 1 in this register, the request is handled by the asynchronous request
context instead of the physical request context. See Table 4–30 for a complete description of the register contents.
Bit
31
30
29
28
27
26
Name
Type
25
24
23
22
21
20
19
18
17
16
Physical request filter low
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
Type
Default
Physical request filter low
Register:
Offset:
Type:
Default:
Physical request filter low
118h set register
11Ch clear register
Read/Set/Clear
0000 0000h
Table 4–30. Physical Request Filter Low Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
physReqResource31
RSC
If bit 31 is set to 1 for local bus node number 31, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
30
physReqResource30
RSC
If bit 30 is set to 1 for local bus node number 30, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
29–2
physReqResourcen
RSC
Bits 29 through 2 (physReqResourcen, where n = 29, 28, 27, …, 2) follow the same pattern as
bits 31 and 30.
1
physReqResource1
RSC
If bit 1 is set to 1 for local bus node number 1, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
0
physReqResource0
RSC
If bit 0 is set to 1 for local bus node number 0, physical requests received by the TSB43AB23
device from that node are handled through the physical request context.
4.39 Physical Upper Bound Register (Optional Register)
The physical upper bound register is an optional register and is not implemented. This register returns all 0s when
read.
Bit
31
30
29
28
27
26
25
Name
24
23
22
21
20
19
18
17
16
Physical upper bound
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
Physical upper bound
Register:
Offset:
Type:
Default:
4–36
Physical upper bound
120h
Read-only
0000 0000h
4.40 Asynchronous Context Control Register
The asynchronous context control set/clear register controls the state and indicates status of the DMA context. See
Table 4–31 for a complete description of the register contents.
Bit
31
30
29
28
27
26
Type
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
Name
Default
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
0
0
0
0
0
0
0
6
5
4
3
2
1
0
Asynchronous context control
Name
Type
25
Asynchronous context control
RSCU
R
R
RSU
RU
RU
R
R
RU
RU
RU
RU
RU
RU
RU
RU
0
0
0
X
0
0
0
0
X
X
X
X
X
X
X
X
Register:
Offset:
Type:
Default:
Asynchronous context control
180h set register
[ATRQ]
184h clear register [ATRQ]
1A0h set register
[ATRS]
1A4h clear register [ATRS]
1C0h set register
[ARRQ]
1C4h clear register [ARRQ]
1E0h set register
[ARRS]
1E4h clear register [ARRS]
Read/Set/Clear/Update, read/set/update, read/update, read-only
0000 X0XXh
Table 4–31. Asynchronous Context Control Register Description
BIT
FIELD NAME
TYPE
31–16
RSVD
R
15
run
RSCU
14–13
RSVD
R
12
wake
RSU
Software sets bit 12 to 1 to cause the TSB43AB23 device to continue or resume descriptor processing.
The TSB43AB23 device clears this bit on every descriptor fetch.
11
dead
RU
The TSB43AB23 device sets bit 11 to 1 when it encounters a fatal error, and clears the bit when
software clears bit 15 (run). Asynchronous contexts supporting out-of-order pipelining provide unique
ContextControl.dead functionality. See Section 7.7 in the 1394 Open Host Controller Interface
Specification (Revision 1.1) for more information.
The TSB43AB23 device sets bit 10 to 1 when it is processing descriptors.
10
active
RU
9–8
RSVD
R
7–5
spd
RU
DESCRIPTION
Reserved. Bits 31–16 return 0s when read.
Bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by software
to stop descriptor processing. The TSB43AB23 device changes this bit only on a system (hardware)
or software reset.
Reserved. Bits 14 and 13 return 0s when read.
Reserved. Bits 9 and 8 return 0s when read.
This field indicates the speed at which a packet was received or transmitted and only contains
meaningful information for receive contexts. This field is encoded as:
000 = 100M bits/sec
001 = 200M bits/sec
010 = 400M bits/sec
All other values are reserved.
4–0
eventcode
RU
This field holds the acknowledge sent by the link core for this packet or an internally generated error
code if the packet was not transferred successfully.
4–37
4.41 Asynchronous Context Command Pointer Register
The asynchronous context command pointer register contains a pointer to the address of the first descriptor block
that the TSB43AB23 device accesses when software enables the context by setting bit 15 (run) in the asynchronous
context control register (see Section 4.40, Asynchronous Context Control Register) to 1. See Table 4–32 for a
complete description of the register contents.
Bit
31
30
29
28
27
26
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
Default
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
Name
Type
Default
24
23
22
21
20
19
18
17
16
RWU
RWU
RWU
RWU
RWU
RWU
X
X
X
X
X
X
5
4
3
2
1
0
Asynchronous context command pointer
Name
Type
25
Asynchronous context command pointer
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
RWU
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Register:
Offset:
Type:
Default:
Asynchronous context command pointer
18Ch [ATRQ]
1ACh [ATRS]
1CCh [ARRQ]
1ECh [ARRS]
Read/Write/Update
XXXX XXXXh
Table 4–32. Asynchronous Context Command Pointer Register Description
BIT
FIELD NAME
TYPE
31–4
descriptorAddress
RWU
Contains the upper 28 bits of the address of a 16-byte aligned descriptor block.
3–0
Z
RWU
Indicates the number of contiguous descriptors at the address pointed to by the descriptor address.
If Z is 0, it indicates that the descriptorAddress field (bits 31–4) is not valid.
4–38
DESCRIPTION
4.42 Isochronous Transmit Context Control Register
The isochronous transmit context control set/clear register controls options, state, and status for the isochronous
transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3,
…, 7). See Table 4–33 for a complete description of the register contents.
Bit
31
30
29
28
27
26
Name
Type
25
24
23
22
21
20
19
18
17
16
Isochronous transmit context control
RSCU
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Isochronous transmit context control
RSC
R
R
RSU
RU
RU
R
R
RU
RU
RU
RU
RU
RU
RU
RU
0
0
0
X
0
0
0
0
X
X
X
X
X
X
X
X
Register:
Offset:
Type:
Default:
Isochronous transmit context control
200h + (16 * n)
set register
204h + (16 * n)
clear register
Read/Set/Clear/Update, read/set/clear, read/set/update, read/update, read-only
XXXX X0XXh
Table 4–33. Isochronous Transmit Context Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
cycleMatchEnable
RSCU
When bit 31 is set to 1, processing occurs such that the packet described by the context first
descriptor block is transmitted in the cycle whose number is specified in the cycleMatch field
(bits 30–16). The cycleMatch field (bits 30–16) must match the low-order two bits of cycleSeconds
and the 13-bit cycleCount field in the cycle start packet that is sent or received immediately before
isochronous transmission begins. Since the isochronous transmit DMA controller may work ahead,
the processing of the first descriptor block may begin slightly in advance of the actual cycle in which
the first packet is transmitted.
The effects of this bit, however, are impacted by the values of other bits in this register and are
explained in the 1394 Open Host Controller Interface Specification. Once the context has become
active, hardware clears this bit.
30–16
cycleMatch
RSC
This field contains a 15-bit value, corresponding to the low-order two bits of the isochronous cycle
timer register at OHCI offset F0h (see Section 4.34, Isochronous Cycle Timer Register)
cycleSeconds field (bits 31–25) and the cycleCount field (bits 24–12). If bit 31 (cycleMatchEnable)
is set to 1, this isochronous transmit DMA context becomes enabled for transmits when the low-order
two bits of the isochronous cycle timer register at OHCI offset F0h cycleSeconds field (bits 31–25)
and the cycleCount field (bits 24–12) value equal this field (cycleMatch) value.
15
run
RSC
Bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by software
to stop descriptor processing. The TSB43AB23 device changes this bit only on a system (hardware)
or software reset.
14–13
RSVD
R
12
wake
RSU
Software sets bit 12 to 1 to cause the TSB43AB23 device to continue or resume descriptor
processing. The TSB43AB23 device clears this bit on every descriptor fetch.
11
dead
RU
The TSB43AB23 device sets bit 11 to 1 when it encounters a fatal error, and clears the bit when
software clears bit 15 (run) to 0.
10
active
RU
The TSB43AB23 device sets bit 10 to 1 when it is processing descriptors.
9–8
RSVD
R
7–5
spd
RU
This field in not meaningful for isochronous transmit contexts.
4–0
event code
RU
Following an OUTPUT_LAST* command, the error code is indicated in this field. Possible values are:
ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown.
Reserved. Bits 14 and 13 return 0s when read.
Reserved. Bits 9 and 8 return 0s when read.
† On an overflow for each running context, the isochronous transmit DMA supports up to 7 cycle skips, when the following are true:
1. Bit 11 (dead) in either the isochronous transmit or receive context control register is set to 1.
2. Bits 4–0 (eventcode field) in either the isochronous transmit or receive context control register is set to evt_timeout.
3. Bit 24 (unrecoverableError) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) is set to 1.
4–39
4.43 Isochronous Transmit Context Command Pointer Register
The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor
block that the TSB43AB23 device accesses when software enables an isochronous transmit context by setting bit 15
(run) in the isochronous transmit context control register (see Section 4.42, Isochronous Transmit Context Control
Register) to 1. The isochronous transmit DMA context command pointer can be read when a context is active. The
n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, …, 7).
Bit
31
30
29
28
27
26
Type
R
R
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
Name
25
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
X
X
X
X
X
X
5
4
3
2
1
0
Isochronous transmit context command pointer
Name
Isochronous transmit context command pointer
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Register:
Offset:
Type:
Default:
Isochronous transmit context command pointer
20Ch + (16 * n)
Read-only
XXXX XXXXh
4.44 Isochronous Receive Context Control Register
The isochronous receive context control set/clear register controls options, state, and status for the isochronous
receive DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3).
See Table 4–34 for a complete description of the register contents.
Bit
31
30
29
28
27
26
Name
Type
25
24
23
22
21
20
19
18
17
16
Isochronous receive context control
RSC
RSC
RSCU
RSC
RSC
R
R
R
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Isochronous receive context control
RSCU
R
R
RSU
RU
RU
R
R
RU
RU
RU
RU
RU
RU
RU
RU
0
0
0
X
0
0
0
0
X
X
X
X
X
X
X
X
Register:
Offset:
Isochronous receive context control
400h + (32 * n)
set register
404h + (32 * n)
clear register
Read/Set/Clear/Update, read/set/clear, read/set/update, read/update, read-only
XX00 X0XXh
Type:
Default:
Table 4–34. Isochronous Receive Context Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
bufferFill
RSC
When bit 31 is set to 1, received packets are placed back-to-back to completely fill each receive
buffer. When this bit is cleared, each received packet is placed in a single buffer. If bit 28
(multiChanMode) is set to 1, this bit must also be set to 1. The value of this bit must not be changed
while bit 10 (active) or bit 15 (run) is set to 1.
30
isochHeader
RSC
When bit 30 is set to 1, received isochronous packets include the complete 4-byte isochronous
packet header seen by the link layer. The end of the packet is marked with a xferStatus in the first
doublet, and a 16-bit timeStamp indicating the time of the most recently received (or sent) cycleStart
packet.
When this bit is cleared, the packet header is stripped from received isochronous packets. The
packet header, if received, immediately precedes the packet payload. The value of this bit must not
be changed while bit 10 (active) or bit 15 (run) is set to 1.
4–40
Table 4–34. Isochronous Receive Context Control Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
29
cycleMatchEnable
RSCU
When bit 29 is set to 1 and the 13-bit cycleMatch field (bits 24–12) in the isochronous receive context
match register (See Section 4.46, Isochronous Receive Context Match Register) matches the 13-bit
cycleCount field in the cycleStart packet, the context begins running. The effects of this bit, however,
are impacted by the values of other bits in this register. Once the context has become active,
hardware clears this bit. The value of this bit must not be changed while bit 10 (active) or bit 15 (run)
is set to 1.
28
multiChanMode
RSC
When bit 28 is set to 1, the corresponding isochronous receive DMA context receives packets for
all isochronous channels enabled in the isochronous receive channel mask high register at OHCI
offset 70h/74h (see Section 4.19, Isochronous Receive Channel Mask High Register) and
isochronous receive channel mask low register at OHCI offset 78h/7Ch (see Section 4.20,
Isochronous Receive Channel Mask Low Register). The isochronous channel number specified in
the isochronous receive context match register (see Section 4.46, Isochronous Receive Context
Match Register) is ignored.
When this bit is cleared, the isochronous receive DMA context receives packets for the single
channel specified in the isochronous receive context match register (see Section 4.46, Isochronous
Receive Context Match Register). Only one isochronous receive DMA context may use the
isochronous receive channel mask registers (see Sections 4.19, Isochronous Receive Channel
Mask High Register, and 4.20, Isochronous Receive Channel Mask Low Register). If more than one
isochronous receive context control register has this bit set, the results are undefined. The value of
this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1.
27
dualBufferMode
RSC
26–16
RSVD
R
15
run
RSCU
14–13
RSVD
R
12
wake
RSU
Software sets bit 12 to 1 to cause the TSB43AB23 device to continue or resume descriptor
processing. The TSB43AB23 device clears this bit on every descriptor fetch.
11
dead
RU
The TSB43AB23 device sets bit 11 to 1 when it encounters a fatal error, and clears the bit when
software clears bit 15 (run).
The TSB43AB23 device sets bit 10 to 1 when it is processing descriptors.
10
active
RU
9–8
RSVD
R
7–5
spd
RU
When bit 27 is set to 1, receive packets are separated into first and second payload and streamed
independently to the firstBuffer series and secondBuffer series as described in Section 10.2.3 in the
1394 Open Host Controller Interface Specification. Also, when bit 27 is set to 1, both bits 28
(multiChanMode) and 31 (bufferFill) are cleared to 0. The value of this bit does not change when
either bit 10 (active) or bit 15 (run) is set to 1.
Reserved. Bits 26–16 return 0s when read.
Bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by software
to stop descriptor processing. The TSB43AB23 device changes this bit only on a system (hardware)
or software reset.
Reserved. Bits 14 and 13 return 0s when read.
Reserved. Bits 9 and 8 return 0s when read.
This field indicates the speed at which the packet was received.
000 = 100M bits/sec
001 = 200M bits/sec
010 = 400M bits/sec
All other values are reserved.
4–0
event code
RU
For bufferFill mode, possible values are: ack_complete, evt_descriptor_read, evt_data_write, and
evt_unknown. Packets with data errors (either dataLength mismatches or dataCRC errors) and
packets for which a FIFO overrun occurred are backed out. For packet-per-buffer mode, possible
values are: ack_complete, ack_data_error, evt_long_packet, evt_overrun, evt_descriptor_read,
evt_data_write, and evt_unknown.
4–41
4.45 Isochronous Receive Context Command Pointer Register
The isochronous receive context command pointer register contains a pointer to the address of the first descriptor
block that the TSB43AB23 device accesses when software enables an isochronous receive context by setting bit 15
(run) in the isochronous receive context control register (see Section 4.44, Isochronous Receive Context Control
Register) to 1. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3).
Bit
31
30
29
28
27
Type
R
R
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
Name
26
25
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
X
X
X
X
X
X
5
4
3
2
1
0
Isochronous receive context command pointer
Name
Isochronous receive context command pointer
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Register:
Offset:
Type:
Default:
4–42
Isochronous receive context command pointer
40Ch + (32 * n)
Read-only
XXXX XXXXh
4.46 Isochronous Receive Context Match Register
The isochronous receive context match register starts an isochronous receive context running on a specified cycle
number, filters incoming isochronous packets based on tag values, and waits for packets with a specified
synchronous value. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). See
Table 4–35 for a complete description of the register contents.
Bit
31
30
29
28
27
26
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Default
X
X
X
X
0
0
0
X
X
Bit
15
14
13
12
11
10
9
8
7
Name
Type
Default
24
23
22
21
20
19
18
17
16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
6
5
4
3
2
1
0
Isochronous receive context match
Name
Type
25
Isochronous receive context match
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
Register:
Offset:
Type:
Default:
Isochronous receive context match
410Ch + (32 * n)
Read/Write, Read-only
XXXX XXXXh
Table 4–35. Isochronous Receive Context Match Register Description
BIT
FIELD NAME
TYPE
31
tag3
R/W
If bit 31 is set to 1, this context matches on isochronous receive packets with a tag field of 11b.
DESCRIPTION
30
tag2
R/W
If bit 30 is set to 1, this context matches on isochronous receive packets with a tag field of 10b.
29
tag1
R/W
If bit 29 is set to 1, this context matches on isochronous receive packets with a tag field of 01b.
28
tag0
R/W
If bit 28 is set to 1, this context matches on isochronous receive packets with a tag field of 00b.
27
RSVD
R
26–12
cycleMatch
R/W
This field contains a 15-bit value corresponding to the two low-order bits of cycleSeconds and the 13-bit
cycleCount field in the cycleStart packet. If cycleMatchEnable (bit 29) in the isochronous receive
context control register (see Section 4.44, Isochronous Receive Context Control Register) is set to 1,
this context is enabled for receives when the two low-order bits of the isochronous cycle timer register
at OHCI offset F0h (see Section 4.34, Isochronous Cycle Timer Register) cycleSeconds field
(bits 31–25) and cycleCount field (bits 24–12) value equal this field (cycleMatch) value.
11–8
sync
R/W
This 4-bit field is compared to the sync field of each isochronous packet for this channel when the
command descriptor w field is set to 11b.
7
RSVD
R
6
tag1SyncFilter
R/W
Reserved. Bit 27 returns 0 when read.
Reserved. Bit 7 returns 0 when read.
If bit 6 and bit 29 (tag1) are set to 1, packets with tag 01b are accepted into the context if the two most
significant bits of the packet sync field are 00b. Packets with tag values other than 01b are filtered
according to bit 28 (tag0), bit 30 (tag2), and bit 31 (tag3) without any additional restrictions.
If this bit is cleared, this context matches on isochronous receive packets as specified in bits 28–31
(tag0–tag3) with no additional restrictions.
5–0
channelNumber
R/W
This 6-bit field indicates the isochronous channel number for which this isochronous receive DMA
context accepts packets.
4–43
5 TI Extension Registers
The TI extension base address register provides a method of accessing memory-mapped TI extension registers. See
Section 3.10, TI Extension Base Address Register, for register bit field details. See Table 5–1 for the TI extension
register listing.
Table 5–1. TI Extension Register Map
REGISTER NAME
OFFSET
Reserved
00h–A7Fh
Isochronous Receive DV Enhancement Set
A80h
Isochronous Receive DV Enhancement Clear
A84h
Link Enhancement Control Set
A88h
Link Enhancement Control Clear
A8Ch
Isochronous Transmit Context 0 Timestamp Offset
A90h
Isochronous Transmit Context 1 Timestamp Offset
A94h
Isochronous Transmit Context 2 Timestamp Offset
A98h
Isochronous Transmit Context 3 Timestamp Offset
A9Ch
Isochronous Transmit Context 4 Timestamp Offset
AA0h
Isochronous Transmit Context 5 Timestamp Offset
AA4h
Isochronous Transmit Context 6 Timestamp Offset
AA8h
Isochronous Transmit Context 7 Timestamp Offset
AA8h
5.1 DV and MPEG2 Timestamp Enhancements
The DV timestamp enhancements are enabled by bit 8 (enab_dv_ts) in the link enhancement control register located
at PCI offset F4h and are aliased in TI extension register space at offset A88h (set) and A8Ch (clear).
The DV and MPEG transmit enhancements are enabled separately by bits in the link enhancement control register
located in PCI configuration space at PCI offset F4h. The link enhancement control register is also aliased as a
set/clear register in TI extension space at offset A88h (set) and A8Ch (clear).
Bit 8 (enab_dv_ts) of the link enhancement control register enables DV timestamp support. When enabled, the link
calculates a timestamp based on the cycle timer and the timestamp offset register and substitutes it in the SYT field
of the CIP once per DV frame.
Bit 10 (enab_mpeg_ts) of the link enhancement control register enables MPEG timestamp support. Two MPEG time
stamp modes are supported. The default mode calculates an initial delta that is added to the calculated timestamp
in addition to a user-defined offset. The initial offset is calculated as the difference in the intended transmit cycle count
and the cycle count field of the timestamp in the first TSP of the MPEG2 stream. The use of the initial delta can be
controlled by bit 31 (DisableInitialOffset) in the timestamp offset register (see Section 5.5, Timestamp Offset
Register).
The MPEG2 timestamp enhancements are enabled by bit 10 (enab_mpeg_ts) in the link enhancement control
register located at PCI offset F4h and aliased in TI extension register space at offset A88h (set) and A8Ch (clear).
When bit 10 (enab_mpeg_ts) is set to 1, the hardware applies the timestamp enhancements to isochronous transmit
packets that have the tag field equal to 01b in the isochronous packet header and a FMT field equal to 10h.
5–1
5.2 Isochronous Receive Digital Video Enhancements
The DV frame synchronous and branch enhancement provides a mechanism in buffer-fill mode to synchronize 1394
DV data that is received in the correct order to DV frame-sized data buffers described by several INPUT_MORE
descriptors (see 1394 Open Host Controller Interface Specification, Revision 1.1). This is accomplished by waiting
for the start-of-frame packet in a DV stream before transferring the received isochronous stream into the memory
buffer described by the INPUT_MORE descriptors. This can improve the DV capture application performance by
reducing the amount of processing overhead required to strip the CIP header and copy the received packets into
frame-sized buffers.
The start of a DV frame is represented in the 1394 packet as a 16-bit pattern of 1FX7h (first byte 1Fh and second
byte X7h) received as the first two bytes of the third quadlet in a DV isochronous packet.
5.3 Isochronous Receive Digital Video Enhancements Register
The isochronous receive digital video enhancements register enables the DV enhancements in the TSB43AB23
device. The bits in this register may only be modified when both the active (bit 10) and run (bit 15) bits of the
corresponding context control register are 0. See Table 5–2 for a complete description of the register contents.
Bit
31
30
29
28
27
Type
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
Name
26
25
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
0
0
0
0
0
0
5
4
3
2
1
0
Isochronous receive digital video enhancements
Name
Isochronous receive digital video enhancements
Type
R
R
RSC
RSC
R
R
RSC
RSC
R
R
RSC
RSC
R
R
RSC
RSC
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Isochronous receive digital video enhancements
A80h
set register
A84h
clear register
Read/Set/Clear, read-only
0000 0000h
Table 5–2. Isochronous Receive Digital Video Enhancements Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31–14
RSVD
R
13
DV_Branch3
RSC
When bit 13 is set to 1, the isochronous receive context 3 synchronizes reception to the DV frame start
tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by frameBranch if
a DV frame start tag is received out of place. This bit is only interpreted when bit 12 (CIP_Strip3) is
set to 1 and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset
460h/464h (see Section 4.44, Isochronous Receive Context Control Register) is cleared to 0.
12
CIP_Strip3
RSC
When bit 12 is set to 1, the isochronous receive context 3 strips the first two quadlets of payload. This
bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at
OHCI offset 460h/464h (see Section 4.44, Isochronous Receive Context Control Register) is cleared
to 0.
11–10
RSVD
R
9
DV_Branch2
RSC
5–2
Reserved. Bits 31–14 return 0s when read.
Reserved. Bits 11 and 10 return 0s when read.
When bit 9 is set to 1, the isochronous receive context 2 synchronizes reception to the DV frame start
tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by frameBranch if
a DV frame start tag is received out of place. This bit is only interpreted when bit 8 (CIP_Strip2) is set
to 1 and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset
440h/444h (see Section 4.44, Isochronous Receive Context Control Register) is cleared to 0.
Table 5–2. Isochronous Receive Digital Video Enhancements Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
8
CIP_Strip2
RSC
When bit 8 is set to 1, the isochronous receive context 2 strips the first two quadlets of payload. This
bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at
OHCI offset 440h/444h (see Section 4.44, Isochronous Receive Context Control Register) is cleared
to 0.
7–6
RSVD
R
5
DV_Branch1
RSC
Reserved. Bits 7 and 6 return 0s when read.
When bit 5 is set to 1, the isochronous receive context 1 synchronizes reception to the DV frame start
tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by frameBranch if
a DV frame start tag is received out of place. This bit is only interpreted when bit 4 (CIP_Strip1) is set
to 1 and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset
420h/424h (see Section 4.44, Isochronous Receive Context Control Register) is cleared to 0.
4
CIP_Strip1
RSC
When bit 4 is set to 1, the isochronous receive context 1 strips the first two quadlets of payload. This
bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at
OHCI offset 420h/424h (see Section 4.44, Isochronous Receive Context Control Register) is cleared
to 0.
3–2
RSVD
R
1
DV_Branch0
RSC
When bit 1 is set to 1, the isochronous receive context 0 synchronizes reception to the DV frame start
tag in bufferfill mode if input_more.b = 01b and jumps to the descriptor pointed to by frameBranch if
a DV frame start tag is received out of place. This bit is only interpreted when bit 0 (CIP_Strip0) is set
to 1 and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset
400h/404h (see Section 4.44, Isochronous Receive Context Control Register) is cleared to 0.
0
CIP_Strip0
RSC
When bit 0 is set to 1, the isochronous receive context 0 strips the first two quadlets of payload. This
bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at
OHCI offset 400h/404h (see Section 4.44, Isochronous Receive Context Control Register) is cleared
to 0.
Reserved. Bits 3 and 2 return 0s when read.
5–3
5.4 Link Enhancement Register
This register is a memory-mapped set/clear register that is an alias of the link enhancement control register at PCI
offset F4h. These bits may be initialized by software. Some of the bits may also be initialized by a serial EEPROM,
if one is present, as noted in the bit descriptions below. If the bits are to be initialized by software, the bits must be
initialized prior to setting bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see Section 4.16,
Host Controller Control Register). See Table 5–3 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
Default
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Link enhancement
Name
Type
24
Link enhancement
RSC
R
RSC
RSC
R
RSC
R
RSC
RSC
R
R
R
R
R
RSC
R
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Link enhancement
A88h
set register
A8Ch
clear register
Read/Set/Clear, read-only
0000 0000h
Table 5–3. Link Enhancement Register Description
BIT
FIELD NAME
TYPE
31–16
RSVD
R
15
dis_at_pipeline
RSC
14
RSVD
R
13–12
atx_thresh
RSC
DESCRIPTION
Reserved. Bits 31–16 return 0s when read.
Disable AT pipelining. When bit 15 is set to 1, out-of-order AT pipelining is disabled.
Reserved.
This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the
TSB43AB23 device retries the packet, it uses a 2K-byte threshold, resulting in a store-and-forward
operation.
00 = Threshold ~ 2K bytes resulting in a store-and-forward operation
01 = Threshold ~ 1.7K bytes (default)
10 = Threshold ~ 1K bytes
11 = Threshold ~ 512 bytes
These bits fine-tune the asynchronous transmit threshold. For most applications the 1.7K-byte
threshold is optimal. Changing this value may increase or decrease the 1394 latency depending on
the average PCI bus latency.
Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds
or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger
than the AT threshold, the remaining data must be received before the AT FIFO is emptied; otherwise,
an underrun condition occurs, resulting in a packet error at the receiving node. As a result, the link
then commences store-and-forward operation. Wait until it has the complete packet in the FIFO
before retransmitting it on the second attempt, to ensure delivery.
An AT threshold of 2K results in store-and-forward operation, which means that asynchronous data
will not be transmitted until an end-of-packet token is received. Restated, setting the AT threshold
to 2K results in only complete packets being transmitted.
Note that this device always uses store-and-forward when the asynchronous transmit retries register
at OHCI offset 08h (see Section 4.3, Asynchronous Transmit Retries Register) is cleared.
5–4
11
RSVD
R
10
enab_mpeg_ts
RSC
9
RSVD
R
8
enab_dv_ts
RSC
Reserved. Bit 11 returns 0 when read.
Enable MPEG timestamp enhancements. When bit 10 is set to 1, the enhancement is enabled for
MPEG transmit streams (FMT = 20h).
Reserved. Bit 9 returns 0 when read.
Enable DV CIP timestamp enhancement. When bit 8 is set to 1, the enhancement is enabled for DV
CIP transmit streams (FMT = 00h).
Table 5–3. Link Enhancement Register Description (Continued)
7
enab_unfair
RSC
Enable asynchronous priority requests. iOHCI-Lynx compatible. Setting bit 7 to 1 enables the link
to respond to requests with priority arbitration. It is recommended that this bit be set to 1.
6
RSVD
R
This bit is not assigned in the TSB43AB23 follow-on products, since this bit location loaded by the
serial EEPROM from the enhancements field corresponds to bit 23 (programPhyEnable) in the host
controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control
Register).
5–2
RSVD
R
Reserved. Bits 5–2 return 0s when read.
1
enab_accel
RSC
0
RSVD
R
Enable acceleration enhancements. iOHCI-Lynx compatible. When bit 1 is set to 1, the PHY layer
is notified that the link supports the IEEE Std 1394a-2000 acceleration enhancements, that is,
ack-accelerated, fly-by concatenation, etc. It is recommended that this bit be set to 1.
Reserved. Bit 0 returns 0 when read.
5.5 Timestamp Offset Register
The value of this register is added as an offset to the cycle timer value when using the MPEG, DV, and CIP
enhancements. A timestamp offset register is implemented per isochronous transmit context. The n value following
the offset indicates the context number (n = 0, 1, 2, 3, …, 7). These registers are programmed by software as
appropriate. See Table 5–4 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
R/W
R
R
R
R
R
R
R/W
Name
Type
24
23
22
21
20
19
18
17
16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timestamp offset
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Timestamp offset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Timestamp offset
A90h + (4*n)
Read/Write, read-only
0000 0000h
Table 5–4. Timestamp Offset Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
DisableInitialOffset
R/W
Bit 31 disables the use of the initial timestamp offset when the MPEG2 enhancements are enabled.
A value of 0 indicates the use of the initial offset, a value of 1 indicates that the initial offset must not
be applied to the calculated timestamp. This bit has no meaning for the DV timestamp
enhancements.
30–25
RSVD
R
24–12
CycleCount
R/W
This field adds an offset to the cycle count field in the timestamp when the DV or MPEG2
enhancements are enabled. The cycle count field is incremented modulo 8000; therefore, values in
this field must be limited between 0 and 7999.
11–0
CycleOffset
R/W
This field adds an offset to the cycle offset field in the timestamp when the DV or MPEG2
enhancements are enabled. The cycle offset field is incremented modulo 3072; therefore, values in
this field must be limited between 0 and 3071.
Reserved. Bits 30–25 return 0s when read.
5–5
6 Serial EEPROM Interface
The TSB43AB23 device provides a serial bus interface to initialize the GUID registers and a few PCI configuration
registers through a serial EEPROM. The TSB43AB23 device communicates with the serial EEPROM via the 2-wire
serial interface.
After power up the serial interface initializes the locations listed in Table 6–1. While the TSB43AB23 device accesses
the serial EEPROM, all incoming PCI slave accesses are terminated with retry status. Table 6–2 shows the serial
EEPROM memory map required for initializing the TSB43AB23 registers.
NOTE: If an EEPROM is implemented in the design, byte offsets 00h–16h must be
programmed. An unprogrammed EEPROM defaults to all 1s, which can adversely impact
device operation.
Table 6–1. Registers and Bits Loadable Through Serial EEPROM
EEPROM BYTE OFFSET
OHCI/PCI
CONFIGURATION
OFFSET
REGISTER NAME
REGISTER BITS
LOADED
FROM EEPROM
00h
PCI register (3Eh)
PCI maximum latency, PCI minimum grant
15–0
01h
PCI register (2Dh)
Vendor identification
15–0
03h
PCI register (2Ch)
Subsystem identification
15–0
05h (bit 6)
OHCI register (50h)
Host controller control
05h
PCI register (F4h)
Link enhancement control
06h
OHCI register (04h)
GUID ROM
7–0
07h–0Ah
OHCI register (24h)
GUID high
31–0
0Bh–0Eh
OHCI register (28h)
GUID low
31–0
10h
PCI register (F4h)
Link enhancement control
15–12
11h–12h
PCI register (F0h)
Miscellaneous configuration†
PCI PHY control‡
15, 4
23
7, 6, 1
16h
PCI register (ECh)
7–0
† Bits 2–0 at EEPROM byte offset 11h must be programmed to 000b to ensure proper functioning. By default, unprogrammed EEPROM
bits are 1.
‡ Bits 6–4 and 2–0 at EEPROM byte offset 16h must be programmed to 0 to ensure proper functioning. Bit 3 must be programmed to 1.
If CNA functionality is desired on terminal 96, bit 7 must be programmed to 1; otherwise, bit 7 can be programmed to 0.
6–1
Table 6–2. Serial EEPROM Map
EEPROM
BYTE
ADDRESS
00
BYTE DESCRIPTION
PCI maximum latency (0h)
PCI_minimum grant (0h)
01
PCI vendor ID
02
PCI vendor ID (msbyte)
03
PCI subsystem ID (lsbyte)
04
PCI subsystem ID (msbyte)
05
06
[7]
Link_enhancement
Control.enab_unfair
[6]
HCControl.
ProgramPhy
Enable
[7–6]
RSVD
[5–3]
RSVD
[2]
RSVD†
Mini
ROM
address
GUID high (lsbyte 0)
08
GUID high (byte 1)
09
GUID high (byte 2)
0A
GUID high (msbyte 3)
0B
GUID low (lsbyte 0)
0C
GUID low (byte 1)
0D
GUID low (byte 2)
0E
GUID low (msbyte 3)
0F
Checksum
[15]
dis_at_pipeline
[14]
RSVD
[13–12]
ATX threshold
[7–5]
RSVD
11§
12
[11–8]
RSVD
[4]
Disable
Target
Abort
[3–0]
RSVD
[15]
PME D3 Cold
[14–8]
RSVD
13
[7–0]
RSVD
14
[7–0]
RSVD
15
16¶
[0]
RSVD
[4–3]
RSVD
07
10‡
[1]
Link_enhancement
Control.enab_accel
RSVD
[7]
CNA OUT Enable
[6–4]
RSVD
[3]
RSVD
[2–0]
RSVD
17–1F
RSVD
† Bit 2 at EEPROM byte offset 05h must be programmed to 0b.
‡ Bit 14 must be programmed to 0 for normal operation.
§ Bits 2–0 at EEPROM byte offset 11h must be programmed to 000b to ensure proper functioning. By default, unprogrammed EEPROM bits are
1.
¶ Bits 6–4 and 2–0 at EEPROM byte offset 16h must be programmed to 0 to ensure proper functioning. Bit 3 must be programmed to 1. If CNA
functionality is desired on terminal 96, bit 7 must be programmed to 1; otherwise, bit 7 can be programmed to 0.
6–2
7 PHY Register Configuration
There are 16 accessible internal registers in the TSB43AB23 device. The configuration of the registers at addresses
0h through 7h (the base registers) is fixed, whereas the configuration of the registers at addresses 8h through Fh (the
paged registers) is dependent upon which one of eight pages, numbered 0h through 7h, is currently selected. The
selected page is set in base register 7h.
7.1 Base Registers
Table 7–1 shows the configuration of the base registers, and Table 7–2 shows the corresponding field descriptions.
The base register field definitions are unaffected by the selected page number.
A reserved register or register field (marked as reserved in the following register configuration tables) is read as 0,
but is subject to future usage. All registers in address pages 2 through 6 are reserved.
Table 7–1. Base Register Configuration
BIT POSITION
ADDRESS
0
1
0000
0001
2
3
4
5
Physical ID
RHB
IBR
6
7
R
CPS
Gap_Count
0010
Extended (111b)
Reserved
Total_Ports (0011b)
0011
Max_Speed (010b)
Reserved
Delay (0000b)
Jitter (000b)
0100
LCtrl
C
0101
Watchdog
ISBR
0110
0111
Loop
Pwr_fail
Pwr_Class
Timeout
Port_event
Enab_accel
Enab_multi
Reserved
Page_Select
Reserved
Port_Select
7–1
Table 7–2. Base Register Field Descriptions
FIELD
SIZE
TYPE
DESCRIPTION
Physical ID
6
R
This field contains the physical address ID of this node determined during self-ID. The physical ID is invalid
after a bus reset until self-ID has completed as indicated by an unsolicited register-0 status transfer.
R
1
R
Root. This bit indicates that this node is the root node. The R bit is cleared to 0 by bus reset and is set to 1
during tree-ID if this node becomes root.
CPS
1
R
Cable-power-status. This bit indicates the state of the CPS input terminal. The CPS terminal is normally tied
to serial bus cable power through a 400-kΩ resistor. A 0 in this bit indicates that the cable power voltage has
dropped below its threshold for ensured reliable operation.
RHB
1
R/W
Root-holdoff bit. This bit instructs the PHY layer to attempt to become root after the next bus reset. The RHB
bit is cleared to 0 by a system (hardware) reset and is unaffected by a bus reset.
IBR
1
R/W
Initiate bus reset. This bit instructs the PHY layer to initiate a long (166 µs) bus reset at the next opportunity.
Any receive or transmit operation in progress when this bit is set will complete before the bus reset is
initiated. The IBR bit is cleared to 0 after a system (hardware) reset or a bus reset.
Gap_Count
6
R/W
Arbitration gap count. This value sets the subaction (fair) gap, arb-reset gap, and arb-delay times. The gap
count can be set either by a write to the register, or by reception or transmission of a PHY_CONFIG packet.
The gap count is reset to 3Fh by system (hardware) reset or after two consecutive bus resets without an
intervening write to the gap count register (either by a write to the PHY register or by a PHY_CONFIG
packet).
Extended
3
R
Extended register definition. For the TSB43AB23 device, this field is 111b, indicating that the extended
register set is implemented.
Total_Ports
4
R
Number of ports. This field indicates the number of ports implemented in the PHY layer. For the TSB43AB23
device this field is 3.
Max_Speed
3
R
PHY speed capability. For the TSB43AB23 PHY layer this field is 010b, indicating S400 speed capability.
Delay
4
R
PHY repeater data delay. This field indicates the worst case repeater data delay of the PHY layer, expressed
as 144+(delay × 20) ns. For the TSB43AB23 device this field is 0.
LCtrl
1
R/W
Link-active status control. This bit controls the active status of the LLC as indicated during self-ID. The
logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet. The LLC
is considered active only if both the LPS input is active and the LCtrl bit is set.
The LCtrl bit provides a software controllable means to indicate the LLC active/status in lieu of using the LPS
input.
The LCtrl bit is set to 1 by a system (hardware) reset and is unaffected by a bus reset.
NOTE: The state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state of the
LCtrl bit. If the PHY-LLC interface is operational as determined by the LPS input being active, received
packets and status information continues to be presented on the interface, and any requests indicated on the
LREQ input are processed, even if the LCtrl bit is cleared to 0.
C
1
R/W
Contender status. This bit indicates that this node is a contender for the bus or isochronous resource
manager. This bit is replicated in the c field (bit 20) of the self-ID packet.
Jitter
3
R
PHY repeater jitter. This field indicates the worst case difference between the fastest and slowest repeater
data delay, expressed as (Jitter+1) × 20 ns. For the TSB43AB23 device, this field is 0.
Pwr_Class
3
R/W
Node power class. This field indicates this node power consumption and source characteristics and is
replicated in the pwr field (bits 21–23) of the self-ID packet. This field is reset to the state specified by the
PC0–PC2 input terminals upon a system (hardware) reset and is unaffected by a bus reset. See Table 7–9.
Watchdog
1
R/W
Watchdog enable. This bit, if set to 1, enables the port event interrupt (Port_event) bit to be set whenever
resume operations begin on any port. This bit is cleared to 0 by system (hardware) reset and is unaffected by
bus reset.
7–2
Table 7–2. Base Register Field Descriptions (Continued)
FIELD
ISBR
SIZE
TYPE
DESCRIPTION
1
R/W
Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY layer to initiate a short (1.3 µs)
arbitrated bus reset at the next opportunity. This bit is cleared to 0 by a bus reset.
NOTE: Legacy IEEE Std 1394-1995 compliant PHY layers can not be capable of performing short bus
resets. Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a
long bus reset being performed.
Loop
1
R/W
Loop detect. This bit is set to 1 when the arbitration controller times out during tree-ID start and may indicate
that the bus is configured in a loop. This bit is cleared to 0 by system (hardware) reset or by writing a 1 to this
register bit.
If the Loop and Watchdog bits are both set and the LLC is or becomes inactive, the PHY layer activates the
LLC to service the interrupt.
NOTE: If the network is configured in a loop, only those nodes which are part of the loop generate a
configuration-timeout interrupt. All other nodes instead time out waiting for the tree-ID and/or self-ID process
to complete and then generate a state time-out interrupt and bus-reset.
Pwr_fail
1
R/W
Cable power failure detect. This bit is set to 1 whenever the CPS input transitions from high to low indicating
that cable power may be too low for reliable operation. This bit is cleared to 0 by system (hardware) reset or
by writing a 1 to this register bit.
Timeout
1
R/W
State time-out interrupt. This bit indicates that a state time-out has occurred (which also causes a bus reset
to occur). This bit is cleared to 0 by system (hardware) reset or by writing a 1 to this register bit.
Port_event
1
R/W
Port event detect. This bit is set to 1 upon a change in the bias (unless disabled) connected, disabled, or fault
bits for any port for which the port interrupt enable (Int_enable) bit is set. Additionally, if the Watchdog bit is
set, the Port_event bit is set to 1 at the start of resume operations on any port. This bit is cleared to 0 by
system (hardware) reset or by writing a 1 to this register bit.
Enab_accel
1
R/W
Enable accelerated arbitration. This bit enables the PHY layer to perform the various arbitration acceleration
enhancements defined in IEEE Std 1394a-2000 (ACK-accelerated arbitration, asynchronous fly-by
concatenation, and isochronous fly-by concatenation). This bit is cleared to 0 by system (hardware) reset
and is unaffected by bus reset.
Enab_multi
1
R/W
Enable multispeed concatenated packets. This bit enables the PHY layer to transmit concatenated packets
of differing speeds in accordance with the protocols defined in IEEE Std 1394a-2000. This bit is cleared to 0
by system (hardware) reset and is unaffected by bus reset.
Page_Select
3
R/W
Page_Select. This field selects the register page to use when accessing register addresses 8 through 15.
This field is cleared to 0 by a system (hardware) reset and is unaffected by bus reset.
Port_Select
4
R/W
Port_Select. This field selects the port when accessing per-port status or control (for example, when one of
the port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is cleared
to 0 by system (hardware) reset and is unaffected by bus reset.
7–3
7.2 Port Status Register
The port status page provides access to configuration and status information for each of the ports. The port is selected
by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. Table 7–3
shows the configuration of the port status page registers and Table 7–4 shows the corresponding field descriptions.
If the selected port is not implemented, all registers in the port status page are read as 0.
Table 7–3. Page 0 (Port Status) Register Configuration
BIT POSITION
ADDRESS
0
1
1000
AStat
1001
Peer_Speed
2
3
4
5
Ch
Con
Int_enable
Fault
BStat
1010
Reserved
1011
Reserved
1100
Reserved
1101
Reserved
1110
Reserved
1111
Reserved
6
7
Bias
Dis
Reserved
Table 7–4. Page 0 (Port Status) Register Field Descriptions
FIELD
SIZE
TYPE
DESCRIPTION
AStat
2
R
TPA line state. This field indicates the TPA line state of the selected port, encoded as follows:
Code
Arb Value
11
Z
10
0
01
1
00
invalid
BStat
2
R
TPB line state. This field indicates the TPB line state of the selected port. This field has the same encoding as
the AStat field.
Ch
1
R
Child/parent status. A 1 indicates that the selected port is a child port. A 0 indicates that the selected port is
the parent port. A disconnected, disabled, or suspended port is reported as a child port. The Ch bit is invalid
after a bus reset until tree-ID has completed.
Con
1
R
Debounced port connection status. This bit indicates that the selected port is connected. The connection
must be stable for the debounce time of approximately 341 ms for the Con bit to be set to 1. The Con bit is
cleared to 0 by system (hardware) reset and is unaffected by bus reset.
NOTE: The Con bit indicates that the port is physically connected to a peer PHY device, but the port is not
necessarily active.
Bias
1
R
Debounced incoming cable bias status. A 1 indicates that the selected port is detecting incoming cable bias.
The incoming cable bias must be stable for the debounce time of 52 µs for the Bias bit to be set to 1.
Dis
1
R/W
Port disabled control. If the Dis bit is set to 1, the selected port is disabled. The Dis bit is cleared to 0 by
system (hardware) reset (all ports are enabled for normal operation following system (hardware) reset). The
Dis bit is not affected by bus reset.
Peer_Speed
3
R
Port peer speed. This field indicates the highest speed capability of the peer PHY device connected to the
selected port, encoded as follows:
Code
Peer Speed
000
S100
001
S200
010
S400
011–111
invalid
The Peer_Speed field is invalid after a bus reset until self-ID has completed.
NOTE: Peer speed codes higher than 010b (S400) are defined in IEEE Std 1394a-2000. However, the
TSB43AB23 device is only capable of detecting peer speeds up to S400.
7–4
Table 7–4. Page 0 (Port Status) Register Field Descriptions (Continued)
FIELD
SIZE
TYPE
DESCRIPTION
Int_enable
1
R/W
Port event interrupt enable. When the Int_enable bit is set to 1, a port event on the selected port sets the port
event interrupt (Port_event) bit and notifies the link. This bit is cleared to 0 by a system (hardware) reset and
is unaffected by bus reset.
Fault
1
R/W
Fault. This bit indicates that a resume-fault or suspend-fault has occurred on the selected port, and that the
port is in the suspended state. A resume-fault occurs when a resuming port fails to detect incoming cable
bias from its attached peer. A suspend-fault occurs when a suspending port continues to detect incoming
cable bias from its attached peer. Writing 1 to this bit clears the fault bit to 0. This bit is cleared to 0 by system
(hardware) reset and is unaffected by bus reset.
7.3 Vendor Identification Register
The vendor identification page identifies the vendor/manufacturer and compliance level. The page is selected by
writing 1 to the Page_Select field in base register 7. Table 7–5 shows the configuration of the vendor identification
page, and Table 7–6 shows the corresponding field descriptions.
Table 7–5. Page 1 (Vendor ID) Register Configuration
BIT POSITION
ADDRESS
0
1
2
3
4
1000
Compliance
1001
Reserved
1010
Vendor_ID[0]
1011
Vendor_ID[1]
1100
Vendor_ID[2]
1101
Product_ID[0]
1110
Product_ID[1]
1111
Product_ID[2]
5
6
7
Table 7–6. Page 1 (Vendor ID) Register Field Descriptions
FIELD
SIZE
TYPE
DESCRIPTION
Compliance
8
R
Compliance level. For the TSB43AB23 device this field is 01h, indicating compliance with IEEE Std
1394a-2000.
Vendor_ID
24
R
Manufacturer’s organizationally unique identifier (OUI). For the TSB43AB23 device this field is 08 0028h
(Texas Instruments) (the MSB is at register address 1010b).
Product_ID
24
R
Product identifier. For the TSB43AB23 device this field is 42 4499h (the MSB is at register address 1101b).
7–5
7.4 Vendor-Dependent Register
The vendor-dependent page provides access to the special control features of the TSB43AB23 device, as well as
to configuration and status information used in manufacturing test and debug. This page is selected by writing 7 to
the Page_Select field in base register 7. Table 7–7 shows the configuration of the vendor-dependent page, and
Table 7–8 shows the corresponding field descriptions.
Table 7–7. Page 7 (Vendor-Dependent) Register Configuration
BIT POSITION
ADDRESS
0
1000
NPA
1
2
3
4
Reserved
5
6
7
Link_Speed
1001
Reserved for test
1010
Reserved for test
1011
Reserved for test
1100
Reserved for test
1101
Reserved for test
1110
Reserved for test
1111
Reserved for test
Table 7–8. Page 7 (Vendor-Dependent) Register Field Descriptions
FIELD
SIZE
TYPE
DESCRIPTION
NPA
1
R/W
Null-packet actions flag. This bit instructs the PHY layer to not clear fair and priority requests when a null
packet is received with arbitration acceleration enabled. If this bit is set to 1, fair and priority requests are
cleared only when a packet of more than 8 bits is received; ACK packets (exactly 8 data bits), null packets
(no data bits), and malformed packets (less than 8 data bits) do not clear fair and priority requests. If this bit is
cleared to 0, fair and priority requests are cleared when any non-ACK packet is received, including null
packets or malformed packets of less than 8 bits. This bit is cleared to 0 by system (hardware) reset and is
unaffected by bus reset.
Link_Speed
2
R/W
Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows:
Code
Speed
00
S100
01
S200
10
S400
11
illegal
This field is replicated in the sp field of the self-ID packet to indicate the speed capability of the node (PHY
and LLC in combination). However, this field does not affect the PHY speed capability indicated to peer
PHYs during self-ID; the TSB43AB23 PHY layer identifies itself as S400 capable to its peers regardless of
the value in this field. This field is set to 10b (S400) by system (hardware) reset and is unaffected by bus
reset.
7–6
7.5 Power-Class Programming
The PC0–PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field
(bits 21–23) of the transmitted self-ID packet. Table 7–9 shows the descriptions of the various power classes. The
default power-class value is loaded following a system (hardware) reset, but is overridden by any value subsequently
loaded into the Pwr_Class field in register 4.
Table 7–9. Power Class Descriptions
PC0–PC2
DESCRIPTION
000
Node does not need power and does not repeat power.
001
Node is self-powered and provides a minimum of 15 W to the bus.
010
Node is self-powered and provides a minimum of 30 W to the bus.
011
Node is self-powered and provides a minimum of 45 W to the bus.
100
Node may be powered from the bus and is using up to 3 W. No additional power is needed to enable the link.
101
Reserved
110
Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link.
111
Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link.
7–7
8 Application Information
8.1 PHY Port Cable Connection
TSB43AB23
400 kΩ
CPS
1 µF
Cable
Power
Pair
TPBIAS
56 Ω
56 Ω
TPA+
Cable
Pair
A
TPA–
Cable Port
TPB+
Cable
Pair
B
TPB–
56 Ω
220 pF
(see Note A)
56 Ω
5 kΩ
Outer Shield
Termination
NOTE A: IEEE Std 1394-1995 calls for a 250-pF capacitor, which is a nonstandard component value. A 220-pF capacitor is recommended.
Figure 8–1. TP Cable Connections
8–1
Outer Cable Shield
0.01 µF
1 MΩ
0.001 µF
Chassis Ground
Figure 8–2. Typical Compliant DC Isolated Outer Shield Termination
Outer Cable Shield
Chassis Ground
Figure 8–3. Non-DC Isolated Outer Shield Termination
8.2 Crystal Selection
The TSB43AB23 device is designed to use an external 24.576-MHz crystal connected between the XI and XO pins
to provide the reference for an internal oscillator circuit. This oscillator in turn drives a PLL circuit that generates the
various clocks required for transmission and resynchronization of data at the S100 through S400 media data rates.
A variation of less than ±100 ppm from nominal for the media data rates is required by IEEE Std 1394-1995. Adjacent
PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHY devices
must be able to compensate for this difference over the maximum packet length. Large clock variations may cause
resynchronization overflows or underflows, resulting in corrupted packet data.
The following are some typical specifications for crystals used with the PHYs from TI in order to achieve the required
frequency accuracy and stability:
•
Crystal mode of operation: Fundamental
•
Frequency tolerance @ 25°C: Total frequency variation for the complete circuit is ±100 ppm. A crystal with
±30 ppm frequency tolerance is recommended for adequate margin.
•
Frequency stability (over temperature and age): A crystal with ±30 ppm frequency stability is recommended
for adequate margin.
NOTE: The total frequency variation must be kept below ±100 ppm from nominal with some
allowance for error introduced by board and device variations. Trade-offs between frequency
tolerance and stability may be made as long as the total frequency variation is less than
±100 ppm. For example, the frequency tolerance of the crystal may be specified at 50 ppm and
the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible
variation due to the crystal alone. Crystal aging also contributes to the frequency variation.
•
8–2
Load capacitance: For parallel resonant mode crystal circuits, the frequency of oscillation is dependent
upon the load capacitance specified for the crystal. Total load capacitance (CL) is a function of not only the
discrete load capacitors, but also board layout and circuit. It is recommended that load capacitors with a
maximum of ±5% tolerance be used.
For example, load capacitors (C9 and C10 in Figure 8–4) of 16 pF each were appropriate for the layout of the
TSB43AB23 evaluation module (EVM), which uses a crystal specified for 12-pF loading. The load specified for the
crystal includes the load capacitors (C9 and C10), the loading of the PHY pins (CPHY), and the loading of the board
itself (CBD). The value of CPHY is typically about 1 pF, and CBD is typically 0.8 pF per centimeter of board etch; a typical
board can have 3 pF to 6 pF or more. The load capacitors C9 and C10 combine as capacitors in series so that the
total load capacitance is:
C L + C9 C10 ) C PHY ) C BD
C9 ) C10
C9
X1
X1
24.576 MHz
IS
CPHY + CBD
X0
C10
Figure 8–4. Load Capacitance for the TSB43AB23 PHY
The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency, minimizing noise
introduced into the PHY phase-lock loop, and minimizing any emissions from the circuit. The crystal and two load
capacitors must be considered as a unit during layout. The crystal and the load capacitors must be placed as close
as possible to one another while minimizing the loop area created by the combination of the three components.
Varying the size of the capacitors may help in this. Minimizing the loop area minimizes the effect of the resonant
current (Is) that flows in this resonant circuit. This layout unit (crystal and load capacitors) must then be placed as
close as possible to the PHY X1 and X0 pins to minimize etch lengths, as shown in Figure 8–5.
C9
C10
X1
For more details on crystal selection, see application report SLLA051 available from the TI website:
http://www.ti.com/sc/1394.
Figure 8–5. Recommended Crystal and Capacitor Layout
8.3 Bus Reset
In the TSB43AB23 device, the initiate bus reset (IBR) bit may be set to 1 in order to initiate a bus reset and initialization
sequence. The IBR bit is located in PHY register 1, along with the root-holdoff bit (RHB) and Gap_Count field, as
required by IEEE Std 1394a-2000. Therefore, whenever the IBR bit is written, the RHB and Gap_Count are also
written.
The RHB and Gap_Count may also be updated by PHY-config packets. The TSB43AB23 device is IEEE 1394a-2000
compliant, and therefore both the reception and transmission of PHY-config packets cause the RHB and Gap_Count
to be loaded, unlike older IEEE 1394-1995 compliant PHY devices which decode only received PHY-config packets.
The gap-count is set to the maximum value of 63 after 2 consecutive bus resets without an intervening write to the
Gap_Count, either by a write to PHY register 1 or by a PHY-config packet. This mechanism allows a PHY-config
8–3
packet to be transmitted and then a bus reset initiated so as to verify that all nodes on the bus have updated their
RHBs and Gap_Count values, without having the Gap_Count set back to 63 by the bus reset. The subsequent
connection of a new node to the bus, which initiates a bus reset, then causes the Gap_Count of each node to be set
to 63. Note, however, that if a subsequent bus reset is instead initiated by a write to register 1 to set the IBR bit, all
other nodes on the bus have their Gap_Count values set to 63, while this node Gap_Count remains set to the value
just loaded by the write to PHY register 1.
Therefore, in order to maintain consistent gap-counts throughout the bus, the following rules apply to the use of the
IBR bit, RHB, and Gap_Count in PHY register 1:
•
Following the transmission of a PHY-config packet, a bus reset must be initiated in order to verify that all
nodes have correctly updated their RHBs and Gap_Count values and to ensure that a subsequent new
connection to the bus causes the Gap_Count to be set to 63 on all nodes in the bus. If this bus reset is
initiated by setting the IBR bit to 1, the RHB and Gap_Count field must also be loaded with the correct values
consistent with the just transmitted PHY-config packet. In the TSB43AB23 device, the RHB and Gap_Count
are updated to their correct values upon the transmission of the PHY-config packet, so these values may
first be read from register 1 and then rewritten.
•
Other than to initiate the bus reset, which must follow the transmission of a PHY-config packet, whenever
the IBR bit is set to 1 in order to initiate a bus reset, the Gap_Count value must also be set to 63 so as to
be consistent with other nodes on the bus, and the RHB must be maintained with its current value.
•
The PHY register 1 must not be written to except to set the IBR bit. The RHB and Gap_Count must not be
written without also setting the IBR bit to 1.
8.4 EMI Guidelines
For electromagnetic interference (EMI) guidelines and recommendations send a request via e-mail to
1394–[email protected].
8–4
9 Electrical Characteristics
9.1 Absolute Maximum Ratings Over Operating Temperature Ranges†
Supply voltage range:
REG18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.2 V to 2.2 V
AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4.0 V
DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4.0 V
PLLVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4.0 V
VDDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 5.5 V
Input voltage range for PCI, VI, PHY, and Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 to VDD + 0.5 V
Output voltage range for PCI, VO, PHY, and Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 to VDD + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VDD) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Electrostatic discharge (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HBM: 2 kV
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from cage for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies to external input and bidirectional buffers. For 5-V tolerant use VI > VDDI. For PCI use VI > VDDP.
2. Applies to external output and bidirectional buffers. For 5-V tolerant use VO > VDDI. For PCI use VO > VDDP.
3. HBM is human body model, MM is machine model.
DISSIPATION RATING TABLE
PACKAGE
PDT‡
PDT§
TA ≤ 25°C
POWER RATING
DERATING FACTOR§
ABOVE TA = 25°C
TA = 70°C
POWER RATING
1.116 W
0.013 W/°C
0.563 W
0.967 W
0.009 W/°C
0.523 W
‡ Standard JEDEC high-K board
§ Standard JEDEC low-K board
9–1
9.2 Recommended Operating Conditions
TEST
CONDITION
REG18
Core voltage, AVDD
Core voltage, DVDD
Core voltage, PLLVDD
Output voltage, VO
TTL and LVCMOS terminals
3.3 V
PCI
5V
High-level
High
level input
in ut voltage, VIH† PC(0–2)
G_RST
Miscellaneous‡
Low-level
Low
level in
input
ut voltage, VIL†
MAX
UNIT
1.6
1.8
2.0
V
3
3.3
3.6
V
3
3.3
3.6
V
2.7
3
3.6
V
DVDD
V
3
3.3
3.6
4.5
5
5.5
0.475 VDDP
2
VDDP
VDDP
0.7 DVDD
DVDD
0.6 DVDD
DVDD
2
PCI
3.3 V
0
PCI
5V
0
0.2 DVDD
G_RST
0
0.3 DVDD
Miscellaneous‡
0
Miscellaneous‡
0
0
DVDD
0
DVDD
Input transition time
(tr and tf), tt
PCI
0
Operating free-air
temperature, TA
RθJA = 70.82°C/W, TA = 70°C
Output current, IO
TPBIAS outputs
voltage VID
Differential input voltage,
Common mode in
Common-mode
input
ut voltage,
VIC
Maximum junction
temperature, TJ
Power-up reset time, tpu
3.3 V
9–2
99.3
°C
mA
1.3
118
260
Cable inputs, during arbitration
168
265
TPB cable inputs, source power node
0.4706
TPB cable inputs, nonsource power node
0.4706
2.515
2.015¶
128-PDT high-K JEDEC board
RθJA = 74.6°C/W, TA = 70°C, Pd = 0.6 W
119.2
128-PDT low-K JEDEC board
RθJA = 101.3°C/W, TA = 70°C, Pd = 0.6 W
136.9
mV
V
°C
2
ms
± 1.08
TPA, TPB cable inputs, S200 operation
± 0.5
TPA, TPB cable inputs, S400 operation
± 0.315
† Applies to external inputs and bidirectional buffers without hysteresis.
‡ Miscellaneous terminals are: GPIO2 (90), GPIO3 (89), SDA (92), SCL (91).
§ Applies to external output buffers.
¶ For a node that does not source power; see Section 4.2.2.2 in IEEE Std 1394a-2000.
V
ns
– 5.6
TPA, TPB cable inputs, S100 operation
Receive in
input
ut jitter
V
6
Cable inputs, during data reception
G_RST input
V
0.8
VDDP
VDDP
Miscellaneous‡
Output voltage,
voltage VO§
PCI
0
V
0.8
0
3.3 V
V
VDDP
0.325 VDDP
PC(0–2)
PCI
voltage VI
Input voltage,
NOM
0
VDDP = 3.3 V
VDDP = 5 V
PCI I/O clam
clamping
ing voltage,
VDDP
MIN
ns
Recommended Operating Conditions (Continued)
TEST
CONDITION
Receive
R
i input
i
t
skew
MIN
NOM
MAX
Between TPA and TPB cable inputs, S100 operation
± 0.8
Between TPA and TPB cable inputs, S200 operation
± 0.55
Between TPA and TPB cable inputs, S400 operation
± 0.5
UNIT
ns
9.3 Electrical Characteristics Over Recommended Operating Conditions
(unless otherwise noted)
PARAMETER
VOH
High-level
output
High
level out
ut voltage
OPERATION
PCI
Miscellaneous‡
VOL
Low-level
Low
level out
output
ut voltage
PCI
Miscellaneous‡
IOZ
3-state output high-impedance
Output pins
3.6 V
3.6 V
IIL
Low level input current
Low-level
Input pins
I/O pins†
IIH
High level input current
High-level
PCI†
Others†
TEST
CONDITIONS
MIN
IOH = – 0.5 mA
IOH = – 2 mA
0.9 DVDD
IOH = – 4 mA
IOL = 1.5 mA
DVDD – 0.6
2.4
UNIT
V
0.1 DVDD
IOL = 6 mA
IOL = 4 mA
0.55
VO = DVDD or GND
VI = GND
± 20
V
0.5
± 20
± 20
3.6 V
VI = GND
VI = DVDD
3.6 V
VI = DVDD
± 20
3.6 V
MAX
± 20
µA
A
µA
µA
† For I/O terminals, input leakage (IIL and IIH) includes IOZ of the disabled output.
‡ Miscellaneous terminals are: GPIO2 (90), GPIO3 (89), SDA (92), SCL (91).
9–3
9.4 Electrical Characteristics Over Recommended Ranges of Operating Conditions
(unless otherwise noted)
9.4.1
Device
PARAMETER
TEST CONDITIONS
MIN
See Note 4
Supply
S
l currentt (internal
(i t
l voltage
lt
regulator
l t enabled,
bl d
REG_EN
REG EN = L)
IDD
TYP
MAX
See Note 5
128
See Note 6
69.8
mA
VTH
VO
Power status threshold, CPS input†
Ports disabled
VDD = 1.8 V (internal)
TA = 25°C
Ports disabled
VDD = 1.8 V (external)
TA = 25°C
400-kΩ resistor†
TPBIAS output voltage
At rated IO current
II
Input current (PC0 – PC2 inputs)
– 90
– 20
IIRST
Pullup current (G_RST
(G RST input)
VDD = 3.6 V
VI = 1.5 V
VI = 0 V
– 90
– 20
IDD(ULP)
Supply current—ultralow power mode (internal voltage
regulator enabled, REG_EN = L)
IDD(ULP)
Supply current—ultralow power mode (internal voltage
regulator disabled, REG_EN = H, REG18 = 1.8 V)
UNIT
158
3
mA
50
µA
4.7
7.5
V
1.665
2.015
V
5
µA
µA
A
† Measured at cable power side of resistor.
NOTES: 4. Transmit data (transmit on all ports full isochronous payload of 84 µs, S400, data value of CCCC CCCCh).
5. Repeat data (receive on one port, transmit on other two ports, full isochronous payload of 84 µs, S400, data value of CCCC CCCCh),
VDD = 3.3 V, TA = 25°C
6. Idle (receive cycle start on one port, transmit cycle start on other two ports), VDD = 3.3 V, TA = 25°C
9.4.2
Driver
PARAMETER
TEST CONDITIONS
VOD
IDIFF
Differential output voltage
56 Ω , see Figure 9–1
Driver difference current, TPA+, TPA–, TPB+, TPB –
Drivers enabled, speed signaling off
ISP200
ISP400
Common-mode speed signaling current, TPB+, TPB –
S200 speed signaling enabled
Common-mode speed signaling current, TPB+, TPB –
S400 speed signaling enabled
MIN
MAX
UNIT
172
– 1.05‡
265
1.05‡
mV
– 4.84§
– 12.4§
– 2.53§
– 8.10§
mA
mA
mA
VOFF
Off state differential voltage
Drivers disabled, see Figure 9–1
20
mV
‡ Limits defined as algebraic sum of TPA+ and TPA– driver currents. Limits also apply to TPB+ and TPB – algebraic sum of driver currents.
§ Limits defined as absolute limit of each of TPB+ and TPB – driver currents.
TPAx+
TPBx+
56 Ω
TPAx–
TPBx–
Figure 9–1. Test Load Diagram
9–4
9.4.3
Receiver
PARAMETER
TEST CONDITIONS
ZID
Differential impedance
Drivers disabled
ZIC
Common mode impedance
Common-mode
Drivers disabled
VTH-R
VTH-CB
Receiver input threshold voltage
Drivers disabled
Cable bias detect threshold, TPBx cable inputs
Drivers disabled
VTH+
VTH–
Positive arbitration comparator threshold voltage
MIN
TYP
4
7
MAX
UNIT
kΩ
4
pF
20
kΩ
24
pF
– 30
30
mV
0.6
1.0
V
Drivers disabled
89
168
mV
Negative arbitration comparator threshold voltage
Drivers disabled
–168
– 89
mV
VTH–SP200
Speed signal threshold
TPBIAS–TPA common mode
voltage, drivers disabled
49
131
mV
VTH–SP400
Speed signal threshold
TPBIAS–TPA common mode
voltage, drivers disabled
314
396
mV
MAX
UNIT
9.5 Thermal Characteristics
PARAMETER
128-PDT
128-PDT
RθJA, high-K board
RθJA, low-K board
128-PDT
RθJC
TEST CONDITIONS
MIN
TYP
Board mounted,, no air flow,, JEDEC test board
74.6
°C/W
101.3
°C/W
18.7
°C/W
9.6 Switching Characteristics for PHY Port Interface
PARAMETER
tr
tf
TEST CONDITIONS
MIN
Jitter, transmit
Between TPA and TPB
Skew, transmit
Between TPA and TPB
TP differential rise time, transmit
10% to 90%, at 1394 connector
0.5
TP differential fall time, transmit
90% to 10%, at 1394 connector
0.5
TYP
MAX
UNIT
± 0.15
ns
± 0.10
ns
1.2
ns
1.2
ns
9.7 Operating, Timing, and Switching Characteristics of XI
PARAMETER
VDD
VIH
High-level input voltage
VIL
Low-level input voltage
MIN
TYP
MAX
3.0
3.3
3.6
UNIT
V (PLLVDD)
0.63 VDD
V
0.33 VDD
Input clock frequency
V
24.576
Input clock frequency tolerance
Input slew rate
Input clock duty cycle
MHz
<100
PPM
0.2
4
V/ns
40%
60%
9.8 Switching Characteristics for PCI Interface†
MEASURED
MIN
Setup time before PCLK
PARAMETER
– 50% to 50%
7
ns
Hold time before PCLK
– 50% to 50%
0
ns
tval
Delay time, PCLK to data valid
† These parameters are ensured by design.
–50% to 50%
2
tsu
th
TYP
MAX
11
UNIT
ns
9–5
10 Mechanical Information
The TSB43AB23 device is packaged in a 128-terminal PDT package. The following shows the mechanical
dimensions for the PDT package.
PDT (S-PQFP-G128)
PLASTIC QUAD FLATPACK
0,23
0,13
0,40
96
0,05 M
65
97
64
128
33
1
0,13 NOM
32
12,40 TYP
Gage Plane
14,05
SQ
13,95
16,10
SQ
15,90
0,05 MIN
0,25
0°–ā5°
0,75
0,45
1,05
0,95
Seating Plane
1,20 MAX
0,08
4087726/A 11/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136
10–1
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
0,08 M
0,50
144
0,13 NOM
37
1
36
Gage Plane
17,50 TYP
20,20 SQ
19,80
22,20
SQ
21,80
0,25
0,05 MIN
0°–ā7°
0,75
0,45
1,45
1,35
Seating Plane
1,60 MAX
0,08
4040147 / C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
10–2