TI SN75173DR

SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
D
D
D
D
D
D
D
D
description
The SN55173, SN65173, and SN75173 are
monolithic quadruple differential line receivers
with 3-state outputs. They are designed to meet
the
requirements
of
TIA/EIA-422-B,
TIA/EIA-423-B, TIA/EIA-485-A, and several ITU
recommendations. The standards are for
balanced multipoint bus transmission at rates up
to 10 megabits per second. The four receivers
share two OR enable inputs, one active when
high, the other active when low. These devices
feature high input impedance, input hysteresis for
increased noise immunity, and input sensitivity of
± 200 mV over a common-mode input voltage
range of – 12 V to 12 V. Fail-safe design specifies
that if the inputs are open circuited, the outputs are
always high. The SN65173 and SN75173 are
designed for optimum performance when used
with the SN75172 or SN75174 quad differential
line drivers.
SN55173 . . . J PACKAGE
SN65173, SN75173 . . . D OR N PACKAGE
(TOP VIEW)
1B
1A
1Y
G
2Y
2A
2B
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4B
4A
4Y
G
3Y
3A
3B
SN55173 . . . FK PACKAGE
(TOP VIEW)
1A
1B
NC
VCC
4B
D
Meet or Exceed the Requirements of
TIA/EIA-422-B, TIA/EIA-423-B, and
TIA/EIA-485-A and ITU Recommendations
V.10, V.11, X.26, and X.27
Designed for Multipoint Bus Transmission
on Long Bus Lines in Noisy Environments
3-State Outputs
Common-Mode Input Voltage Range of
– 12 V to 12 V
Input Sensitivity . . . ± 200 mV
Input Hysteresis . . . 50 mV Typ
High Input Impedance . . . 12 kΩ Min
Operate From Single 5-V Supply
Low Power Requirements
Pin-to-Pin Replacement for AM26LS32
1Y
G
NC
2Y
2A
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
4Y
NC
G
3Y
2B
GND
NC
3B
3A
D
NC – No internal connection
THE SN55173 IS NOT RECOMMENDED
FOR NEW DESIGNS.
The SN55173 is characterized over the full military temperature range of – 55°C to 125°C. The SN65173 is
characterized for operation from –40°C to 85°C. The SN75173 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
PLASTIC
SMALL OUTLINE
(D)
PLASTIC
CHIP CARRIER
(FK)
CERAMIC DIP
(J)
PLASTIC DIP
(N)
0°C to 70°C
SN75173D
—
—
SN75173N
–40°C to 85°C
SN65173D
—
—
SN65173N
–55°C to 125°C
—
SN55173FK
SN55173J
—
The D package is available taped and reeled. Add the suffix R to the device type (e.g., SN75173DR).
FUNCTION TABLE
(each receiver)
ENABLES
DIFFERENTIAL
A–B
VID ≥ 0.2
02V
0 2 V < VID < 0
2V
–0.2
0.2
VID ≤ –0.2
02V
X
Open circuit
G
G
OUTPUT
Y
H
X
H
X
L
H
H
X
?
X
L
?
H
X
L
X
L
L
L
H
Z
X
L
H
H
X
H
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
logic symbol †
G
G
1A
1B
2A
2B
3A
3B
4A
4B
4
≥1
12
2
EN
3
1Y
1
6
7
10
9
14
15
5
2Y
11
3Y
13
4Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
logic diagram (positive logic)
G
4
12
G
1A
1B
2A
2B
3A
3B
4A
2
3
1
6
5
7
10
9
14
15
11
13
1Y
2Y
3Y
4Y
4B
Pin numbers shown are for the D, J, and N packages.
schematics of inputs and outputs
EQUIVALENT OF EACH A OR B INPUT
EQUIVALENT OF G OR G INPUT
VCC
VCC
8.3 kΩ
NOM
100 kΩ
NOM
A Pins Only
Input
20 kΩ
NOM
960 Ω
NOM
TYPICAL OF ALL OUTPUTS
85 Ω
NOM
VCC
Input
Output
100 kΩ
NOM
B Pins Only
960 Ω
NOM
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (VI or B inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V
Enable input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Low-level output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Case temperature for 60 seconds, TC: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential input voltage, are with respect to network ground terminal.
2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.
3. The package thermal impedance is calculated in accordance with JESD 51.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING
FACTOR
TA = 70°C
POWER RATING
TA = 125°C
POWER RATING
FK
1375 mW
11 mW/°C
880 mW
275 mW
J
1375 mW
11 mW/°C
880 mW
275 mW
recommended operating conditions
MIN
NOM
4.5
5
5.5
V
4.75
5
5.25
V
Common-mode input voltage, VIC
± 12
V
Differential input voltage, VID
± 12
V
SN55173
Supply voltage
voltage, VCC
SN65173, SN75173
High-level enable-input voltage, VIH
2
Low-level enable-input voltage, VIL
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
4
MAX
POST OFFICE BOX 655303
V
0.8
V
– 400
µA
16
mA
SN55173
– 55
125
SN65173
–40
85
SN75173
0
70
• DALLAS, TEXAS 75265
UNIT
°C
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature
PARAMETER
TEST CONDITIONS
MIN
VIT+
VIT–
Positive-going input threshold voltage
Negative-going input threshold voltage
VO = 2.7 V,
VO = 0.5 V,
Vhys
VIK
Hysteresis (VIT+ – VIT–)
See Figure 4
Enable-input clamp voltage
II = – 18 mA
VOH
High-level output voltage
VID = 200 mV,
IOH = – 400 µA
VOL
Low level output voltage
Low-level
VID = – 200 mV
mV,
See Figure 1
IOL = 8 mA
IOL = 16 mA
IOZ
High-impedance-state output current
VO = 0.4 V to 2.4 V
See Note 3
VI = 12 V
VI = – 7 V
II
Line input current
Other input at 0 V,
V
IIH
IIL
High-level enable-input current
VIH = 2.7 V
VIL = 0.4 V
ri
Input resistance
Low-level enable-input current
IO = – 0.4 mA
IO = 16 mA
TYP†
MAX
0.2
– 0.2‡
UNIT
V
V
50
mV
– 1.5
V
SN55173
2.5
V
SN65173,
SN75173
2.7
V
0.45
0.5
± 20
1
– 0.8
V
µA
mA
20
µA
– 100
µA
12
kΩ
IOS
Short-circuit output current
– 15
– 85
mA
ICC
Supply current
Outputs disabled
70
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold voltage
levels only.
NOTE 3: Refer to TIA/EIA-422-B and TIA/EIA-423-B for exact conditions.
switching characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TYP
MAX
20
35
ns
Propagation delay time, high-to-low-level output
VID = – 1.5 V to 1.5 V,,
CL = 15 pF,
See Figure 1
TEST CONDITIONS
22
35
ns
tPZH
tPZL
Output enable time to high level
CL = 15 pF,
See Figure 2
17
22
ns
Output enable time to low level
CL = 15 pF,
See Figure 3
20
25
ns
tPHZ
tPLZ
Output disable time from high level
CL = 5 pF,
See Figure 2
21
30
ns
Output disable time from low level
CL = 5 pF,
See Figure 3
30
40
ns
tPLH
tPHL
Propagation delay time, low-to-high-level output
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
UNIT
5
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
Generator
(see Note B)
50 Ω
Output
0V
Input
CL = 15 pF
(see Note A)
1.5 V
[2.5 V]†
0V
– 1.5 V
†
tPHL [– 2.5 V]
VOH
tPLH
Output
1.3 V
1.3 V
VOL
2V
VOLTAGE WAVEFORMS
TEST CIRCUIT
† Voltage for the SN55173 only.
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 1. tPLH, tPHL Test Circuit and Voltage Waveforms
VCC
Output
2 kΩ
S1
1.5 V
[2.5 V]†
Input
CL
(see Note A)
1.3 V
0V
tPZH
5 kΩ
Generator
(see Note B)
3V
1.3 V
0.5 V
(see Note C)
Output
S1 Open
2V
tPHZ
(see Note D)
1.3 V
≈0 V
VOH
S1 Closed
≈1.4 V
VOLTAGE WAVEFORMS
50 Ω
TEST CIRCUIT
† Voltage for the SN55173 only.
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
C. All diodes are 1N916, or equivalent.
D. To test the active-low enable G, ground G and apply an inverted input waveform to G.
Figure 2. tPHZ, tPZH Test Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
VCC
2 kΩ
– 2.5 V
3V
Input
CL
(see Note A)
Generator
(see Note B)
1.3 V
1.3 V
0V
5 kΩ
(see Note C)
tPZL
S2 Open
Output
2V
tPLZ
S2 Closed
≈ 1.4 V
1.3 V
VOL
(see Note D)
S2
0.5 V
50 Ω
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
C. All diodes are 1N916, or equivalent.
D. To test the active-low enable G, ground G and apply an inverted input waveform to G.
Figure 3. tPZL, tPLZ Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS†
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5
IO = 0
TA = 25°C
VO – Output Voltage – V
4
3.5
VIC =
0
VIC =
–12 V
VIC =
12 V
3
VIT–
VIT–
VIT–
2.5
2
VIT+
VIT+
VIT+
1.5
1
0.5
VID = 0.2 V
TA = 25°C
4.5
VOH – High-Level Output Voltage – V
4.5
5
VCC = 5 V
4
3.5
VCC = 5.5 V
3
2.5
VCC = 5 V
2
1.5
1
VCC = 4.5 V
0.5
0
–125 –100 – 75 – 50 – 25 0
25 50 75 100 125
VID – Differential Input Voltage – mV
0
0
– 5 –10 –15 –20 –25 –30 –35 – 40 – 45 – 50
IOH – High-Level Output Current – mA
Figure 4
Figure 5
† Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS†
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
0.6
5
VOH – High-Level Output Voltage – V
4.5
4
VOL– Low-Level Output Voltage - V
VCC = 5 V
VID = 0.2 V
IOH = – 400 µA
3.5
3
2.5
2
1.5
1
VCC = 5 V
TA = 25°C
0.5
0.4
0.3
0.2
0.1
0.5
0
0
0
10
70
20
30 40
50
60
TA – Free-Air Temperature – °C
80
0
90
5
10
Figure 6
20
25
30
Figure 7
OUTPUT VOLTAGE
vs
ENABLE G VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
5
0.5
VCC = 5 V
VID = – 0.2 V
IOL = 8 mA
0.4
VID = 0.2 V
Load = 8 kΩ to GND
TA = 25°C
4.5
VCC = 5.5 V
4
VO – Output Voltage – V
VOL – Low-Level Output Voltage – V
15
IOL – Low-Level Output Current – mA
0.3
SN65173 only
0.2
VCC = 5 V
3.5
VCC = 4.5 V
3
2.5
2
1.5
1
0.1
0.5
0
0
0
10
20
30
40
50
60
70
80
90
0
0.5
TA – Free-Air Temperature – °C
1
1.5
2
2.5
3
VI – Enable G Voltage – V
Figure 8
Figure 9
† Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
ENABLE G VOLTAGE
INPUT CURRENT
vs
INPUT VOLTAGE
6
1
VCC = 5.5 V
5
VCC = 5 V
0.75
I I – Input Current – mA
VO – Output Voltage – V
VID = – 0.2 V
Load = 1 kΩ to VCC
TA = 25°C
VCC = 4.5 V
4
3
2
VCC = 5 V
TA = 25°C
0.5
0.25
0
–0.25
The Unshaded Area
Conforms to
Figure 3.2 of
TIA/EIA-485-A
–0.5
1
–0.75
0
0
0.5
1
1.5
2
2.5
–1
–8
3
–6
–4 –2
VI – Enable G Voltage – V
0
2
4
6
8
10
12
VI – Input Voltage – V
Figure 10
Figure 11
APPLICATION INFORMATION
1/4 SN75175
1/4 SN75172
1/4 SN75173
1/4 SN75174
Up to 32
Driver/Receiver
Pairs
1/4 SN75172 1/4 SN75173
1/4 SN75173
1/4 SN75174
NOTE A: The line should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short as
possible.
Figure 12. Typical Application Circuit
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
1
Lead/Ball Finish
MSL Peak Temp (3)
SN55173J
ACTIVE
CDIP
J
16
TBD
A42 SNPB
SN65173D
OBSOLETE
SOIC
D
16
TBD
Call TI
N / A for Pkg Type
Call TI
SN65173DR
OBSOLETE
SOIC
D
16
TBD
Call TI
Call TI
SN65173N
OBSOLETE
PDIP
N
16
TBD
Call TI
Call TI
SN75173D
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75173DE4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75173DR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75173DRE4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75173J
OBSOLETE
CDIP
J
16
TBD
Call TI
SN75173N
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
Call TI
N / A for Pkg Type
SN75173NE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN75173NSR
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75173NSRE4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SNJ55173FK
ACTIVE
LCCC
FK
20
1
TBD
SNJ55173J
ACTIVE
CDIP
J
16
1
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
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