TI AM26LS32AID

AM26LS32AC, AM26LS32AI, AM26LS33AC,
AM26LS32AM, AM26LS33AM
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS115D – OCTOBER 1980 – REVISED MARCH 2002
D
D
D
D
D
D
D
D
D
AM26LS32AC . . . D, N, OR NS PACKAGE
AM26LS32AI, AM26LS33AC . . . D OR N PACKAGE
AM26LS32AM, AM26LS33AM . . . J PACKAGE
(TOP VIEW)
AM26LS32A Devices Meet or Exceed the
Requirements of ANSI TIA/EIA-422-B,
TIA/EIA-423-B, and ITU Recommendations
V.10 and V.11
AM26LS32A Devices Have ±7-V
Common-Mode Range With ±200-mV
Sensitivity
AM26LS33A Devices Have ±15-V
Common-Mode Range With ±500-mV
Sensitivity
Input Hysteresis . . . 50 mV Typical
Operate From a Single 5-V Supply
Low-Power Schottky Circuitry
3-State Outputs
Complementary Output-Enable Inputs
Input Impedance . . . 12 kΩ Min
Designed to Be Interchangeable With
Advanced Micro Devices AM26LS32 and
AM26LS33
1B
1A
1Y
G
2Y
2A
2B
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4B
4A
4Y
G
3Y
3A
3B
AM26LS32AM, AM26LS33AM . . . FK PACKAGE
(TOP VIEW)
1A
1B
NC
VCC
4B
D
1Y
G
NC
2Y
2A
description
3
2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
4Y
NC
G
3Y
2B
GND
NC
3B
3A
The AM26LS32A and AM26LS33A devices are
quadruple differential line receivers for balanced
and unbalanced digital data transmission. The
enable function is common to all four receivers
and offers a choice of active-high or active-low
input. The 3-state outputs permit connection
directly to a bus-organized system. Fail-safe
design ensures that, if the inputs are open, the
outputs always are high.
4
NC – No internal connection
Compared to the AM26LS32 and the AM26LS33, the AM26LS32A and AM26LS33A incorporate an additional
stage of amplification to improve sensitivity. The input impedance has been increased, resulting in less loading
of the bus line. The additional stage has increased propagation delay; however, this does not affect
interchangeability in most applications.
The AM26LS32AC and AM26LS33AC are characterized for operation from 0°C to 70°C. The AM26LS32AI is
characterized for operation from –40°C to 85°C. The AM26LS32AM and AM26LS33AM are characterized for
operation over the full military temperature range of –55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
AM26LS32 and AM26LS33 are trademarks of Advanced Micro Devices, Inc.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
AM26LS32AC, AM26LS32AI, AM26LS33AC,
AM26LS32AM, AM26LS33AM
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS115D – OCTOBER 1980 – REVISED MARCH 2002
FUNCTION TABLE
(each receiver)
DIFFERENTIAL
A–B
VID ≥ VIT
IT+
VIT
IT
IT– ≤ VID ≤ VIT+
VID ≤ VIT
IT–
X
Open
ENABLES
OUTPUT
Y
G
G
H
X
H
X
L
H
H
X
?
X
L
?
H
X
L
X
L
L
L
H
Z
H
X
H
X
L
H
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
logic diagram (positive logic)
G
G
1A
1B
2A
2B
3A
3B
4A
4B
2
4
12
2
1
6
7
10
9
14
15
POST OFFICE BOX 655303
3
5
11
13
1Y
2Y
3Y
4Y
• DALLAS, TEXAS 75265
AM26LS32AC, AM26LS32AI, AM26LS33AC,
AM26LS32AM, AM26LS33AM
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS115D – OCTOBER 1980 – REVISED MARCH 2002
schematics of inputs and outputs
EQUIVALENT OF EACH
DIFFERENTIAL INPUT
EQUIVALENT OF EACH ENABLE INPUT
VCC
TYPICAL OF ALL OUTPUTS
VCC
85 Ω
NOM
VCC
8.3 kΩ
NOM
100 kΩ
A Input Only
960 Ω
NOM
20 kΩ
NOM
Enable
Output
Input
960 Ω
NOM
100 kΩ
B Input Only
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI: Any differential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
Other inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Case temperature for 60 seconds, TC: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the network ground terminal.
2. Differential voltage values are at the noninverting (A) input terminals with respect to the inverting (B) input terminals.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 125°C
POWER RATING
FK
1375 mW
11.0 mW/°C
880 mW
275 mW
J
1375 mW
11.0 mW/°C
880 mW
275 mW
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
AM26LS32AC, AM26LS32AI, AM26LS33AC,
AM26LS32AM, AM26LS33AM
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS115D – OCTOBER 1980 – REVISED MARCH 2002
recommended operating conditions
VCC
Supply voltage
VIH
VIL
High-level input voltage
AM26LS32AC, AM26LS32AI, AM26LS33AC
AM26LS32AM, AM26LS33AM
MIN
NOM
MAX
4.75
5
5.25
4.5
5
5.5
2
UNIT
V
V
Low-level input voltage
0.8
AM26LS32A
±7
AM26LS33A
±15
V
VIC
Common mode input voltage
Common-mode
IOH
IOL
High-level output current
–440
µA
Low-level output current
8
mA
AM26LS32AC, AM26LS33AC
TA
Operating free-air temperature
0
V
70
AM26LS32AI
–40
85
AM26LS32AM, AM26LS33AM
–55
125
°C
electrical characteristics over recommended ranges of VCC, VIC, and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT
IT+
Positive-going
g g
input threshhold voltage
VO = VOHmin
min, IOH = –440
440 µA
VIT
IT–
Negative-going
g
g g
input threshhold voltage
VO = 0
0.45
45 V
V, IOL = 8 mA
VIK
Hysteresis voltage
(VIT+ – VIT–)
Enable-input clamp voltage
VOH
High
level output voltage
High-level
Vhys
TYP†
MAX
AM26LS32A
0.2
AM26LS33A
0.5
AM26LS32A
AM26LS33A
–0.2‡
–0.5‡
VCC = MIN,
VCC =MIN,, VID = 1 V,,
VI(G) = 0.8 V, IOH = –440 µA
Low level output voltage
Low-level
VCC = MIN,, VID = –1 V,,
VI(G) = 0.8 V
IOZ
Off-state
(high impedance state)
(high-impedance
output current
VCC = MAX
II
Line input current
VI = 15 V,
VI = –15 V,
II(EN)
IIH
Enable input current
IIL
rI
Low-level enable current
Input resistance
VI = 0.4 V
VIC = –15 V to 15 V,
IOS
Short-circuit output current§
VCC = MAX
II = –18 mA
AM26LS32AC
AM26LS33AC
AM26LS32AM, AM26LS32AI,
AM26LS33AM
V
mV
–1.5
V
2.7
V
2.5
IOL = 4 mA
IOL = 8 mA
0.45
VO = 2.4 V
20
VO = 0.4 V
–20
0.4
Other input at –10 V to 15 V
1.2
Other input at –15 V to 10 V
–1.7
VI = 5.5 V
VI = 2.7 V
100
One input to ac ground
UNIT
V
50
VOL
High-level enable current
MIN
12
–15
V
µA
mA
µA
20
µA
–0.36
mA
15
kΩ
–85
mA
ICC
Supply current
VCC = MAX,
All outputs disabled
52
70
mA
† All typical values are at VCC = 5 V, TA = 25°C, and VIC = 0.
‡ The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold levels
only.
§ Not more than one output should be shorted to ground at a time, and duration of the short circuit should not exceed one second.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
AM26LS32AC, AM26LS32AI, AM26LS33AC,
AM26LS32AM, AM26LS33AM
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS115D – OCTOBER 1980 – REVISED MARCH 2002
switching characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
tPLH
tPHL
Propagation delay time, low-to-high-level output
tPZH
tPZL
Output enable time to high level
tPHZ
tPLZ
Output disable time from high level
Propagation delay time, high-to-low-level output
Output enable time to low level
Output disable time from low level
MIN
pF
CL = 15 pF,
See Figure 1
CL = 15 pF,
pF
See Figure 1
CL = 5 pF,
pF
See Figure 1
TYP
MAX
20
35
22
35
17
22
20
25
21
30
30
40
UNIT
ns
ns
ns
PARAMETER MEASUREMENT INFORMATION
VCC
Test
Point
RL = 2 kΩ
2.5 V
S1
From Output
Under Test
CL
(see Note A)
Input
0
0
–2.5 V
5 kΩ
tPLH
See Note B
tPHL
VOH
Output
S2
1.3 V
1.3 V
VOL
S1 and S2 Closed
TEST CIRCUIT
VOLTAGE WAVEFORMS FOR tPLH, tPHL
≤5 ns
90%
Enable G
1.3 V
≤5 ns
3V
90%
10%
See Note C
90%
90%
10%
Output
S1 Open
S2 Closed
0
See Note C
3V
90%
90%
10%
S1 Closed
S2 Closed
tPZL
VOH
≈1.4 V
S1 Closed
S2 Closed
1.3 V
Output
VOLTAGE WAVEFORMS FOR tPHZ, tPZH
S1 Closed
S2 Open
3V
1.3 V
1.3 V
10%
1.3 V
tPHZ
1.3 V
10%
0
0.5 V
3V
90%
1.3 V
Enable G
10%
tPZH
≤5 ns
10%
0
1.3 V
1.3 V
90%
Enable G
1.3 V
10%
Enable G
≤5 ns
tPLZ
0
≈1.4 V
VOL
0.5 V
VOLTAGE WAVEFORMS FOR tPLZ, tPZL
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Enable G is tested with G high; G is tested with G low.
Figure 1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
AM26LS32AC, AM26LS32AI, AM26LS33AC,
AM26LS32AM, AM26LS33AM
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS115D – OCTOBER 1980 – REVISED MARCH 2002
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT†
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
5
5
4
3
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
VID = 0.2 V
TA = 25°C
VCC = 5.25 V
VCC = 5 V
2
VCC = 5.5 V
VCC = 4.75 V
1
VCC = 4.5 V
VCC = 5 V
VID = 0.2 mV
IOH = –440 µA
4
3
2
1
0
0
–10
–20
–30
–40
–50
0
IOH – High-Level Output Current – mA
0
10
† VCC = 5.5 V and VCC = 4.5 V applies to M-suffix devices only.
20
30
40
50
60
TA – Free-Air Temperature – °C
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
0.5
0.6
VCC = 5 V
TA = 25°C
VID = –0.2 mV
0.5
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
80
Figure 3
Figure 2
0.4
0.3
0.2
0.1
0
VCC = 5 V
VID = –0.2 V
IOL = 8 mA
0.4
0.3
0.2
0.1
0
0
15
20
25
10
IOL – Low-Level Output Current – mA
5
30
0
10
Figure 4
6
70
20
30
40
50
60
TA – Free-Air Temperature – °C
Figure 5
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
70
80
AM26LS32AC, AM26LS32AI, AM26LS33AC,
AM26LS32AM, AM26LS33AM
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS115D – OCTOBER 1980 – REVISED MARCH 2002
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
ENABLE G VOLTAGE
OUTPUT VOLTAGE
vs
ENABLE G VOLTAGE
5
5
VID = 0.2 V
TA = 25°C
Load = 8 kΩ to GND
4.5
VCC = 5.5 V
4
4
VCC = 5 V
3.5
VO – Output Voltage – V
VO – Output Voltage – V
VCC = 5 V
VID = 0.2 V
Load = 8 kΩ to GND
4.5
VCC = 4.5 V
3
2.5
2
1.5
TA = 70°C
TA = 25°C
TA = 0°C
3.5
3
2.5
2
1.5
1
1
0.5
0.5
0
0
0
0.5
1
1.5
2
2.5
0
3
0.5
1
1.5
2
2.5
3
Enable G Voltage – V
Enable G Voltage – V
Figure 6
Figure 7
OUTPUT VOLTAGE
vs
ENABLE G VOLTAGE
OUTPUT VOLTAGE
vs
ENABLE G VOLTAGE
6
6
VCC = 5.5 V
VCC = 5 V
5
5
VO – Output Voltage – V
VO – Output Voltage – V
VCC = 4.5 V
4
3
2
1
0
0.5
1
TA = 70°C
3
2
1
VID = –0.2 V
Load = 1 kΩ to VCC
TA = 25°C
0
TA = 0°C
TA = 25°C
4
1.5
2
2.5
3
VCC = 5 V
VID = –0.2 V
Load = 1 kΩ to VCC
0
0
0.5
Enable G Voltage – V
1
1.5
2
2.5
3
Enable G Voltage – V
Figure 9
Figure 8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
AM26LS32AC, AM26LS32AI, AM26LS33AC,
AM26LS32AM, AM26LS33AM
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS115D – OCTOBER 1980 – REVISED MARCH 2002
TYPICAL CHARACTERISTICS
AM26LS32A
AM26LS33A
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
5
5
VO – Output Voltage – V
4
VCC = 5 V, IO = 0, TA = 25°C
4.5
4
VIC =
–7 V
3.5
VIC =
0
VO – Output Voltage – V
4.5
VCC = 5 V
IO = 0
TA = 25°C
VIC =
7V
3
2.5
2
VIT–
VIT+
1.5
VIT–
VIT+
VIT–
VIT+
2
0.5
100
VIT–
VIT–
VIT+
1.5
0.5
50
VID – Differential Input Voltage – mV
VIT–
VIT+
0
–200 –150 –100 –50
150 200
VIC =
15 V
2.5
1
0
VIC =
0
3
1
0
–200 –150 –100 –50
VIC =
–15 V
3.5
0
VIT+
50
100
150 200
VID – Differential Input Voltage – mV
Figure 11
Figure 10
INPUT CURRENT
vs
INPUT VOLTAGE
4
3
I I – Input Current – mA
2
1
0
VCC = 0
–1
–2
VCC = 5 V
The Unshaded Area
Shows Requirements of
Paragraph 4.2.1 of ANSI
Standards EIA/TIA-422-B and
EIA/TIA-423-B.
–3
–4
–25 –20 –15 –10 –5
0
5
10
15
VI – Input Voltage – V
Figure 12
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
20
25
AM26LS32AC, AM26LS32AI, AM26LS33AC,
AM26LS32AM, AM26LS33AM
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS115D – OCTOBER 1980 – REVISED MARCH 2002
APPLICATION INFORMATION
1/4 AM26LS31AC
1/4 AM26LS32AC
Data
In
RT†
1/4 AM26LS32AC
Data
Out
1/4 AM26LS33AC
Data
Out
Data
Out
† RT equals the characteristic impedance of the line.
Figure 13. Circuit With Multiple Receivers
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
PACKAGE OPTION ADDENDUM
www.ti.com
19-Oct-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
5962-7802003M2A
ACTIVE
LCCC
FK
20
1
TBD
5962-7802003MEA
ACTIVE
CDIP
J
16
1
TBD
5962-7802003MFA
ACTIVE
CFP
W
16
1
TBD
5962-7802004M2A
ACTIVE
LCCC
FK
20
1
TBD
5962-7802004MEA
ACTIVE
CDIP
J
16
1
TBD
5962-7802004MFA
ACTIVE
CFP
W
16
1
AM26LS32ACD
ACTIVE
SOIC
D
16
40
AM26LS32ACDE4
ACTIVE
SOIC
D
16
40
AM26LS32ACDR
ACTIVE
SOIC
D
AM26LS32ACDRE4
ACTIVE
SOIC
AM26LS32ACN
ACTIVE
AM26LS32ACNE4
Lead/Ball Finish
MSL Peak Temp (3)
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
TBD
A42 SNPB
N / A for Pkg Type
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
AM26LS32ACNSR
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AM26LS32ACNSRG4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AM26LS32AID
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AM26LS32AIDE4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AM26LS32AIDR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AM26LS32AIDRE4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AM26LS32AIN
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
AM26LS32AINE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
AM26LS32AMFKB
ACTIVE
LCCC
FK
20
1
TBD
AM26LS32AMJ
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
AM26LS32AMJB
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
N / A for Pkg Type
AM26LS32AMWB
ACTIVE
CFP
W
16
1
TBD
A42 SNPB
N / A for Pkg Type
AM26LS33ACD
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AM26LS33ACDE4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AM26LS33ACDG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AM26LS33ACDR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AM26LS33ACDRE4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Oct-2006
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
AM26LS33ACDRG4
ACTIVE
SOIC
D
16
AM26LS33ACN
ACTIVE
PDIP
N
16
25
AM26LS33ACNE4
ACTIVE
PDIP
N
16
AM26LS33AMFKB
ACTIVE
LCCC
FK
AM26LS33AMJ
ACTIVE
CDIP
J
AM26LS33AMJB
ACTIVE
CDIP
AM26LS33AMWB
ACTIVE
CFP
2500 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
CU NIPDAU
Level-1-260C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
20
1
TBD
16
1
TBD
A42 SNPB
N / A for Pkg Type
J
16
1
TBD
A42 SNPB
N / A for Pkg Type
W
16
1
TBD
A42 SNPB
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
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